1

SCHOOL OF TECHNOLOGY
COLLEGE OF ENGINEERING
Analog IC Design

Laboratory Exercise 1: The Electric VLSI Tool

This laboratory is intended to familiarize you with the use of Electric VLSI tool incorporated with LT SPICE IV
simulator. You will use Electric to create new library and do schematic entry. You will also learn to do SPICE simulation
using MOS SPICE models and view output using LT SPICE IV. Different circuit analysis techniques will also be
implemented.

I. CMOS Inverter

1. Run Electric VLSI Tool.

2. Create a new library

File > New Library…
Library name is LE1_<lastname><firstnameinitial>

Click OK.

3. Add new schematic cell view

Cell > New Cell
Choose your newly created library. Cell name is NMOS and choose schematic view.

You can browse your library in the Explorer tab.

 2

4. Click on the Components tab and place a 3-terminal NMOS transistor on the workspace.

5. The bigger value on the side of the NMOS symbol corresponds to its WIDTH (W) parameter while the smaller
value corresponds to its LENGTH (L). In this case the default values show that both L and W measure 2 µm with
the unit set by the tool.

Change these values to parameterized variables {W} and {L} by clicking on the NMOS transistor,

Edit > Properties > Object Properties… or use the hotkey Ctrl + I

Click OK.

6. At this point, we will set a transistor SPICE model for the NMOS transistor. All the intrinsic properties of the
transistor will be defined by this model. Click on the NMOS,

Tools > Simulation(Spice) > Set Spice Model…

Rename the transistor model to N_1u using the Object Property. This is an NMOS transistor in a 1 µm process
technology.

7. Repeat Steps 3 to 6 for a PMOS transistor with properties defined by the table below.

Cell Name PMOS

L {Lp}
W {Wp}
SPICE Model P_1u
 3

Note: You can browse for more components by clicking the black arrow on the icon.

8. Create a new schematic cell Inverter.

9. Make the inverter layout using the PMOS and NMOS previously created. Copy the NMOS and PMOS transistors from
NMOS{sch} and PMOS{sch} to the Inverter{sch} and add other components using the devices from the
Components tab.

To wire the inverter circuit, left click on the terminal of the device to where the wire will start then right click
on the terminal of the device to where the wire will end.

10. Now that the inverter transistor-level circuit is done, it is now ready for simulation. We will be simulating the
inverter circuit using the standard inverter symbol. But first, we have to assign the input and output of the two
terminal inverter. For the input, click on the input port,

Export > Create Export

 4

Type in as the export name. For the output port, use out as the export name.

11. Check Design Rule. The checks whether all the cell views and models you used do not have any violation in
usage.

Tools > DRC > Check Hierarchically

There should be no errors at this point.

12. To create the standard inverter symbol, we will be making an icon view of the circuit.

View > Make Icon View

A generic inverter icon will appear in Inverter{sch}. We will modify this symbol to the standard inverter symbol.

13. Click on the icon and go one hierarchy lower.

Cell > Down Hierarchy > Down Hierarchy or use the hotkey Ctrl + D

14. Modify the icon to the icon below. Use the shapes from the Components tab, under artwork menu.

You can use the Edit menu tools such as rotate, size, etc. to modify the inverter icon.
 5

15. Go back to the higher hierarchy.

Cell > Up Hierarchy > Up Hierarchy or use the hotkey Ctrl + U

Noticed that the inverter icon also changed to the modified symbol.

16. Make a new schematic cell view named Simulation. All the simulation analysis will be done in this cell view.

17. Copy the inverter icon from Inverter{sch} to Simulation {sch}.

18. Place a hanging wire from the input and output of the inverter icon and change their property name to in and
out respectively. Note: Rename the wire itself and not the endpoint.

19. Secure a copy of CMOSmodels.txt. This is the SPICE models of the MOS transistors. It contains 4 NMOS and 4
PMOS transistors definition.

20. Press on the MISC from Components tab then choose Spice Code and place it on the workspace. Modify the
property of the SPICE code. Check Multi-line and add in the SPICE code:

vdd vdd 0 DC 5
vin in 0 DC 0
.param L=2u W=10u Lp=2u Wp=20u
.dc vin 0 5 1m
.include <path to CMOSmodels.txt>

The first line of the SPICE code adds a vdd voltage source from vdd( ) to 0( ) which is in the lower hierarchy
of the circuit of value 5V dc. The second line adds vin voltage source from in to 0( ) of value 0V dc. The third
line uses parametric tool to set all the variables to its corresponding values which in this case sets the length and
width values of PMOS and NMOS transistor. The fourth line is the type of analysis used which is a DC Analysis
that sweeps vin from 0V to 5V with 1mV increment. The last line calls the CMOS models to which the transistors
will be based.
 6

21. Check DRC

Tools > DRC > Check Hierarchically

22. To simulate, press on

Tools > Simulation(Spice) > Write Spice Deck…

This will open the LTSpice IV simulation tool.

23. Plot the input and output voltage of the inverter

Plot Settings > Visible Traces

Select both V(in) and V(out).

Click OK.
 7

24. Simulation should look like this:

25. You can browse the plots’ values by clicking on the expression above the graph, in this case V(out) and V(in).
Once clicked, you can drag the cursor to any specified value that is shown on the Simulation window below.
 8

26. Complete the Table below with the corresponding output voltage given the input to the inverter. Also determine
the state (high, low, cannot be determined) of the output if logic low is from 0V to 1.5V and logic 1 is from 3.5V
to 5V.
V(in) V(out) State
1.5V
5V
3.75V
4.2V
2.5V
1V
300mV

27. Now we will be performing a transient analysis on the inverter. Modify the SPICE code on the Simulation{sch} to:

vdd vdd 0 DC 5
vin in 0 DC 0 pulse 0 5 10n 1n
.param L=2u W=10u Lp=2u Wp=20u
cload out 0 1pF
.tran 0 40n
.include <path to CMOSmodels.txt>

The first line of the SPICE code adds a vdd voltage source from vdd( ) to 0( ) which is in the lower hierarchy
of the circuit of value 5V dc. The second line adds vin voltage source from in to 0( ) of value 0V dc with a pulse
of 0V initial value and final value of 5V. The pulse starts at 10ns and has a rise time of 1ns. The third line sets the
parameter variables. The fourth line adds load capacitance cload from the out wire to gnd. This cload can also
just be added directly into the circuit instead of having it coded as a netlist as shown below.

The fifth line is the type of analysis used which is a Transient Analysis from time 0s to 40ns. The last line calls the
CMOS models to which the transistors will be based.

28. To simulate, press on

Tools > Simulation(Spice) > Write Spice Deck…

This will open the LTSpice IV simulation tool.

Plot Settings > Visible Traces

Plot both V(in) and V(out).

 9

29. Simulation should look like this:

This shows the transient response of the inverter to a pulse input.

II. AND Gate

1. Using the same process as with the Inverter Simulation from previous Laboratory Exercise. Simulate an AND Gate
with the following MOS parameters.

PARAMETER NMOS PMOS

SPICE Name N_1u P_1u
L 2um 2um
W 10um 10um

2. Simulate the AND Gate with the following parameter.

PARAMETER Value/Name
Input 1 inA
Input 2 inB
Output out
3. The Spice code for simulation will be:

vdd vdd 0 DC 5
vinA inA 0 DC 0
vinB inB 0 DC 0
.param <set parameter variables here>
.dc vinA 0 5 1m vinB 0 5 1
.include <path to CMOSmodels.txt>
.print DC V(out)
This DC analysis sweeps vinA from 0V to 5V with 1mV increment and parametrically sweeps vinB from 0V to 5V
with 1V increment. The sweep in vinB means an input of 0V, 1V, 2V, 3V, 4V, and 5V. It plots V(out).

4. Add two more plot panes, and separately graph the two inputs V(inA) and V(inB).

Plot Settings > Add Plot Pane

5. Complete the Table below with the corresponding output voltage given the input to the inverter. Also determine
the state (high, low, cannot be determined) of the output if logic low is from 0v to 2V and logic 1 is from 3V to
5V.
V(ina) V(inb) V(out) State
250mV 1V
3.5V 1V
1.2V 2V
4V 2V
1V 3V
3V 3V
2V 4V
4V 4V
2.2V 5V
3V 5V

Screen shot of the simulation and waveforms:

QUESTION: What can you say in the input-output characteristic of the simulated AND gate?

ANSWER: