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SCHOOL OF TECHNOLOGY COLLEGE OF ENGINEERING Analog IC Design

Name: Katigbak, Khristie Joy L. Rating: _____________________

Punzalan, Justine Roy
Date: December 27, 2016
Course/Yr./Sec: BSECE 4A

Laboratory 1: MOSFET Regions of Operation

This laboratory is intended to familiarize you with the MOSFET devices that we will be using throughout the
semester in larger circuit simulations. We will simulate the voltage-current relationships of an NMOS transistor in
Electric VLSI tool with aid of LT Spice IV simulator and estimate some process parameter using the simulation results.

The n-type Metal-Oxide-Semiconductor Field-Effect-Transistor (n MOSFET) consists of a source and a drain, two
highly conducting n-type semiconductor regions, which are isolated from the p-type substrate by reversed-biased pn
diodes. A metal or poly-crystalline gate covers the region between source and drain. The gate is separated from the
semiconductor by the gate oxide. The circuit symbol is shown in Figure 2.1.

Figure 1.1

The source and drain regions are identical. It is the applied voltages, which determine which n-type region provides
the electrons and becomes the source, while the other n-type region receives the electrons and becomes the drain.

I. Pre-laboratory Procedures:

1. For the circuit shown in Figure 1.2 with the NMOS properties given by Table 1.1, complete Table 1.2 with the
corresponding drain current. Write all the formulas you used in Table 1.3.

PARAMETER VALUE
µn Cox 190E-6
VTHN 560 mV
VTHP -560 mV
λ 0.02
L 10 um
W 20 um
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Figure 1.2 NMOS Circuit Table 1.1 MOS Parameter Values

Table 1.2 NMOS Drain Current

Table 1.3 Formulas

2. Perform Step 1 with length and width values of (a) 5 um and 20 um respectively and (b) 10 um and 40 um
respectively. Complete Table 2.2 and Table 2.3 below.

Table 2.2 NMOS Drain Current (a)

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Table 2.3 NMOS Drain Current (b)

3. For the circuit in Step 1, calculate transconductance and output resistance with drain-source voltage of 1.5 V, 3 V
and 4.5 V and gate voltage of 1.5 V, 3 V and 4.5 V. Complete Table 3.1 with the transconductance values and Table
3.2 with output resistance values. Write all the formulas you used in Table 3.3.

Vdd(Transconductance)
Vin
1.5V 3V 4.5V

1.5V

3V

4.5V

Table 3.1 Tranconductance

Vdd(Output Resistance)
Vin
1.5V 3V 4.5V

1.5V

3V

4.5V

Table 3.2 MOS Output Resistance

Table 3.3 Formulas

4. Perform Step 3 with length and width values of (a) 5 um and 20 um respectively and (b) 10 um and 40 um
respectively. Complete Table 3.3 and Table 3.4 below.
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Vdd(Transconductance)
Vin
1.5V 3V 4.5V

1.5V

3V

4.5V

Table 3.4 MOS Tranconductance (a)

Vdd(Output Resistance)
Vin
1.5V 3V 4.5V

1.5V

3V

4.5V

Table 3.5 MOS Output Resistance (a)

Vdd(Transconductance)
Vin
1.5V 3V 4.5V

1.5V

3V

4.5V

Table 3.4 MOS Tranconductance (b)

Vdd(Output Resistance)
Vin
1.5V 3V 4.5V

1.5V

3V

4.5V

Table 3.5 MOS Output Resistance (b)

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II. Laboratory Procedure:

A. Threshold Voltage

1. Start Electric and create a new library for Lab1_<firstnameinitial><lastname>. Create a new cell NMOS{sch}
within this library and place a 4-terminal NMOS transistor with the following properties:

CMOS model CMOSmodels.txt

SPICE Model Name NMOS1
Length {L}
Width {W}

Length and width are set to variables L and W, respectively.

Make another cell NMOS_VTH{sch} and input the circuit with the configuration shown in the figure below with
the input at the gate exported as in.

Set L to 10um and W to 20um in the Spice netlist using .param by adding the following in the Spice code.

.param L=10u W=20u

2. Plot ID vs. VGS for a fix value of VDS =3V. Set up a DC analysis, sweeping VGS from 0 V to 5 V with 1mV increment.
Plot the square root of ID. To enter an expression, click

Plot Settings > Visible Traces

Hold down Alt and double click Id(Xxxxx-x@x). On the Expression editor window, type in the operand
sqrt(Id(Xxxxx-x@x)) to get the square root of current.
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Click OK. Plot this expression.

From this graph, approximate the value of threshold voltage using the process called linear extrapolation.

Vth Plot with Linear Extrapolation:

Determine the value of threshold voltage (VTH).

Answer:
560 mV

3. Change the Spice Model name from NMOS1 to N_1u. Repeat Step 2 to find the threshold voltage VTH. Use Vdd
of 5V.
Answer:
863 mV

4. Determine also the threshold voltage VTH of NMOS model N_50n with a fix Vdd value of 1V and sweeping Vin
from 0V to 1V.
Answer:
222 mV

B. Region of Operation

5. Create another schematic cell view with name NMOS_ROP and circuit configuration and parameters defined in
Step 1. With the following inputs on the NMOS_ROP{sch),

drain input (Vdd) : DC sweep (0V – 5V) Step: 1 mV

gate input (Vin) : Parametric sweep (0V – 5V) Step: 1 V
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simulate drain current (Id) vs. drain-to-source voltage (Vdd) for different values of gate-to-source voltage (Vin).
Also plot Vdd on a separate plot pane.

Have a screen shot of the waveform. Determine the different regions of operation.
Waveform showing different regions of operation of NMOS:

Question: How is the characteristics of each of the region based on the input-output transfer characteristic?

Answer:

From the plot, complete the table below with the values of drain current with each Vin and Vdd.
VDS
0V 1V 2V 3V 4V 5V
VGS
0V 0A 2.01 pA 4.01 pA 6.01 pA 8.01 pA 10.01 pA
1V 0A 38.29 µA 39.04 µA 39.79 µA 40.54 µA 41.29 µA
2V 0A 371.78 µA 418.11 µA 426.15 µA 434.19 µA 442.23 µA
3V 0A 767.29 µA 1.16 mA 1.22 mA 1.25 mA 1.27 mA
4V 0A 1.16 mA 1.97 mA 2.39 mA 2.48 mA 2.52 mA
5V 0A 1.56 mA 2.77 mA 3.63 mA 4.09 mA 4.20 mA
Table 2.1 NMOS Drain Current

Question: How is the drain current affected by Vin (VGS)? Vdd (VDS)?

Answer:

6. Change the width of the transistor to 20 um and the length to 5 um. Plot the ID vs. VDS curve for VGS from 0V to 5V
like in the previous configuration. Fill the table below with corresponding drain current.
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VDS
0V 1V 2V 3V 4V 5V
VGS
0V 0A 2.01 pA 4.01 pA 6.01 pA 8.01 pA 10.01 pA
1V 0A 78.17 µA 79.70 µA 81.23 µA 82.76 µA 84.30 µA
2V 0A 759.05 µA 853.63 µA 870.05 µA 886.46 µA 902.88 µA
3V 0A 1.57 mA 2.37 mA 2.50 mA 2.55 mA 2.59 mA
4V 0A 2.37 mA 4.02 mA 4.88 mA 5.06 mA 5.15 mA
5V 0A 3.18 mA 5.66 mA 7.40 mA 8.34 mA 8.58 mA
Table 2.2 NMOS Drain Current

Question: How is the drain current affected by length?

Answer:

7. Again, change the width of the transistor to 40 um and the length to 10 um. Plot the ID vs. VDS curve for VGS from
0V to 5 V like in the previous configuration. Get a screen shot and fill the table below with corresponding drain
current.
VDS
0V 1V 2V 3V 4V 5V
VGS
0V 0A 2.01 pA 4.01 pA 6.01 pA 8.01 pA 10.01 pA
1V 0A 76.57 µA 78.07 µA 79.57 µA 81.07 µA 82.58 µA
2V 0A 743.56 µA 836.21 µA 852.29 µA 868.37 µA 884.45 µA
3V 0A 1.53 mA 2.32 mA 2.45 mA 2.49 mA 2.54 mA
4V 0A 2.33 mA 3.94 mA 4.78 mA 4.96 mA 5.05 mA
5V 0A 3.12 mA 5.55mA 7.25 mA 8.17 mA 8.41 mA
Table 2.2 NMOS Drain Current

Question: How is the drain current affected by width?

Answer:

C. Transconductance

8. Create a new schematic cell view named NMOS_gm. Input circuit configuration in Step 1. Let us determine the
transconductance (gm) of the circuit using three different methods with VGS = VDS = 3V.

Method 1: DC Analysis

Plot the drain current of the NMOS circuit with Vdd fixed at 3V and a dc sweep in Vin from 0V to 5V with 1mV
step size. To find gm, get the slope of the curve at the operating point using the following formula:

To get gm at Vin = 3V, locate a Vgs1 from the graph equal to 3V – X, and get its corresponding current Id1. X is a
small value (say 10mV). Vgs2 is 3V + X with its corresponding Id2.
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Note that LTSpice has a build in tool that automatically calculates slope. Just place a Cursor 1 at Vgs1 and another
Cursor 2 at Vgs2.

Answer and Cursor calculation:

𝑽𝒈𝒔𝟏 = 3𝑉 − 𝑋 = 3𝑉 − 10𝑚𝑉 = 𝟐. 𝟗𝟗 𝑽
𝑰𝒅𝟏 = 𝟏. 𝟐𝟏𝟑𝟓𝟏𝟕𝟐 𝒎𝑨
𝑽𝒈𝒔𝟐 = 3𝑉 + 𝑋 = 3𝑉 + 10𝑚𝑉 = 𝟑. 𝟎𝟏 𝑽
𝑰𝒅𝟐 = 𝟏. 𝟐𝟑𝟑𝟓𝟕𝟓𝟏 𝒎𝑨
𝐼𝑑1 − 𝐼𝑑2 1.2135172𝑚𝐴 − 1.2335751𝑚𝐴
𝒈𝒎 = = = 𝟏. 𝟎𝟎𝟐𝟖𝟗𝟓𝒎𝑺
𝑉𝑔𝑠1 − 𝑉𝑔𝑠2 2.99𝑉 − 3.01𝑉

Method 2: DC Analysis

Plot the derivative of drain current of the NMOS circuit with Vdd fixed at 3V and a dc sweep in Vin from 0V to
5V with 1mV step size. For the derivative function, use d(). The values at the y-axis are the gm values and the
xaxis is the Vin. Get gm for Vin equals 3V.

Answer and plot:

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𝒈𝒎 = 𝟏. 𝟎𝟎𝟐𝟖𝟓𝟗𝟖 𝒎𝑺

Method 3: Operating Point

Simulate the circuit with Vin equals 3V and Vdd equals 3V. You do not have to sweep Vin so you should remove
.dc line from the Spice code. Add a .op line instead. Run the analysis. In LT Spice, click

View > SPICE Error Log

Look for the Gm variable.
Answer:
𝒈𝒎 = 𝟏. 𝟎𝟎 𝒎𝑺

9. Using any method in obtaining gm, complete the table below.

Vdd (Transconductance)
Vin
1.5V 3V 4.5V
1.5V 375.42 µS 386.35 µS 397.30 µS
3V 599.07 µS 1.00 mS 1.03 mS
4.5V 599.07 µS 1.23 mS 1.67 mS
Question: How is the transconductance affected by Vin (VGS)? Vdd (VDS)?
Answer:

10. Repeat Step 3 with length and width values of (a) 5 um and 20 um respectively and (b) 10 um and 40 um
respectively and complete the tables below.
Vdd (Transconductance)
Vin
1.5V 3V 4.5V
1.5V 766.49 µS 788.82 µS 811.14 µS
3V 1.22 mS 2.05 mS 2.11 mS
4.5V 1.22 mS 2.52 mS 3.40 mS
(a)
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Vdd (Transconductance)
Vin
1.5V 3V 4.5V
1.5V 750.85 µS 772.72 µS 794.59 µS
3V 1.20 mS 2.01 mS 2.06 mS
4.5V 1.20 mS 2.47 mS 3.33 mS
(b)

Question: How is transconductance affected by L? W?

Answer:

D. Output Resistance

11. Create another schematic cell view named NMOS_ro. Input circuit configuration in Step 1. Let us determine the
output resistance (ro) of the circuit using three different methods with VGS = VDS = 3V.

Method 1: DC Analysis

Plot the drain current of the NMOS circuit with Vin fixed at 3V and a dc sweep in Vdd from 0V to 5V with 1mV
step size. Remember that ro is the reciprocal of the output conductance gds. To find ro, get the inverse of slope
of the curve at the operating point using the following formula:

To get ro at Vin = 3V, locate a Vds1 from the graph equal to 3V – Y, and get its corresponding current Id1. Y is a
small value (say 10mV). Vds2 is 3V + Y with its corresponding Id2.

Note that LTSpice has a build in tool that automatically calculates slope. Just place a Cursor 1 at Vds1 and another
Cursor 2 at Vds2. Get the inverse of the slope.
Answer and Cursor calculation:
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𝑽𝒅𝒔𝟏 = 3𝑉 − 𝑌 = 3𝑉 − 10𝑚𝑉 = 𝟐. 𝟗𝟗 𝑽
𝑰𝒅𝟏 = 𝟏. 𝟐𝟐𝟑𝟐𝟗𝟒𝟔 𝒎𝑨
𝑽𝒅𝒔𝟐 = 3𝑉 + 𝑌 = 3𝑉 + 10𝑚𝑉 = 𝟑. 𝟎𝟏 𝑽
𝑰𝒅𝟐 = 𝟏. 𝟐𝟐𝟑𝟕𝟓𝟔𝟓 𝒎𝑨
−1
𝐼 −𝐼 1.2232946𝑚𝐴−1.2237565𝑚𝐴 −1
𝒓𝒐 = (𝑉 𝑑1 −𝑉𝑑2 ) =( 2.99𝑉−3.01𝑉
) = 𝟒𝟑. 𝟑𝟎𝒌𝛀 (using calculation)
𝑔𝑠1 𝑔𝑠2

𝒓𝒐 = 𝟒𝟑. 𝟑𝟏𝒌𝛀 (using graph)

Method 2: DC Analysis

Plot the inverse of derivative of drain current of the NMOS circuit with Vin fixed at 3V and a dc sweep in Vdd
from 0V to 5V with 1mV step size. For the derivative function, use d(). The values at the y-axis are the ro values
and the x-axis is the Vdd. Get ro for Vdd equals 3V.
Answer and plot:

𝒓𝒐 = 𝟒𝟑. 𝟐𝟕 𝒌𝛀

Method 3: Operating Point

Simulate the circuit with Vin equals 3V and Vdd equals 3V. You do not have to sweep Vdd so you should remove
.dc line from the Spice code. Add a .op line instead. Run the analysis. In LT Spice, click

View > SPICE Error Log

Look for the Gds variable. Get its inverse.

Answer:
𝒓𝒐 = 𝟒𝟑. 𝟐𝟗 𝒌𝛀

12. Using any method in obtaining ro, complete the table below.
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Vdd (Output Resistance)

Vin
1.5V 3V 4.5V
1.5V 291.80 kΩ 291.80 kΩ 291.80 kΩ
3V 2.53 kΩ 43.27 kΩ 43.27 kΩ
4.5V 0.99 kΩ 2.26 kΩ 16.61 kΩ

Question: How is the output resistance affected by Vin (VGS)? Vdd (VDS)?
Answer:

13. Repeat Step 3 with length and width values of (a) 5 um and 20 um respectively and (b) 10 um and 40 um
respectively and complete the tables below.
Vdd (Output Resistance)
Vin
1.5V 3V 4.5V
1.5V 143.17 kΩ 142.87 kΩ 142.87 kΩ
3V 1.24 kΩ 21.21 kΩ 21.21 kΩ
4.5V 0.48 kΩ 1.11 kΩ 8.13 kΩ
(a)
Vdd (Output Resistance)
Vin
1.5V 3V 4.5V
1.5V 145.90 kΩ 145.90 kΩ 145.90 kΩ
3V 1.27 kΩ 21.64 kΩ 21.64 kΩ
4.5V 0.49 kΩ 1.13 kΩ 8.31 kΩ
(b)

Question: How is output resistance affected by L? W?

Answer:

Save the library as Lab1_firstnameinitiallastname.jelib

Question: How would you compare the results of the simulation against hand calculation.
Answer:
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III. Design

A MOS should be properly biased such that it will have a desired intrinsic parameter value i.e. specific gm, ro
and/or Id. Length and width parameters can also be modified in order to achieve those parameters. This part
will focus on different techniques in targeting different MOS parameter values by varying and setting the other
parameters. The MOS model to be used is the N_50n.

1. Setting gate-to-source voltage Vgs

To set Vgs (Vin) for a target Id, gm or ro, use the characterization circuit below.

Set parameters L and W as 10um and 20um, respectively.

a. Say we want to find input voltage Vin for target Id of 25uA and Vds of 1V. Use DC analysis to plot Id versus
Vin. From the plot, locate Vin that will give Id of 25uA. If Vin is too high (Vgs > 1V), pick another combination
of L and W.

Answer:
557 mV

Verify Id using. op analysis. Determine Id.

Answer:
25.03 µA

b. This time, we want to have an NMOS with gm of 50uS for a Vds of 1V. Use DC analysis to plot gm versus Vin.
From the plot, locate Vin that will give a gm of 50uS. If Vin is too high, pick another combination of L and W.

Answer:
293 mV

Verify gm using. op analysis. Determine Gm.

Answer:
50.9 µA
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c. Now, target an ro of 250kΩ for a Vds of 1V. Use DC analysis to plot ro versus Vds (swept from 900mV to
1.1V with 1mV step size) for different values of Vin (0V to 1.5V with 100mV step size). Refine your sweep
to the two Vin values where your target ro of 250kΩ falls in between (make your step size smaller). If Vin
doesn’t fall within the swept Vin values, pick another L and W combination. From the plot, determine Vin
that will give ro of 250kΩ at Vds of 1V.

Answer:
990 mV

Verify ro using. op analysis. Determine 1/Gds.

Answer:
250 𝒌𝛀

2. For a target gm, ro or Id with fixed Vin and Vds, the same characterization circuit as Step 1 will be used. The
parameters that we can vary are L and W.

d. Target an Id of 25uA for Vds = Vin = 500mV. First, pick an initial L = 2um. L is chosen to be the smallest
possible length for the given technology. It is parameter W that will be swept in order to get the required
Id.

Vdd Vdd 0 DC 500m

Vin Vin 0 DC 500m
.param L=2u W=20u
.step param W 1u 20u 10n
.op
.include <path to CMOSmodels.txt>\CMOSmodels.txt

Sweep W from 1um to 20um with step size 10nm. Plot Id vs. W and determine W that corresponds to Id of 25uA.
If Id falls out of range, pick another L or increase the range of W.

Answer:
5.49 µm

Verify Id using .op analysis. Determine Id.

Answer:
25 µA

e. Target a gm of 500uS for Vds = Vin = 500mV. First, pick an initial L = 2um. L is chosen to be the smallest
possible length for the given technology. It is parameter W that will be swept in order to get the required
gm.

Vdd Vdd 0 DC 500m

Vin Vin 0 DC 500m
.param L=2u W=20u
.dc Vin 450m 550m 1m
.step param W 1u 20u 1u
.include <path to CMOSmodels.txt>\CMOSmodels.txt
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Use Method 2 in getting gm at Vin = 500mV. Here, W is swept from 1um to 20um with 1um step size. gm vs.
Vin plot will show several waveforms for different values W. Determine the two W values where gm of 500uS
falls in between. Refine the sweep between these two W values while making the step size smaller. Note that
the initial W which is 1um is colored green. Determine W. If gm falls out of range, pick another L or increase
the range of W.

Answer:

Verify gm using. op analysis. Determine Gm.

Answer:

Now, target an ro of 300kΩ for Vds = Vin = 500mV. First, pick an initial L = 2um. L is chosen to be the smallest
possible length for the given technology. It is parameter W that will be swept in order to get the required ro.

Vdd Vdd 0 DC 500m

Vin Vin 0 DC 500m
. param L=2u W=20u
. dc Vdd 450m 550m 1m
. step param W 1u 20u 1u
. include <path to CMOSmodels.txt>\CMOSmodels.txt
Use Method 2 in getting ro at Vin = 500mV. Here, W is swept from 1um to 20um with 1um step size. ro vs. Vin
plot will show several waveforms for different W. Determine the two W values where ro of 300kΩ falls in
between. Refine the sweep between these two W values while making the step size smaller. Note that the
initial W which is 1um is colored green. Determine W. If ro falls out of range, pick another L or increase the
range of W.

Answer:

Verify ro using. op analysis. Determine 1/Gds.

Answer:

3. For a target ro and a target Id, use the characterization circuit in Step 1. The MOS targets two intrinsic parameters
when Vds and Vgs are fixed values.

We want an NMOS transistor with Vds equals 450mV and Vgs equals to 400mV, Id of 10uA and gm of 500kΩ.
Take note that we have a tighter constraint that the only parameters we can vary are L and W.

First, select an initial value for L, pick the smallest possible value for the technology to optimize sizing, 2um.
Next, sweep the parameter W from 1um to 20um with 1um step size using the. step function as shown in the
Spice netlist below. Add. op analysis. Sweep Vin for transconductance plotting.

Vdd Vdd 0 DC 450m

Vin Vin 0 DC 400m
 17

.param L=2u W=20u

.step param W 1u 20u .1u
.dc Vdd 449m 451m .1m
.op
.include <path to CMOSmodels.txt>\CMOSmodels.txt

We have to plot Id vs ro. Plot Id and by default the waveform will show Id plotted with respect to Vin for
different W. We have to change what is plotted in the horizontal axis. Click on the x-axis and enter the equation
for ro.

The following plot of Id vs ro appears.

Each point in the plot represents a specific W (there are 191 W values based on the parametric sweep) and for
an L of 2um. Determine the point on the graph where Id is 10uA and take note of its ro. Determine whether ro
is larger or smaller than the target ro. To achieve the target ro, we will be varying the L of the device.
 18

If ro is lower than the target, pick a lower value of L. But in this case, L is chosen to be the smallest value for the
process technology so it is therefore impossible to to achieve the target. If it is higher, pick a larger L. Repeat
this process until you reach the target ro. Determine L.

Answer:

To get W, repeat plotting Id vs ro but this time make the step size of the W parametric sweep lower.

. step param W 1u 20u 1u

Determine the two W values that the target Id falls in between. Refine your sweep to these two values. Do this
until you reach the correct value of W. Determine W.

Answer:

Verify Id and ro using. op analysis. Determine Id and ro.

Answer:

4. Design a MOS circuit targeting the following properties. a.

Parameter Values
NMOS_VTG
Transistor Model
trans_models\models_nom\NMOS_VTG.inc
VDS 400mV
VGS 450mV
ID 50uA
ro 200kΩ
L
W

Verify Id and ro using. op analysis. Determine Id and ro.

Answer:

b.
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Parameter Values
PMOS_VTG
Transistor Model
trans_modelsmodels_nom\PMOS_VTG.inc
VDS -400mV
VGS -450mV
ID 50uA
ro 200kΩ
L
W

Verify Id and ro using .op analysis. Determine Id and ro.

Answer:

Observations and Conclusions:

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