PRAKASH V

Mobile: +91 9902158038

Email: prakashvishwanath29@gmail.com
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CAREER OBJECTIVE
To be associated with a semiconductor industry that provides me boundless growth
opportunities and exposure to cutting-edge technologies and learning possibilities.

EXPERIENCE

➢ 8 Months ( September 2017 to Current ) experience with Scope Integrated Systems

as ASIC Verification Engineer
➢ 3 Months June 2017 – August 2017) experience with Maven Silicon as Project
Intern

SUMMARY OF QUALIFICATIONS

➢ Good understanding of the ASIC and FPGA design flow.

➢ Extensive experience in writing RTL models in Verilog HDL and Test benchs in
System Verilog and UVM.
➢ Very good knowledge in verification methodologies.
➢ Experience in using industry standard EDA tools for the front-end design and
verification.

VLSI DOMAIN SKILLS

HDL : Verilog
HVL : SystemVerilog
Verification Methodologies : Coverage Driven Verification
: Assertion Based Verification - SVA
TB Methodology : UVM
Bus Protocol : AMBA AXI
Protocols : SPI,UART
EDA Tool : Questasim and ISE
Domain : ASIC/FPGA front-end Design and Verification
Knowledge : RTL Coding, FSM based design, Simulation,
Code Coverage, Functional Coverage, Synthesis,
Static Timing Analysis.
PROFESSIONAL QUALIFICATION

Maven Silicon Certified Advanced VLSI Design and Verification Course

from Maven Silicon VLSI Design and Training Center, Bengaluru
July 2016– Aug 2017

Bachelor of Engineering in Electronics and Communication

R R Institute of Technology, Bengaluru
Visvesvaraya Technological University (VTU), Belagavi, India
Cumulative Percentage : 59.27%
Year : 2016

Karnataka Pre University Education Board (PUC)

S Cadambi Independent PU College
Cumulative Percentage : 56%
Year : 2012

10th STANDARD (KSEEB)

Nandini Public School
Cumulative Percentage : 64.96%
Year : 2010

VLSI PROJECT

AXI UVC - AMBA AXI4 Protocol Verification

HVL: System Verilog

TB Methodology: UVM
EDA Tools: Questasim

Description: The AMBA AXI protocol is targeted at high-performance, high-frequency

system and includes a number of features that make it suitable for a high-speed submicron
interconnects.

AXI UVC is a configurable UVM based verification IP. It verifies the AXI protocol and
generates the required functional coverage

Responsibilities:
➢ Architected the class based verification environment in UVM
➢ Verified the protocol with single master single slave environment
➢ Verified the UVC by connecting maters and slave back to back
➢ Generated functional coverage for verification sign-off.
SPI Controller Core - Verification

HVL: SystemVerilog
TB Methodology: UVM
EDA Tools: Questasim

Description: The SPI IP core provides serial communication capabilities with external device
of variable length of transfer word. This core can be configured to connect with 32 slaves.

Responsibilities:
➢ Architected the class based verification environment in UVM
➢ Verified the RTL module using System Verilog
Generated functional and code coverage for the RTL verification sign-off.

UART- IP Core – Verification

HVL : System Verilog

TB Methodology: UVM
EDA Tools: Questasim

Description: The UART IP core provides serial communication capabilities, which allow
communication with modem or other external devices. UART will operate in three different
modes – Simplex mode, Full Duplex mode and loopback mode.

Responsibilities:
➢ Architected the class based verification environment in UVM
➢ Verified the RTL module using System Verilog
➢ Generated functional and code coverage for the RTL verification sign-off

ACADEMIC PROJECT

Aerodynamic Model Design and Flight Simulation Analysis during Auto-landing

using MATLAB.

OTHER ACCOLADES

"Aerodynamic Model Analysis and 6 DOF Flight simulation model and design using MATLAB",
Conference on Advancement in Science,Engineering and Technology (ASET),May 2016,
R R Institute of Technology, Bengaluru.
PERSONAL PROFILE

Name : PRAKASH V

Father’ s Name : VISHWANATHA REDDY N

Date of Birth : 12/04/1994

Blood Group : B+ve

Gender : Male

Merital Status : Single

Languages Known : Kannada, English, Hindi and Telugu

Hobbies : Playing cricket, Reading books, Listening music

Permanent Address : Hosahalli (V), Gokunte (P), Mulbagal (T), Kolar (D)
KARNATAKA

DECLARATION

I here by declare that the information given above is true to the best of my knowledge
and belief.

Date:

Place: PRAKASH V