Lecture Series 3

Flip-Flops
Sequential Logic

• The outputs of sequential logic circuits depend not only on the present state but also on the
past sequence of inputs.
• They must “remember” the past history of the inputs in order to produce the present output.
• Sequential logic circuits have feedback loops and/or timing delays.
• Flip-flops are the most commonly used memory devices in sequential networks.
• A flip-flop is a device that can assume one of two stable states.
• It has a pair of complementary outputs known as Q and Qbar.
• It has one or more inputs that can cause the output state to change.
• There are several types of flip-flops in common use, the most common being the S-R, the D-
type, the J-K and the T-type.

S-R Flip-Flop

• Two inputs known as Set (S) and Reset (R)

• Can be formed from cross-coupled NOR or NAND gates

• Often referred to as a latch.

• Usually has a front-end enabling circuit or ‘clock input’. Clocked device referred to as a flip-flop.

• Instead of the output changing immediately the inputs are changed the output changes when the next clock
pulse is applied.
• S-R flip-flops are available in chip form.
• Can be represented by a truth table and a Boolean equation
• Q+ is the value of Q after the clock pulse

R S Q Q+
0 0 0 0 No Change
1 1
0 1 0 1 Set to ‘1’
1 1 Q +=S +RQ
1 0 0 0 Reset to ‘0’
1 0
1 1 ? ? Forbidden

Digital Electronics 2 – Outline Lecture Notes 1

 ‘1’
D-Type Flip-Flop ‘0’
Level
sensitive
• D-Types are available as both flip-flops and latches.
• Latches are level sensitive.
• When the clock is high the data passes into the latch. When
the clock is low the data cannot enter the latch.
• Flip-flops are usually edge triggered, taking data into the
flip-flop on either the rising or falling edges of the clock pulse.
• The Q output after the clock is pulsed is equal to the D input Positive - Negative
before it is pulsed. edge triggered
• May be formed by adding a NOT gate to the input of an S-R flip-flop

D Q Q+
0 0 0 Q output
1 0 always
1 0 1 follows
1 1 D input

• Equation for D-type Q+ = D

• D-type flip-flop often fitted with two extra terminals S and R which SET (S) the output to ‘1’ or RESET (R)
the output to ‘0’ without the action of the clock.
• These terminals should not be confused with the S and R terminals on the S-R flip-flop.
• D-type Flip-flops and latches are available as ICs. The 7474 is a dual edge triggered flip-flop and the 7475
is a quad D-type latch.

J-K Flip-Flop

• J-K is the most versatile of all flip-flops.

• Can be formed by adding feedback loops to the S-R flip-flop.
• Usually has additional clock input.
• Positive and negative edge triggered available.
• Set (Pre-set) and Reset (Clear) terminals work independently of clock.

Digital Electronics 2 – Outline Lecture Notes 2

• The feedback loops remove the indeterminate state caused by both inputs being logic ‘1’
• When J =‘1’ and K =‘1’ the output toggles each time the clock is pulsed.
• Can be represented by a truth table and a Boolean equation.

J K Q Q+
0 0 0 0 No
0 0 1 1 Change Q + =J.K.Q +J. K.Q +J KQ +JK Q
0 1 0 0 RESET to
or
0 1 1 0 ‘0’
1 0 0 1 SET to Q + =Q .K +Q .J
1 0 1 1 ‘1’
1 1 0 1 Toggle
1 1 1 0

• Dual J-K flip-flops are available in both 14 and 16 pin packages. Quad J-K flip-flop ICs are also available.

T-Type or Trigger Flip-Flop

• Basic construction from R-S flip-flop shown below.

• Q output changes each time the T input is pulsed.

• More usual to be used with a clock input.

• When T= ‘1’ Q toggles each time the clock is pulsed.
• When T= ‘0’ Q is fixed in its current state.
• Can be represented by a truth table and a Boolean equation.

T Q Q+
0 0 0 No change Q +=TQ +T Q
0 1 1 No change or
1 0 1 Toggle Q +=T ⊕Q
1 1 0 Toggle

T-Type made from D-Type or J-K Flip-Flops.

Digital Electronics 2 – Outline Lecture Notes 3

• A T-type flip-flop can be made from a D-type by connecting the Qbar output to the D input.
• A T-type flip-flop can be made from a J-K by connecting both the J and K inputs to a logic ‘1’.

Digital Electronics 2 – Outline Lecture Notes 4

 Asynchronous Counters
• There are two types of counters, synchronous and asynchronous.
• Both can be constructed using flip-flops.
• In synchronous counters all the flip-flops are clocked at the same time using a common clock.
• In asynchronous counters the flip-flops are not all clocked at the same time.
• Asynchronous counters are slower than synchronous counters but easier to design.

Asynchronous Counters (Ripple Through Counters)

• Asynchronous or ‘ripple through’ counters can be constructed from T-Type flip-flops, or from J-K or D-
Type wired as T-Type.
• The count sequence ‘ripples through’ by connecting the Q output of the first flip-flop to the clock input of
the second flip-flop, and so on.

• Positive or negative edge triggered or master-slave flip-flops can be used to construct counters.
• The operation of the counters is such that the natural counting sequence is in binary.
• Additional circuitry has to be added to design counters to count in decimal or to any other base.
• Counter operation is based on the fact that the flip-flop halves the frequency of the pulse train passing
through it.

Negative
Edge

Clock Input

Q Output

• The Q output wave is twice the period and therefore half the frequency of the clock input.
• If you look at the truth table for a 4-bit binary counter, you will see that the frequency of 0s and 1s halves
each time you move one column to the left.
• Four flip-flops can therefore be used to construct a 4-bit binary counter.
• Notice that the counter counts up to 15, resets to zero and starts again.
• Two flip-flops will count 22 = 4 states i.e. 0 1 2 3; three flip-flops will count 23 = 8 states i.e. 0 1 2 3 4 5 6

Digital Electronics 2 – Outline Lecture Notes 5

 7; four 24 = 16 states i.e. 0 to 15 etc.
• Drawing the truth table as a timing diagram gives the following result.
Decimal 23 22 21 20
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
• The same timing diagram is produced by four negative edge triggered D-Type 11 1 0 1 1
flip-flops connected so that the Q output of the first flip-flop is the clock input 12 1 1 0 0
to the second, and so on. 13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
0 0 0 0 0

Frequency halves as you

move one column to the left.

• Positive edge
triggered flip-flops can be used, but in this case a NOT gate is used to invert the clock and the clock inputs
taken from the Qbar outputs.

• The circuit could have also been designed using J-K flip-flops wired as T-Types.
• The reset terminals are used to initially set the starting point to 0000.
• In order to convert this circuit to a decade counter, i.e. one that will count 0 to 9 and then reset, additional
logic has to be added.

Decade Counter (BCD Counter)

• A decade or binary coded decimal (BCD) counter can be made by stopping the count after 9 and resetting
the counter to zero.
• Nine must be displayed, but instead of ten (in binary) being displayed the counter must reset to zero; i.e. the
counter must zero on the tenth pulse.
• Examination of the truth table shows that the tenth pulse occurs when 1010 is displayed, i.e. Q3 =’1’ and Q1
= ‘1’
• Since the reset terminals are active low, a NAND gate connected between these Q outputs and the reset line
will make the counter reset after 9.

Digital Electronics 2 – Outline Lecture Notes 6

• The counter will try to display ten but the NAND gate will operate within a few nanoseconds and reset the
counter to zero.
• A slight glitch will appear on the waveform, but this should not affect display devices such as 7-segment
displays. It may, however, affect other electronic circuitry.
• Using this technique, counters to any base can be designed.

• To design a counter to count to any given base:

(i) Connect n flip-flops so that 2n is greater than the required base.
(ii) Connect AND (or NAND) gates between selected outputs to zero the counter once the
required base is reached.
• BCD counters can be connected together to form hundreds, tens and units counters.

Hundreds Tens Units Clock

Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0

Down Counters

• Ripple counters can be made that will count down rather than up.
• In the case of negatively triggered flip-flops the clock input is taken from the Qbar rather than Q outputs.
• In the case of positively triggered flip-flops the clock input is taken from the Q rather than Qbar outputs.

Reversible Counters

• Reversible counters will count up and down.

• Since the only difference between count up and count down counters is whether the clock is taken from the
Q or Qbar outputs, Logic gates can be inserted between counter stages to direct either the Q or Qbar outputs
to the next clock input.
• To count up, set the count control select line to logic ‘1’
• To count down, set the count control select line to logic ‘0’

Digital Electronics 2 – Outline Lecture Notes 7

• In each case use the Set and Reset terminals to set all the outputs to either ‘0’ for count up or ‘1’ for count
down.
Frequency Dividers

• We have seen how the frequency of a square wave is halved as it passes

through a flip-flop.
• A series of flip-flops can be used to divide down the frequency of a high
frequency wave to a much lower frequency.
• For example, a crystal can be obtained with a natural frequency of 32.768 kHz.
If this frequency is divided down fifteen times a frequency of exactly 1Hz is
obtained. This is very useful for designing clocks etc.

Counter ICs

• Several ICs are available to construct counters and frequency dividers.

• The 7490 is a decade counter which can also be configured to give a divide-by-ten square wave.
• The 7492 is a divide-by-twelve counter
• The 7493 is a 4-bit binary counter.

Digital Electronics 2 – Outline Lecture Notes 8

 Shift Registers
• Shift registers allow binary words to be stored, processed and moved from one part of the system to another.
• Registers are built up using a series of flip-flops connected in a line. Either D-type or J-K flip-flops can be
used.

Q0 Q1 Q2 Q3
Serial
Serial Output
Input D Q D Q D Q D Q

_ _ _ _
Q Q Q D
Q
A B C
Clock

Serial Input
A B C D Serial Output
Clock

Clock 0 1 2 3 4 5
Clock A B C D
0 0 0 0 0
Data
1 1 0 0 0
2 0 1 0 0
A
3 0 0 1 0
4 0 0 0 1
B
5 0 0 0 0
C

• The logic date pulse is moved one place to the right for each rising edge of the clock.
• A falling edge triggered flip-flop would move the date on the falling or trailing edge of the clock.
• The fifth clock pulse moves the logic ‘1’ out of the register.
• The above register is known as a serial-in, serial-out register.
• Parallel data inputs can be added to give it a more universal application.
• The Set (Pre-set) and Reset (Clear) connections can be used to load parallel data

• The procedure for loading the parallel input

is as follows:
• Clear the register using the reset terminals. The
register content is then 0000
• Enable the parallel inputs by applying a logic ‘1’.
The values of the parallel input values are then
transferred into the register.
• The set terminals are assumed in the diagram to be
active low.

Pseudo-Random Pattern Generators

Digital Electronics 2 – Outline Lecture Notes 9

• A pseudo-random pattern is a pattern of random numbers that repeat themselves over a known cycle length.
• These types of number pattern generators are often used to produce test patterns for testing digital circuits.

Chip Inputs Chip Outputs

Input
Test
Pattern Chip
under
Test
Reference
Chip

• In order to thoroughly test the chip, all possible combinations of input patterns should really be applied, a
method known as ‘exhaustive testing’.
• In practice this is impossible for complex devices, as the number of possible test patterns would run into
hundreds of millions.
• Random pattern testing is a cheap method of obtaining some degree of confidence that the chip is working
OK.
• The input test pattern is just a random pattern to try and pick up any possible faults in the chip.
• The test pattern has to be easy to generate, and in order to ensure that the same test pattern is applied to the
next chip on test, the pattern has to be repeatable.
• A shift register with feedback connections through an XOR gate can produce a series of patterns that appear
to be random, but which in fact are repeatable.
• This circuit arrangement is known as a linear feedback shift register or LFSR.
• The test patterns are applied to both the inputs of the chip or circuit on test and the reference (control) chip.
• If the chips are identical, the output patterns will be the same.
• If the chip on test is faulty, however, the difference between corresponding outputs on the two circuits will
be picked up by the XOR gate, which in turn feeds an Or gate.
• If a logic ‘1’ appears on the final OR gate the chip on test is faulty.
• Note that this test merely tells us that there is something wrong with the chip on test. It doesn’t say what is
wrong with it.

Qo Q1 Q2 Q3

A B C D

Clock

• Set all the Q outputs to ‘1’ using the SET terminals.

• Clock the register and note the Q outputs.
• We have four outputs and the maximum number of combinations of output values is 24 = 16.
• In practice, 0000 is a forbidden state and the maximum number of values obtainable is 15 i.e. (2n-1)

Digital Electronics 2 – Outline Lecture Notes 10

 Clock Q0 Q1 Q2 Q3 Clock Q0 Q1 Q2 Q3
0 1 1 1 1 9 0 1 0 0
1 0 1 1 1 10 0 0 1 0
2 1 0 1 1 11 0 0 0 1
3 0 1 0 1 12 1 0 0 0
4 1 0 1 0 13 1 1 0 0
5 1 1 0 1 14 1 1 1 0
6 0 1 1 0 15 1 1 1 1
7 0 0 1 1 16 0 1 1 1
8 1 0 0 1 17 1 0 1 1

• The Q outputs appear quite random and are not following any particular counting sequence.
• After 2n-1 patterns the pattern sequence repeats itself.
• The XOR of 0 and 0 is 0. If the start (or seed value) is 0000, the pattern would stay 0000 even when the
circuit was clocked.
• The seed value cannot therefore be 0000.
• Apart from 0000 any seed value can be used. The pattern length would remain the same.
• Not all tap-offs will give the maximal length. Other tap-offs will give a sub-set of the maximal length.

Digital Electronics 2 – Outline Lecture Notes 11

 Decoders, Encoders and Multiplexers
• Decoders convert an N-bit binary input into an M-bit binary output.
• The most commonly used decoder is probably the BCD to 7-segment display driver that converts a 4-bit
binary input into a 7-bit output.
• Often only one output is required to be selected from a range of outputs. Two inputs would allow one
output from four, three would allow one from eight.
• In general, n inputs will allow one from 2n outputs to be selected.
• The design procedure is the same as any combinational logic problem. E.g. the design of a 1-from-4
selector;
(i) four outputs, O1, O2, O3. O4 require two input lines A and B
(ii) construct the truth table and extract the Boolean expression.

B A O1 O2 O3 O4 O1 =A B
0 0 1 0 0 0 O2 =A B
0 1 0 1 0 0 O3 =AB
1 0 0 0 1 0 O4 =AB
1 1 0 0 0 1

• BCD to Decimal decoder will select one line from ten. For ten outputs four input select lines are required.
• This could be designed using logic gates as above.
• The 7442 IC is a single chip solution.

Encoders

• These are the opposite to decoders.

• An encoder has a number of input lines, only one of which is activated at a given time, and produces an n-
bit output code, depending on which input is activated.
• E.g. a four to two line encoder produces a unique 2-bit output code when any one of four inputs is activated.

I1 I2 I3 I4 B A
1 A = 0 I1.I02. I3.I40 + 0
I1.I2.I3.I04
0 B= 1 I1.I20.I3.I40 + I1.I2.I3.I14
0
0 0 1 0 1 0
Digital Electronics
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1 1 12
• A logic diagram can be constructed from the Boolean equations.

Multiplexers

• These have several data inputs, but allow only one of them at a time to be connected to the output.
• The ‘select’ inputs determine which input is routed through to the output.
• Two select lines can select up to four inputs; three select lines can select up to eight inputs.
• In general n select inputs can select up to 2n inputs.
I1

• E.G. two input multiplexer; requires one select line S

• S = 0, I1 is selected; S = ‘1’, I2 is selected. Output

S I2 I1 Out
0 0 0 0
I
0 0 1 1 n
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0 Select Lines
1 1 0 1
1 1 1 1

Out =S.I 1.I2 +S.I 1.I 2 +S. I1.I 2 +S.I 1. I2

=S.I 1 +S.I 2

Digital Electronics 2 – Outline Lecture Notes 13