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SP605 Hardware Setup Guide
• Submit cases and report bugs online 24 hours a day through WebCase
• Initiate and manage return of hardware and software products through the RMA Portal This Hardware Setup Guide will provide the step by step setup instructions to run the diagnostic demo design that is pre-
installed on the FLASH of the SP605 Evaluation Board.
For more information about this kit, please refer to the Getting Started Guide also included in the kit box. The Getting Started
Guide provides further instructions on running demos, installing software, and using the available reference designs to quickly
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and efficiently develop your applications.
For additional details, please visit the product page for more details: http://www.xilinx.com/sp605 FPGA: XC6SLX45T SMA CLK
FGG484 Spartan-6 SFP (Differential) Status LEDs
FMC-LPC GTP RefCLK
Connector DDR3 SMA System ACE CF
IIC EEPROM
(reverse side)
© Copyright 2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. All other trademarks are the property of their respective owners. Printed in the U.S.A. Xilinx Part Number: 0402790-01/ PN 2426
hardware setup guide sp605 evaluation kit hardware setup guide sp605 evaluation kit
Setting the Default Jumpers Connecting Cables and CF Card Setting Ethernet Link Select an Image
Header J46 and J44 should have Jumpers installed, J22 should have a Jumper on 1,2 and Install the CF card that is included in the kit. Connect the Ethernet cable to your PC and the In the Base Reference Design GUI Application select the menu item Setup, then select a On the USB FLASH there are images to select. Select the image fractal1.jpg in directory
J19 should have a Jumper on 1,2. The following headers should not have any Jumpers SP605 board. Connect the DVI port to a monitor (DVI2VGA adaptor included), Plug in the network. You will see the GUI indicate “Connected to FPGA” and you will see the Ethernet SP601_BRD_Reference_Design --> SP601_BRD_Images. Then “Click” the “show Display”
installed: J45, J47, J9, J58, J9, J13, J10, J60, J49, and J48. power Adaptor to the local AC power. Plug the 12 volt power jack into the board connector on Status lights active on the SP605. GUI button. If you have connected a DVI or VGA monitor, you will also see this image displayed
J18. Turn on the power by switching the SW1 to the “ON” position. on the monitor.
The Base Reference Design includes an application GUI that must be installed before you will As you select different filter effects, you will see that the image is filtered using these different
be able to run the demo. On the USB FLASH drive, included with the kit, you will find a directory transform effects. You will notice that the 5x5 Filter coefficient table changes every time you
called SP605_BRD_Reference_Design.--> SP605_BRD _Application directory. In there you change an effect.
will find an install image, BaseRefDI_Setup2_0_4.msi. This is an application GUI that is used to
display the graphical information for the Base Reference Design. Please double click on this Using the DSPmode selection, you may choose between “Logic” and “DSP48A.” The “DSP48A”
application to install the software. option will utilize the DPS blocks in the Spartan-6 FPGA. The “Logic” selection will re-load a
new design that only uses FPGA logic resources.
To demonstrate the performance these blocks provide, notice the Processing Time for the DSP
implementation is around 10.66 mS. When you select “Logic” you will see the FPGA Program
and Done LED flash, indicating an FPGA reconfiguration. You will also see that the Ethernet link
will disconnect and then reconnect. You will see that the “Logic” version of the design processes
the image at about 5X slower than the DPS implementation, running at about 53.3 mS.
The Base Reference Design is located in slot 3 of the CF card. The SystemACE (S1) DIP The default filtering in Step 8 was “Identity”, now use the “Effect” menu to select “Edge Detect.”
Switch is set to “1101” where 1, 2, and 4 are set to the “ON” position and switch 3 is set to the Select other Effects. For more options please see the SP605 Getting Started Guide.
“OFF” position. The Configuration Mode (DIP Switch SW1) can be set with both M0 and M1 in
the “OFF” position.
Step 5i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i Step 6i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i
Starting the Base Reference Design GUI Application Load with Base Reference Design Demo
To start the application GUI, please go to your Windows START menu and select Verify the SystemACE (S1) DIP Switch is set to “1101” where 1, 2, and 4 are set to the “ON”
All Programs --> XILINX --> Base Reference Design --> Base Reference position and switch 3 is set to the “OFF” position. Then press the SYSACE Reset switch (SW9)
Design Interface. to make sure the FPGA loads from the CF card slot 3.