THE CMOS INVERTER

Jayson C. Loreto
Department of Electronics Engineering
INTRODUCTION

An inverter circuit outputs a voltage representing the opposite logic-level to its input. Its main
function is to invert the input signal applied. If the applied input is low then the output becomes high
and vice versa. Inverters can be constructed using a single NMOS transistor or a single PMOS transistor
coupled with a resistor. Since this 'resistive-drain' approach uses only a single type of transistor, it can
be fabricated at low cost. However, because current flows through the resistor in one of the two
states, the resistive-drain configuration is disadvantaged for power consumption and processing
speed.

CMOS INVERTER: DC ANALYSIS

Studying the dc value of a signal in static conditions. By doing so, the parameters of the
components, the PMOS and NMOS, can be identified. This can be done by plotting Vout as a function
of Vin known as voltage transfer characteristics.

INVERTER VOLTAGE TRANSFER CHARACTERISTICS

Output High Voltage, VOH

 maximum output voltage

 occurs when input is low (Vin = 0V)
 PMOS is ON, NMOS is OFF
 PMOS pulls Vout to VDD
 VOH = VDD

Output Low Voltage, VOL

 minimum output voltage

 occurs when input is high (Vin = VDD)
 pMOS is OFF, nMOS is ON
 nMOS pulls Vout to Ground
 VOL = 0 V
SIMULATION

The most critical part in designing a CMOS inverter is to identify the sizes of the transistors.
Below are the following steps:

1. Use a suitable design for CMOS inverter.

2. Set the length of the transistor to minimum. Logic levels are not dependent upon the
relative sizes of the device.
LENGTH
60 nm

3. Sweep the PMOS to get the proper W/L ratio of the design.

WIDTH LENGTH
480 nm 60nm
4. Simulate the design using the sizes obtained.
5. Identify the value of Cload.

The typical value of fanout is 3 times the input capacitance of an inverter.

Cload  3x  Cgtotal 
Cload  3  0.2646 fF  .23046 fF 
Cload  1.48519 fF
Cload = 2fF
6. Simulate using the calculated Cload.
7. Fine tune the design by adjusting the width to a certain level.

Width 210
Length 60
Rise time 34.6
Fall time 36.9

Width 220
Length 60
Rise time 34.6
Fall time 35.3

Width 230
Length 60
Rise time 34.5
Fall time 34.6

LENGTH WIDTH RISE TIME FALL TIME

60 200 34.7 36.9
60 210 34.6 36.1
60 220 34.6 35.3
60 230 34.5 34.6
 The designer used w = 220 nm having rise time = 34.6 ps and rise time = 35.3 ps. Notice that
the w = 230 has almost equal rise time and fall time but the values are not consistent for the
other pulse signals. Thus, the third value of the width is more preferable.

NOISE MARGIN

VNM H  VOH  VIH  VDD  VIH  1.2  0.0485  1.1515 V

VNM L  VIL  VOL  VIL  1.15 V
POWER CONSUMPTION

Power  CoutVDD 2 f
Cout  CDN  CDP  CL
 Cout  CDN  CDP  CL
Cout  0.1902 fF  .4077 fF  2 fF
Cout = 2.5979fF
Power  CoutVDD 2 f
Power   2.5979 f  x 1.2   25 GHz 
2

Power = 93.52 nW

DUTY CYCLE

Duty cycle is defined as ratio between on time and total time.

PROPAGATION DELAY

tp 
1
2
 t pf  t pr 
22.7 p  24.7 p
tp 
2
tp = 23.7p

OVERSHOOT AND UNDERSHOOT

Overshoot/undershoot is the occurrence of a signal or function exceeding its target.
SUMMARY

PARAMETER VALUE
RISE TIME 34.6 ps
FALL TIME 35.3 ps
DELAY 23.7 p
DUTY CYCLE 50.1 %
UNDERSHOOT/OVERSHOOT 121 m
POWER CONSUMPTION 93.52 nW

CONCLUSION

Inverter is the fundamental block in digital design. Its operation should be understood
carefully to simplify designs when dealing with complicated digital architectures. The length and
width of NMOS and PMOS should be designed well enough for it will dictate the values of the
important parameters such as rise time and fall time. Rise and fall time should be equal if possible
for a more efficient CMOS inverter device.