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A low-power adaptive bandwidth PLL and clock buffer with supply-noise

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Article  in  IEEE Journal of Solid-State Circuits · December 2003

DOI: 10.1109/JSSC.2003.818300 · Source: IEEE Xplore

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1804
A Low-Power Adaptive Bandwidth PLL and Clock
Buffer With Supply-Noise Compensation
Mozhgan Mansuri, Student Member, IEEE, and Chih-Kong Ken Yang, Member, IEEE
Abstract—This paper describes a fully integrated low-jitter
CMOS phase-locked loop and clock buffer for low-power digital
systems with a wide range of operating frequencies. The design
uses static CMOS inverters as a building block of the voltage-con-
trolled oscillator and clock buffering. To reduce supply-induced
jitter, programmable circuits with opposite sensitivity compensate
0 1% delay 1%
for the delay variations. Both elements have supply-induced delay
sensitivity of DD . The design is
fabricated in 0.25- m CMOS technology and consumes 10 mW
from a 2.5-V supply. The experimental results verify that the
proposed methods significantly improve the jitter.
Index Terms—Adaptive bandwidth PLL, low-power analog cir-
cuits, phase-locked loops (PLLs), self-biased PLL, timing jitter.
I. INTRODUCTION
P HASE-LOCKED LOOPS (PLLs) are widely used in
high-performance digital systems. PLLs multiply low-fre-
quency reference clocks to produce low-jitter high-frequency
clocks that drive large capacitive loads. For many applications,
clock jitter and power dissipation are two important design
criteria. Switching activity in large digital systems introduces
power-supply or substrate noise which perturb the more
sensitive blocks in a PLL. In particular, any noise injected
onto the voltage-controlled oscillator (VCO) elements and the
clock buffers is the dominant source of jitter in these systems.
Power dissipated by PLLs is often a small fraction of the
total active power. However, during sleep modes where the
PLLs must remain in lock, it can be a significant fraction of
the power dissipated. This paper describes designs for both a
PLL and a clock buffer that reduce sensitivity to supply noise
for low-power applications. The PLL operates over a wide
frequency range to accommodate testability and further system
power optimization [1].
Two common strategies improve supply-noise rejection. The
first strategy is to filter the supply voltage using either a passive
or active filter [2]–[5]. The second strategy is to improve the
supply sensitivity of the buffer elements. Differential delay
elements for a VCO have been favored because they reject
common-mode noise [6], [7]. Both methods are often jointly
used for higher performance. Section II describes the proposed
design of the PLL with a new filtering strategy. The design
focuses on improving the power performance while achieving
Manuscript received March 28, 2003; revised June 25, 2003. This work
was supported by UCMicro, Intel Corporation, and National Semiconductor
Corporation.
The authors are with the Department of Electrical Engineering,
University of California, Los Angeles, CA 90095-1594 USA (e-mail:
mozhgan@icsl.ucla.edu; yang@ee.ucla.edu).
Digital Object Identifier 10.1109/JSSC.2003.818300
0018-9200/03$17.00 © 2003 IEEE
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 11, NOVEMBER 2003
both high static and dynamic supply-noise rejection. Clock
buffers with improved delay sensitivity to supply noise using
the second strategy are described in Section III. The design
goal is to compensate the supply-induced delay variation with
an improved dynamic behavior while introducing the minimum
power, area, and delay overhead. The performance of both
circuits is verified in Section IV with measured results.
II. PLL DESIGN
Fig. 1 illustrates the block diagram of the PLL. A three-state
phase-frequency detector (PFD) is followed by a charge pump
filter which produces the VCO control voltage. The VCO
is composed of a voltage-to-current ( – ) converter, a cur-
rent-controlled oscillator (CCO), and a noise-canceling circuit.
The output signal of the VCO passes through a low-to-full
swing (L-F) amplifier and feeds back to the PFD through
a frequency divider. Finally, the generated on-chip clock is
distributed through a clock buffering network to the rest of the
chip.
A. VCO Design
The four VCO design goals are:
1) wide operating frequency range;
2) linear gain for the entire range of the control voltage ;
3) high static and dynamic power-supply noise rejection
ratio (PSRR);
4) low power and low area.
Fig. 2 shows the proposed VCO design. To achieve a wide op-
erating frequency range, the design uses a CMOS inverter-ring
oscillator with controllable supply. Fig. 3 shows the CCO circuit
composing of four stages of pseudo-differential inverters [8].
The design employs negative-skew delay elements to enable the
VCO to run faster at a given . The CCO produces quadra-
ture clock phases, making the design suitable for applications
such as clock/data recovery circuits and multiphase systems.
The – converter circuit, transistors , – , converts
the control voltage to current that drives the CCO and con-
trols the frequency of CCO output signal. To maintain linear
VCO conversion gain , – are designed with large
widths for minimum overdrive voltage. The minimum overdrive
voltage of pMOS transistors guarantees the linear due to
the fact that stays in saturation for almost the entire range of
control voltage VCO ( ), where is the
threshold voltage of . However, at a that is near ,
enters triode region which reduces the conversion gain and
saturates . To compensate for the gain drop at high ,
the circuit uses a source follower transistor . The source
MANSURI AND YANG: LOW-POWER ADAPTIVE BANDWIDTH PLL AND CLOCK BUFFER 1805

Fig. 1. PLL architecture.

Fig. 2. VCO with noise-canceling circuit.

Fig. 3. Quadrature pseudo-differential CCO circuit.

follower is OFF for and gradually turns to both ground and . The gain linearity improvement tech-
ON at high , which injects current and compensates for nique proposed in this paper resolves the problem by coupling
the drop. only to the ground reference.
Fig. 4 shows the simulated – converter gain characteris- Further supply rejection is achieved by capacitively cou-
tics for different process corners. The proposed – converter pling to ground. The capacitor and output resistor
achieves linear gain that varies only by a factor of less than at forms the third pole of the PLL and filters
1.5 for almost the entire range of the control voltage the high-frequency noise. The cascode current source that
. For instance, the varies between 1.15 supplies uses a feedback circuit ( and ) to
and 1.7 GHz/V at a typical corner for . boost the output impedance [10]. The resulting supply sensi-
The slight variation of modestly impacts the loop dy- tivity is % VCO frequency % because the finite
namics. If low- devices were available in the process tech- output resistance of causes to vary with supply.
nology, using one for the follower would further improve the An auxiliary noise-canceling circuit ( , , and )
gain linearity at high VCO frequencies. The – converter in is added to compensate the residual variation of the output
[9] achieves a linear gain for the entire range of current due to supply noise. This circuit generates a
, slightly larger than the range of this proposed compensator current by mirroring a fraction of .
– converter. However, the – converter in [9] suffers from is then subtracted from . The current to the CCO is
high power-supply noise sensitivity due to the coupling of for . The ideal
1806 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 11, NOVEMBER 2003

5 ns (curves (3) and (4)) improves the dynamic PSRR of the

– converter with noise-canceling circuit to 8 and 12 dB,
respectively. Also, the bandwidth of the feedback cascode
current source of this design is sufficiently high to correct the
high-frequency supply-induced noise in . This bandwidth
is larger than 20 the loop bandwidth of the PLL. For dc supply
noise, the PSRR is improved by more than 15 dB. Equivalently,
the supply sensitivity of VCO frequency is improved from
% (for the – converter without the
noise-canceling circuit) to % (for
the – converter with noise-canceling circuit).
Table I compares the performance of the proposed VCO
with prior state-of-the-art designs. The first two designs, by
Fig. 4. Simulated V –I converter gain characteristic across the process corners. Sidiropoulos [2] and Ingino [3], are examples of the regulated
VCOs, whereas the designs by Kaenel [5] and Ahn [10] are
examples of – converters with cascode current sources.
The design by Maneatis [7] is an example of the differential
VCO, and finally, the design by Minami [9] is an example of
a – converter with linear gain for the entire range of the
VCO control voltage. For a fair comparison, all designs are
normalized to 0.25- m technology with 2.5-V supply by the
use of scaling equations for the short-channel and long-channel
devices. The proposed design achieves the lowest power and
area among all designs while achieving noise rejection perfor-
mance comparable with the regulated VCO proposed in [2].
The regulated VCO proposed by Ingino achieves an excellent
dynamic noise rejection of 0.007%/1% by coupling the
to ground with a large capacitor of 1.2 nF with higher power
Fig. 5. V response of V –I converter (with the feedback cascode) to
consumption. While the area and noise rejection performance
0 10%-V step inserted at t = 2 ns. of the proposed PLL is comparable with [2], it consumes 43%
less power than the design in [2]. With a comparable power
supply-noise cancellation occurs when variation is equal consumption, the proposed PLL achieves better dynamic noise
to variation due to noise, i.e. . rejection than the VCO in [5].
In other words, when there is no supply-induced variation in At very high frequencies, enters triode region, which
, . The noise-canceling circuit is designed increases beyond the available . Therefore, the
to have a much worse supply sensitivity than the feedback supply sensitivity of the VCO degrades at high control volt-
cascode circuit that generates . The noise-canceling circuit ages similar to regulated VCOs and differential VCOs. At very
uses a single device without the feedback cascode and with low control voltages, the supply sensitivity also degrades due
minimum channel length. The simulation result shows that to greater susceptibility of the CCO to noise. While the VCO
is four times more sensitive to variation than , has an operating range of 200–2300 MHz, the simulation re-
i.e., . By setting the ratio sults indicate that the VCO achieves the supply-noise rejec-
of the mirroring to the ratio of the supply sensitivity of tion of over a smaller range of
the currents , will be equal to .1 400–2000 MHz in the typical corner.
The power penalty to source the same for a given is B. PFD and Loop Filter
40%. The proposed VCO consumes 2 mW at 1 GHz.
To verify the noise performance of the proposed – The design uses a three-state PFD based on dynamic two-
converter, the dynamic response of to supply noise is phase master–slave pass-transistor flip-flop proposed in [11].
simulated. The curves (1) and (2) shown in Fig. 5 demonstrate The loop filter, shown in Fig. 6, is composed of a charge pump
the response for the – converter (with the feedback circuit, a loop-stabilizing zero, and a third pole. The design
cascode) without and with the noise-canceling circuit, when a is similar to [2], [7], and [10] in that the loop characteristics
10%- step with 100-ps slew rate inserted at ns. track the VCO operating frequency such that the loop bandwidth
Adding the noise-canceling circuit to the – converter scales with operating frequency in a constant phase margin.
improves the PSRR by 6 dB for very high-frequency noise. The charge pump uses a similar structure as [2] where it is
Increasing the slew rate of the step from 100 ps to 1 and self-biased with the VCO control voltage. Therefore, the charge
pump current scales with the PLL operating frequency. The se-
1Adjusting = alleviates any output impedance variation over the process
ries of a resistor and a capacitor forms the loop-stabilizing zero.
corners. The simulation results indicate that the proposed VCO maintains its
noise-rejection performance at the process corners by adjusting the value of The design implements the resistor and capacitor with a MOS

=, 3=16 = 1=4.  channel resistance [13] and a MOS capacitor, respectively, as
MANSURI AND YANG: LOW-POWER ADAPTIVE BANDWIDTH PLL AND CLOCK BUFFER
TABLE I
PERFORMANCE COMPARISON OF THE PROPOSED PLL WITH PRIOR STATE-OF-THE-ART DESIGNS
Fig. 6. Loop filter architecture.
Fig. 7. Loop-stabilizing zero with a 4-bit controller (n = 4).
shown in Fig. 7. The MOS resistor is biased by the VCO con-
trol voltage so that the loop zero scales with the PLL’s operating
frequency. The proposed circuit achieves the scalable zero with
a modest improvement in power and area upon the previous de-
signs ([2] and [7]) that use an additional charge pump to inject
current in a feedforward path. Digital-to-analog converters ad-
just the charge pump current and MOS resistor to allow further
loop-parameter adjustments to optimize jitter at the output clock
1807
[12]. The area overhead due to a 3-bit controller for the charge
pump current and a 4-bit controller for the loop filter resistor
is negligible in comparison with the overall charge pump area
and loop filter capacitor. The tunability of the MOS resistor also
provides an additional tuning to adjust the zero position for any
process variation of the MOS capacitor.
The switching activity of the PFD produces ripple on the
VCO control voltage at the same rate as the reference clock fre-
quency. The ripple modulates the VCO frequency, resulting in
jitter at the output clock. This effect worsens with higher fre-
quency multiplication by the loop. The loop’s third pole (formed
at the CCO input) filters out the ripple. The third pole also tracks
the PLL operating frequency because the output resistor
scales with the oscillator’s frequency. With all primary loop pa-
rameters adapting to the oscillator frequency, the loop operates
with a wide frequency range with a constant phase margin.
III. CLOCK BUFFER DESIGN
One of the challenges in digital systems is the distribution
of the generated on-chip clock with a small uncertainty. Static
CMOS inverters are traditionally used for clock buffering due to
their simplicity and drive capability with low power consump-
tion. However, CMOS inverters have poor supply-induced delay
sensitivity of approximately . With long
chains, this poor supply-noise rejection of the inverter could
result in significant jitter. This paper introduces a compensator
circuit added to the inverter that offsets any supply-induced delay
variation. This circuit technique supplements other methods of
1808
(a)
(b)
Fig. 8. (a) Ideal compensation of supply-induced inverter delay variation.
(b) Proposed compensated inverter.
reducing supply noise such as supply-voltage regulation and
filtering.
Ideally, the task of the noise compensator circuit is to intro-
duce an inverse and equal delay sensitivity to the supply noise
as an inverter [Fig. 8(a)]. This noise compensation can be ac-
complished by using a variable capacitor at the output of each
inverter such that as drops, the capacitor value decreases to
compensate for inverter delay increase and vice versa. A simple
circuit capable of the delay compensation is a MOS resistor in
series with a capacitor. Fig. 8(b) shows the clock buffer with the
compensator circuit, where the capacitor and resistor are imple-
mented by pMOS transistors.2 The gate voltage of the pMOS re-
sistor is set to a constant voltage with respect to ground. As
drops, the source-gate voltage of the pMOS resistor
is decreased, increasing the resistance . Thus, the capacitor
appears as a lower capacitive loading, which compensates for
the increase in the inverter’s resistance.
One of the main advantages of this compensation technique
is the circuit’s excellent dynamic behavior due to a very small
time constant of the compensator circuit. The compensated in-
verter can have a high PSRR for both low and high supply-noise
frequencies. Also, for most applications, the supply noise does
not exceed 15% of supply voltage. Thus, the extra capacitive
loading introduced by the compensator circuit would be within
10%–15% of the inverter’s load and does not change the fanout
of the inverter significantly. Due to the small loading effect, the
delay and power overhead added by the compensator circuit are
a small fraction of the inverter’s total delay and power.
2If the pMOS resistor and capacitor are switched in the compensator circuit,
the circuit is similar to delay elements commonly used for variable-delay lines
[14]. However, this configuration is undesirable for the noise compensation be-
cause the V is decoupled from V by the pMOS capacitor, whereas the V
in Fig. 8(b) experiences the V noise directly.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 11, NOVEMBER 2003
Fig. 9. (a) Delay variation of the compensated inverter due to V variation.
(b) Delay sensitivity of the compensator circuit, normalized to delay sensitivity
of an inverter.
To achieve the high PSRR in the compensated inverter, the
compensator circuit should provide an inverse and equal delay
variation (from noise) as the delay variation of an uncom-
pensated inverter. While the delay variation of an inverter is
roughly proportional to , the delay variation of the com-
pensator circuit varies nonlinearly with . Fig. 9(a) shows the
nonlinear behavior of the delay variation of the compensator cir-
cuit as a function of . For minimum power, delay, and area
overhead, the compensator circuit should be used over the range
where it achieves the maximum delay sensitivity
. The maximum delay sensitivity
occurs over the range where the resistance of the pMOS
device is the most sensitive to the variation. in
Fig. 9(a) indicates the middle of the region with maximum delay
sensitivity. Therefore, should be set to
. The delay variation of the inverter is well compensated
over the range of where the delay
sensitivity of the compensator circuit approximates the delay
sensitivity of the inverter. For noise exceeding this range,
the delay compensation performance of the compensator circuit
degrades. Fig. 9(b) shows the desired delay sensitivity of the
compensator circuit (normalized to the supply-induced delay
sensitivity of the uncompensated inverter) for a proper delay
compensation. The voltage range where the normalized sensi-
tivity curve crosses “1” is when the compensator circuit com-
pensates for the delay variation of the uncompensated inverter
due to noise. The delay sensitivity and the compensating
range of the compensator circuit are adjusted through sizing the
devices in the compensator circuit.
Fig. 10 illustrates the behavior of the delay sensitivity of the
compensator circuit (normalized to the delay sensitivity of the
uncompensated inverter) as the pMOS resistor and capacitor
vary. Fig. 10(a) shows the delay sensitivity behavior as a func-
tion of the capacitor while keeping the width of pMOS resistor
constant. Using a larger compensating capacitor as a fraction
of the total capacitive load of the inverter increases the delay
variation and, hence, the delay sensitivity of the compensator
circuit. However, increasing the capacitor reduces the compen-
sating range. Fig. 10(b) shows similar curves, varying the pMOS
MANSURI AND YANG: LOW-POWER ADAPTIVE BANDWIDTH PLL AND CLOCK BUFFER 1809

Fig. 12. Bias circuit generating V .

Fig. 10. Behavior of normalized delay sensitivity of compensator circuit due to

V (V ) variation as a function of: (a) pMOS capacitor; (b) pMOS resistor.

Fig. 13. Sensitivity of supply-induced delay variation of compensated inverter

due to V offset.

Fig. 11. Supply-induced delay variation of: (1) uncompensated inverter;

alternate metric is defined as the maximum percentage delay
(2) compensated inverter with inverter’s V held constant; (3) compensated variation from its nominal value
inverter. within the noise range . The
maximum delay variation for curve (3) is 1.2% within 10%
resistor value in a constant capacitor value. Decreasing the re- noise.
sistor value increases the delay sensitivity by introducing larger The previous discussion of the delay compensation indicates
capacitive loading to the inverter while reducing the compen- that the bias circuit for must be constant with respect
sating range. By proper adjustment of the resistor and capacitor, to ground. Also, the optimum biasing point for the
both the maximum normalized delay sensitivity and the com- (the middle of the voltage range with the maximum delay
pensating range can be set to “1” and peak-to-peak supply noise, sensitivity) varies across process corners as pMOS devices
respectively. Curve (2) in Fig. 10(a) or (b) is an example of the become faster or slower. To maintain the high PSRR across the
proper sizing that roughly results in the same delay sensitivity corners, the biasing circuit for should track the variation
as an inverter within the operating range of 10% noise. of the pMOS threshold such that is set to the middle of
Fig. 11 illustrates the simulated delay compensation charac- the compensating range. Therefore, the desired should
teristics of the compensated inverter (with and values of be composed of a voltage that is independent of supply and
curve (2) in Fig. 10) when varies by 10%. Curve (1) il- process, voltage, and temperature (PVT) (a bandgap reference)
lustrates the supply-induced delay variation of the compensated and a voltage that depends on the pMOS threshold voltage.
inverter while keeping of the compensator circuit constant. Fig. 12 shows a realization of the bias circuit. A diode-con-
This curve represents the delay variation of an uncompensated nected pMOS transistor is biased with a small current such that
inverter. Curve (2) illustrates the supply-induced delay variation . To generate , the is subtracted from
while keeping of the inverter constant. This curve repre- an amplified bandgap voltage.
sents the delay variation solely due to the compensator circuit. The generated bias is distributed to all the clock buffers.
Curve (3) shows the overall delay variation of the compensated Due to the coupling noise into , there is uncertainty in the
inverter to noise. Curve (3) is effectively an average of the voltage from buffer to buffer. The deviation of from
first two curves. The overall delay sensitivity of the compen- the middle of the compensating range decreases the effective
sated inverter is approximately for compensating range. Fig. 13 shows the simulated delay vari-
variation of 10%. ation of the compensated inverter for the optimum , and
Although the delay sensitivity metric has been traditionally 100-mV deviation from the optimum . The maximum
used to illustrate the circuit noise performance, the overall delay delay variation increases from 1.2% (within 10% noise)
variation of curve (3) in Fig. 11 suggests another useful metric. at the optimum to 2% and 2.7% at 50 and 100 mV of the
Since the delay may not change linearly with variation, the offset in the value, respectively. The uncertainty in the
1810 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 11, NOVEMBER 2003

Fig. 16. Five stages of fanout of four (FO-4) compensated inverters (n = 5).

Fig. 14. Delay variation of compensated clock buffer over temperature as V

varies  610%.

Fig. 17. PLL and clock buffering die photograph.

Fig. 15. Delay variation of compensated clock buffer across the corners as
V varies 610%.

can be reduced by minimizing the coupling capacitors with a

careful layout design. Also, the uncertainty can be signifi-
cantly suppressed by supplying the clock buffers with their own
local bias generator with the cost of power and area over-
head added by each bias circuit.
To characterize the performance of the delay compensating
technique, the compensated clock buffer is simulated over
temperature and process variations. As the temperature in-
creases, the increases due to the negative sensitivity of
to the temperature mV K . Fig. 14 demonstrates
the supply-induced delay variation of the compensated clock
buffer as the temperature varies from 0 C to 125 C. Increasing
the temperature from 25 C to 125 C increases the maximum
delay variation from 1.2% to 2.4% (within 10% noise).
Fig. 15 shows the supply-induced delay variation across the
process corners where tracks the pMOS threshold varia-
tion. The maximum delay variation increases to 2.5% (within
10% noise) at fast nMOS corners in the worst case. The
PSRR degradation at fast nMOS corners is due to the fact that
neither the compensated circuit nor the voltage tracks
the nMOS corner variation. To further improve the PSRR, a
series of an nMOS capacitor and resistor can be added to the
compensator circuit.
Five stages of fanout-4 (FO-4) compensated inverters
(Fig. 16) are used in the simulation. The optimum sizes of
Fig. 18. Measured and simulated VCO gain.
the pMOS resistor and capacitor are 0.5 and 3 the pMOS
transistor-width size in the preceding inverter stage. The
simulated power and delay increase due to the compensator
circuit (the bias circuit is not included) are 25% and 12%
of the conventional clock buffer (uncompensated inverter),
respectively.
IV. MEASUREMENT RESULTS
The PLL and clock buffer have been designed and fab-
ricated in a 0.25- m CMOS technology. As shown in the
chip micrograph in Fig. 17, the PLL core area is mm
m m . The measured VCO operating frequency
is 130–1600 MHz. Fig. 18 depicts the measured VCO gain,
indicating that the gain varies only between 0.9–1.35 GHz/V
for the entire range of control voltage. The input reference
frequency generated by a signal generator is set to 250 MHz
and the loop multiplication factor is four. The long-term jitter
performance of the PLL output at 1 GHz is demonstrated in
MANSURI AND YANG: LOW-POWER ADAPTIVE BANDWIDTH PLL AND CLOCK BUFFER
Fig. 19. PLL output jitter histogram at 1 GHz.
Fig. 20. Measured sensitivity of VCO output clock frequency to static and
dynamic supply noise.
Fig. 19. The jitter histogram measures the rms jitter at 3.28 ps
and peak-to-peak jitter at 28.89 ps ( 45 K hits) without the
supply noise. The measured power consumption is 10 mW at
2.5-V supply and 1-GHz output clock frequency.
To characterize the sensitivity of the VCO frequency to
supply noise, both static and dynamic VCO supply sensi-
tivity measurements are performed. For static measurement,
the dc value of the supply is varied by 10% and the fre-
quency variation of free-running VCO is measured. Fig. 20
demonstrates the measured sensitivity results expressed in
. The measurement results indicate that the
VCO achieves at low-frequency
supply noise for (in terms of frequency,
MHz GHz). At greater than 1.7 V,
where the noise-canceling circuit becomes less effective, the
noise sensitivity increases to . The
dynamic sensitivity of the VCO is characterized by measuring
the overall jitter performance of the PLL to high-frequency
noise. A 10% supply step with 1-ns slew rate (the fastest pos-
sible on-chip frequency) is injected to the VCO supply and the
peak-to-peak jitter at the PLL output clock is measured. Fig. 20
demonstrates the measured long-term peak-to-peak jitter
expressed in terms of the percentage of the PLL output clock
period, . The measurement results indicate that the
1811
Fig. 21. Measured supply-induced delay variation of uncompensated (dashed
line) and compensated (solid line) clock buffer.
PLL achieves jitter performance of
step with the VCO frequency varying from 800 MHz to
1.4 GHz. The PLL bandwidth is set to roughly 1/40 of the VCO
frequency.
To characterize the delay sensitivity of the clock buffer, both
static and dynamic variations are measured. Five stages
of FO-4 inverters and compensator inverters are fabricated. The
compensator inverters includes the pMOS compensator circuit
only. For measurement purposes, a separate power supply is
used to supply the instead of the bias generator shown
in Fig. 12. is held constant as noise is injected. The
measurement results shown in Fig. 21 indicates that the com-
pensated clock buffer at optimum V has a max-
imum delay variation of 3.8% within 10% noise for a
slow corner device, which is 5 less than the uncompensated
inverter. The measured maximum delay variation of the com-
pensated clock buffer is greater than the simulation results in a
typical corner (1.2% within 10% ) due to not tracking the
nMOS process variation and also the parasitic capacitances. The
supply-noise rejection performance can be improved by adding
an nMOS compensator circuit.
For comparison, Fig. 21 also demonstrates the performance
of the compensated clock buffer for values far from the
optimum V. The measured result at
shows an increased maximum delay variation to 5.7% (within
10% noise) and for , where the pMOS
resistor is off, the maximum delay variation becomes 22%,
which is roughly the same as that of an inverter. The measured
power and delay overhead are 30% and 18%, slightly greater
than simulation results due to the parasitic capacitances. The
area overhead is 50% as compared with inverters alone. The
overhead numbers do not include the overhead due to the
bias generator.
Table II summarizes the performance of the proposed PLL.
V. CONCLUSION
To produce low-jitter clocks in noisy supply-noise environ-
ments, two effective supply rejection techniques have been
demonstrated for the VCO and the clock buffer, respectively.
The proposed VCO achieves high supply-noise rejection
comparable with that of a regulated supply VCO with lower
power consumption. The VCO operates over a wide operating
1812
TABLE II
PROPOSED PLL PERFORMANCE SUMMARY
frequency range and has a linear voltage-to-frequency gain.
The PLL design demonstrates scaling loop parameters with
the oscillator’s frequency that tracks over a 10 frequency
range. The self-biased design allows the PLL to operate over
a wide frequency range with an adaptive loop bandwidth and
a constant phase margin. The proposed clock buffer achieves
high supply-noise rejection with an excellent dynamic behavior
and with small area and power overhead. This technique can
supplement existing supply filtering using decoupling capaci-
tors and supply-voltage regulation. The designs dissipate low
power for their jitter performance and have low area overhead.
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Mozhgan Mansuri (S’97) was born in Tehran, Iran.
She received the B.S. and M.S. degrees in electronics
engineering from Sharif University of Technology,
Tehran, in 1995 and 1997, respectively. She is cur-
rently working towards the Ph.D. degree in electrical
engineering at University of California, Los Angeles.
From 1997 to 1999, she was a Design Engineer
with Kavoshgaran Company, Tehran, working on
the design of 46–49-MHz cordless and 900-MHz
cellular phones. Her current research interests in-
clude low-power low-jitter clock synthesis/recovery
circuits (PLL and DLL) and low-power high-speed I/O links.
Chih-Kong Ken Yang (S’94–M’98) was born in
Taipei, Taiwan. He received the B.S. and M.S.
degrees in 1992 and the Ph.D. degree in 1998, all
in electrical engineering, from Stanford University,
Stanford, CA.
He joined the University of California, Los
Angeles, as an Assistant Professor in 1999. His
current research interests include high-speed
data and clock-recovery circuits for large digital
systems (2–10 Gb/s), low-power digital design, and
low-power high-precision MEMS interface design.
Dr. Yang is an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS
AND SYSTEMS—PART II: ANALOG AND DIGITAL SIGNAL PROCESSING. He is a
member of Tau Beta Pi and Phi Beta Kappa.