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VHDL Description
Preliminary
Universidad Central
Faculty of Engineering & Basic Sciences
Department of Electronic Engineering
Bogotá, Colombia
System Bus
(Address/Data/Control)
Memory
(ROM, EPROM, Memory Input/Output
EEPROM, (RAM) Interfaces
FLASH)
Address bus
Registers
ALU
section Data bus
Fetch / Execute: Bring memory and decode the instructions are in memory (User
Program) to generate the control signals necessary to execute the instructions.
Reset returns the entire system to default initial state.
CLK (Clock): Sets the speed at which instructions are executed by the sequencer.
Control unit
Data IR Decoder
Status Secuencer
Control signals internal
Reset CLK
Initial value of registers. Status register.
Initial value of the Program Counter Memory status.
(PC).
5/14/2017 Juan S. Rubiano L. Sistemas Digitales 4
Faculty of Engineering & Basic Sciences
Department of Electronic Engineering
Microprocessor blocks
IR
Data register
Temporal accumulator
Accumulator
PC
Instruction
Data
Instruction
Data
Program
memory Instruction
(ROM)
Data
.
.
.
.
Instruction
Data
Instructions
Program
memory
(ROM)
References