K SRAVANKUMAR

Bangalore-560037 Mail ID: sravanyadav101@gmail.com

Mob : 8106118163

Career Objective:
To be part of an organization, which utilizes my skills and its process of growth, challenges and
changes, while giving me ample opportunity to learn and enrich my competencies, so as to make
meaningful and substantial contribution in my professional career.

Professional Experience:
 Physical Design Intern in Semicon TechnoLabs Pvt Ltd.

Technical Skills:
 Good in Digital Electronics
 Good in fundamentals of CMOS
 Good knowledge in Synthesis and Physical design fundamentals.
 Good knowledge in Floor planning, Placement, Clock tree synthesis and Routing.
 Good knowledge in Physical verification.
 EDA tools- Cadence Encounter (RTL to GDSII).
 Good knowledge in documentation tools like MS-Word, MS-PowerPoint and MS-Excel.

Educational Qualifications:
 BE in 2017 with 7.94 CGPA from Sri Venkateswara College of Engineering and Technology.

 Diploma in 2014 with 91% from Loyola Polytechnic College.

 SSLC in 2011 with 88% from Chaitanya High School.

Domain Specific Projects :

Semicon Techno Labs Pvt ltd, Bengaluru
Project 1:
Technology : 28nm
Instance Count : 200K
Hard Macros : 45
Frequency : 250 MHz
Tools Used : Cadence Encounter

1
Role : Floor Plan to Route

 Having initial utilization 55%.

 Floor Plan- Placing of high macro count during floorplan with the help of data flow diagram
and Flylines to minimize total chip area and to make routing phase easy.
 Experiments for best pin placement to get good logic distribution.
 Avoid congestion issue by proper blockages & region approach. Area shrinking experiments,
leakage power saving experiments, floor planning based on routing resource distribution to reduce
congestion.
 Propagating clock to all sequential cells and balancing clock skew and insertion delay.

Project 2:

Technology : 28nm
Instance Count : 300K
Hard Macros : 35
Frequency : 500 MHz
Tools Used : Cadence Encounter
Role : Floor Plan to Route

 Having initial utilization 65%.

 Performed placement of macros with congestion free in floor planning
 Avoid congestion issue by proper blockages & region approach. Performing timing driven
placement and congestion removal by fine tuning the macro placement.
 Propagating clock to all sequential cells and balancing clock skew and insertion delay.