Shweta Sharma Mobile: +91-9886184420

Email: shwetalike@gmail.com

Experience Summary:

12+ years of hands-on experience in leading FPGA Designs at Cisco Systems, C2Sis & Wipro technologies.
 Proficient in leading FPGA teams, designing high-speed datapath FPGAs from micro architecture stage to RTL
coding, implementation, timing closure, functional simulation and board bring up.
 Presented a paper on “Concept to Deployment: Hardened Hardware” at SAP Ariba SWE Mini Conference in Dec
2017.
 Presented a paper on “Smart Approach in FPGA for Ethernet, SONET and OTN Network Clocking” at Xilinx Club
Vivado Conference, 2016.
 Authored internal Cisco patent submissions on “Automated Design & Verification of Environmental Poller in
FPGAs/ASICs” and “Smart Approach in FPGA for Ethernet, SONET and OTN Network Clocking”.
 Recipient of various Connected Recognition Awards at Cisco Systems.
 Was awarded with the "Above & Beyond: On Time Every Time” Award, “All for the Best” Award & “Feather In My
Cap” award as recognitions for delivering successful FPGA & CPLD designs & resolving high priority customer issues
at Wipro.
 Rich experience of working at Nortel Networks (now Avaya) at Belleville, Canada for long term.
 Excellent written & verbal communication skills

Technical Skills:
 RTL/Modeling Languages: Verilog, VHDL, ABEL, Specter, RDL
 Hardware Tools:
 Back end tools : Vivado, Xilinx ISE, Altera Quartus, Tabula Stylus, Libero
 Simulators: Mentor graphic Modelsim SE, DVE
 Synthesizers: Synplify Pro, Xilinx XST
 Debuggers: Xilinx Chipscope Pro, Altera Signal Tap
 Standards/ Protocols: IEEE C37.94 Protocol, XFI, XAUI/eXAUI, SGMII, PCIe DMA, I2C, SPI, MDIO, UART, Wired TDM
interface, DDR3 PHY interface, SPI4.2, Any-Phy PL2/PL3 interface, IEEE1588 timestamping, CCITT Q.921 HDLC
standard.
 Software Languages: C, C++ (basics)
 FPGA Devices: Xilinx Utrascale, Zynq 7000, Artix 7, Microsemi SF2, Spartan 6, Virtex 5, Altera Cyclone Series

Education:
 B.Tech. (Hons.) (ECE) from IET, Lucknow, U.P, India with 77.64% (among top 3 in college).
 12th ISC Board with 93.25%

Work Experience:
 Cisco Systems, Bangalore, India (July 2012- till date): Designation: ASIC/FPGA Engineer IV
 Concept2Silicon Pvt. Ltd, Bangalore, India (Jan 2012- June 2012): Designation: Lead Design Engineer. Worked for
Tabula Offshore Development Centre (ODC).
 Wipro Technologies, Bangalore, India (Aug'05 – Dec’2011): Designation: Senior Project Engineer. Worked for
Nortel Networks (now Avaya Inc) ODC & Nokia Siemens Semiconductor ODC.

Professional Experience
1. FPGA design lead for Qumran/Denverton based Access router [Nov 2017 to present]
 Requirement gathering from all cross functional teams to micro architect the FPGA.
 Aiming to architect FPGA into reusable modules so that same FPGA image can be re-used over 8 different
cards of this platform.
 Microsemi Smartfusion2 Device design in Libero.

2. FPGA design lead for Tomahawk NP/Broadwell based router [April 2016 to present]
  Complete ownership of leading design of 2 FPGA (Artix 7 & Zync-7000 designs) for a new router platform
starting from micro architecture definition to customer deployment.
 The Zynq ARM FPGA design also involved ownership of hardware specific boot code that runs on init.
 Designing auto pollers to enable SW to offload the periodic polling from pluggables, autonomously.
 Working with cross functional teams from HW, SW, Diags, EDVT, DT etc to ensure smooth bringup &
testing.

3. Enhancement to enable Duplex DMA S2C & C2S over PCIe for DDR3 [April 2017 to October 2017]
 Micro architected and designed a DMA over PCIe based application offload engine. This was to enable SW
to be able to transfer the context data from main Route processor(RP) to Line Card(LC) before switchover
& then transfer it back from LC to RP, to retain the context.
 Before this enhancement, due to memory constraint SW was able to store the context of only 4 LCs &
hence customer was not able to deploy the system to its full capacity.
 NWL DMA IP was used for this on a Zync-7000 based design.

4. FPGA design lead for Ultrascale based Datapath link bridge FPGA [May 2015 to Feb 2017]
 Worked on Requirement gathering for Design, Bringup and SW integration test for a Xilinx Ultrascale
based FPGA & Broadcom ARAD+, Hyphy based design.
 Main interfaces were, XFI-XFI slingshot interface, XFI to eXAUI bridge, SGMII to RGMII Bridge, Out of Band
flow control interface.

5. IEEE C37.94 datapath engine for Smart Grid [IOT initiative] [May 2014 to August 2016]
 Datapath design from scratch based on the IEEE specification for C37.94 protocol.
 Worked with cross functional teams to analyze the corner cases & micro architect the FPGA.
 Worked with Delta Networks Inc, Taiwan as it was a turnkey design from HW & Diags perspective.

6. Multiple Control FPGA design for a new satellite pizzabox aggregator [July 2013 to April 2014]
 Complex IOFPGA design that controls & interfaces to all the major peripherals of Freescale’s P2041 CPU,
for a new Aggregator that works as a satellite to the existing Scapa & ASR9K routers of CISCO.
 Task involves IO/logic estimation, device selection, documentation, FPGA register definition for driver
development (using RDL), RTL coding (in Specter), Synthesis/Implementation, along with the bringup of
the same in lab.
 Sensor Auto poller design & Secure Boot core integration along with Multiboot for Xilinx S6 FPGA.

7. Redesign of four Cisco’s Shared Port Adaptors (SPA) [July 2012 to June 2013]
 Complete ownership of FPGA redesigns for the Shared Port Adaptor cards used on Cisco Routers, as part
of Pb-free conversion. This included RTL porting (Virtex2/3 to S6), implementation & board bringup.

8. Design & Simulation of Hard & Soft implementation of DDR3 subsystem for Tabula’s latest ABAX2 devices.
(Jan’12-June’12]
 IP development for DFI compliant DDR3 Phy for the spacetime technology based FPGA from Tabula.
 RTL design of the DDR3 PHY that would work for both the Hard and Soft DDR3 Controller
implementations, including read and write leveling for the DDR3 memories [333 MHz]. Used Stylus
Backend tool.

Maternity Break: March’11 to Dec’11

9. Design of a multipurpose FPGA for a new standalone baseband transceiver station: (June’10-Mar’11)
 Successfully lead a team working on a multipurpose FPGA for an all new standalone Baseband Transceiver
Station for Nokia Siemens Semiconductor for both design & DV(using SV-OVM).
 Part of client interfacing team for requirement closure, micro architecture development, RTL design &
review.

10. Retargeting of two legacy ASICs onto a single FPGA onboard: (Mar’09-May’10)
  Responsible for project proposal, development plan, requirement matrix, design document, device
selection, RTL design, implementation & verification.
 Designed a 32 channel, full duplex HDLC controller, with asynchronous Transmit & receive ports. The
design was based on CCITT Q.921 layer 2 signaling protocol. Major blocks include the processor
configurable register set, the link interface & the TDM side backplane interface with context switcher.
 Designed a DMA Controller with 32 independent DMA ports having separate incoming & outgoing queues
(32 TX & 32 RX ports with their respective message queues). The main Function is to allow messages to &
fro between a link device (HDLC Controller) & a large buffer memory. Major blocks being the Memory
Address Generator, the opcode decoder, link interface & the Motorola 68K compatible bus arbiter.

11. Designed handshake mechanism between main PBX processor & on-board processor: (July’08-Feb’09)
 Due to obsolescence of two Altera EPLDs, redesign into Xilinx 5V XC9500 device. Tested the new design,
by replacing the Altera EPLDs with an available Xilinx CPLD daughterboard, on an existing card. The quick
turnaround time for delivering a successful redesign was highly appreciated by the client & Wipro
management.

12. Tasks at Onsite (Nortel Networks, Canada) (Jan 2008 to June 2008):
 Various high priority issues from field & factory were resolved quickly due to comprehensive system level
understanding & systematic approach. This was highly appreciated.
 Drafted a proposal for design of a cost improved Telecom signaling processor card which was readily
approved by Nortel. Completed the RTL design & first level simulations while at Nortel and completed
board bringup at Bangalore lab.

13. Redesign of BRI & PRI Signaling processor boards for Cost Improvement. & Component Obsolescence: (June’06-
Dec’07)
 Worked on Motorola CPU based designs to port DRAM based memory architecture to SRAM based
without impacting firmware for cost savings & simplified design as the DRAM Controller & Parity
generation logic was removed. Also integrated third party 68901 Multi Functional Peripheral core, in the
FPGA to address the obsolescence of the same.
 Xilinx Spartan-3A based design
 This design also involved porting the Asynchronous SRAM based Shared Memory logic into FPGA’s Block
RAM.A Design was further simplified by coding the various EPLDs, PALs & related glue logic inside the
FPGA.

14. Redesign of a PBX control card for value engineering & cost reduction: (Aug’05-May’06)
 Responsibilities included Functional Specification documentation, RTL Coding in VHDL, Functional &
Timing Simulation, Synthesis, Implementation, Schematic & Layout Review, BOM creation for prototypes,
Test Plan Documentation & Board bring up.
 Seven On-board GALs, two EPLDs & a DRAM Memory Controller were implemented inside a Spartan FPGA
along with lots of other glue logic.Detailed study of existing design was done by taking captures from
Logic Analyzer, understanding ABEL Code for programmable GALs & Motorola processor architecture.

15. Tasks as part of sustenance activity: (Aug’05-May’10, Nortel Networks ODC)

 Handled issues on Component Obsolescence for the entire ISDN portfolio involving RoHS compliant,
datasheet comparison, final testing of samples & test report documentation.
 Worked on various Field & Factory Issues involving System level understanding at the problem site,
duplicating the problem in the lab, analyzing the complete interfacing hardware & firmware of the board
& working towards speedy resolution of the problem.
 Trained & maintained the access for all the hardware design tools required by the team & trained all new
joiners on the same.

Address
B-212, Euphoria Block, Suncity Apartments,
Sarjapur-Outer Ring Road, Ibblur, Bangalore-560102, Karnataka, India.