9. Flip-Flops 9.1.

Latches
o Objectives o Problem: Design a network to control a lamp from two
pushbutton switches labeled S and R. If we push switch S the
This section is the first dealing with sequential circuits. It light should turn on. If we then release S, the light should stay
introduces Flip-Flops, an important building block for most on. If we push switch R, the lamp should turn off and stay off
sequential circuits. after releasing R. Assume that both S and R are not pushed at
the same time. +
n First it defines the most basic sequential building block, the
RS latch, and investigates some of its properties.
S + Q
n Then, it introduces clocks and shows how they can be used ? Lamp

to synchronize latches to get gated latches.

n Finally, it extends gated latches to flip-flops by developing R

a more stable clocking technique called dynamic clocks.

n The Section also develops the state table behavioral model R

for gated latches and flip-flops S

o Reading Assignment
Q
n Chapter 7, sections 7.1 through 7.7, in Brown & Vranesic.

Elec 326 9.1 Flip-Flops Elec 326 9.2 Flip-Flops

o The previous circuit is called an SR Latch and is usually drawn

n A Solution as shown below:
R R Q
Q R Q
S X
S Q
S Q_L
Logic Diagram Symbol
n Construct a truth table for this circuit. n Observations
u The latch has two states, Q = 0 and Q = 1
R S X Q
u The output depends on the state as well as the inputs, so the circuit is
0 0 sequential
0 1 u The circuit has a loop, as all sequential circuits do
1 0 u The outputs Q and Q_L are logical complements unless inputs S and R are
1 1 both 1
n Write Boolean expressions for X and Q. u Asserting S (i.e., setting it to 1) sets Q to 1 (and Q_L to 0).
u Asserting R (i.e., setting it to 1) resets Q to 0 ( and Q_L to 1)
u If neither S nor R are asserted, Q retains a value determined by the last
time S or R were asserted
u Bad things can happen if both S and R are asserted simultaneously as we
will see below.

Elec 326 9.3 Flip-Flops Elec 326 9.4 Flip-Flops

1
o Unstable latch behavior (Oscillation)
n Assume that all gates have a fixed delay d modeled as n Now set S = R = 1, so that both Q and X are equal to 0 after
follows: at most a delay of d. Then change both R and S to 0 at
X d Y
X exactly the same time. Then
Y Q(t+d) = X(t)' and X(t+d) = Q(t)'
Y(t+d) = X(t) d

n This gives the following latch model: d d d d

R
Q(t+d)

R S
d Q(t)

X(t) Q
S d

X(t+d)
X
n Then Q(t+d) = (R(t) + X(t))' = R(t)' • X(t)', and
X(t+d) = (S(t) + Q(t))' = S(t)' • Q(t)'

Elec 326 9.5 Flip-Flops Elec 326 9.6 Flip-Flops

o Unstable latch behavior (Metastable state) n Now consider the behavior of the following circuit:
vi1 vo1 vi2 vo2
n Equivalent circuit for the latch when R = S = 0
vi1 vo1 vi2 vo2

n Transfer characteristics of an inverter:

vout

n Superimposing the two graphs gives the following:

vo1, vi2
Inverter 1

Inverter 2

vin vi1,vo2

Elec 326 9.7 Flip-Flops Elec 326 9.8 Flip-Flops

2
 n Now consider connecting v02 to vi1
vo1 = vi2 vo2 = vi1
d d o Avoiding unstable behavior of SR latches
n Since both the oscillation and the metastable state are
u The dots on the graph represent points where the input outputs of undesirable behavior, we should try to avoid them. this can
the delays are equal.
u The dots on the two ends represent the two stable states of the
be done with the following rules:
system. Small changes in any of the signals are damped out u Do not change R and S from 1 to 0 at the same time.
quickly.
l This is necessary to avoid the oscillation behavior seen above
u The dot in the middle represents a metastable state. Small changes
in any of the signals are amplified and the circuit leaves the l One way to guarantee that this will not happen is to never allow them to both
metastable state. be 1 at the same time.
n The hill analogy: u Once you change an input, do not change it again until the circuit
has had time to complete all its signal transitions and reach a stable
n The latch could get in the metastable state in the following state.
way:
l This is necessary to avoid the metastable behavior illustrated above
R
S
Q

u What is the relationship between hazards and the metastable state?

Elec 326 9.9 Flip-Flops Elec 326 9.10 Flip-Flops

o /R/S Latch o Verilog description of an SR latch

R_L
Q_L
R Q
module srlatch1 (s, r, q, q_n);
Q
S Q input s, r;
S_L output q, q_n;
Logic Diagram Symbol

n Changing from 00 to 11 can produce nondeterministic assign q_n = ~(s | q);

behavior assign q = ~(r | q_n);

endmodule

o Propagation Delay of Ungated Latches module srlatch2 (s, r, q); module srlatch3 (s, r, q);
tPRQ - Delay from the R input to the Q output input s, r; input s, r;
output q; output q;
tPSQ - Delay from the S input to the Q output reg q; reg q;
tPRQ_L - Delay from the R input to the Q_L output
always @(s or r) always @(s or r)
tPSQ_L - Delay from the S input to the Q_L output if (s & r) q = 0; case ({s,r})
else if (~s & r) q = 0; 3: q = 0;
S else if (s & ~r) q = 1; 2: q = 1;
Q
1: q = 0;
tPSQ endmodule endcase
endmodule

Elec 326 9.11 Flip-Flops Elec 326 9.12 Flip-Flops

3
9.2. Gated Latches o Gated SR Latch
o Clock Signals R
Q_L R Q

n It is easier to avoid the metastable state if we place CK

CK
S Q
restrictions on when a latch can change states. This is Q
S
usually done with a clock signal.
Logic Diagram Symbol
1 2 3 4
CK n Gated Latch Function Table
1 2 3 4 5
CK S R Q(t+d)
n The effect of the clock is to define discrete time intervals. 0 0
0 0
0
1
Q(t)
Q(t)
n The clock signal is used so that the latch inputs are ignored 0 1 0 Q(t)
0 1 1 Q(t)
except when the clock signal is asserted. 1 0 0 Q(t)
n This effectively makes time discrete, since we do not care 1 0 1 0
1 1 0 1
what happens when the clock is not asserted. 1 1 1 0

u Note that when CK is 0, the simple latch has both inputs 0 and the
inputs S and R have no effect

Elec 326 9.13 Flip-Flops Elec 326 9.14 Flip-Flops

n Gated Latch Transition Table o Gated D Latch

u Note that the internal latch inputs will both go from 1 to 0 if the S and R n This latch is useful when you need a device to store (remember) a bit of
inputs are both 1 when the clock goes low. Hence we must never have S
and R at 1 when the clock is 1. data. D S Q D Q
CK CK
u We make the following rules for changing inputs. R Q CK Q
l Don't change the inputs while the clock is asserted.
l Don't apply the inputs S = R = 1 when the clock is asserted. Logic Diagram Symbol
u Then we can use the following model of flip-flop behavior: n The D stands for "data" or "delay."
l While the clock is not asserted, the inputs are ignored and the state does not change.
l When the clock is asserted, the flip-flop can change state and the values of the input u The term data refers to the fact that the latch stores data.
signals S(t) and R(t) and current state Q(t) just prior to the clock assertion determine the
new value of the flip-flop's state Q(t+1). u The term delay refers to the fact the output Q is equal to the input D one
u Assuming this model, we can describe the flip-flops behavior by a table time period later. That is, Q is equal to D delayed by one time period.
that gives the new state Q(t+1) that will occur when the clock is asserted
given the current state Q(t) and the current inputs S(t) and R(t). n Gated D Latch Transition Table
D(t)
S(t) R(t) Q(t) 0 1
Q(t) 00 01 11 10 0 0 1
0 0 0 d 1 1 0 1
1 1 0 d 1 Q(t+1)
Q(t+1)
n There is no such thing as an ungated D latch. Why?
u This table is called a transition table or state transition table. n The gated D latch is also called a transparent latch.
u The clock is not shown explicitly, but is inherent in the interpretation we
place on table.
Elec 326 9.15 Flip-Flops Elec 326 9.16 Flip-Flops

4
 n Alternative Design of the gated D Latch
CK
D Q
o Propagation Delay of Gated Latches
n Since changes in the data inputs of a gated latch have no
effect unless the clock is asserted, propagation delay is not
measured from the data inputs.
n Propagation delay is measured from the clock input to the
outputs.
tPCQ (or tPQ) - delay from time clock is asserted until the Q output changes

u Exercise: Compare this implementation with the following one: CLK

Q
tPCQ
D
Q tPCQ_L (or tPQ_L) - delay from time clock is asserted until the Q_L output changes
CLK
CK
Q
Q_L tPCQ_L
n Propagation delays can be different from high-to-low
transition and low-to-high transitions
CLK
Q
tPQHL tPQLH

Elec 326 9.17 Flip-Flops Elec 326 9.18 Flip-Flops

o Verilog description of gated latches o Exercise

n Gated SR Latch: module gatedsr (G, S, R, Q); n Consider the following 4-stage shift register made from
input G, R, S; gated D latches:
output Q;
reg Q;
Q1 Q2 Q3 Q4
DIN D Q D Q D Q D Q
always @(G or S or R)
CK Q CK Q CK Q CK Q
if (G)
CLK
if (S & ~R) Q = 1;
else if (~S & R) Q = 0;
else if (S & R) Q = 0;
n The intended behavior is that data bits are shifted in at the
endmodule DIN terminal and shifted out at the Q4 terminal four clock
n Gated D Latch: pulses later. The first clock pulse loads the bit into Q1 and
module gatedd (D, Clk, Q); the second clock pulse transfers this bit from Q1 to Q2
input D, Clk; while a new bit is loaded into Q1, and so on.
output Q;
reg Q; n What applications could you suggest for this circuit?
always @(D or Clk)
if (Clk)
Q = D;
endmodule

Elec 326 9.19 Flip-Flops Elec 326 9.20 Flip-Flops

5
 n Draw a timing diagram for this circuit assuming that the 9.3. Flip-Flops
propagation delay of the latch is greater than the clock
pulse width. o Dynamic Clock Inputs
CLK
n The gated latch only looks at its data inputs while the clock
DIN=1
is asserted; it ignores them at other times
Q1=0 u The window of time when the latch is looking at and reacting to its
Q2=0
inputs is the duration of the time that the clock is asserted
Q3=0 n It is easier to design the circuits that generate a latch’s data
Q4=0 inputs if the window when the latch is looking at the data
inputs is small.
n Draw a timing diagram for this circuit assuming that the u We could only assert the clock for a short time, but this creates
propagation delay of the latch is less than the clock pulse other problems
width. n Dynamic clock inputs and the latches that use them reduce
CLK the window to a very small time around an edge of the
DIN=1 clock
Q1=0 n There are two types of dynamic clock inputs, edge-
Q2=0 triggered and master-slave.
Q3=0
n Latches that use dynamic clocks are called flip-flop
Q4=0

Elec 326 9.21 Flip-Flops Elec 326 9.22 Flip-Flops

o Positive Edge-Triggered D Flip-Flops o Edge-triggered flip-flop behavior

Q1 Q2
Q1 Q2
D D Q D Q Q
D D Q D Q Q D Q
CK Q CK Q Q_L
CK Q CK Q Q_L Q
CK CK
Logic Diagram Symbol
n When the clock is low, the master latch is enabled and its output
follows its D input. When the clock makes a low-to-high transition, the
master latch is deactivated and the last value it saw in its D input is
n This flip-flop samples its D input on the rising edge of the stored in its memory. At the same time, this value is transferred from
clock and is therefore called an edge-triggered flip-flop. the master to the slave latch.
n The first latch is called the master latch and the second one n The slave is enabled while the clock is high, it will only change its
is called the slave latch. The slave latch always follows the value at the time the clock goes high, since its input is connected to the
master latch. master, and it cannot change while the clock is high.

n Note that Brown & Vranesic call this a master-slave flip- n The edge-triggered flip-flop behaves as if it samples its input during
rising edges of the clock, and that is the only time its output can change.
flop.
n The sampling window is very short, and that is the only time during
which the input signal must be held constant.

Elec 326 9.23 Flip-Flops Elec 326 9.24 Flip-Flops

6
o Negative Edge-Triggered D Flip-Flops o Edge-Triggered JK Flip-Flops
Q1 Q2 n The JK Flip-Flop has two inputs J and K. All four possible
D D Q D Q Q
Q_L
input configurations are valid. The J acts like S and the K
CK Q CK Q
CK
acts like R, when there is only one input with value 1.
When both J and K are 1, the flip-flop toggles.
o Asynchronous Inputs
JK
Q 00 01 11 10
CLR_L
D R Q R Q Q D
PR
Q 0 0 0 1 1 J D Q Q
S Q S Q Q_L K
Q 1 1 0 0 1 Q Q_L
PR_L CLR CK
CK Q*
Logic Diagram Symbol Q* = J•Q’ + K’•Q

n If CLK is held at 0, the D flip-flop acts like an SR latch n What would happen if we used a gated D latch instead of
with PR the set input and CLR the reset input an edge triggered flip-flop?

Elec 326 9.25 Flip-Flops Elec 326 9.26 Flip-Flops

o Verilog descriptions of edge-triggered flip-flops o Trigger Flip-Flop

n D Flip-Flop
T Q
module flipflopd (D, Ck, Clr, Q); T D Q Q
input D, Ck, Clr; Q_L
Q
output Q; CK Q

reg Q; Logic Diagram Symbol

always @(posedge Ck or posedge Clr)
if (Clr) Q = 0; o Master-Slave Flip-Flops
else Q = D; n SR master-slave flip-flop
endmodule QM QS
S S Q S Q Q S Q
CK CK
n JK Flip-Flop R R Q R Q Q_L CK
R Q

module flipflopjk (Ck, J, K, Q); CK

input Ck, J, K; Logic Diagram Symbol
output Q;
reg Q; n JK master-slave flip-flop
always @(negedge Ck) QM QS
J S Q S Q Q J Q
if (J & ~K) Q = 1; K
CK CK CK
else if (~J & K) Q = 0; R Q R Q Q_L K Q

else if (J & K) Q = ~Q; CK

endmodule Logic Diagram Symbol

Elec 326 9.27 Flip-Flops Elec 326 9.28 Flip-Flops

7
 n Pulse Catching n Verilog description of master-slave flip-flops
CK
module flipflopms (Ck, S, R, Q, master);
J input Ck, S, R;
output Q, master;
K reg master, Q;
QM
always @(Ck or S or R)
QS if (Ck) begin
if (S & ~R) master = 1;
else if (~S & R) master = 0;
n Comparison of flip-flop types else if (S & R) master = 0;
end
QL QMS QET else
S Q = master;
S Q S Q S Q
CK CK endmodule
R Q R Q R Q
R
CK

CK
S
R
QL
QMS
QET

Elec 326 9.29 Flip-Flops Elec 326 9.30 Flip-Flops

9.4. Sequential PLDs o Typical PAL & CPLD output logic

o Sequental PLAs and PALs
n Sequential PLDs are programmable logic devices that contain flip-flops and
can be used to realize synchronous sequential circuits.
u Sequential PLDs are also called registered PLDs

OE

D Q

Combinational PAL
D Q n Sequential PLD Timing Specifications
tPD Input or feedback to combinational output delay
CK
tCO Clock to flip-flop output
tCF Clock to feedback signals (may not be given)
u Typical Characteristics tSU Setup time for input, or feedback signals
Common clock
l
l Common OE
tH Hold time for input signals
l Flip-flops feedback to combinational array

Elec 326 9.31 Flip-Flops Elec 326 9.32 Flip-Flops

8
9.5. Tips & Tricks 9.7. Review
o Designing with flip-flops is much easier than with o The behavior of latches
gated latches. n Metastability
o Avoid the use of master-slave (pulse triggered) flip-
flops. o Adding clocks to latches - gated latches
o Latches can be used to debounce switches in the o The properties of dynamic clocks - flip-flops
following way: +
n Edge-triggering

RQ
o Types of flip-flops:
S Q n SR, D and JK
9. 6. Pitfalls o The transition table model for flip-flop behavior
o Ignoring flip-flop timing parameters.

Elec 326 9.33 Flip-Flops Elec 326 9.34 Flip-Flops