Gates and Logic Networks: o Objectives o Reading Assignment

2.
Gates and Logic Networks

o Objectives o Reading Assignment
This section is a review and expansion of the following n Most of the concepts covered in this chapter were
material covered in Elec 220: introduced in Elec 220.
n The nature of digital signals n Most of the material in this chapter is covered in a little
more depth in Chapter 2: Introduction To Logic Circuits of
n Behavioral models of gates: Truth Table & Logical
the Brown & Vranesic book. A few of the topics are
Expressions
covered in chapters 3 and 4.
n The definition of gate networks.
u The negative logic system is covered in section 3.4 (pages 82-83)
n Analysis of gate networks. of Chapter 3 in Brown & Vranesic.
n Simple synthesis of gate networks. u The analysis of multi-level logic networks is covered in section 4.7
(pages 184-189) of Chapter 4 in Brown & Vranesic.
n A synthesis technique that uses only NAND or NOR gates.
u A technique for synthesizing simple, two-level NAND and NOR
n An introduction to Verilog and its use in specifying gate networks is given in Chapter 2 of Brown & Vranesic. The notes
network behavior. present the more general technique (for multi-level networks) given
in section 4.6.3 (pages 181-184) of the text.
Elec 326 2.1 Gates and Logic Networks Elec 326 2.2 Gates and Logic Networks
2.1. Binary Valued Signals

n If a finite number of ranges is good, using only two ranges
o Signal Values should be best.
n In any physical system, the voltages can, in theory, take on u There is only one boundary.
an unlimited number of different values. u Pick a value th called, the threshold, in the middle of all voltages
n A physical measuring device can only detect a finite possible on a wire.
number of voltages on a wire. The actual number is l If the observed voltage is > th, we say the signal has one of the two values.
determined by: l If the observed voltage is < th, we say it has the other.
u Noise (in the circuit and/or the measuring device).
u Binary-valued signals don’t really have only two values, we just
u The complexity (cost) of the measuring device. treat them as if they did.
n In a digital system the possible voltages on a wire are u Many models are based on this two-valued assumption.
grouped into a small number (usually two) of ranges and a
u The actual symbol we use for the two values is not very important,
unique discrete value assigned to each range. what matters is that there are only two.
u Now we only need to detect which range the voltage is in.
l Common examples: 0 and 1, Low (L) and High (H),True (T)
u More noise can be tolerated.
u This is much easier to do, if the signal is not too near a boundary
(i.e., less expensive circuits).
1
n How do we represent a large number of values with only
two values and what is the tradeoff involved? o Logic Conventions
u Use several signals: n signals can represent 2 n values.
u This can increase the cost and complexity enormously. n The use of 0 (F) and 1(T) must be associated with the H
u VLSI to the rescue. and L voltages. It does not matter which way it is done.
n It is easier to deal with binary-valued signals if we keep the u If 1(T) is assigned to H and 0(F) to L we say we are using the
voltage away from the single threshold. positive logic convention.
Vmax
1 u If 0(F) is assigned to H and 1(T) to L we say we are using the
VH
negative logic convention.
Unstable
u In this course we will use the positive logic convention unless
VL explicitly indicated otherwise.
0 Vmin
u If the observed voltage is > V H, call it a 1, High or True.
u If the observed voltage is < V L call it a 0, Low or False.
u For TTL, a 1 is anything over 2v and a 0 is anything under 0.8v.
2.2. Gates
o Exercise: o Gate: A simple electronic circuit (a system) that
The signal on a wire can vary between 0 and 10 volts. realizes a logical operation.
Circuits that use this signal can only determine voltage n The direction of information flow is from the input
values to one digit of accuracy. That is, it will round the terminals to the output terminal.
actual voltage to the nearest integer, so that any actual
voltage between 2.5v and 3.5v will be perceived as 3v. n The number of input and output terminals is finite and they
Noise can alter the voltage on the wire by ±0.05v. carry binary-valued signals (i.e, 0 and 1).
Determine the number of possible discrete signal values n The transformation of input signals to output signals can be
and determine the voltage range associated with each of modeled as a logical operation.
them.
X
Gate Z = f(X,Y)
Y
2
o Truth Tables o Some standard gates and their symbols and truth
n Since there is a finite number of input signal combinations, tables: X X
Z
we can represent the behavior of a gate by simply listing all X Z X Z Y Y
Z
X Y Z
of it possible input configurations and the corresponding X Z X Z 0 0 0
X Y Z
0 0 0
output signal. Such a list is called a truth table. 0 0
1 1
0 1
1 0
0 1 0
1 0 0
0 1 1
1 0 1
a. Buffer b. Inverter 1 1 1 1 1 1
n For example, the following gate could have the behavior c. AND Gate d. OR Gate
given by the following truth tables. X
Z X
Y Z X X
Y Z Z
X Y Z X Y Z X Y Z or or Y Y
X X
X L L L 0 0 0 1 1 1 Z Z
0 1 1 1 0 0 Y Y
GATE Z L H H X Y Z X Y Z
Y 1 0 1 0 1 0
H L H X Y Z X Y Z
H H H 1 1 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 1 0 1 1 0 1 0
0 1 1 0 1 0 1 0 1 1 0 0
1 0 1 1 0 0 1 1 0 1 1 1
1 1 0 1 1 0
n The use of the symbols L and H usually correlates with the e. NAND Gate f. NOR Gate
g. Exclusive OR Gate h. Equivalence Gate
high and low voltages.
o Logical Expressions
n Gates with more than 3 inputs: n We can also represent the behavior of gates with a logical
u AND gates: The output is 1 if and only if … ? expressions constructed from variables and logical
u OR gates: The output is 1 if and only if … ? operations symbols.
u NAND gates: The output is 0 if and only if … ? n The following table gives the most common ones.
u NOR gates: The output is 0 if and only if … ?
Connective Example Meaning
u EXCLUSIVE OR gates: The output is 1 if and only if … ?
NEGATION C = A' C is 1 iff A is 0.
u EQUIVALENCE gates: The output is 1 if and only if … ? AND C = A•B C is 1 iff A is 1 and B is 1.
OR C = A+B C is 1 iff A is 1 or B is 1.
EXCLUSIVE OR C = A⊕B C is 1 iff A or B is 1, both not both.
NAND C = A↑B C is 1 iff It is not the case that A and B are both 1.
NOR C = AØB C is 1 iff It is not the case that either A or B is 1.
EQUIVALENCE C = A≡B C is 1 iff Both A and B are 1 or both A and B are 0.
3
2.3. Gate Networks
n Comments on the logical symbols o A gate network is a finite collection of interconnected
u The NAND and NOR symbols are not very useful. gates, network input terminals, and network output
u There are several different symbols that have been used for the terminals with the following restrictions:
logical connectives.
n No gate output terminal or network input terminal is
connected to another gate output terminal or network input
terminal.
n Every network output terminal or gate input terminal is
wired (via one or more wires) to a constant value, a
o Exercise: network input terminal, or a gate output terminal.
Determine how many different two-input gates there can be? o Example
How many three-input gates? A
X
Network B Network
Input Output
Terminals Terminals
Y
C
o Types of networks o Exercise:

n A combinational gate network is one in which the values of the signals
present on its input terminals uniquely determine the signal values at its Which of the following networks are combinational and
output terminals. which are sequential?
n A gate network that is not combinational is called a sequential gate
network.
n A loop in a gate network is a path that starts at a gate terminal, passes
along wires and through gates, does not pass any wire or gate more
than once, and terminates back at the starting gate terminal. Net 1 Net 2
Loop
Net 3 Net 4
u Networks without loops are combinational.
l We call a gate network without loops a logic network, since we can describe
its behavior with a logical expression.
u Sequential networks have loops.
u Combinational networks may have loops.
4
2.4. Analysis & Synthesis of Logic Networks o Analysis of Logic Networks
o Overview n Logic Network
A Z1
1 Z4
Synthesis Logic Analysis 4 6 X
Network B Z2
2
7 1 2 6
Z3 5 Y
3
C
4
Truth 3 Logical
Expression
n Truth Table Behavioral Description
Table
ABC Z1 Z2 Z3 Z4 X Y
5
0 0 0
1. For a given logic network, find a truth table that describes its behavior. 0 0 1
2. For a given logic network, find a set of logical expressions that describes its behavior.
3. Transform a logical expression into the equivalent truth table representation. 0 1 0
4. Transform a truth table into an equivalent logical expression representation. 0 1 1
5. Transform a logical expression into an equivalent (and possibly simpler) logical
1 0 0
expression.
6. Design a logic network to have the behavior specified by a given set of!logical 1 0 1
expressions. 1 1 0
7. Design a logic network to have the behavior specified by a given truth table.
1 1 1
n Example
n Logical Expression Behavioral Description
ABC X Y
A Z1
1 Z4
X
0 0 0 0 0
4 6
A 0 0 1 0 0
B Z2 X
2 B 0 1 0 0 0
0 1 1 0 0
Z3 5 Y
3 1 0 0 0 0
C
Y 1 0 1 0 1
C
1 1 0 1 0
1 1 1 1 0
X = A•B
Y = A•B'•C
n The networks in these two examples are equivalent because they have the same
truth table. The logical expressions for X and Y are also equivalent, but very
different structurally.
5
n Notation: We can represent a truth table by simply listing o Synthesis of Logic Networks
the indices of the rows that have value 1 or listing those n Example
that have value 0.
u Example Z = (A ⊕ B) + ((C + D)•B')
ABC X Y
0 0 0 0 0
0 0 1 0 0
0 1 0 0 0
0 1 1 0 0
1 0 0 0 0
1 0 1 0 1
1 1 0 1 0
1 1 1 1 0
l List of 1’s:
X = S A,B,C (6, 7) Y = S A,B,C (5)
l List of 0’s:
X = PA, B, C (0, 1, 2, 3, 4, 5) Y = P A,B,C (0, 1, 2, 3, 4, 6, 7)
u The value of this notation is that it is a more compact way of

specifying a logical function than writing the truth table. It is useful
for specifying a function to be designed (e.g., in homework
problems).
n Example n Two level gate networks and logical expressions

X = ((A ⊕ B) + C)' u Sum-of-Products (SOP) logical expressions
Y = (B•C + D)'•E A•B + A•C’ + B•C’•A + C
Z = (A + D) + (B•C)
u Two level AND-OR Networks

A
B X A
C B
C
D Y Y
E
Z
u Product-of-Sums (POS) logical expressions
Original Network (A+B’)•(B+C’)•A
A A
B X B X
C C
u Two level OR-AND Networks
Y Y A
D D
E E B
Z Z
C Y
First Simplification Second Simplification
6
2.5. NAND/NOR Networks n One approach is to replace AND and OR gates by the
following equivalent NAND or NOR circuits:
o This topic deals with designing combinational logic
networks using only NAND or NOR gates. A
B
A•B
A
B
A+B
n Approach: First design the network with AND, OR and A A

NOT gates. Then Transform it to an equivalent network of NAND: B A•B
B
A+B
NAND or NOR gates.

A A
u The following alternative NAND and NOR symbols are useful for NOR: B
A•B
B
A+B
this.
A A
(A•B)'
B B A' + B'
n NAND Network Example:
A A
(A + B)' A' • B'
B B A' 4
A'
4 C'
C' 2
2 1
B 5 Z
5 1 Z B
D
A D
3 3
D A
AND-OR Network D
NAND Network
n NOR Network Example

o Algorithm 1: (Converts network N1 of inverters, AND gates,
A OR gates, NAND gates, and NOR gates into network N2
B Z containing only NAND Gates)
C
D Step 1.
E'
AND-OR Network
a) Replace each AND gate symbol in the diagram of N 1 by the symbol
for a NAND gate.
b) Replace each OR gate or NOR gate symbol in the diagram of N1 by the
!!!!!!!!!symbol for a NAND gate.
A
B Z
c) Replace all INVERTERS in the diagram of N 1 by a direct connection.
Step 2.
C
D a) Consider each connection (1) from a gate output to a gate input, (2) from
E' a network input terminal to a gate input, or (3) from a gate output
terminal to a network output terminal, in the network produced by Step 1.
NOR Network
b) Insert enough INVERTERS in each of these connecting paths so that the
number of inversion bubbles on gate inputs or outputs has the same
parity (i.e., odd or even) as the corresponding path in the original
network N 1.
7
o Algorithm 2: (Converts network N1 of inverters, o Example of Transformation to a NAND Network:
AND gates, OR gates, NAND gates, and NOR gates
into network N2 containing only NOR Gates) A 1
Step 1. 3 4
a) Replace each OR gate symbol in the diagram of N1 by the symbol for B 2 6 Z
a NOR gate. 5
C
b) Replace each AND gate or NAND gate symbol in the diagram of N1 by the Original Network N1
!!!!!!!!symbol for a NOR gate.
c) Replace all INVERTERS in the diagram of N 1 by a direct connection. A 1
3
Step 2. B 2
4
6 Z
Same as for Algorithm 1. C 5
Intermediate Network After Step 1
o Networks with NANDs and NORs

n The first steps of these previous two algorithms can be A 1
easily combined to get an algorithm that produces a 3

4
network containing both NAND and NOR gates. B 2
6 Z
5
C
NAND Network N2
o Example of Transformation to a NAND and a NOR Network: o Exercise:

n Derive logical expressions, using only the logical
operations • , + and ', for the following two networks.
A
B
Z
C
D A B C D E
Original Network N1
X
A
Net 1
B
Z
C
D
NAND Network N2 A B C D E
A X
B
Z Net 2
C
D
NOR Network N2
8
2.6. An Introduction to Verilog
o Verilog is a programming language that was o Verilog Uses
developed for describing the behavior and structure n Verilog can be viewed as a simulation modeling language
of digital systems. Languages such as this are called u Enables digital designers to simulate and verify the behavior of
Hardware Description Languages or HDL’s. their systems before they design a detailed implementation.
l Verification of functional behavior
n Verilog is an IEEE standard and widely used today. l Timing analysis
n Verilog is probably most useful for describing systems at a n Verilog is also used to specify the input to synthesis tools
high-level of abstraction, before the implementation details that produce implementations automatically.
of the systems are developed. u When this is possible, the designer need not use the classical design
u While HDL’s have been around for 30 years, it has only been with techniques.
the advent of large integrated circuits that they have become
popular with digital designers.
l Why?
o Verilog Modules o Example of a behavioral Verilog module

n An elementary Verilog program is called a module. n Circuit:
E D C B A
u A module corresponds to a digital circuit.
X
u Modules have input and output ports that correspond to the input
and output terminals of a digital circuit.
Y
u The ports and variables used to represent internal signals are
declared at the beginning of the program.
Z
u Modules have other statements used to define how it transforms the
input signals to output signals.
n Verilog modules can be used to specify the structure or the n Verilog module:
behavior of a digital circuit.
module circuit1b (A, B, C, D, E, X, Y, Z);
u Structural modules consist of a list of component modules (defined
input A, B, C, D, E;
elsewhere) and a list of wires used to interconnect the modules.
output X, Y, Z;
u Behavior modules specify the output signals as functions of the assign X = ~((A ^ B) | C);
input signals. They need not give any indication of the structure of
assign Y = ~((B & C) | D) & E;
the circuit.
assign Z = A | D | (B & C);
endmodule
9
n Comments on the module
u Case matters in Verilog statements.
u The three assign statements are independent and can execute in any
l The symbol string “Out”, “out”, and “OUT” represent three different variables.
order or concurrently.
u Individual signals (e.g., A, B, … in the previous example) can take l The right side of an assign statement is evaluated and its resulting value
any of the following four values: assigned to the signal on the left side whenever one of the signals used in the
l 0 = logic value 0 right side changes value.
l 1 = logic value 1 t This type of assignment is also called a continuous assignment.
l z = tri-state (high impedance) l This method of interpreting the execution of assign statements is quite different
from that use in conventional programming languages in the following ways:
l x = unknown value
t Two or more assignments can execute simultaneously. This is necessary to represent
u The unknown value is used by simulators to indicate that they do timing characteristics of hardware systems.
not know how to determine a signals value (e.g., the user has not t An assignment executes whenever it is ready (i.e., has new data for the variables on
specified a value for an input signal). The tri-state value means that its right side)
t There is no concept of "locus of control" or “program counter” that determines the
no signal is assigned to the variable. next instruction to execute. Therefore, the order the assignments are written does not
u Note that ports must be listed in the module statement (first line) matter
and their direction (input or output) declared in the following l This method of assignment statement execution is sometimes called
statements. non-procedural or data-driven execution, where conventional
programming languages are said to be procedural.
o Behavioral vs. Structural Verilog Descriptions

n The previous example is a behavioral descriptions because module circuit1s (A, B, C, D, E, X, Y, Z);
input A, B, C, D, E;
it specifies the logical values of the circuit's outputs as output X, Y, Z;
logical equations with no reference to how the gates in a wire T1, T2, T3, T4, T5, T6, T7;
possible implementation might be interconnected.
xor(T1, A, B);
n It is also possible to specify a structural description in or(T2, T1, C); E D C B A
Verilog that specifies explicitly how a set of smaller not(X, T2);
T1 T2
X
components (e.g., gates) are interconnected to form a larger and(T3, B, C);
T3 T4 T5
system as shown on the following slide. or(T4, T3, D); Y
not(T5, T4);
u Note that the internal connections from gate outputs to gate inputs
and(Y, T5, E); T6
are declared to be of type wire. Z
or(T6, A, D); T7
l These wire declarations could be omitted as long as the component modules
are simple gates. Verilog will assume that any gate output signal that is not and(T7, B, C);
declared is of type wire. or(Z, T6, T7);
u Each gate is specified by its name (e.g., and, or, …) and a list of
endmodule
ports or wires connected to its terminals. All gates have a single
output and it is always listed first in this list.
10
o Always Blocks n Example
n A procedural block is a construct that contains statements
that are executed procedurally (i.e., in the order they are module always_example(x, y, z);
written). input x, y;
always @(sensitivity_list) output z;
begin reg z, s;
procedural statements
end always @(x or y)
begin
n The sensitivity list is a list of signals separated by or. s = x ^ y;
u When any one of the signals in the sensitivity list changes value,
the always block wakes up, executes its procedural statements, and z = x & s;
the goes back to sleep. end
u Unfortunately, the Altera compiler does not support this feature
very well. endmodule
n The always block acts like a generalized assign statement
where the action that takes place can be specified by
sequential code.
n Variables declared as type reg hold their value until they module mux1 (x1, x2, s, y); module mux2 (x1, x2, s, y);
are assigned a new value. It is said that the assigned value input x1, x2, s; input x1, x2, s;
is registered in the variable output y; output y;
n Whenever x or y changes value, the always block is reg y;
assign y = (s & x1) | (~s & x2);
executed as follows:
u First, the statement s = x^y executes and registers a new value in s always @(x1 or x2 or s)
endmodule
if (s == 1)
u Next, the statement z = x & s executes using the new value of s that
it received when the first statement was executed. y = x1;
u Then the blocks stops executing and waits for either x or y to else
change again. y = x2;
endmodule
n Variables on the left side of a procedural statement must be
declared as type reg.
n The main advantage of using always blocks to represent
combinational circuits is that you can use control u Modules mux1 and mux2 do exactly the same thing.
statements such as “if then else” as illustrated by the u The control statements used in always blocks will be covered in
following example more detail in later chapters.
11
n Exercise: Explain how the behaviors of the following two 2.9. Tips and Tricks
modules differ.
o Think of the bubbles on gates as inverters
n Thus is equivalent to
module always_example(x, y, z, f); module assign_example (x, y, z, f); o Think of Exclusive Or and Equivalence as a parity circuits that
input x, y, z; input x, y, z; produce a 1 out if the number of 1's in is odd or even
output f; output f;
reg f, s; wire s;
respectively.
o Be aware that you can make an inverter from an Exclusive OR
always @(x or y or z) assign s = x ^ y;
begin assign f = z & s; o Use the alternative NAND/NOR symbols to emphasize the
s = x ^ y; logical functions of the gates.
f = z & s; endmodule o A two-level NAND-NAND network is equivalent to a two-
end
level AND-OR network and both realize Sum-of-Product
endmodule
logical expressions.
o A two-level NOR-NOR network is equivalent to a two-level
n How would the behavior of each of these modules change if OR-AND network and both realize Product-of-Sums logical
the order of the two assignment statements is reversed?
expressions.
2.10. Pitfalls 2.11. Review

o Not realizing that is a NAND gate or is a o The nature of binary-valued signals and how they
NOR gate and not using them where appropriate. relate to continuous measured signal values (the 3
n Not using them is not logically incorrect, but it can ranges of 0, 1, and unstable).
make logic diagram more difficult to read and lead to
errors. n What are the advantage of binary-valued signals?
o Using the ↑ and Ø for NAND and NOR o The relationship between logical networks, logical
n Again, they are not wrong, just not very useful. expressions and truth tables.
o Forgetting that case matters in Verilog names. o The relationship between combination networks,
sequential networks and loops in networks.
o Forgetting that “assign” statements in Verilog
are executed in parallel and are “data-driven.” o The alternative NAND and NOR symbols.
12

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2.

Gates and Logic Networks

2.1. Binary Valued Signals

high and low voltages.

o Types of networks o Exercise:

u The value of this notation is that it is a more compact way of

n Example n Two level gate networks and logical expressions

u Two level AND-OR Networks

n Approach: First design the network with AND, OR and A A

NAND or NOR gates.

n NOR Network Example

o Networks with NANDs and NORs

easily combined to get an algorithm that produces a 3

o Example of Transformation to a NAND and a NOR Network: o Exercise:

o Verilog Modules o Example of a behavioral Verilog module

o Behavioral vs. Structural Verilog Descriptions

2.10. Pitfalls 2.11. Review

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