Power losses for inductive load switching

A comparison between dynamic power losses with resistive or inductive loads is sketched in
the figure below, where the instantaneous power dissipation for the two cases are plotted
during a turn-on phase of 200 ns, for the case of IMAX = 10 A, VMAX = 10V: for the case of
inductive load, the average power dissipation PDd is more than three times larger than for the
resistive load.
120
I
100
Power dissipation, W

IMAX
80

60 resistive load
inductive load

40

20
VMAX V

0
Operation point movement during turn-on (the
0 100 200 ns
0 5 10 15 opposite path is true for turn-off)

Even in that case, the switching power can be handled by the device, provided that IMAX
and VMAX are contained in the device ratings, because the operation point will move
along the limits of the square SOA assumed for the fast switching times.

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Dept of Electronics and Telecommunications Power Devices and Circuits 2012
A further effect, that must be pointed out for the case of dynamic power losses with inductive
switching, is the modification of the switching locus due to the effects of diode reverse
recovery and stray inductance .
With reference to the simplified circuit in figure (assuming as example a BJT as the active
device), with an inductive load with a fly-back diode, we have at turn-on a current overshoot
in the IV locus at VCE = VCC due to the reverse current IR of the diode that adds to the IL
current, increasing the ICMAX value. For the turn-off locus we have instead a voltage
overshoot due to the added effect of the parasitic stray inductance: when the current IC starts
to decrease

IC IC

IL ID

IC luogo I-V turn-on luogo I-V turn-off

VCE VCE

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Dept of Electronics and Telecommunications Power Devices and Circuits 2012
 Snubber circuits
To reduce the power dissipation into the device during switching and to protect it from
overvoltage and overcurrent caused by nonideal circuit components, some circuits named
snubber circuits can be used; they are basically made by some additional passive elements
networks ( in the schematic these are reported for both the turn-on and the turn-off switching).

IL
In the above schematic the R2-C2-D2 network is
the turn-off snubber, while the R1-L1-D1 network
is the turn-on snubber; these circuits are inserted
in a basic MOS switching circuit made by the
inductance L and recirculating diode D.

The snubber networks are used to change the

locus of operating point of the active device
during switching, that will differ from the square
path indicated in the first slide.
These circuits will reduce the power dissipation
into the active device, at the expense of a slower
switching time of the circuit.

University Federico II Paolo Spirito

Dept of Electronics and Telecommunications Power Devices and Circuits 2012
 Turn-off snubber circuit
To avoid overvoltage problem during turn-off, the turn-off
snubber can provide a reduction of the collector voltage
IL while the current is going to zero. The analysis is done
with reference to a MOS, but it equally applies to a BJT.

In the ON state the collector voltage of the MOS is low

and the capacitor C2 is discharged at the same voltage
through R2.
During the turn-off from a given current IL, the drain
voltage begin to rise, and the diode D2 becomes forward
biased. Then the drain current ID, instead to be constant
will decrease, because the difference IL- ID will flow into
the diode D2, charging the capacitor C2, and the drain
IL voltage VDS will be linked to the one of C2, that is
increasing at a slower rate.
ID

IL The path of the operating point of the MOS will be then

the green line indicated in the bottom plot; the effect on
the reduction of the power dissipation in the MOS is more
pronounced if the value of C2 is larger, but this reduction
will be at the expense of an increase of the switching
VDD VDS time, due to the time required to charge the capacitance.

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Dept of Electronics and Telecommunications Power Devices and Circuits 2012
 ID
The effect of the value of C2 can be sketched in this plot.
IL If C2 is too small, it will charge at faster time, reaching the
supply value VDD before the drain current ID is decreased
C small to zero. Then a part of the operating point locus will reach
the max voltage limit.
If the value of C2 is too large, then it is still charging when
C limit the drain current has reached zero value, but in this latter
case the voltage rise time in turn-off is slowered, and the
C large switching losses of the MOS + the snubber circuit will
increase. The best choice is to use a value of C2 (C limit)
VDD VDS
that will bring the drain current to zero joust at time when
the drain voltage reaches the VDD limit.

I, V C small I, V C limit I, V C large

VD VD VD
ID ID ID

IC2 IC2 IC2

t t t
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Dept of Electronics and Telecommunications Power Devices and Circuits 2012
 In steady-state operation one must recall that the
charge stored in the capacitance C2 during turn-off
must be eliminated during the following turn-on of the
MOS.

This is done by the discharge of the capacitance C2 into

the MOS at turn-on, through the resistance R2 (the
diode D2 is in off state in that phase because the
voltage across C2 during discharge is larger than the
drain voltage VON of the MOS).
The lower the value of R2, the larger will be the peak
current that will flow into the MOS: this increase of the
drain current will pose a lower limit on the resistance
value to limit the increase of the power losses during
turn-on due to the presence of the snubber circuit.

On the other hand, larger values of the resistance will increase the discharge time of C2,
and then the total turn-on time will be increased. For shorted Ton times and large R2
values it could happen than C2 can not completely discharge before the next turn-off.
A good choice is to choose an R2 value that will give a peak current into the MOS during
discharge lower than the peak current given by the reverse recovery of the main flyback
diode D. Assuming the increase of drain current ΔID = VDD/R2 < IRR, a rough value can be
assumed for R2 as: R2 > VDD/IRR
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Dept of Electronics and Telecommunications Power Devices and Circuits 2012
50
R2 = 5 ohm
PD tot As an example of the effect of C2 values on the
dynamic power dissipation of the MOS using
40
turn-off snubber is reported in this graphic.
PD ton Here the Pd losses both in turn-on and in turn-
30 off, and the total losses of the MOS are
reported for different C2 values, for the turn-off
20
snubber circuit indicated before, with VDD =
PD toff 100V, and a current IL of 10A.
A FR diode is used , with Irr = 20 A, so the R2
10
value chosen is 5 ohm.

0
0 1000 2000 3000 4000 C2 pF 5000
One can note that, when the C2 value is
increased, the turn-off losses will decrease, but
the turn-on losses will increase, because the
energy stored in C2 during turn-off will be
released to the MOS during turn-on.
Then the ratio between turn-on and turn-off
losses will wary if C2 is varied, while the total
losses remain constant.

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Dept of Electronics and Telecommunications Power Devices and Circuits 2012
 Turn-on snubber circuit

The turn-on snubber circuit is employed to decrease the voltage

across the switching device during the current rise, to reduce the
IL power dissipation during the turn-on. It will also allow to reduce
the overcurrent in the switching device M due to the reverse
recovery of the flyback diode D, because of the slower rate of
rise of the current.

The voltage reduction on the MOS during the current rise is due
to the voltage drop across the inductance L1 that will subtract a
part of the VDD voltage from the drain voltage of the MOS during
turn-on.
The slower current rise due to the snubber network will also
contribute to a decrease of the reverse current of the flyback
diode D during the reverse recovery, and then it will limit the
ID overcurrent across the switching device (MOS in this case), if
the L1 is chosen large enough to limit the current rate of rise.
IL
The energy stored in the snubber inductance L1 during turn-on
must be discharged into the resistance R1 and diode D1 during
turn-off, and this release should be done in a time lower than the
Toff, to allow energy storage at the following turn-on.
VDD VDS
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Dept of Electronics and Telecommunications Power Devices and Circuits 2012
 The effect of the value of L1 on the turn-on snubber can be sketched in these plots.

The linear rise of the current will give a constant voltage drop across the inductance L1 of the
snubber, that will be subtracted to the supply voltage VDD .

If L1 is small, the voltage drop is small, and the voltage across the device is still large. The turn-
on will be faster, but the power losses on the device are quite large.
When the value of L1 increases, the voltage drop atross it will increase, and the current rise is
slowerd. The turn-on is slowered but the power losses on the device are reduced.
To reduce the overcurrent due to the reverse recovery of the diode D, the inductance L1 must be
increased largely, to slow down the rate of rise of the current, and reduce the reverse current Irr

I, V L1 small I, V L1 medium I, V L1 large

VD VD VD
ID

ID ID

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Dept of Electronics and Telecommunications Power Devices and Circuits 2012
As an example of the effect of L1 values on the dynamic power dissipation of the MOS using a
turn-on snubber is reported in this graphic.

Here the dynamic Pd losses either in turn-on or in turn-off, and the total losses of the MOS are
reported for different L1 values, for the turn-on snubber circuit indicated before, with VDD = 100V,
and a current IL in the inductance L of 10A. A FR diode is used , with Irr = 20 A.

50

R1 = 0.5 ohm In the case of turn-on snubber, the

40
Pd tot total power losses are decreasing
with the decrease of tun-on losses.
30
This is due to the fact that the total
losses are largely due to the turn-on
Pd ton
losses, due to the reverse recovery
20
overcurrent.
Furhermore, in this circuit, the energy
Pd toff
10
stored in the inductance during turn-
on will be discharged into R1 and D1,
0 L1 uH and not in the switching device M.
0,00 0,01 0,02 0,03 0,04 0,05 0,06 0,07 0,08 0,09 0,10

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Dept of Electronics and Telecommunications Power Devices and Circuits 2012