Color Television Chassis

L11M1.1L
LA

19132_000_111221.eps
111221

Contents Page 313912365231 SSB Layout 100

1. Revision List 2 J 272217100896 IR/LED 102
2. Technical Specifications and Connections 2 J 272217190275 IR/LED 104
3. Precautions, Notes, and Abbreviation List 6 E 272217190347 Leading Edge Module 106
4. Mechanical Instructions 10 E 272217190276 Keyboard 108
5. Service Modes, Error Codes, and Fault Finding 19 T01 313912365071 109
6. Alignments 25 11. Styling Sheets
7. Circuit Descriptions 28 Styling Sheet Thriller 32" 116
8. IC Data Sheets 37 Styling Sheet Thriller 40" 117
9. Block Diagrams Styling Sheet Berlinale 32" 118
Wiring Diagram 32" (Thriller) 45 Styling Sheet Berlinale 40" 119
Wiring Diagram 40" (Thriller) 46
Wiring Diagram 32" (Berlinale) 47
Wiring Diagram 40" (Berlinale) 48
Block Diagram Video 3939 123 65052 49
Block Diagram Audio 3939 123 65052 50
Block Diagram Control & Clock Signals 3939 123
65052 51
Block Diagram I2C 3939 123 65052 52
Supply Lines Overview 3939 123 65052 53
Block Diagram Video 3939 123 65231 54
Block Diagram Audio 3939 123 65231 55
Block Diagram Control & Clock Signals 3939 123
65231 56
Block Diagram I2C 3939 123 65231 57
Supply Lines Overview 3939 123 65231 58
10. Circuit Diagrams and PWB Layouts
A 272217190323 - 272217190353 PSL 59
A 272217190354 PSL 62
A 272217190355 - 272217190359 PSL 65
B01 313912365052 68
B02 313912365052 69
B03 313912365052 71
B04 313912365052 72
B05 313912365052 76
B06 313912365052 78
B07 313912365052 82
313912365052 SSB Layout 83
B01 313912365231 85
B02 313912365231 86
B03 313912365231 88
B04 313912365231 89
B05 313912365231 93
B06 313912365231 95
B07 313912365231 99

Published by ER/JY 1267 Quality Printed in the Netherlands Subject to modification EN 3122 785 19134
2012-Jul-20

2012 © TP Vision Netherlands B.V.

All rights reserved. Specifications are subject to change without notice. Trademarks are the
property of Koninklijke Philips Electronics N.V. or their respective owners.
TP Vision Netherlands B.V. reserves the right to change products at any time without being obliged to adjust
earlier supplies accordingly.
PHILIPS and the PHILIPS’ Shield Emblem are used under license from Koninklijke Philips Electronics N.V.
 EN 2 1. L11M1.1L LA Revision List

1. Revision List
Manual xxxx xxx xxxx.0 Manual xxxx xxx xxxx.2
• First release. • Chapter 2: Table 2-1 updated (added Thriller CTNs).
• Chapter 7: changed PSU repair policy; see sections 5.7
Manual xxxx xxx xxxx.1 and 7.2.1.
• Chapter 2: Table 2-1 updated (added Berlinale CTNs).
• Chapter 4: added wiring diagrams; see section 4.1. Manual xxxx xxx xxxx.3
• Chapter 6: added white tone alignment data, see section • Chapter 7: added safety instruction; see section 7.2.1.
6.3.
• Chapter 7: added Berlinale architecture diagrams; see Manual xxxx xxx xxxx.4
section 7.1. • Chapter 6: added white tone values 32" and 40" Berlinale
FHD; see Table 6-5 and Table 6-6.

2. Technical Specifications and Connections

Index of this chapter:
2.1 Technical Specifications
2.2 Directions for Use 2.1 Technical Specifications
2.3 Connections For on-line product support please use the links in Table 2-1.
Here is product information available, as well as getting started,
Notes: user manuals, frequently asked questions and software &
• Figures can deviate due to the different set executions. drivers.
• Specifications are indicative (subject to change).

Table 2-1 Described Model Numbers and Diversity

SSB 2 4 9 10
Mechanics Block Diagrams Schematics

E (Keyboard/Leading Edge)

T01 (LVDS Display, TCON

B04 (Power, DDR, LVDS)
B02 (Tuner & Dig. Dem.)

B06 (analog I/O, VGA)

Connection Overview

B03 (Class D & mute)

Assembly Removal

B05 (HDMI, USB)

B07 (Hospitality)
Control & Clock
Wiring Diagram
3139 123 xxxxx

Wire Dressing

Power Supply
LCD Removal

B01 (DC-DC)
Supply lines

J (IR/LED)
Dressing

Audio
Video

I2C

CTN Styling
32PFL3406D/77 Thriller 65052 2-1 4-1 4.3 4.3.2 9-1 9-5 9-6 9-7 9-8 9-9 - 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.23 10.20 -
11-1
32PFL3406D/78 Thriller 65052 2-1 4-1 4.3 4.3.2 9-1 9-5 9-6 9-7 9-8 9-9 - 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.23 10.21 -
11-1
32PFL3606D/77 Thriller 65052 2-1 4-1 4.3 4.3.2 9-1 9-5 9-6 9-7 9-8 9-9 - 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.23 10.20 -
11-1
32PFL3606D/78 Thriller 65052 2-1 4-1 4.3 4.3.2 9-1 9-5 9-6 9-7 9-8 9-9 - 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.23 10.21 -
11-1
32PFL5606D/77 Berlinale 65231 2-2 4-3 4.4 4.4.8 9-3 9-10 9-11 9-12 9-13 9-14 10.2 10.12 10.13 10.14 10.15 10.16 10.17 10.18 10.23 - -
11-3
32PFL5606D/78 Berlinale 65231 2-2 4-3 4.4 4.4.8 9-3 9-10 9-11 9-12 9-13 9-14 10.2 10.12 10.13 10.14 10.15 10.16 10.17 10.18 10.22 - -
11-3
40PFL3606D/78 Thriller 65052 2-1 4-2 4.3 4.3.2 9-2 9-5 9-6 9-7 9-8 9-9 - 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.23 10.21 10.24
11-2
40PFL5606D/77_1 Berlinale 65231 2-2 4-4 4.4 4.4.8 9-4 9-10 9-11 9-12 9-13 9-14 10.3 10.12 10.13 10.14 10.15 10.16 10.17 10.18 10.22 - -
11-4
40PFL5606D/77_2 Berlinale 65231 2-2 4-4 4.4 4.4.8 9-4 9-10 9-11 9-12 9-13 9-14 10.3 10.12 10.13 10.14 10.15 10.16 10.17 10.18 10.22 - -
11-4
40PFL5606D/77_3 Berlinale 65231 2-2 4-4 4.4 4.4.8 9-4 9-10 9-11 9-12 9-13 9-14 10.1 10.12 10.13 10.14 10.15 10.16 10.17 10.18 10.22 - -
11-4
40PFL5606D/78_1 Berlinale 65231 2-2 4-4 4.4 4.4.8 9-4 9-10 9-11 9-12 9-13 9-14 10.3 10.12 10.13 10.14 10.15 10.16 10.17 10.18 10.22 - -
11-4
40PFL5606D/78_2 Berlinale 65231 2-2 4-4 4.4 4.4.8 9-4 9-10 9-11 9-12 9-13 9-14 10.3 10.12 10.13 10.14 10.15 10.16 10.17 10.18 10.22 - -
11-4
40PFL5606D/78_3 Berlinale 65231 2-2 4-4 4.4 4.4.8 9-4 9-10 9-11 9-12 9-13 9-14 10.1 10.12 10.13 10.14 10.15 10.16 10.17 10.18 10.22 - -
11-4

2.2 Directions for Use

You can download this information from the following websites:
http://www.philips.com/support
http://www.p4c.philips.com

2012-Jul-20 back to
div. table
 Technical Specifications and Connections L11M1.1L LA 2. EN 3

2.3 Connections

REAR CONNECTORS SIDE CONNECTORS

DIGITAL AUDIO IN
CVI 1 AUDIO OUT SERV.U DVI/VGA

R L Pr Pb Y

4 5 6 7

BOTTOM REAR CONNECTORS 2

8 9 10 11

3
R L Pr Pb Y HDMI 1 VGA
(ARC)
CVI 2 ANTENNA

19130_001_110421.eps
110421

Figure 2-1 Connection overview Thriller (xxPFL3x06/xx)

REAR CONNECTORS SIDE CONNECTORS

1
6 4 5 7

BOTTOM REAR CONNECTORS

8 12 9 10 11 2

19131_021_110623.eps
110623

Figure 2-2 Connection overview Berlinale (xxPFL5x06/xx)

back to 2012-Jul-20
div. table
 EN 4 2. L11M1.1L LA Technical Specifications and Connections

Note: The following connector color abbreviations are used 2.3.3 Bottom Connections
(according to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green,
Gy= Grey, Rd= Red, Wh= White, Ye= Yellow. 8 - CVI-2: Cinch: Video YPbPr - In, Audio - In
Wh - Audio - L 0.5 VRMS / 10 k jq
2.3.1 Side Connections Rd - Audio - R 0.5 VRMS / 10 k jq
Rd - Video Pr 0.7 VPP / 75  jq
1 - USB2.0 Bu - Video Pb 0.7 VPP / 75  jq
Gn - Video Y 1 VPP / 75  jq
1 2 3 4
10000_022_090121.eps 9 - HDMI1 Audio Return Channel: Digital Video, Digital
090121
Audio - In
Figure 2-3 USB (type A) 19 1
18 2

10000_017_090121.eps
1 - +5V k 090428
2 - Data (-) jk
3 - Data (+) jk Figure 2-5 HDMI (type A) connector
4 - Ground Gnd H
1 - D2+ Data channel j
2 - AV IN: Cinch: Video CVBS - In, Audio - In 2 - Shield Gnd H
Ye - Video CVBS 1 VPP / 75 ohm jq 3 - D2- Data channel j
Wh - Audio L 0.5 VRMS / 10 kohm jq 4 - D1+ Data channel j
Rd - Audio R 0.5 VRMS / 10 kohm jq 5 - Shield Gnd H
6 - D1- Data channel j
3 - HDMI: Digital Video, Digital Audio - In 7 - D0+ Data channel j
8 - Shield Gnd H
19 1
18 2 9 - D0- Data channel j
10 - CLK+ Data channel j
10000_017_090121.eps
090428 11 - Shield Gnd H
12 - CLK- Data channel j
Figure 2-4 HDMI (type A) connector 13 - Easylink Control channel/CEC jk
14 - ARC Audio Return Channel j
1 - D2+ Data channel j 15 - DDC_SCL DDC clock j
2 - Shield Gnd H 16 - DDC_SDA DDC data jk
3 - D2- Data channel j 17 - Ground Gnd H
4 - D1+ Data channel j 18 - +5V j
5 - Shield Gnd H 19 - HPD Hot Plug Detect j
6 - D1- Data channel j 20 - Ground Gnd H
7 - D0+ Data channel j
8 - Shield Gnd H 10 - Aerial - In
9 - D0- Data channel j - - F-type Coax, 75  D
10 - CLK+ Data channel j
11 - Shield Gnd H 11 - VGA: Video RGB - In
12 - CLK- Data channel j 1 5
13 - Easylink Control channel/CEC jk 6
10

14 - n.c. 11 15

15 - DDC_SCL DDC clock j 10000_002_090121.eps

16 - DDC_SDA DDC data jk 090127

17 - Ground Gnd H
Figure 2-6 VGA Connector
18 - +5V j
19 - HPD Hot Plug Detect j
20 - Ground Gnd H 1 - Video Red 0.7 VPP / 75  j
2 - Video Green 0.7 VPP / 75  j
3 - Video Blue 0.7 VPP / 75  j
2.3.2 Rear Connections
4 - n.c.
5 - Ground Gnd H
4 - CVI-1: Cinch: Video YPbPr - In, Audio - In 6 - Ground Red Gnd H
Wh - Audio - L 0.5 VRMS / 10 k jq 7 - Ground Green Gnd H
Rd - Audio - R 0.5 VRMS / 10 k jq 8 - Ground Blue Gnd H
Rd - Video Pr 0.7 VPP / 75  jq 9 - +5VDC +5 V j
Bu - Video Pb 0.7 VPP / 75  jq 10 - Ground Sync Gnd H
Gn - Video Y 1 VPP / 75  jq 11 - n.c.
12 - DDC_SDA DDC data j
5 - Cinch: Digital Audio - Out 13 - H-sync 0-5V j
Bk - Coaxial 0.4 - 0.6VPP / 75 ohm kq 14 - V-sync 0-5V j
15 - DDC_SCL DDC clock j
6 - Service Connector (UART)
1 - Ground Gnd H 12 - HDMI2: Digital Video, Digital Audio - In (optional)
2 - UART_TX Transmit k
3 - UART_RX Receive j 19
18 2
1

10000_017_090121.eps
7 - Mini Jack: Audio - In DVI/VGA 090428
Bk - Audio 0.5 VRMS / 10 k jo
Figure 2-7 HDMI (type A) connector

2012-Jul-20 back to
div. table
 Technical Specifications and Connections L11M1.1L LA 2. EN 5

1 - D2+ Data channel j

2 - Shield Gnd H
3 - D2- Data channel j
4 - D1+ Data channel j
5 - Shield Gnd H
6 - D1- Data channel j
7 - D0+ Data channel j
8 - Shield Gnd H
9 - D0- Data channel j
10 - CLK+ Data channel j
11 - Shield Gnd H
12 - CLK- Data channel j
13 - Easylink Control channel/CEC jk
14 - n.c.
15 - DDC_SCL DDC clock j
16 - DDC_SDA DDC data jk
17 - Ground Gnd H
18 - +5V j
19 - HPD Hot Plug Detect j
20 - Ground Gnd H

back to 2012-Jul-20
div. table
 EN 6 3. L11M1.1L LA Precautions, Notes, and Abbreviation List
3. Precautions, Notes, and Abbreviation List
Index of this chapter:
3.1 Safety Instructions
3.2 Warnings
3.3 Notes
3.4 Abbreviation List
3.1 Safety Instructions
Safety regulations require the following during a repair:
• Connect the set to the Mains/AC Power via an isolation
transformer (> 800 VA).
• Replace safety components, indicated by the symbol h,
only by components identical to the original ones. Any
other component substitution (other than original type) may
increase risk of fire or electrical shock hazard.
Safety regulations require that after a repair, the set must be
returned in its original condition. Pay in particular attention to
the following points:
• Route the wire trees correctly and fix them with the
mounted cable clamps.
• Check the insulation of the Mains/AC Power lead for
external damage.
• Check the strain relief of the Mains/AC Power cord for
proper function.
• Check the electrical DC resistance between the Mains/AC
Power plug and the secondary side (only for sets that have
a Mains/AC Power isolated power supply):
1. Unplug the Mains/AC Power cord and connect a wire
between the two pins of the Mains/AC Power plug.
2. Set the Mains/AC Power switch to the “on” position
(keep the Mains/AC Power cord unplugged!).
3. Measure the resistance value between the pins of the
Mains/AC Power plug and the metal shielding of the
tuner or the aerial connection on the set. The reading
should be between 4.5 M and 12 M.
4. Switch “off” the set, and remove the wire between the
two pins of the Mains/AC Power plug.
• Check the cabinet for defects, to prevent touching of any
inner parts by the customer.
3.2 Warnings
• All ICs and many other semiconductors are susceptible to
electrostatic discharges (ESD w). Careless handling
during repair can reduce life drastically. Make sure that,
during repair, you are connected with the same potential as
the mass of the set by a wristband with resistance. Keep
components and tools also at this same potential.
• Be careful during measurements in the high voltage
section.
• Never replace modules or other components while the unit
is switched “on”.
• When you align the set, use plastic rather than metal tools.
This will prevent any short circuits and the danger of a
circuit becoming unstable.
3.3 Notes
3.3.1 General
• Measure the voltages and waveforms with regard to the
chassis (= tuner) ground (H), or hot ground (I), depending
on the tested area of circuitry. The voltages and waveforms
shown in the diagrams are indicative. Measure them in the
Service Default Mode with a colour bar signal and stereo
sound (L: 3 kHz, R: 1 kHz unless stated otherwise) and
picture carrier at 475.25 MHz for PAL, or 61.25 MHz for
NTSC (channel 3).
• Where necessary, measure the waveforms and voltages
with (D) and without (E) aerial signal. Measure the
voltages in the power supply section both in normal
operation (G) and in stand-by (F). These values are
indicated by means of the appropriate symbols.
2012-Jul-20
div. table
3.3.2 Schematic Notes
• All resistor values are in ohms, and the value multiplier is
often used to indicate the decimal point location (e.g. 2K2
indicates 2.2 k).
• Resistor values with no multiplier may be indicated with
either an “E” or an “R” (e.g. 220E or 220R indicates 220 ).
• All capacitor values are given in micro-farads (  10-6),
nano-farads (n  10-9), or pico-farads (p  10-12).
• Capacitor values may also use the value multiplier as the
decimal point indication (e.g. 2p2 indicates 2.2 pF).
• An “asterisk” (*) indicates component usage varies. Refer
to the diversity tables for the correct values.
• The correct component values are listed on the Philips
Spare Parts Web Portal.
3.3.3 Spare Parts
For the latest spare part overview, consult your Philips Spare
Part web portal.
3.3.4 BGA (Ball Grid Array) ICs
Introduction
For more information on how to handle BGA devices, visit this
URL: http://www.atyourservice-magazine.com. Select
“Magazine”, then go to “Repair downloads”. Here you will find
Information on how to deal with BGA-ICs.
BGA Temperature Profiles
For BGA-ICs, you must use the correct temperature-profile.
Where applicable and available, this profile is added to the IC
Data Sheet information section in this manual.
3.3.5 Lead-free Soldering
Due to lead-free technology some rules have to be respected
by the workshop during a repair:
• Use only lead-free soldering tin. If lead-free solder paste is
required, please contact the manufacturer of your soldering
equipment. In general, use of solder paste within
workshops should be avoided because paste is not easy to
store and to handle.
• Use only adequate solder tools applicable for lead-free
soldering tin. The solder tool must be able:
– To reach a solder-tip temperature of at least 400°C.
– To stabilize the adjusted temperature at the solder-tip.
– To exchange solder-tips for different applications.
• Adjust your solder tool so that a temperature of around
360°C - 380°C is reached and stabilized at the solder joint.
Heating time of the solder-joint should not exceed ~ 4 sec.
Avoid temperatures above 400°C, otherwise wear-out of
tips will increase drastically and flux-fluid will be destroyed.
To avoid wear-out of tips, switch “off” unused equipment or
reduce heat.
• Mix of lead-free soldering tin/parts with leaded soldering
tin/parts is possible but PHILIPS recommends strongly to
avoid mixed regimes. If this cannot be avoided, carefully
clear the solder-joint from old tin and re-solder with new tin.
3.3.6 Alternative BOM identification
It should be noted that on the European Service website,
“Alternative BOM” is referred to as “Design variant”.
The third digit in the serial number (example:
AG2B0335000001) indicates the number of the alternative
B.O.M. (Bill Of Materials) that has been used for producing the
specific TV set. In general, it is possible that the same TV
model on the market is produced with e.g. two different types
of displays, coming from two different suppliers. This will then
back to
 Precautions, Notes, and Abbreviation List L11M1.1L LA 3. EN 7

result in sets which have the same CTN (Commercial Type 6 = play 16 : 9 format, 12 = play 4 : 3
Number; e.g. 28PW9515/12) but which have a different B.O.M. format
number. AARA Automatic Aspect Ratio Adaptation:
By looking at the third digit of the serial number, one can algorithm that adapts aspect ratio to
identify which B.O.M. is used for the TV set he is working with. remove horizontal black bars; keeps
If the third digit of the serial number contains the number “1” the original aspect ratio
(example: AG1B033500001), then the TV set has been ACI Automatic Channel Installation:
manufactured according to B.O.M. number 1. If the third digit is algorithm that installs TV channels
a “2” (example: AG2B0335000001), then the set has been directly from a cable network by
produced according to B.O.M. no. 2. This is important for means of a predefined TXT page
ordering the correct spare parts! ADC Analogue to Digital Converter
For the third digit, the numbers 1...9 and the characters A...Z AFC Automatic Frequency Control: control
can be used, so in total: 9 plus 26= 35 different B.O.M.s can be signal used to tune to the correct
indicated by the third digit of the serial number. frequency
AGC Automatic Gain Control: algorithm that
Identification: The bottom line of a type plate gives a 14-digit controls the video input of the feature
serial number. Digits 1 and 2 refer to the production centre (e.g. box
SN is Lysomice, RJ is Kobierzyce), digit 3 refers to the B.O.M. AM Amplitude Modulation
code, digit 4 refers to the Service version change code, digits 5 AP Asia Pacific
and 6 refer to the production year, and digits 7 and 8 refer to AR Aspect Ratio: 4 by 3 or 16 by 9
production week (in example below it is 2010 week 10 / 2010 ASF Auto Screen Fit: algorithm that adapts
week 17). The 6 last digits contain the serial number. aspect ratio to remove horizontal black
bars without discarding video
information
ATSC Advanced Television Systems
Committee, the digital TV standard in
the USA
ATV See Auto TV
Auto TV A hardware and software control
system that measures picture content,
and adapts image parameters in a
dynamic way
AV External Audio Video
AVC Audio Video Controller
AVIP Audio Video Input Processor
B/G Monochrome TV system. Sound
carrier distance is 5.5 MHz
BDS Business Display Solutions (iTV)
BLR Board-Level Repair
BTSC Broadcast Television Standard
Committee. Multiplex FM stereo sound
system, originating from the USA and
used e.g. in LATAM and AP-NTSC
10000_053_110228.eps countries
110228 B-TXT Blue TeleteXT
C Centre channel (audio)
Figure 3-1 Serial number (example) CEC Consumer Electronics Control bus:
remote control bus on HDMI
3.3.7 Board Level Repair (BLR) or Component Level Repair connections
(CLR) CL Constant Level: audio output to
connect with an external amplifier
If a board is defective, consult your repair procedure to decide CLR Component Level Repair
if the board has to be exchanged or if it should be repaired on ComPair Computer aided rePair
component level. CP Connected Planet / Copy Protection
If your repair procedure says the board should be exchanged CSM Customer Service Mode
completely, do not solder on the defective board. Otherwise, it CTI Color Transient Improvement:
cannot be returned to the O.E.M. supplier for back charging! manipulates steepness of chroma
transients
CVBS Composite Video Blanking and
3.3.8 Practical Service Precautions
Synchronization
DAC Digital to Analogue Converter
• It makes sense to avoid exposure to electrical shock. DBE Dynamic Bass Enhancement: extra
While some sources are expected to have a possible low frequency amplification
dangerous impact, others of quite high potential are of DCM Data Communication Module. Also
limited current and are sometimes held in less regard. referred to as System Card or
• Always respect voltages. While some may not be Smartcard (for iTV).
dangerous in themselves, they can cause unexpected DDC See “E-DDC”
reactions that are best avoided. Before reaching into a D/K Monochrome TV system. Sound
powered TV set, it is best to test the high voltage insulation. carrier distance is 6.5 MHz
It is easy to do, and is a good service precaution. DFI Dynamic Frame Insertion
DFU Directions For Use: owner's manual
3.4 Abbreviation List DMR Digital Media Reader: card reader
0/6/12 SCART switch control signal on A/V DMSD Digital Multi Standard Decoding
board. 0 = loop through (AUX to TV), DNM Digital Natural Motion

back to 2012-Jul-20
div. table
 EN 8 3. L11M1.1L LA Precautions, Notes, and Abbreviation List

DNR Digital Noise Reduction: noise The SDI signal is self-synchronizing,

reduction feature of the set uses 8 bit or 10 bit data words, and has
DRAM Dynamic RAM a maximum data rate of 270 Mbit/s,
DRM Digital Rights Management with a minimum bandwidth of 135
DSP Digital Signal Processing MHz.
DST Dealer Service Tool: special remote iTV Institutional TeleVision; TV sets for
control designed for service hotels, hospitals etc.
technicians LS Last Status; The settings last chosen
DTCP Digital Transmission Content by the customer and read and stored
Protection; A protocol for protecting in RAM or in the NVM. They are called
digital audio/video content that is at start-up of the set to configure it
traversing a high speed serial bus, according to the customer's
such as IEEE-1394 preferences
DVB-C Digital Video Broadcast - Cable LATAM Latin America
DVB-T Digital Video Broadcast - Terrestrial LCD Liquid Crystal Display
DVD Digital Versatile Disc LED Light Emitting Diode
DVI(-d) Digital Visual Interface (d= digital only) L/L' Monochrome TV system. Sound
E-DDC Enhanced Display Data Channel carrier distance is 6.5 MHz. L' is Band
(VESA standard for communication I, L is all bands except for Band I
channel and display). Using E-DDC, LPL LG.Philips LCD (supplier)
the video source can read the EDID LS Loudspeaker
information form the display. LVDS Low Voltage Differential Signalling
EDID Extended Display Identification Data Mbps Mega bits per second
(VESA standard) M/N Monochrome TV system. Sound
EEPROM Electrically Erasable and carrier distance is 4.5 MHz
Programmable Read Only Memory MHEG Part of a set of international standards
EMI Electro Magnetic Interference related to the presentation of
EPG Electronic Program Guide multimedia information, standardised
EPLD Erasable Programmable Logic Device by the Multimedia and Hypermedia
EU Europe Experts Group. It is commonly used as
EXT EXTernal (source), entering the set by a language to describe interactive
SCART or by cinches (jacks) television services
FDS Full Dual Screen (same as FDW) MIPS Microprocessor without Interlocked
FDW Full Dual Window (same as FDS) Pipeline-Stages; A RISC-based
FLASH FLASH memory microprocessor
FM Field Memory or Frequency MOP Matrix Output Processor
Modulation MOSFET Metal Oxide Silicon Field Effect
FPGA Field-Programmable Gate Array Transistor, switching device
FTV Flat TeleVision MPEG Motion Pictures Experts Group
Gb/s Giga bits per second MPIF Multi Platform InterFace
G-TXT Green TeleteXT MUTE MUTE Line
H H_sync to the module MTV Mainstream TV: TV-mode with
HD High Definition Consumer TV features enabled (iTV)
HDD Hard Disk Drive NC Not Connected
HDCP High-bandwidth Digital Content NICAM Near Instantaneous Compounded
Protection: A “key” encoded into the Audio Multiplexing. This is a digital
HDMI/DVI signal that prevents video sound system, mainly used in Europe.
data piracy. If a source is HDCP coded NTC Negative Temperature Coefficient,
and connected via HDMI/DVI without non-linear resistor
the proper HDCP decoding, the NTSC National Television Standard
picture is put into a “snow vision” mode Committee. Color system mainly used
or changed to a low resolution. For in North America and Japan. Color
normal content distribution the source carrier NTSC M/N= 3.579545 MHz,
and the display device must be NTSC 4.43= 4.433619 MHz (this is a
enabled for HDCP “software key” VCR norm, it is not transmitted off-air)
decoding. NVM Non-Volatile Memory: IC containing
HDMI High Definition Multimedia Interface TV related data such as alignments
HP HeadPhone O/C Open Circuit
I Monochrome TV system. Sound OSD On Screen Display
carrier distance is 6.0 MHz OAD Over the Air Download. Method of
I2 C Inter IC bus software upgrade via RF transmission.
I2 D Inter IC Data bus Upgrade software is broadcasted in
I2 S Inter IC Sound bus TS with TV channels.
IF Intermediate Frequency OTC On screen display Teletext and
IR Infra Red Control; also called Artistic (SAA5800)
IRQ Interrupt Request P50 Project 50: communication protocol
ITU-656 The ITU Radio communication Sector between TV and peripherals
(ITU-R) is a standards body PAL Phase Alternating Line. Color system
subcommittee of the International mainly used in West Europe (colour
Telecommunication Union relating to carrier = 4.433619 MHz) and South
radio communication. ITU-656 (a.k.a. America (colour carrier
SDI), is a digitized video format used PAL M = 3.575612 MHz and
for broadcast grade video. PAL N = 3.582056 MHz)
Uncompressed digital component or PCB Printed Circuit Board (same as “PWB”)
digital composite signals can be used. PCM Pulse Code Modulation

2012-Jul-20 back to
div. table
 Precautions, Notes, and Abbreviation List L11M1.1L LA 3. EN 9

PDP Plasma Display Panel SWAN Spatial temporal Weighted Averaging

PFC Power Factor Corrector (or Pre- Noise reduction
conditioner) SXGA 1280 × 1024
PIP Picture In Picture TFT Thin Film Transistor
PLL Phase Locked Loop. Used for e.g. THD Total Harmonic Distortion
FST tuning systems. The customer TMDS Transmission Minimized Differential
can give directly the desired frequency Signalling
POD Point Of Deployment: a removable TS Transport Stream
CAM module, implementing the CA TXT TeleteXT
system for a host (e.g. a TV-set) TXT-DW Dual Window with TeleteXT
POR Power On Reset, signal to reset the uP UI User Interface
PSDL Power Supply for Direct view LED uP Microprocessor
backlight with 2D-dimming UXGA 1600 × 1200 (4:3)
PSL Power Supply with integrated LED V V-sync to the module
drivers VESA Video Electronics Standards
PSLS Power Supply with integrated LED Association
drivers with added Scanning VGA 640 × 480 (4:3)
functionality VL Variable Level out: processed audio
PTC Positive Temperature Coefficient, output toward external amplifier
non-linear resistor VSB Vestigial Side Band; modulation
PWB Printed Wiring Board (same as “PCB”) method
PWM Pulse Width Modulation WYSIWYR What You See Is What You Record:
QRC Quasi Resonant Converter record selection that follows main
QTNR Quality Temporal Noise Reduction picture and sound
QVCP Quality Video Composition Processor WXGA 1280 × 768 (15:9)
RAM Random Access Memory XTAL Quartz crystal
RGB Red, Green, and Blue. The primary XGA 1024 × 768 (4:3)
color signals for TV. By mixing levels Y Luminance signal
of R, G, and B, all colors (Y/C) are Y/C Luminance (Y) and Chrominance (C)
reproduced. signal
RC Remote Control YPbPr Component video. Luminance and
RC5 / RC6 Signal protocol from the remote scaled color difference signals (B-Y
control receiver and R-Y)
RESET RESET signal YUV Component video
ROM Read Only Memory
RSDS Reduced Swing Differential Signalling
data interface
R-TXT Red TeleteXT
SAM Service Alignment Mode
S/C Short Circuit
SCART Syndicat des Constructeurs
d'Appareils Radiorécepteurs et
Téléviseurs
SCL Serial Clock I2C
SCL-F CLock Signal on Fast I2C bus
SD Standard Definition
SDA Serial Data I2C
SDA-F DAta Signal on Fast I2C bus
SDI Serial Digital Interface, see “ITU-656”
SDRAM Synchronous DRAM
SECAM SEequence Couleur Avec Mémoire.
Colour system mainly used in France
and East Europe. Colour
carriers = 4.406250 MHz and
4.250000 MHz
SIF Sound Intermediate Frequency
SMPS Switched Mode Power Supply
SoC System on Chip
SOG Sync On Green
SOPS Self Oscillating Power Supply
SPI Serial Peripheral Interface bus; a 4-
wire synchronous serial data link
standard
S/PDIF Sony Philips Digital InterFace
SRAM Static RAM
SRP Service Reference Protocol
SSB Small Signal Board
SSC Spread Spectrum Clocking, used to
reduce the effects of EMI
STB Set Top Box
STBY STand-BY
SVGA 800 × 600 (4:3)
SVHS Super Video Home System
SW Software

back to 2012-Jul-20
div. table
 EN 10 4. L11M1.1L LA Mechanical Instructions

4. Mechanical Instructions
Index of this chapter:
4.1 Cable Dressing
4.2 Service Positions Notes:
4.3 Assy/Panel Removal (Thriller styling; xxPFL3x06D/xx) • Figures below can deviate slightly from the actual situation,
4.4 Assy/Panel Removal (Berlinale styling; xxPFL5x06D/xx) due to the different set executions.
4.5 Set Re-assembly

4.1 Cable Dressing

19130_002_110421.eps
110421

Figure 4-1 Cable dressing 32" Thriller (xxPFL3x06D/xx)

2012-Jul-20 back to
div. table
 Mechanical Instructions L11M1.1L LA 4. EN 11

11 mm saddle × 1
150 mm tape × 3
70 mm tape × 4
Foam × 2

19130_003_110426.eps
110426

Figure 4-2 Cable dressing 40" Thriller (xxPFL3x06D/xx)

back to 2012-Jul-20
div. table
 EN 12 4. L11M1.1L LA Mechanical Instructions

19131_025_110623.eps
110623

Figure 4-3 Cable dressing 32" Berlinale (xxPFL5x06D/xx)

2012-Jul-20 back to
div. table
 Mechanical Instructions L11M1.1L LA 4. EN 13

19131_026_110623.eps
110623

Figure 4-4 Cable dressing 40" Berlinale (xxPFL5x06D/xx)

back to 2012-Jul-20
div. table
 EN 14 4. L11M1.1L LA Mechanical Instructions

4.2 Service Positions
For easy servicing of a TV set, the set should be put face down
on a soft flat surface, foam buffers or other specific workshop
tools. Ensure that a stable situation is created to perform
measurements and alignments. When using foam bars take
care that these always support the cabinet and never only the
display. Caution: Failure to follow these guidelines can
seriously damage the display!
Ensure that ESD safe measures are taken.

4.3 Assy/Panel Removal (Thriller styling;

xxPFL3x06D/xx)
Instructions below apply to the 40PFL3606D/78, but will be
similar for other models.

4.3.1 Rear Cover

2
3 2
2 2

3 3
3

2
3 2

3 3

1
3 1 1 3 2
2
3
1 1

19130_004_110426.eps
110426

Figure 4-5 Rear cover removal (40")

Warning: Disconnect the mains power cord before removing

the rear cover.
See Figure 4-5.
1. Remove fixation screws [2] and [3] that secure the rear
cover. It is not necessary to remove the stand first [1].
2. Lift the rear cover from the TV. Make sure that wires and
flat foils are not damaged while lifting the rear cover from
the set.

2012-Jul-20 back to
div. table
 Mechanical Instructions L11M1.1L LA 4. EN 15

4.3.2 LCD Panel 4. Remove the IR/LED board [F].

5. Remove the Local Control board [G].
Refer to Figure 4-6 for details. 6. Remove the clamps [1].
1. Remove the Stand [A]. 7. Remove all metal subframes [2] that do not belong to the
2. Remove the Speakers/Subwoofer [B]. LCD display.
3. Remove the PSU [C], SSB [D] and TCON (E).

1 1 1 1

2
1 2
1
C
1

2
1

B
1
2
1 D

F
1 1

A
1

19130_006_110426.eps
110426

Figure 4-6 LCD Panel removal (based on 40" model)

4.4 Assy/Panel Removal (Berlinale styling;

xxPFL5x06D/xx)
Instructions below apply to the 40PFL5606H/12 (European
model), but will be similar for other models.

4.4.1 Rear Cover

Refer to Figure 4-7 to Figure 4-9 for details.

Warning: Disconnect the mains power cord before removing
the rear cover.
1. Remove screw caps [1] that cover VESA screw holes.
2. Remove all fixation screws [2], [3] that secure the rear
cover.
3. Release the bottom catches [4], [5].
4. At the indicated areas [6] the cover is secured by clips. Be
very careful with releasing those.
5. Lift the rear cover from the TV starting from the bottom [7]
and tilt it vertically [8]. Make sure that wires and flat foils are
not damaged while lifting the rear cover from the set.

back to 2012-Jul-20
div. table
 EN 16 4. L11M1.1L LA Mechanical Instructions

2 2 2 2
1 1

6
2
2 2

8 8

3
2 2 2

1 1
2 2
2 2

7 7

19150_006_110512.eps
110512

Figure 4-7 Rear cover removal -1-

4.4.2 Small Signal Board (SSB)

Caution: it is mandatory to remount all different screws at their

original position during re-assembly. Failure to do so may result
in damaging the SSB.
1. Release the clips from both the LVDS Flat Foil connectors
that connect with the SSB.
Caution: be careful, as these are very fragile connectors!
Take the flat foils out of their connectors.
4 4 2. Unplug all other connectors.
3. Remove all fixation screws from the SSB. Note that one
19150_013_110513.eps screw is located below the upper flat foil cable.
110513
4. Take out the SSB together with side and bottom I/O
Figure 4-8 Rear cover removal -2- bracket.
5. Remove the screws between the bottom Y-Pb and L-R
audio connectors.
6. Remove the side and bottom I/O bracket from the SSB.
Note that these parts are kept in place by very fragile clips.
Release those clips gently!

4.4.3 Power Supply Unit (PSU)

Caution: it is mandatory to remount all different screws at their

original position during re-assembly. Failure to do so may result
in damaging the PSU.
1. Release the tape from the Power board cables.
2. Unplug power connectors from the SSB, as it is not unplug-
able at the PSU itself (soldered connector).
5 3. Unplug both other connectors from the PSU.
4. Remove all fixation screws from the PSU.
19150_014_110513.eps
110513
5. The PSU can be taken out of the set now.
When defective, replace the whole unit.
Figure 4-9 Rear cover removal -3-

2012-Jul-20 back to
div. table
 Mechanical Instructions L11M1.1L LA 4. EN 17

4.4.4 Stand removal

1. Remove the four fixation screws.

2. Take the stand out in a downwards direction.

4.4.5 Stand bracket removal

Refer to Figure 4-10 for details.

Caution: it is mandatory to remount all different screws at their
original position during re-assembly. Be sure to put the set in
the Service Position.
1. Remove the fixation screws [1], [2]. 1 1
2. Take the Stand bracket out.

2
3 2
19150_009_110512.eps
110512
2
3 2
Figure 4-12 IR/LED/Keyboard removal

Stand Bracket 4.4.8 LCD Panel

Refer to Figure 4-14 for details.

2 1. Remove the SSB as described earlier.
2
3 1 1 2. Remove the PSU as described earlier.
3. Remove the stand as described earlier.
4. Remove the stand bracket as described earlier.
5. Remove the Power switch and mains plug as described
19150_007_110512.eps
110512
earlier and remove the plastic subframe.
6. Remove the speakers.
7. Remove all tapes that secure any cable and remove the
Figure 4-10 Stand bracket removal
cables from the set.
8. Release the clips from the LVDS flat
4.4.6 Power switch and mains plug foil connector [1].
Caution: be careful, as these are very fragile cables and
Refer to Figure 4-11 for details. connectors! Take the flat foil out of it’s connector.
1. Unplug the connector from the PSU. 9. Release the metal clips [2] at the top, sides and bottom of
2. The switch and mains inlet can be removed by lifting the the panel that secure the LCD panel with the bezel and
catches with a screwdriver [1] and sliding them out [2]. remove the clips from their position. Be careful not to break
When defective, replace the power switch and mains plug the plastic catches [3] that secure the metal brackets.
assembly. 10. Lift the LED Panel from the bezel.
When defective, replace the whole unit.

2
2
3
3
2

19150_010_110512.eps
19150_008_110512.eps 110512
110512

Figure 4-13 LCD Panel removal -1-

Figure 4-11 Power switch and mains plug removal

4.4.7 IR/LED/Keyboard

Refer to Figure 4-12 for details.

1. Remove the stand bracket as described earlier.
2. Remove the screws [1] that connect the IR/LED/Keyboard
to the bezel.
When defective, replace the whole unit.

back to 2012-Jul-20
div. table
 EN 18 4. L11M1.1L LA Mechanical Instructions

2 2 2 2
2 2

2 2

1
2 2

2 2

2 2 2 2

19150_011_110512.eps
110512

Figure 4-14 LCD Panel removal -2-

4.5 Set Re-assembly

To re-assemble the whole set, execute all processes in reverse
order.

Notes:
• While re-assembling, make sure that all cables are placed
and connected in their original position. See Figure 4-15
• Pay special attention not to damage the EMC foams in the
set. Ensure that EMC foams are mounted correctly.

Panel

Thinner blue FFC supporting Proper FFC insertion: Silver line is not
tape belong to Panel side visible when connector lock is closed

TCON

Thicker blue FFC supporting Improper FFC insertion: Silver line is

tape belong to SSB side visible when connector lock is closed

19130_007_110426.eps
110426

Figure 4-15 Flat Foil Cable (FFC) precautions

2012-Jul-20 back to
div. table
 Service Modes, Error Codes, and Fault Finding L11M1.1L LA 5. EN 19

5. Service Modes, Error Codes, and Fault Finding

Index of this chapter: 5.2.1 General
5.1 Test Points
5.2 Service Modes Next items are applicable to all Service Modes or are general.
5.3 Service Tools
5.4 Error Codes
Life Timer
5.5 The Blinking LED Procedure
During the life time cycle of the TV set, a timer is kept (called
5.6 Fault Finding and Repair Tips
“Op. Hour”). It counts the normal operation hours (not the
5.8 Repair Policy TCON Boards
Stand-by hours). The actual value of the timer is displayed in
5.9 Software Upgrading
SDM and SAM in a decimal value. Every two soft-resets
increase the hour by +1. Stand-by hours are not counted.
5.1 Test Points
In the chassis schematics and layout overviews, the test points
Software Identification, Version, and Cluster
are mentioned. In the schematics and layouts, test points are
The software ID, version, and cluster will be shown in the main
indicated with “Fxxx” or “Ixxx”.
menu display of SDM, SAM, and CSM.
As most signals are digital, it will be difficult to measure
The screen will show: “AAAAAAB-XX.YY”, where:
waveforms with a standard oscilloscope. Several key ICs are
• AAAAAA is the chassis name: L11M11.
capable of generating test patterns, which can be controlled via
• B is the region indication: E= Europe, A= AP/China, U=
ComPair. In this way it is possible to determine which part is
NAFTA, L= LATAM.
defective.
• XX is the main version number: this is updated with a major
change of specification (incompatible with the previous
Perform measurements under the following conditions:
software version). Numbering will go from 01 - 99 and AA -
• Service Default Mode.
ZZ.
• Video: Color bar signal.
– If the main version number changes, the new version
• Audio: 3 kHz left, 1 kHz right.
number is written in the NVM.
– If the main version number changes, the default
5.2 Service Modes settings are loaded.
The Service Mode feature is split into four parts: • YY is the sub version number: this is updated with a minor
• Service Default Mode (SDM). change (backwards compatible with the previous versions)
• Service Alignment Mode (SAM). Numbering will go from 00 - 99.
• Customer Service Mode (CSM). – If the sub version number changes, the new version
• Computer Aided Repair Mode (ComPair). number is written in the NVM.
– If the NVM is fresh, the software identification, version,
SDM and SAM offer features, which can be used by the Service and cluster will be written to NVM.
engineer to repair/align a TV set. Some features are:
• A pre-defined situation to ensure measurements can be
Display Option Code Selection
made under uniform conditions (SDM).
When after an SSB or display exchange, the display option
• Activates the blinking LED procedure for error identification
code is not set properly, it will result in a TV with “no display”.
when no picture is available (SDM).
Therefore, it is required to set this display option code after
• The possibility to overrule software protections when SDM
such a repair.
is entered via the Service pins.
To do so, press the following key sequence on a standard RC
• Make alignments (e.g. White Tone), (de)select options,
transmitter: “062598” directly followed by MENU/HOME and
enter options codes, reset the error buffer (SAM).
“xxx”, where “xxx” is a 3 digit decimal value of the panel type,
• Display information (“SDM” or “SAM” indication in upper
see sticker on the side/bottom of the cabinet. When the value
right corner of screen, error buffer, software version, is accepted and stored in NVM, the set will switch to Stand-by,
operating hours, options and option codes, sub menus).
to indicate that the process has been completed.

The CSM is a Service Mode that can be enabled by the

consumer. The CSM displays diagnosis information, which the
customer can forward to the dealer or call centre. In CSM
mode, “CSM”, is displayed in the top right corner of the screen. Display Option
The information provided in CSM and the purpose of CSM is to: Code
• Increase the home repair hit rate.
• Decrease the number of nuisance calls.
• Solved customers' problem without home visit. 39mm

PHILIPS 040
27mm

MODEL:
ComPair Mode is used for communication between a computer 32PF9968/10
PROD.SERIAL NO:
and a TV on I2C /UART level and can be used by a Service AG 1A0620 000001

engineer to quickly diagnose the TV set by reading out error (CTN Sticker)
codes, read and write in NVMs, communicate with ICs and the
uP (PWM, registers, etc.), and by making use of a fault finding 10000_038_090121.eps
090819
database. It will also be possible to up and download the
software of the TV set via I2C with help of ComPair. To do this,
Figure 5-1 Location of Display Option Code sticker
ComPair has to be connected to the TV set via the ComPair
connector, which will be accessible through the rear of the set
During this algorithm, the NVM-content must be filtered,
(without removing the rear cover).
because several items in the NVM are TV-related and not SSB-
related (e.g. Model and Prod. S/N). Therefore, “Model” and
“Prod. S/N” data is changed into “See Type Plate”.
In case a call centre or consumer reads “See Type Plate” in
CSM mode, he needs to look to the side/bottom sticker to
identify the set, for further actions.

back to 2012-Jul-20
div. table
 EN 20 5. L11M1.1L LA Service Modes, Error Codes, and Fault Finding
5.2.2 Service Default Mode (SDM)
Purpose
Set the TV in SDM mode in order to be able to create a pre-
defined setting for measurements to be made. In this platform,
a simplified SDM is introduced (without protection override and
without tuning to a predefined frequency).
Specifications
• Set linear video and audio settings to 50%, but volume to
25%. Stored user settings are not affected.
• Set Smart Picture to “Game”.
• Set Smart Sound to “Standard”.
• Tune channel to:
- for analogue SDM: channel 3 (61.25 MHz)
- for digital SDM: channel 26 (545.143 MHz).
• For digital SDM: set PID default from the stream.
• All service-unfriendly modes (if present) are disabled, since
they interfere with diagnosing/repairing a set. These
service unfriendly modes are:
– (Sleep) timer.
– Blue mute/Wall paper.
– Auto switch “off” (when there is no “ident” signal).
– Hotel or hospital mode.
– Child lock or parental lock (manual or via V-chip).
– Skipping, blanking of “Not favorite”, “Skipped” or
“Locked” presets/channels.
– Automatic storing of Personal Preset or Last Status
settings.
– Automatic user menu time-out (menu switches back/
OFF automatically.
– Auto Volume levelling (AVL).
How to Activate
To activate analogue SDM, use one of the following methods:
• Press the following key sequence on the RC transmitter:
“062596” directly followed by the MENU button.
• Short one of the “Service” pads on the TV board during cold
start (see Figure 5-2). Then press the mains button
(remove the short after start-up).
Caution: When doing this, the service-technician must
know exactly what he is doing, as it could damage the
television set.
To activate digital SDM:
• Press the following sequence on the RC transmitter:
“062593” directly followed by the MENU button.
SDM
19130_008_110426.eps
110426
Figure 5-2 Service pads (SSB component side)
On Screen Menu
After activating SDM, the following items are displayed, with
“SDM” in the upper right corner of the screen to indicate that the
television is in Service Default Mode.
Menu items and explanation:
• xxxxx: Operating hours (in decimal).
• AAAAAAB-XX.YY: See paragraph Software
Identification, Version, and Cluster for the SW name
definition.
2012-Jul-20
div. table
• ERR: Shows all errors detected since the last time the
buffer was erased in format <xxx> <xxx> <xxx> <xxx>
<xxx> (five errors possible).
• OP: Used to read-out the option bytes. Ten codes (in two
rows) are possible.
How to Navigate
As this mode is read only, there is not much to navigate. To
switch to other modes, use one of the following methods:
• Command MENU from the user remote will enter the
normal user menu (brightness, contrast, color, etc...) with
“SDM” OSD remaining, and pressing MENU key again will
return to the last status of SDM again.
• To prevent the OSD from interfering with measurements in
SDM, command “OSD” or “i+” (“STATUS” or “INFO” for
NAFTA and LATAM) from the user remote will toggle the
OSD “on/off” with “SDM” OSD remaining always “on”.
• Press the following key sequence on the remote control
transmitter: “062596” directly followed by the INFO[i+]/OK
button to switch to SAM (do not allow the display to time out
between entries while keying the sequence).
How to Exit
Switch the set to Stand-by by
• pressing the standby button on the remote control
transmitter or on the television set, or
• via a standard RC-transmitter by keying the “00” sequence.
If you switch the television set “off” by removing the mains (i.e.,
unplugging the television), the television set will remain in SDM
when mains is re-applied, and the error buffer is not cleared.
The error buffer will only be cleared when the “clear” command
is used in the SAM menu.
Note:
• If the TV is switched “off” by a power interrupt while in SDM,
the TV will show up in the last status of SDM menu as soon
as the power is supplied again. The error buffer will not be
cleared.
• In case the set is accidentally in Factory mode (with an “F”
displayed on the screen), pressing and holding “VOL-“
button for 5 seconds and then followed by pressing and
holding the “CH-” button for another 5 seconds should exit
the Factory mode.
5.2.3 Service Alignment Mode (SAM)
Purpose
• To change option settings.
• To display / clear the error code buffer.
• To perform alignments.
Specifications
• Operation hours counter (maximum five digits displayed).
• Software version, error codes, and option settings display.
• Error buffer clearing.
• Option settings.
• Software alignments (White Tone).
• NVM Editor.
• Set screen mode to full screen (all content is visible).
• Set Smart Picture to “Game”.
How to Activate
To activate SAM, use one of the following methods:
• Press the following key sequence on the remote control
transmitter: “062596” directly followed by the INFO[i+] /OK
button. Do not allow the display to time out between entries
while keying the sequence.
• Or via ComPair.
After entering SAM, the following items are displayed, with
“SAM” in the upper right corner of the screen to indicate that the
television is in Service Alignment Mode.
back to
 Service Modes, Error Codes, and Fault Finding
Menu items and explanation:
1. System Information.
• Op Hour: This represents the life timer. The timer
counts normal operation hours, but does not count
Stand-by hours.
• MAIN SW ID: See paragraph Software Identification,
Version, and Cluster for the SW name definition.
• ERR: Shows all errors detected since the last time the
buffer was erased. Five errors possible.
• OP1/OP2: Used to read-out the option bytes. See
paragraph 6.7 Option Settings in the Alignments
section for a detailed description. Ten codes are
possible.
2. Tuner.
• AGC Adjustment: See paragraph 6.3.1 for
instructions.
• Store: To store the data.
3. Clear. Erases the contents of the error buffer. Select this
menu item and press the MENU RIGHT key on the remote
control. The content of the error buffer is cleared.
4. Options. To set the option bits. See paragraph 6.7 Option
Settings in the “Alignments” chapter for a detailed
description.
5. RGB Align. To align the White Tone. See White Tone
Alignment: for a detailed description.
6. NVM Editor. To change the NVM data in the television set.
See also paragraph 5.6 Fault Finding and Repair Tips.
7. Upload to USB.
8. Download from USB.
9. Initialise NVM. To initialize a (corrupted) NVM. Be careful,
this will erase all settings!
10. Auto ADC. Refer to chapter 6. Alignments for detailed
information.
11. EDID Write Enable. Enables EDID writing (not applicable
to Berlinale sets).
12. Service Data. Virtual Key board for character input entry.
How to Navigate
• In the SAM menu, select menu items with the UP/DOWN
keys on the remote control transmitter. The selected item
will be indicated. When not all menu items fit on the screen,
use the UP/DOWN keys to display the next / previous
menu items.
• With the LEFT/RIGHT keys, it is possible to:
– Activate the selected menu item.
– Change the value of the selected menu item.
– Activate the selected sub menu.
• When you press the MENU button twice while in top level
SAM, the set will switch to the normal user menu (with the
SAM mode still active in the background). To return to the
SAM menu press the MENU button.
• The “INFO[i+]/OK” key from the user remote will toggle the
OSD “on/off” with “SAM” OSD remaining always “on”.
• Press the following key sequence on the remote control
transmitter: “062596” directly followed by the MENU button
to switch to SDM (do not allow the display to time out
between entries while keying the sequence).
How to Store SAM Settings
To store the settings changed in SAM mode (except the
OPTIONS and RGB ALIGN settings), leave the top level SAM
menu by using the POWER button on the remote control
transmitter or the television set. The mentioned exceptions
must be stored separately via the STORE button.
How to Exit
Switch the set to STANDBY by pressing the mains button on
the remote control transmitter or the television set, or by
keying-in the “00” sequence on a standard RC-transmitter.
Note:
• When the TV is switched “off” by a power interrupt while in
SAM, the TV will show up in “normal operation mode” as
back to
div. table
L11M1.1L LA 5. EN 21
soon as the power is supplied again. The error buffer will
not be cleared.
• In case the set is in Factory mode by accident (with “F”
displayed on screen), pressing and holding “VOL-“ button
for 5 seconds and then followed by pressing and holding
the “CH-” button for another 5 seconds should exit the
Factory mode.
5.2.4 Customer Service Mode (CSM)
Purpose
The Customer Service Mode shows error codes and
information on the TV’s operation settings. A call centre can
instruct the customer (by telephone) to enter CSM in order to
identify the status of the set. This helps them to diagnose
problems and failures in the TV before making a service call.
The CSM is a read-only mode; therefore, modifications are not
possible in this mode.
Specifications
• Ignore “Service unfriendly modes”.
• Set volume to 25%.
• Set Smart Picture to “Game”.
• Set Smart Sound to “Standard”.
• Line number for every line (to make CSM language
independent).
• Set the screen mode to full screen (all contents on screen
is visible).
• After leaving the Customer Service Mode, the original
settings are restored.
• Possibility to use “CH+” or “CH-” for channel surfing, or
enter the specific channel number on the RC.
How to Activate
To activate CSM, press the following key sequence on a
standard remote control transmitter: “123654” (do not allow the
display to time out between entries while keying the sequence).
After entering the Customer Service Mode, the following items
are displayed:
Menu Explanation CSM1
1. Set Type. Type number, e.g. 32PFL3605/78. (*)
2. Production code. Product serial no., e.g.
BZ1A1008123456 (*). BZ= Production centre, 1= BOM
code, A= Service version change code, 10= Production
year, 08= Production week, 123456= Serial number.
3. Installation date. Indicates the date of the first initialization
of the TV. This date is acquired via time extraction.
4. a - Option Code 1. Option code information (group 1).
b - Option Code 2. Option code information (group 2).
5. SSB. Indication of the SSB factory ID (= 12nc). (*)
6. Display. Indication of the display ID (=12 nc). (*)
7. PSU. Indication of the PSU factory ID (= 12nc).
(*) If an NVM IC is replaced or initialized, these items must be
re-written to it. ComPair will foresee in a possibility to do this.
Also the NVM editor in the SAM menu can be used.
Menu Explanation CSM2
1. Current Main SW. Shows the main software version.
2. Standby SW. Shows the Stand-by software version.
3. Panel Code. Shows the current display code.
4. Bootloader ID. Shows the Bootloader software ID.
5. NVM Version. The NVM software version no.
6. Flash ID. Shows the flash ID.
Menu Explanation CSM3
1. Signal Quality. Shows the signal quality (No Tuned/Poor/
Average/Good).
2. Child lock. This is a combined item for locks. If any lock
(Preset lock, child lock, lock after, or Parental lock) is
active, this item indicates “active”.
2012-Jul-20
 EN 22 5. L11M1.1L LA Service Modes, Error Codes, and Fault Finding

3. HDCP Keys. Indicates if the HDMI keys (or HDCP keys)

are valid or not. Not applicable to Berlinale series. TO TV
4. not used TO TO TO
I2C SERVICE
5. not used UART SERVICE
CONNECTOR CONNECTOR
UART SERVICE
CONNECTOR

6. not used
7. not used.
ComPair II
Multi
RC in function
RC out

Create a CSM dump on an USB stick

There will be CSM dump to a plugged in USB-stick upon Optional Power Link/ Mode
Switch Activity I2C RS232 /UART
entering CSM-mode. An extended CSM dump will be created
when the “OK” button on RC is pressed in CSM while a USB
stick is plugged in. A direct CSM flash dump will be created
PC
when the buttons “red + 2679” on the remote control are
pressed in CSM while a USB stick is plugged in.

How to Exit
To exit CSM, use one of the following methods:
ComPair II Developed by Philips Brugge
• Press the MENU/HOME button on the remote control
transmitter. HDMI
Optional power
5V DC
I2C only
• Press the POWER button on the remote control
transmitter.
• Press the POWER button on the television set. 10000_036_090121.eps
091118

5.3 Service Tools Figure 5-3 ComPair II interface connection

5.3.1 ComPair Caution: It is compulsory to connect the TV to the PC as

Introduction
ComPair (Computer Aided Repair) is a Service tool for Philips
Consumer Electronics products. and offers the following:
1. ComPair helps you to quickly get an understanding on how
to repair the chassis in a short and effective way.
2. ComPair allows very detailed diagnostics and is therefore
capable of accurately indicating problem areas. You do not
have to know anything about I2C or UART commands
yourself, because ComPair takes care of this.
3. ComPair speeds up the repair time since it can
automatically communicate with the chassis (when the uP
is working) and all repair information is directly available.
4. ComPair features TV software up possibilities.
shown in the picture above (with the ComPair interface in
between), as the ComPair interface acts as a level shifter. If
one connects the TV directly to the PC (via UART), ICs will be
blown!
How to Order
ComPair II order codes:
• ComPair II interface: 3122 785 91020.
• ComPair UART interface cable: 3138 188 75051.
• Program software can be downloaded from the Philips
Service web portal.
Note: For this chassis, “Pgammar” and “T-con NVM”
programming (VCOM alignment) are added to ComPair.

Specifications Additional cables for VCOM Alignment

ComPair consists of a Windows based fault finding program
and an interface box between PC and the (defective) product.
The (new) ComPair II interface box is connected to the PC via
an USB cable. For the TV chassis, the ComPair interface box
and the TV communicate via a bi-directional cable via the
service connector(s).
How to Connect
This is described in the ComPair chassis fault finding database.
• ComPair/I2C interface cable: 3122 785 90004.
• ComPair/VGA adapter cable: 9965 100 09269.
5.4 Error Codes
5.4.1 Introduction
Error codes are required to indicate failures in the TV set. In
principle a unique error code is available for every:
• Activated (SW) protection.
• Failing I2C device.
• General I2C error.
The last five errors, stored in the NVM, are shown in the
Service menu’s. This is called the error buffer.
The error code buffer contains all errors detected since the last
time the buffer was erased. The buffer is written from left to
right. When an error occurs that is not yet in the error code
buffer, it is displayed at the left side and all other errors shift one
position to the right.
An error will be added to the buffer if this error differs from any
error in the buffer. The last found error is displayed on the left.
An error with a designated error code never leads to a
deadlock situation. It must always be diagnosable (e.g. error
buffer via OSD or blinking LED or via ComPair).
In case a failure identified by an error code automatically
results in other error codes (cause and effect), only the error
code of the MAIN failure is displayed.

2012-Jul-20 back to
div. table
 Service Modes, Error Codes, and Fault Finding L11M1.1L LA 5. EN 23

5.4.2 How to Read the Error Buffer

Example (2): the content of the error buffer is “12 9 6 0 0”
You can read the error buffer in three ways: After entering SDM, the following occurs:
• On screen via the SAM/SDM/CSM (if you have a picture). • 1 long blink of 5 seconds to start the sequence,
Example: • 12 short blinks followed by a pause of 1.5 seconds,
– ERROR: 0 0 0 0 0 : No errors detected • 9 short blinks followed by a pause of 1.5 seconds,
– ERROR: 6 0 0 0 0 : Error code 6 is the last and only • 6 short blinks followed by a pause of 1.5 seconds,
detected error • 1 long blink of 1.5 seconds to finish the sequence,
– ERROR: 9 6 0 0 0 : Error code 6 was detected first and • The sequence starts again with 12 short blinks.
error code 9 is the last detected (newest) error
• Via the blinking LED procedure (when you have no 5.5.2 Displaying the Entire Error Buffer
picture). See paragraph 5.5 The Blinking LED Procedure.
• Via ComPair. Additionally, the entire error buffer is displayed when Service
Mode “SDM” is entered.
5.4.3 Error codes
5.6 Fault Finding and Repair Tips
The “layer 1” error codes are pointing to the defective board. Notes:
They are triggered by LED blinking when CSM is activated. In • It is assumed that the components are mounted correctly
the LC10 platform, only two boards are present: the SSB and with correct values and no bad solder joints.
the PSU/IPB, meaning only the following layer 1 errors are • Before any fault finding actions, check if the correct
defined: options are set.
• 2: SSB
• 3: IPB/PSU 5.6.1 NVM Editor
• 4: Display
In some cases, it can be convenient if one directly can change
Table 5-1 Error code table the NVM contents. This can be done with the “NVM Editor” in
SAM mode. With this option, single bytes can be changed.
Layer-1 Defective Layer-2
error code board error code Defective device Caution:
2 SSB 11 Speaker DC protection active on SSB • Do not change these, without understanding the
3 IPB/PSU 16 +12 missing/low, PSU defective function of each setting, because incorrect NVM
3 IPB/PSU 17 POK line defective settings may seriously hamper the correct functioning
2 SSB 35 EEPROM I2C error on SSB, M24C16 of the TV set!
2 SSB 34 Tuner I2C error on SSB • Always write down the existing NVM settings, before
2 SSB 23 HDMI Mux IC I2C error on SSB - Berlinale changing the settings. This will enable you to return to the
models with Mux only
original settings, if the new settings turn out to be incorrect.
2 SSB 27 Channel decoder on SSB
4 Display 18 LCD Panel inverter error. INV_STATUS
(Inverter) (for 32” sets only) 5.6.2 Load Default NVM Values

It is possible to download default values automatically into the

5.4.4 How to Clear the Error Buffer
The error code buffer is cleared in the following cases:
• By using the CLEAR command in the SAM menu:
• By using the following key sequence on the remote control
transmitter: “062599” directly followed by the OK button.
• If the contents of the error buffer have not changed for 50
hours, the error buffer resets automatically.
Note: If you exit SAM by disconnecting the mains from the
television set, the error buffer is not reset.
5.5 The Blinking LED Procedure
5.5.1 Introduction
The software is capable of identifying different kinds of errors.
Because it is possible that more than one error can occur over
time, an error buffer is available, which is capable of storing the
last five errors that occurred. This is useful if the OSD is not
working properly.
Errors can also be displayed by the blinking LED procedure.
The method is to repeatedly let the front LED pulse with as
many pulses as the error code number, followed by a period of
1.5 seconds in which the LED is “off”. Then this sequence is
repeated.
Example (1): error code 4 will result in four times the sequence
LED “on” for 0.25 seconds / LED “off” for 0.25 seconds. After
this sequence, the LED will be “off” for 1.5 seconds. Any RC
command terminates the sequence. Error code LED blinking is
in red color.
NVM in case a blank NVM is placed or when the NVM first 20
address contents are “FF”. After the default values are
downloaded, it is possible to start-up and to start aligning the
TV set. To initiate a forced default download the following
action has to be performed:
1. Switch “off” the TV set with the mains cord disconnected
from the wall outlet (it does not matter if this is from “Stand-
by” or “Off” situation).
2. Short-circuit the SDM pads on the SSB (keep short
circuited, see Figure 5-2).
3. Press “P+” or “CH+” on the local keyboard (and keep it
pressed).
4. Reconnect the mains supply to the wall outlet.
5. Release the “P+” or “CH+” when the set is started up and
has entered SDM.
When the downloading has completed successfully, the set will
perform a restart. After this, put the set to Stand-by and remove
the short-circuit on the SDM pads.
Alternative method:
It is also possible to upload the default values to the NVM with
ComPair in case the SW is changed, the NVM is replaced with
a new (empty) one, or when the NVM content is corrupted.
After replacing an EEPROM (or with a defective/no EEPROM),
default settings should be used to enable the set to start-up and
allow the Service Default Mode and Service Alignment Mode to
be accessed.

back to 2012-Jul-20
div. table
 EN 24 5. L11M1.1L LA Service Modes, Error Codes, and Fault Finding

5.6.3 No Picture 5.9.3 How to Copy NVM Data to/from USB

When you have no picture, first make sure you have entered Write NVM Data to USB
the correct display code. 1. Insert the USB stick into the USB slot while in SAM mode.
See Display Option Code Selection for the instructions. 2. Execute the command "NVM Copy" > "NVM Copy to USB",
to copy the NVM data to the USB stick. The NVM filename
5.6.4 Unstable Picture via HDMI input on the USB stick will be named
"L11M11L_NVM_T2U.BIN" (this takes a couple of
Check (via ComPair) if HDMI EDID data is properly seconds).
programmed.
Write NVM Data to TV
5.6.5 No Picture via HDMI input 1. First, ensure (via a PC) that the filename on the USB stick
has the correct format: "L11M11L_NVM_U2T.BIN".
2. Insert the USB stick into the USB slot while in SAM mode.
Check if HDCP key is valid. This can be done in CSM.
3. Execute the command "NVM Copy" > "NVM Copy from
USB" to copy the USB data to NVM (this takes about a
5.6.6 HDMI CEC Not Functioning minute to complete).
To write an NVM mask to the TV, ensure that the mask has the
Go to Home/Menu ->Setup -> Installation -> Preference and correct format: "L11M11L_NVM_U2T.MAK" (0x00 to write
set the Easylink option to “on”. Also check if the connected protect, 0xFF to overwrite).
device is CEC enabled. Important: The file must be located in the "/Repair" directory
of the USB stick.
5.6.7 TV Will Not Start-up from Stand-by.
5.9.4 How to Copy EDID Data to/from USB
Possible Stand-by Controller failure. Reflash the SW.
Write EDID Data to USB
5.7 Repair Policy Power Supply Units 1. Insert the USB stick into the USB slot while in SAM mode.
For the xxPFL5606D/xx sets, supply units should be repaired. 2. Execute the command "NVM Copy" > "EDID Copy to
Detailed info is available in section 7.2.1. USB", to copy the EDID data to the USB stick. The
For the xxPFL3606D/xx sets, supply units should be swapped. filename on the USB stick will be named
"L11M11L_EDID_T2U.BIN" (this takes a couple of
seconds).
5.8 Repair Policy TCON Boards
Thriller sets (xxPFL3x06D/xx) in the 40" range have an
additional “Philips” TCON board (diagram T01). This board Write EDID Data to TV
should be swapped separately from the bare LCD panel. 1. First, ensure (via a PC) that the filename on the USB stick
Alignment can be done using ComPair. All other TCON boards has the correct format: "L11M11L_EDID_U2T.BIN".
come with the LCD panel and should be swapped together as 2. Insert the USB stick into the USB slot while in SAM mode.
one entity. 3. Execute the command "NVM Copy" > "EDID Copy from
USB" to copy the USB data to EDID (this takes about a
minute to complete).
5.9 Software Upgrading
Important: The file must be located in the "/Repair" directory
5.9.1 Introduction
of the USB stick.

It is possible for the user to upgrade the main software via the
5.9.5 How to Copy the Channel List to/from USB
USB port. This allows replacement of a software image in a
stand alone set. A description on how to upgrade the main
software can be found in the DFU or on the Philips website. Write Channel List Data to USB
1. Insert the USB stick into the USB slot while in SAM mode.
2. Execute the command "Channel list Copy to USB", to copy
5.9.2 Main Software Upgrade
the channel list data to the USB stick. The filename on the
USB stick will be named "L11M11L_CHTB_T2U.BIN" (this
Automatic Software Upgrade takes a couple of seconds).
In “normal” conditions, so when there is no major problem with
the TV, the main software and the default software upgrade
Write Channel List Data to TV
application can be upgraded with the “autorun.upg” (FUS part
1. First, ensure (via a PC) that the filename on the USB stick
in the one-zip file). This can also be done by the consumers
has the correct format: "L11M11L_CHTB_U2T.BIN".
themselves, but they will have to get their software from the
2. Insert the USB stick into the USB slot while in SAM mode.
commercial Philips website or via the Software Update
3. Execute the command "Channel list Copy from USB" to
Assistant in the user menu (see DFU). The “autorun.upg” file
copy the USB data to the TV (this takes about a minute to
must be placed in the root of your USB stick.
complete).
How to upgrade:
Important: The file must be located in the "/Repair" directory
1. Copy the “autorun.upg” file to the root of an USB stick.
of the USB stick.
2. Insert the USB stick in the side I/O while the set is “on”.
The TV will prompt an upgrade message. Press “Update”
to continue, after which the upgrading process will start. As
soon as the programming is finished, the set must be
restarted.
In the “Setup” menu you can check if the latest software is
running.

2012-Jul-20 back to
div. table
 Alignments L11M1.1L LA 6. EN 25

6. Alignments
Index of this chapter: 6.3 Software Alignments
6.1 General Alignment Conditions With the software alignments of the Service Alignment Mode
6.2 Hardware Alignments (SAM) the Tuner and RGB settings can be aligned.
6.3 Software Alignments
6.4 ADC gain adjustment
6.5 TCON Alignment (= VCOM alignment) 6.3.1 Tuner Adjustment (RF AGC Take Over Point)
6.6 Additional TCON Board
6.7 Option Settings Purpose: To keep the tuner output signal constant as the input
signal amplitude varies.
Note: Figures below can deviate slightly from the actual
situation, due to the different set executions.
No alignment is necessary, as the AGC alignment is done
automatically.
General: The Service Default Mode (SDM) and Service
Alignment Mode (SAM) are described in chapter 5. Menu
6.3.2 RGB Alignment
navigation is done with the CURSOR UP, DOWN, LEFT or
RIGHT keys of the remote control transmitter.
Before alignment, set the picture as follows:
6.1 General Alignment Conditions Picture Setting
Perform all electrical adjustments under the following Dynamic backlight Off
conditions: Dynamic Contrast Off
• Power supply voltage (depends on region): Color Enhancement Off
– AP-NTSC: 120 VAC or 230 VAC / 50 Hz ( 10%). Picture Format Unscaled
– AP-PAL-multi: 120 - 230 VAC / 50 Hz ( 10%). Light Sensor Off
– EU: 230 VAC / 50 Hz ( 10%). Brightness 50
– LATAM-NTSC: 120 - 230 VAC / 50 Hz ( 10%). Color 0
– US: 120 VAC / 60 Hz ( 10%). Contrast 100
• Connect the set to the mains via an isolation transformer
with low internal resistance. White Tone Alignment:
• Allow the set to warm up for approximately 15 minutes. • Activate SAM.
• Measure voltages and waveforms in relation to correct • Select “RGB Align.“ and choose a color temperature.
ground (e.g. measure audio signals in relation to • Use a 100% white screen as input signal and set the
AUDIO_GND). following values:
Caution: It is not allowed to use heatsinks as ground. – “Red BL Offset” and “Green BL Offset” to “7” (if
• Test probe: Ri > 10 Mohm, Ci < 20 pF. present).
• Use an isolated trimmer/screwdriver to perform – All “White point” values initial to “127”.
alignments.
In case you have a color analyzer:
6.2 Hardware Alignments • Measure with a calibrated (phosphor- independent) color
There are no hardware alignments foreseen for this chassis, analyzer (e.g. Minolta CA-210) in the centre of the screen.
but below find an overview of the most important DC voltages Consequently, the measurement needs to be done in a
on the SSB. These can be used for checking proper functioning dark environment.
of the DC/DC converters. • Adjust the correct x,y coordinates (while holding one of the
White point registers R, G or B on max. value) by means of
Test Specifications (V)
decreasing the value of one or two other white points to the
Description Point Min. Typ. Max. Diagram
correct x,y coordinates (see Table 6-1 White D alignment
+12VS F118 11.7 12.3 12.91 B01_DC-DC
values). Tolerance: dx:  0.002, dy:  0.002.
+3V3_STBY F113 3.2 3.3 3.4 B01_DC-DC
• Repeat this step for the other color Temperatures that need
+3V3_SW F133 3.17 3.34 3.5 B01_DC-DC
to be aligned.
+1V25_SW F131 1.18 1.25 1.31 B01_DC-DC
• When finished return to the SAM root menu and press
+5V_SW F132 4.98 5.25 5.51 B01_DC-DC
STANDBY on the RC to store the aligned values to the
+1V8_SW F125 1.74 1.83 1.92 B01_DC-DC
NVM.
+1V1_SW F101 0.94 1.1 1.15 B01_DC-DC
+5VS F235 4.94 5.2 5.46 B02A_Tuner_IF
+2V5_SW F136 2.38 2.5 2.62 B01_DC-DC
Table 6-1 White D alignment values
+5VTUN_DI F236 4.75 5 5.25 B02_Tuner_IF
GITAL Value Cool (11000 K) Normal (9000 K) Warm (6500 K)
VLS_15V6 FJ01 14.82 15.6 16.38 B08C_TCON DC/DC x 0.276 0.287 0.313
VGH_35V FM02 34.0 35.0 36.0 B08F_MINI LVDS y 0.282 0.296 0.329
VGL_-6V FJ14 -7.0 -6.0 -5.0 B08C_TCON DC/DC
VCC_3V3 FJ13 3.14 3.3 3.47 B08C_TCON DC/DC
If you do not have a color analyzer, you can use the default
VCC1V8 FJ05 1.71 1.8 1.89 B08C_TCON DC/DC
values. This is the next best solution. The default values are
average values coming from production (statistics).
• Set the RED, GREEN and BLUE default values per
temperature according to the values in the “Tint settings”
table.
• When finished return to the SAM root menu and press
STANDBY on the RC to store the aligned values to the
NVM.

back to 2012-Jul-20
div. table
 EN 26 6. L11M1.1L LA Alignments

Table 6-2 Tint settings 32" Thriller HD (xxPFL3406D/xx) Upon appearance of the “Auto ADC Completed” message, the
alignment is completed.
Colour Temp. R G B
Cool 201 240 255 Notes:
Normal 227 255 243 1. Peak-to-Peak
Warm 243 249 164 2. Black-to-Peak.

Table 6-3 Tint settings 32" Thriller FHD (xxPFL3606D/xx) 6.4.2 PC VGA

Colour Temp. R G B Following instructions result in correct alignment of ADC gain,

Cool 246 246 248 offset and phase, related to PC VGA input signal. Apply a
Normal 242 240 246 signal of format “DMT1060”.
Warm 255 231 155 • Apply following signals to the PC VGA input connector:
– Red signal of 0.7 Vp-p1 / 75 ohm.
– Green signal of 0.7 Vp-p1 / 75 ohm.
Table 6-4 Tint settings 40" Thriller FHD (xxPFL3606D/xx) – Blue signal of 0.7 Vp-p1 / 75 ohm.
• Select the input source to PC VGA input.
Colour Temp. R G B • In SAM, initiate the “Auto ADC” calibration command.
Cool 212 244 254 Upon appearance of the “Auto ADC Completed” message, the
Normal 231 255 236 alignment is completed.
Warm 242 252 161

6.5 TCON Alignment (= VCOM alignment)

Table 6-5 Tint settings 32" Berlinale FHD (xxPFL5606D/xx) New requirement for “TCON on SSB” project:
• The purpose of VCOM alignment is to obtain an equal
Colour Temp. R G B voltages for both Positive and Negative LC polarity. This is
Cool 189 254 243 important to avoid “Flicker” and “Image Sticking”.
Normal 212 255 220 • The P-Gamma + VCOM calibrator IC, ISL24837 is used for
Warm 233 255 157 VCOM adjustment.
• The adjusted VCOM data will be stored inside on-chip
memory and will be automatically recalled during each
Table 6-6 Tint settings 40" Berlinale FHD (xxPFL5606D/xx)
power-up.

Colour Temp. R G B
ComPair (see 5.3.1 ComPair) will foresee in a possibility to do
Cool 211 233 255
this alignment.
Normal 250 252 247
Warm 254 238 161
6.6 Additional TCON Board
Thriller sets (xxPFL3x06D/xx) in the 40" range have an
6.4 ADC gain adjustment additional “Philips” TCON board (diagram T01). This board
Use a Quantum Data Patters Generator 802BT and apply a should be swapped separately from the bare LCD panel.
“PgcWrgb” image (“dot, cross and color bar mix pattern”) Alignment can be done using ComPair. All other TCON boards
according to Figure 6-1. come with the LCD panel and should be swapped together as
one entity.

6.7 Option Settings

6.7.1 Introduction

The microprocessor communicates with a large number of I2C

ICs in the set. To ensure good communication and to make
digital diagnosis possible, the microprocessor has to know
which ICs to address. The presence/absence of these specific
ICs (or functions) is made known by the option codes.

Notes:
18920_200_100317.eps • After changing the option(s), save them with the STORE
100317 command.
• The new option setting becomes active after the TV is
Figure 6-1 “PgcWrgb” pattern switched “off” and “on” again with the mains switch (the
EAROM is then read again).
6.4.1 YPbPr
6.7.2 How To Set Option Codes
Following instructions result in correct alignment of ADC gain,
offset and phase, related to YPbPr input signal. Apply a signal When the NVM is replaced, all options will require resetting. To
of format “1080i25”. be certain that the factory settings are reproduced exactly, you
• Apply following signals to the YPbPr input connectors: must set all option numbers. You can find the correct option
– Pr signal of 0.7 Vp-p1 / 75 ohm to the red cinch numbers see sticker on the inside the cabinet.
connector.
– Y signal of 0.7 Vb-p2 / 75 ohm with a sync pulse of 0.3 How to Change Options Codes
Vp-p1 to the green cinch connector. An option code (or “option byte”) represents eight different
– Pb signal of 0.7 Vb-p1 / 75 ohm to the blue cinch options (bits). All options are controlled via ten option bytes
connector. (OP#1... OP#10).
• Select the input source to YPbPr input.
• In SAM, initiate the “Auto ADC” calibration command.

2012-Jul-20 back to
div. table
 Alignments L11M1.1L LA 6. EN 27

Activate SAM and select “Options”. Now you can select the
option byte (OP#1... OP#10) with the CURSOR UP/ DOWN
keys, and enter the new 3 digit (decimal) value. For the correct
factory default settings, see the sticker inside the set.

back to 2012-Jul-20
div. table
 EN 28 7. L11M1.1L LA Circuit Descriptions

7. Circuit Descriptions
Index of this chapter: 7.1 Introduction
7.1 Introduction The LC11M1.1L LA chassis is a digital chassis using a
7.2 Power Supply Mediatek chipset. It covers screen sizes of 32" to 40".
7.3 Video
7.3.1 Video: Front-End The xxPFL3x06D/xx sets come with the “Thriller” styling, and
7.4 Audio the xxPFL5x06D/xx come with the “Berlinale” styling.
7.5 Inputs
7.5.1 Inputs: HDMI Main key components are the Mediatek MT5363 integrated
7.5.2 Inputs: USB
“System On Chip” (SoC) that supports multimedia video/audio
input, and the integrated TCON (Timing Controller), part for the
Notes: LCD panel. Thriller sets (xxPFL3x06D/xx) in the 40" range
• Only new circuits (circuits that are not published recently) however have an additional “Philips” TCON board (diagram
are described. T01) that comes separate from the LCD panel and that should
• Figures can deviate slightly from the actual situation, due be swapped separately.
to different set executions.
• For a good understanding of the following circuit
System SoC is based on MT5363:
descriptions, please use chapter 9. Block Diagrams and
• NAND Flash – 128 Mbyte, NumOnyx/Hynix.
10. Circuit Diagrams and PWB Layouts. Where necessary, • DDR – 128 Mbyte (32 × 16M, 2 pcs), Hynix.
you will find a separate drawing for clarification.
• Use internal MT5363 Stand-by micro-controller.

Tuner/Frontend configuration:
• Half NIM tuner (VA1E1BF2403) from Sharp.
• Toshiba Channel Decoder (TC90517).

Interfaces for debug and SW upgrade:

• UART (3.5 mm jack).
• USB port.
• JTAG.

Refer to Figure 7-1 for details.

19130_009_110426.eps
110429

Figure 7-1 L11M1.1L LA Architecture Thriller (xxPFL3x06D/xx)

2012-Jul-20 back to
div. table
 Circuit Descriptions L11M1.1L LA 7. EN 29

19131_022_110623.eps
110623

Figure 7-2 L11M1.1L LA Architecture Berlinale (xxPFL5x06D/xx)

back to 2012-Jul-20
div. table
 EN 30 7. L11M1.1L LA Circuit Descriptions

19130_010_110426.eps
110426

Figure 7-3 SSB cell layout Thriller (xxPFL3x06D/xx)

19130_047_110429.eps
110429

Figure 7-4 SSB key component overview Thriller (xxPFL3x06D/xx)

2012-Jul-20 back to
div. table
 Circuit Descriptions L11M1.1L LA 7. EN 31

19131_023_110623.eps
110623

Figure 7-5 SSB cell layout Berlinale (xxPFL5x06D/xx)

19131_024_110623.eps
110623

Figure 7-6 SSB key component overview Berlinale (xxPFL5x06D/xx)

back to 2012-Jul-20
div. table
 EN 32 7. L11M1.1L LA Circuit Descriptions

19130_048_110429.eps
110429

Figure 7-7 TCON key component overview

7.2 Power Supply

For the xxPFL3x06D/xx sets, the Power Supply Unit (PSU) in 1.1 V ±0.05 V
+12 VS DCDC
this chassis is a buy-in and is a black-box for Service. When
defective, a new panel must be ordered and the defective panel 1.8 V ±0.09 V
DCDC DDR2 × 2
must be returned for repair, unless the main fuse of the unit is
3.3 V ±0.16 V 1.25 V ±0.06 V
broken. Always replace the fuse with one with the correct DCDC Regulator

specifications! This part is commonly available in the regular

5.25 V ±0.26 V 2.5 V
market. DCDC ±0.12 V MT5363
Regulator Dig Demod

Refer to Figure 7-8 and Figure 7-9 for details. Regulator USB NVM

5.25 V ±0.25 V
For the xxPFL5x06D/xx sets, refer to 7.2.1 for detailed repair Tuner
EEPROM
info.
Flash

The power supply system consists of stand-by, switched and +3.3 VSTBY
regulated voltages. The stand-by voltage, +3V3STBY, will be
19130_012_110426.eps
available once AC supply is provided to the system. As for the 110426
other voltages, namely switched and regulated voltages, these
are available once the STANDBY signal is pulled “low” to allow Figure 7-8 Power distribution overview
other supplies from the IPB to turn “on”. The switched supplies
are generated from the main +12VS supply, while the regulated
supplies are derived from the switched supplies. There are a
number of detection circuits to detect the following supplies:
+12VS, +12Vdisp and +3V3_SW. The +12VS is the main
supply voltage from the IPB that enables the switched voltages
to be generated. The +12Vdisp is the supply to the display
timing controller, while the +3V3_SW is powering the
microprocessor and its flash memory.

The mains power supply unit distribute the following voltages to

the TV system: +3V3STBY, 12VS, +24Vaudio, and +24Vpanel
for panel with inverter (or) high voltage (HV) for inverterless
panel. Requirement of the High Voltage depend on the
specification of the LCD panel.

18980_203_100402.eps
100402

Figure 7-9 Power timing overview

2012-Jul-20 back to
div. table
 Circuit Descriptions L11M1.1L LA 7. EN 33

7.2.1 xxPFL5x06D/xx sets Connector

no. 1308 1316 - 1319 1M95
Table 7-1 Connector overview Descr. Mains Display Description PSU to SSB
Pin CN1 CN2 - CN3 CN4

Connector 8 - n.c. -* GND_SND

no. 1308 1316 - 1319 1M95 9 - Anode 3+ LED input * BL-ON-OFF

Descr. Mains Display Description PSU to SSB 10 - n.c. -* BL-DIM1(Vsync)

Pin CN1 CN2 - CN3 CN4 11 - Cathode 3- LED output * BL-I-CTRL

1 N Anode 1+ LED input 3V3stdby 12 - n.c. -* POK

2 L n.c. - Standby 13 - Anode 4+ LED input * +24V (AL2_DVBS)

3 - Cathode 1- LED output GND1 14 - n.c. -* GND1

4 - n.c. - GND1 15 - Cathode 4- LED output * -

5 - Anode 2+ LED input +12V

6 - n.c. - +12V Note: * optional
7 - Cathode 2- LED output +Vsnd

BL Driver 1
Line Back Light
filter PFC Resonant
converter BL Driver 2
ACin
198 V - 264 V Diode
VSSB
90 V - 276 V bridge

STBY VSTB Regulator VSND

19132_012_111221.eps
111221

Figure 7-10 Block diagram

Check First step Second step

Normal operation Check the fuse (F101)

Apply the mains voltage (ACin) Check the Standby voltage Check the entire block (PC102, VCC, etc.)
at C306: measure 3.3 V

Check the PFC voltage at C644

PFC present: measure 380 V to 400 V
Check the entire block (VCC, ICs, etc.)
Pull the Standby pin to LOW (GND) PFC not present: measure ACin × 2

Check the main supply at C208: measure 12.3 V Check the entire block (VCC, ICs, etc.)
Check the audio supply at C233: measure 24.5 V

Pull the BL_ON_OFF pin to HIGH (3.3 V) Allow the power supply to start-up a few times No turn on

Check the reference voltage of the

LED Driver (U401): measure approximately 12 V

19132_013_111221.eps
111222

Figure 7-11 Test instructions

Following checks have to be performed: SAFETY INSTRUCTION

• check fuse (F101) Replace safety components, indicated by the symbol h, only
• standby check VSTB (C306), measure 3.3 V by components identical to the original ones. Any other
• PFC voltage check (C644), measure 380 - 400 V; if no PFC component substitution (other than original type) may increase
applied, measure 311 @ 220 V risk of fire or electrical shock hazard.
• multi-level check VSSB (C208), measure 12.3 V
• multi-level check VSND (C233), measure 24.5 V
• reference voltage check (U401), measure 12 V (appr.).

back to 2012-Jul-20
div. table
 EN 34 7. L11M1.1L LA Circuit Descriptions

7.3 Video • Toshiba channel decoder TC90517 (external ISDB-T

channel decoder).
7.3.1 Video: Front-End • Analog demodulator (using internal MT5363 analog
demodulator - pin AH35 VIP, AH37 VIN).
Key components for the tuner section are:
• Sharp Half NIM tuner VA1E1BF2403, Refer to Figure 7-12 for details.

19130_013_110426.eps
110426

Figure 7-12 Front-end functional block diagram

7.4 Audio A_STBY

In this chassis, audio processing is done by the following key From uP to class D Class D outputs
components: RESET_AUDIO LOW HIGH Operating (unmute)
• MT5363 micro-processor for input selection and audio HIGH LOW Class D shutdown (mute)
processing, MUTE LOW - Operating (unmute)
• TPA3123D2 class-D power amplifier for 2 x 10 W HIGH - MUTE
amplification. DC_PROT LOW - DC detected -> set going to protection
HIGH - No DC -> normal operating
The audio profile (optimal setting per screen size and styling) is
stored at Option 10 (bit 0 to bit 4). Profile 1 for 32-inch Dali and
profile 2 for 40-inch Dali.

Table 7-2 Microprocessor control lines - 1 -

From uP At class D Usage

SW_MUTE SW_MUTE Will pull audio signals to LOW upon DC drops, help
to eliminate plop sound.
RESET_AUDIO A_STBY Control SHUTDOWN pin of class D amplifier:
ON/OFF the amplifier
MUTE MUTE Corresponding to the MUTE button on Remote
Control, to mute/unmute speakers
DC_PROT DC_PROT Detecting present of DC at speakers output and
feedback to uP. This will trigger TV into protection
mode. This is important to protect speakers

Table 7-3 Microprocessor control lines - 2 -

A_STBY
From uP to class D Class D outputs
SW_MUTE LOW - MUTE
HIGH - Operating (unmute)

2012-Jul-20 back to
div. table
 Circuit Descriptions L11M1.1L LA 7. EN 35

19130_014_110426.eps
110426

Figure 7-13 Audio signal flow

7.5 Inputs

7.5.1 Inputs: HDMI RX2 TMDS

OPWR2_5V PWR5V
HDMI_HPD2 SIDE_HDMI_HPD1
In this chassis, the main Mediatek MT5363 SoC has an on-chip HDMI_SCL2 SIDE_HDMI_SCL1
HDMI multiplexer. HDMI_SDA2 SIDE_HDMI_SDA1
Refer to Figure 7-14 for the implementation. ARC eHDMI+
HDMI_CEC CEC
MT5363
GPIO_7
GPIO 7 EDID_WC
EDID WC EDID

RX1 TMDS
OPWR1_5V PWR5V
HDMI_HPD1 HDMI_HPD2
HDMI_SDA1 HDMI_SDA2
HDMI_SDA1 HDMI_SCL2

ASPDIF_OUT EDID
ARC_SW

Buffer & Selection

circuit

19130_015_110426.eps
110426

Figure 7-14 HDMI implementation

Signal description:
• TMDS: Signals that contain audio and video information.
• PWR5V: Signal to detect the presence of any HDMI source
connected to the TV’s HDMI input port.
• SIDE_HDMI_HPD1 and HDMI_HPD2: Signal to initiate
reading of the TV EDID data by the source device.

back to 2012-Jul-20
div. table
 EN 36 7. L11M1.1L LA Circuit Descriptions

• I2C: The EDID data reading and the HDCP authentication

process runs via I2C.
• CEC: Signal direct connected between inputs and uP.
• EDID_WC: Signal used to disable the write protect pin of
the EEPROM. When updating, the program will temporarily
pull this pin “LOW” before writing new data.

7.5.2 Inputs: USB

In this chassis, the main Mediatek MT5363 SoC has an on-chip

USB processor.
Refer to Figure 7-15 for the implementation.

18980_207_100402.eps
100402

Figure 7-15 USB implementation

2012-Jul-20 back to
div. table
 IC Data Sheets L11M1.1L LA 8. EN 37

8. IC Data Sheets
This section shows the internal block diagrams and pin layouts
of ICs that are drawn as "black boxes" in the electrical diagrams
(with the exception of "memory" and "logic" ICs).

8.1 Diagram 10-4-1 DC-DC B01A, Type TPS54386 (IC7116 and 7117)

BLOCK DIAGRAM
2 BOOT1
BP
CLK1 Level
1 PVDD1
Shift
Current
f(IDRAIN1) + DC(ofst) Comparator
S Q
+
GND 4 R
R Q
+
f(IDRAIN1)
FB1 7 Overcurrent Comp
0.8 VREF + 3 SW1
RCOMP BP
f(ISLOPE1) f(IMAX1)

Soft Start Weak

SD1 CLK1 Pull-Down
1 CCOMP Anti-Cross
Conduction MOSFET

VDD2 f(ISLOPE1)
Ramp
Gen 1
TSD 1.2 MHz Divide CLK1
6 A 6 A Oscilator by 2/4 f(ISLOPE2)
EN1 5 SD1 Ramp
Gen 2
Internal
EN2 6 SD2 CLK2
Control
UVLO
150 k
SEQ 10 BP
FB1 Output
150 k Undervoltage 13 BOOT2
FB2 Detect
BP
CLK2 Level
14 PVDD2
Shift
Current
Comparator FET
f(IDRAIN2) + DC(ofst)
S Q Switch
+
GND 4 R
R Q
+
f(IDRAIN2)
FB2 8
Overcurrent Comp
0.8 VREF + 12 SW2
RCOMP BP
f(ISLOPE2) f(IMAX2)

Soft Start Weak

SD2 CLK2 Pull-Down
2 CCOMP Anti-Cross
Conduction MOSFET

5.25-V
BP 11 PVDD2
Regulator
150 k
BP
Level
ILIM2 9
Select

150 k 0.8 VREF

References
IMAX2 (Set to one of three limits)

UDG-07124

PIN CONNECTIONS
HTSSOP (PWP)
(Top View)

PVDD1 1 14 PVDD2

BOOT1 2 13 BOOT2

SW1 3 12 SW2

GND 4 Thermal Pad 11 BP

(bottom side)
EN1 5 10 SEQ

EN2 6 9 ILIM2

FB1 7 8 FB2

18980_300_100402.eps
100402

Figure 8-1 Internal block diagram and pin configuration

back to 2012-Jul-20
div. table
 EN 38 8. L11M1.1L LA IC Data Sheets

8.2 Diagram 10-4-1 DC-DC B01A, Type LD1117D (IC7119)

Block diagram
LD1117DT

Pinning information

DPAK

F_15710_166.eps
100402

Figure 8-2 Internal block diagram and pin configuration

2012-Jul-20 back to
div. table
 IC Data Sheets L11M1.1L LA 8. EN 39

8.3 Diagram 10-6-1 Class-D & muting B03, Type TPA3123 (IC7400)

Block diagram 1 F
0.22 F
LIN BSR
22 H 470 F
RIN ROUT
1 F 0.68 F
PGNDR

PGNDL 0.68 F
1 F
BYPASS LOUT
22 H 470 F
AGND BSL
0.22 F

PVCCL
AVCC
PVCCR

VCLAMP
Shutdown
SD 1 F
Control

MUTE
GAIN0

GAIN1
} Control

Pinning information
PVCCL 1 24 PGNDL
SD 2 23 PGNDL
PVCCL 3 22 LOUT
MUTE 4 21 BSL
LIN 5 20 AVCC
RIN 6 19 AVCC
BYPASS 7 18 GAIN0
AGND 8 17 GAIN1
AGND 9 16 BSR
PVCCR 10 15 ROUT
VCLAMP 11 14 PGNDR
PVCCR 12 13 PGNDR

TERMINAL
24-PIN I/O/P DESCRIPTION
NAME
(PWP)
Shutdown signal for IC (low = disabled, high = operational). TTL logic levels with compliance to
SD 2 I
AVCC
RIN 6 I Audio input for right channel
LIN 5 I Audio input for left channel
GAIN0 18 I Gain select least-significant bit. TTL logic levels with compliance to AVCC
GAIN1 17 I Gain select most-significant bit. TTL logic levels with compliance to AVCC
Mute signal for quick disable/enable of outputs (high = outputs switch at 50% duty cycle, low =
MUTE 4 I
outputs enabled). TTL logic levels with compliance to AVCC
BSL 21 I/O Bootstrap I/O for left channel
PVCCL 1, 3 P Power supply for left-channel H-bridge, not internally connected to PVCCR or AVCC
LOUT 22 O Class-D 1/2-H-bridge positive output for left channel
PGNDL 23, 24 P Power ground for left-channel H-bridge
VCLAMP 11 P Internally generated voltage supply for bootstrap capacitors
BSR 16 I/O Bootstrap I/O for right channel
ROUT 15 O Class-D 1/2-H-bridge negative output for right channel
PGNDR 13, 14 P Power ground for right-channel H-bridge.
PVCCR 10, 12 P Power supply for right-channel H-bridge, not connected to PVCCL or AVCC
AGND 9 P Analog ground for digital/analog cells in core
AGND 8 P Analog ground for analog cells in core
Reference for preamplifier inputs. Nominally equal to AVCC/8. Also controls start-up time via
BYPASS 7 O
external capacitor sizing.
AVCC 19, 20 P High-voltage analog power supply. Not internally connected to PVCCR or PVCCL
Connect to ground. Thermal pad should be soldered down on all applications to properly
Thermal pad Die pad P
secure device to printed wiring board.

18440_302_090303.eps
090318

Figure 8-3 Internal block diagram and pin configuration

back to 2012-Jul-20
div. table
 EN 40 8. L11M1.1L LA IC Data Sheets

8.4 Diagram 10-7-1 MT5363 Power B04, Type MT5363 (IC7700)

Block diagram
CVBS/ HDMI Audio
YC Input Rx Input Panel CVBS

HDMI In Audio Audio LVDS VDAC DDR

VADCx4
DVB-T ATD I/F Demod ADC TVE DRAM
TV Controller
Decoder
Audio In Mix andPost
VDO-In Processing
TS
ARM Demux JPEG,MPEG
PreProc H.264 Vplane
OSD
BIM scaler/PIP
2-D Graphic scaler
MDDi

IO Bus Standby uP CKGEN

Audio DSP
Audio I/F JTAG IrDA SIF USB2.0 Watchdog Serial Flash Servo ADC

Audio DAC BScan PVR RTC UART MS,SD PWM NAND Flash

SPDIF, I2S

18850_300_100107.eps
100222

Figure 8-4 Internal block diagram

2012-Jul-20 back to
div. table
 IC Data Sheets L11M1.1L LA 8. EN 41

Pinning information
LT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

A RCLK0_ RDQ10 RDQ15 RDQS0_ RDQ14 RDQ12 AO1N AOCKN

B VCC2IO RCLK0 RDQ8 RDQS1 RDQS0 RDQ11 VCC2IO AO0N AO2N AO3N

C VCC2IO RDQ13 RDQS1_ DVSS RDQM1 VCC2IO AO1P AOCKP

D RA9 VCC2IO RDQ5 RDQ0 DVSS RDQ9 VCC2IO AO0P AO2P AO3P

E RA12 VCC2IO RDQ2 DVSS RDQM0 VCC2IO VCC2IO AE0N AE2N

F RA5 AVDD33_L
RA7 VCC2IO RDQ7 DVSS RDQ6 VCC2IO AE1N AECKN
VDS

G RA10 RA3 VCC2IO DVSS DVSS RDQ3 VCC2IO AE0P AE2P

AVDD33_L
H RBA2 RBA0 RA1 VCC2IO RDQ1 RDQ4 AE1P AECKP
VDS

J AVSS33_L
RBA1 DVSS DVSS VCC2IO
VDS

K RCKE RWE_ MEMTN MEMTP

L RCAS_ DVSS DVSS

M RA13 RA2 RA4 RA6 TP_VPLL

DVSS AVDD12_L AVDD12_V

N RA11 RA0 RODT RVREF
VDS PLL

P RA8 AVDD12_M AVSS12_L AVSS12_V

RCS_ RRAS_ RVREF DVSS
EMPLL VDS PLL

R VCC2IO VCC2IO VCC2IO DVSS VCCK DVSS

AVSS12_M
T RDQ19 RDQ20 RDQ30 RDQ25 DVSS DVSS DVSS
EMPLL

U RDQ22 RDQ17 RDQM3 VCCK DVSS DVSS

V RDQM2 RDQS2 RDQ28 RDQ27 VCCK DVSS DVSS DVSS

W RDQS2_ DVSS DVSS DVSS DVSS DVSS

Y RDQS3 DVSS RDQ24 RDQ31 VCCK VCCK DVSS DVSS

AA RDQS3_ RDQ29 RDQ26 VCCK DVSS DVSS

AB RDQ16 RDQ23 REXTDN DVSS DVSS DVSS DVSS

AC RDQ21 RDQ18 VCC2IO DVSS DVSS DVSS

AD RCLK1 RCLK1_ VCC2IO VCC2IO DVSS VCCK VCCK VCCK

AE VCC2IO VCC2IO GPIO39 DVSS VCCK VCCK VCCK

AF VCC2IO VCC2IO GPIO37 GPIO40 DVSS VCCIO33-1 VCCIO33-1

AG GPIO38 GPIO41 GPIO42 VCCK

AH GPIO44 GPIO43 JTDO VCCK

AJ JTDI JTMS VCCK VCCK

AK JTRST_ JTCK VCCK VCCK

AVDD12_U HDMI_SCL HDMI_SDA HDMI_HPD

AL VCCK VCCK VCCK VCCK PWR5V_1
SB 2 2 1

AVSS12_U AVDD33_U AVDD33_H HDMI_SCL

AM VCCK VCCK VCCK VCCK PWR5V_2 OPCTRL1
SB SB DMI 1
AVSS33_H HDMI_HPD HDMI_SDA
AN VCCK VCCK POCE1_ USB_VRT HDMI_CEC
DMI 2 1
AVSS33_U AVDD12_H
AP OSDA0 OSCL0 PDD1 PDD4 RX2_0 RX2_2 RX1_0 RX1_2
SB DMI

AR PDD0 PAALE PDD2 PDD6 USB_DM RX2_C RX2_1 RX1_C RX1_1

AVSS33_U AVSS33_U
AT POCE0_ POWE_ PARB_ PDD5 RX2_0B RX2_2B RX1_0B RX1_2B
SB SB

AU POOE_ PACLE PDD3 PDD7 USB_DP RX2_CB RX2_1B RX1_CB RX1_1B

AV 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

18850_301_100107.eps
100222

Figure 8-5 Internal block diagram

back to 2012-Jul-20
div. table
 EN 42 8. L11M1.1L LA IC Data Sheets

Pinning information
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 RT

AO4N GPI O35 GPI O21 GPI O3 ETTXD0 ETRXD2 ETRXD0 A

DVSS GPIO32 GPIO26 GPIO17 GPIO9 ETTXD3 ETRXCLK ETRXD1 ETRXDV B

AO4P GPIO36 GPIO28 GPIO22 GPIO11 GPIO4 ETTXD1 ETRXD3 ETCRS C

DVSS GPIO34 GPIO27 GPIO18 GPIO10 ETTXEN ETTXCLK ETRXER ETMDIO D

AE3N DVSS GPIO30 GPIO20 GPIO12 GPIO6 ETTXD2 ETTXER ETMDC E

CI_MOSTR
AE4N GPIO33 GPIO24 GPIO16 GPIO8 ETPHYCLK CI_MCLKO CI_MCLKI F
T

AE3P DVSS GPIO29 GPIO19 GPIO14 GPIO5 ETCOL CI_MIVAL CI_MOVAL G

AE4P VCCIO33 GPIO25 GPIO15 GPIO7 VCCIO33 CI_MISTR

CI_MDI0 CI_MDO0 H
T

GPIO31 GPIO23 GPIO13 VCCIO33 GPIO2 OPWM0 OPWM1 J

AOSDATA3 ASPDIF GPIO0 GPIO1 K

FSRC_WR ALIN AOBCK AOSDATA0 L

IF_AGC RF_AGC AOMCLK AOLRCK M

TUNER_DA TUNER_CL
DVSS VCCK VCCK AOSDATA4 N
TA K

DVSS DVSS DVSS OSCL2 OSDA2 AOSDATA1 AOSDATA2 P

DVSS DVSS DVSS OSDA1 OSCL1 U1RX R

AVDD33_A VCXO T
DVSS DVSS VCCK OPWM2 U1TX
DAC1

AVSS33_A U
DVSS DVSS DVSS AL1 AR2 AR3
DAC1

DVSS DVSS VCCK VCCIO33 AR1 AL2 AL3 V

DVSS DVSS VCCK AVDD33_R VCCIO33 VCCIO33 VCCIO33 W

EF_AADC

AVSS33_R AVDD33_A AVSS33_A AIN5_R_A AIN6_R_A

DVSS DVSS VCCK
EF_AADC ADC ADC ADC Y
ADC
VMID_AAD AIN4_L_AA AIN5_L_AA AIN6_L_AA
DVSS DVSS VCCK AA
C DC DC DC
AIN1_L_AA AIN4_R_A AIN2_R_A AIN3_R_A
DVSS DVSS VCCK AB
DC ADC ADC
ADC
AIN1_R_A AIN0_R_A AIN3_L_AA
DVSS DVSS DVSS AC
ADC ADC DC

AIN0_L_AA AIN2_L_AA
DVSS DVSS DVSS AD
DC DC
AVSS33_A
VCCK VCCK DVSS AR0 AE
DAC0
AVDD12_T AVDD33_
AVICM AL0 AF
VDPLL ADAC0

AVDD12_A AVDD12_S AVDD33_ AVSS33_D

PLL YSPLL DEMOD1 EMOD1 AG
AVSS12_P AVSS12_P AVDD12_A ADCINN_D ADCINP_D
LL LL DCPLL EMOD AH
EMOD
AVSS33_D
XTALO XTALI AJ
IG
AVSS33_SI AVDD33_D ADIN1_SR AVDD33_X AVSS33_X
AK
F IG V TAL_STB TAL
AVSS33_V AVDD33_S ADIN0_SR ADIN3_SR ADIN5_SR
OPWRSB ORESET_ AL
GA_STB IF V V V
AVDD10_L AVDD12_R ADIN2_SR ADIN4_SR
OPCTRL0 FS_VDAC BYPASS0 AF
V V AM
DO GB
AVDD33_V AVSS12_R AVDD33_V AVDD33_C
OPCTRL2 OIRI MPXP MPXN AN
GA_STB GB DAC VBS

VDAC_OUT TUNER_BY
U0TX SOG SOY1 PR1P PB0P SY0 CVBS2P
1 AP
PASS
AVSS33_V AVSS33_C
OPCTRL3 HSYNC COM COM1 Y0P SY1 CVBS0N AR
DAC VBS
VDAC_OUT
U0RX BP RP PB1P COM0 SC0 CVBS3P CVBS0P AT
2

OPCTRL4 VSYNC GP Y1P SOY0 PR0P SC1 CVBS1P AU

20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 RB

18850_302_100107.eps
100222

Figure 8-6 Internal block diagram

2012-Jul-20 back to
div. table
 IC Data Sheets L11M1.1L LA 8. EN 43

8.5 Diagram 10-9-2 Analog I/O - Audio B06B, Type LM833 (IC7B01)

Pinning information

Output 1 1 8 VCC

2 1 7 Output 2
Inputs 1
3 6

2 Inputs 2
VEE 4 5

(Top View)
18520_306_090325.eps
100402

Figure 8-7 Pin configuration

back to 2012-Jul-20
div. table
 EN 44 8. L11M1.1L LA IC Data Sheets

8.6 Diagram 10-24-3 TCON DC/DC T01C, Type ISL97653 (IC7J00)

Block diagram RSET HVS VREF PROT

HVS SAWTOOTH
CM1
LOGIC GENERATOR
GM AMPLIFIER
FBB - SLOPE LX1
+ COMPENSATION LX2
VREF BUFFER

CONTROL
Ε
UVLO COMPARATOR LOGIC
-
+
RSENSE
CURRENT PGND1
0.75 VREF AMPLIFIER PGND2

680kHz
FREQ
OSCILLATOR
VL

PVIN1,2 CURRENT LIMIT

REGULATOR
COMPARATOR
REFERENCE BIAS

CDEL AND
CURRENT LIMIT
EN SEQUENCE CONTROLLER THRESHOLD

VL
PVIN1,2 CB
SUPN

LXL1
LXL2
NOUT CONTROL
LOGIC
CURRENT
BUFFER CM2
LIMIT GM AMPLIFIER
COMPARATOR CURRENT AMPLIFIER
FBN - - FBL
+ - Ε +
+
0.2V VREF
CURRENT LIMIT SLOPE
THRESHOLD COMPENSATION
UVLO COMPARATOR
- SAWTOOTH
+ GENERATOR
0.4V

0.75 VREF LDO-CTL

LDO
- CONTROL
+ LOGIC2 LDO-FB

SUPP TEMP TEMP

FBP - SENSOR
+
VREF

POUT

SUPP

C1- C1+ POUT C2+ C2- DRN CTL COM

Pinning information
LDO-CTL

LDO-FB

PGND2

PGND1
AGND
PVIN1

TEMP
PROT

LX2

LX1

40 39 38 37 36 35 34 33 32 31

PVIN2 1 30 COMP

CB 2 29 FBB

LXL1 3 28 RSET

LXL2 4 27 HVS

PGND3 5 ISL97653A 26 EN
40 LD 6X6 QFN
PGND4 6 TOP VIEW 25 CDEL

CM2 7 24 CTL

FBL 8 23 DRN

VL 9 22 COM

VREF 10 21 POUT

11 12 13 14 15 16 17 18 19 20
PGND5

C1P

C2P

SUPP

FBP
FBN

SUPN

NOUT

C1N

C2N

18770_307_100217.eps
100217

Figure 8-8 Internal block diagram and pin configuration

2012-Jul-20 back to
div. table
 Block Diagrams L11M1.1L LA 9. EN 45

9. Block Diagrams
9-1 Wiring Diagram 32" (Thriller)
WIRING DIAGRAM 32" THRILLER

Board Level Repair

Component Level Repair

Only For Authorized Workshop
LCD DISPLAY
(1004) TO DISPLAY

1M99 8G51
TO BACKLIGHT

14P

8319

MAIN POWER SUPPLY LOUDSPEAKER

32 PSLC-P002A (5213)
(1005)

1M99
9P 1G51
1M95 51P

1M99
11P

8M99

9P

USB
SSB
B

1M95
3139 123 6505.x

11P
8M95
(1150)
KEYBOARD CONTROL

1M20 1735
4P
8P

TUNER

HDMI
(1114)

8M20
HDMI VGA
2P3
3P
J1

1308
N L

8308
INLET

J2 J1 IR/LED BOARD
3P 8P (1112)
MAINS CORD
8191

1M95 (B01) 1M99 (B01) 1M20 (B04c) 1735 (B03) 1G51 (B04D)
1. +3V3STDBY 1. +12VDISP 1. LIGHT-SENSOR 1. LEFT_SPEAKER 1. +VDISP-INT
2. STANDBY 2. +12VDISP 2. GND 2. GND-AUDIO 2. +VDISP-INT
3. GND 3. GND 3. RC 3. GND-AUDIO 3. +VDISP-INT
4. GND 4. GND 4. LED-2 4. RIGHT_SPEAKER 4. +VDISP-INT
5. GND 5. LAMP-ON 5. +3V3STBY |
6. +12VS 6. BACKLIGHT-PWM 6. LED-1 51. GND
7. +12VS 7. BACKLIGHT-BOOST 7. KEYBOARD
8. +12VS 8. INV_STATUS 8. +5V_SW
9. +24VAUDIO 9. POWER-OK
10. GND-AUDIO
19130_044_110428.eps
11. ...
110429

2012-Jul-20 back to
div. table
 Block Diagrams L11M1.1L LA 9. EN 46

9-2 Wiring Diagram 40" (Thriller)

WIRING DIAGRAM 40" THRILLER

TO DISPLAY LCD DISPLAY TO DISPLAY

Board Level Repair (1004)

Component Level Repair

8KA1
Only For Authorized Workshop 8KA2

TO BACKLIGHT
TO BACKLIGHT

8319

8316
1KA2 1KA1
80P 80P

TCON
T (1157)

1N01
LOUDSPEAKER 51P
1319 1316
(5213)
1P3 1P3

HIGH VOLTAGE

8G51
MAIN POWER SUPPLY

1M99
9P
IPB 40 PLHE-P986A
(1005)

1G51
51P
SSB
B
1M95
11P
3139 123 6505.x
(1150)

1M99
8M99

9P
1M95
11P
8M95

TUNER
1M20 1735
4P
8P
KEYBOARD CONTROL

USB
HDMI
PHONE
SPDIF
HDMI HDMI

8M20
VGA

2P3
(1114)

1308
N L
1M95 (B01) 1M99 (B01) 1M20 (B04c) 1KA1 (T01F) 1KA2 (T01F)
1. +3V3STDBY 1. +12VDISP 1. LIGHT-SENSOR 1. GND 1. GND
8308
INLET 2. STANDBY 2. +12VDISP 2. GND | |
3P
J1

3. GND 3. GND 3. RC 11. VLS_15V6 11. VLS_15V6

4. GND 4. GND 4. LED-2 12. VLS_15V6 12. VLS_15V6
5. GND 5. LAMP-ON 5. +3V3STBY | |
6. +12VS 6. BACKLIGHT-PWM 6. LED-1 33. VCC_3V3 33. VCC_3V3
7. +12VS 7. BACKLIGHT-BOOST 7. KEYBOARD 34. VCC_3V3 34. VCC_3V3
8. +12VS 8. INV_STATUS 8. +5V_SW | |
9. +24VAUDIO 9. POWER-OK 78. VGH_35V 78. VGH_35V
MAINS CORD

IR/LED BOARD 10. GND-AUDIO 79. VGL_-6V 79. VGL_-6V

1735 (B03)
8191

J2 J1 11. ... 80. GND 80. GND

3P 8P (1112) 1G51 (B04D) 1. LEFT_SPEAKER
1. +VDISP-INT 2. GND-AUDIO
2. +VDISP-INT 3. GND-AUDIO 1N01 (T01A)
3. +VDISP-INT 4. RIGHT_SPEAKER 1. GND
4. +VDISP-INT |
| 47. +VDISP-INT
51. GND 48. +VDISP-INT
49. +VDISP-INT
50. +VDISP-INT
|
51. GND

19130_043_110428.eps
110429

2012-Jul-20 back to
div. table
 Block Diagrams L11M1.1L LA 9. EN 47

9-3 Wiring Diagram 32" (Berlinale)

WIRING DIAGRAM 32" BERLINALE

8M95

TO DISPLAY
SUPPLY
1316 1M95
10P 14P

LOUDSPEAKER
(5213)

MAIN POWER SUPPLY

32" PLDC-P015A
(1005)

1M95
14P

SSB
B

USB
1G51
51P
8G51 3139 123 6523.x
(1150)

TUNER
1D38
3P

HDMI
1M20
LCD DISPLAY TO DISPLAY

8P
(1004) 51P
2P HDMI HDMI VGA
130
8
LOUDSPEAKER

LOUDSPEAKER
8308
(5216)

(5216)
INLET

C2 C1
MAINS
SWITCH

(8308) IR/LED/CONTROL BOARD J1

(1108) 8P
LEADING EDGE
1M95 (B01) 1735 (B03A)
1D38 (B03) 1M20 (B04C)
1. +3V3STBY 1. LEFT-SPEAKER
LEFT_SPEAKER 1. LIGHT-SENSOR
2. STANDBY 2. GND-AUDIO 2. GND
3. GND 3. GND-AUDIO
RIGHT_SPEAKER 3. RC
4. GND 4. RIGHT-SPEAKER 4. LED-2
5. +12VS 5. +3V3STBY
6. +12VS 6. LED-1
7. +24VAUDIO 1G51 (B06B) 7. KEYBOARD
8. GND 1. +VDISP-INT 8. +5V_SW
9. LAMP-ON 2. +VDISP-INT
10. BACKLIGHT-PWM 3. +VDISP-INT
11. BACKLIGHT-BOOST 4. +VDISP-INT
12. POWER-OK |
13. N.C. |
14. GND 51. GND 19130_053_110616.eps
110928

2012-Jul-20 back to
div. table
 Block Diagrams L11M1.1L LA 9. EN 48

9-4 Wiring Diagram 40" (Berlinale)

WIRING DIAGRAM 40" BERLINALE

TO DISPLY
SUPPLT

1316
10P

1M99
14P
8M95

MAIN POWER SUPPLY

40" PLDE-P016A
(1005)

1M95
14P

SSB
B

USB
1G51
51P
3139 123 6523.x

1308
2P
(1150)

TUNER
1D38
LOUDSPEAKER

3P

HDMI
(5213) 8G51

1M20
8P
HDMI HDMI VGA

LCD DISPLAY TO DISPLAY

(1004) 51P

8308

INLET

LOUDSPEAKER LOUDSPEAKER
(5216) (5217)

MAINS C2 C1
SWITCH

(8308)
IR/LED/CONTROL BOARD J1
(1108) 8P 1M95 (B01) 1735 (B03A)
1D38 (B03) 1M20 (B04C)
1. +3V3STBY 1. LEFT-SPEAKER
LEFT_SPEAKER 1. LIGHT-SENSOR
LEADING EDGE 2. STANDBY 2. GND-AUDIO 2. GND
3. GND 3. GND-AUDIO
RIGHT_SPEAKER 3. RC
4. GND 4. RIGHT-SPEAKER 4. LED-2
5. +12VS 5. +3V3STBY
6. +12VS 6. LED-1
7. +24VAUDIO 1G51 (B06B) 7. KEYBOARD
8. GND 1. +VDISP-INT 8. +5V_SW
9. LAMP-ON 2. +VDISP-INT
10. BACKLIGHT-PWM 3. +VDISP-INT
11. BACKLIGHT-BOOST 4. +VDISP-INT
12. POWER-OK |
13. N.C. |
51. GND 19130_054_110617.eps
14. GND 110617

2012-Jul-20 back to
div. table
 Block Diagrams L11M1.1L LA 9. EN 49

9-5 Block Diagram Video 3939 123 65052

VIDEO SBB 3139 123 6505.x
B02A TUNER +5VTUN_DIGITAL B02A DIGITAL DEMOD B04 MT5363: B04D LVDS DISPLAY T01A LVDS T01B TCON CONTROL T01E MPD T01F MINI LVDS
1201 7302 7700 DISLAY 7H01
VA1E1BF2403 VPP1501BFG

5208
TC90517FG MT5363BIMG
8 1KA1
B04C MAC-CI B08A
+B RESET_DEMOD 42 1KA1 1N01 81
B04C DIGITAL 58 TSO_VALID G34 B05A HDMI-LVDS INTERFACE
CI_MIVAL 60 1 79
TUNER DEMODULATOR
59 TSO_SYNC H33 7L00
VGL_-6V
78
CI_MISTRT VGH_35V
10 DIF_N 29 ISL24016IRTZ 72
IF_OUT+ 61 TSO_CLK F35
CI_MCLKI LEVEL CS(1-12)
11 DIF_P 30 RXO ASIC_CS 61
IF_OUT- 60 TSO_DATA0 H35 AO PX1 PX1 SHIFTER
6 CI_MDIO VH
SCL AGCCNTI 9
7 (I2C) 50
SDA B04C CONTROL TO DISPLAY
9 IF_AGC M31 LLV(0-7)
IF_AGC AGC_IF 13
3 7218 RF_AGC M33 AE PX2 PX2 RXE 34
RF_AGC AGC_RF
47 33
VCC_3V3
4 48 12
3 49 11
7217 VLS_15V6
RF_AGC_SW 2 50 10
B04C RF_AGC_SW +VDISP-INT
1 60 VL
B06B AUDIO-VIDEO
+VDISP-INT T01D P GAMMA & 2
B06C ANALOG I/O - VIDEO B06B ANALOG I/O VCOM & NVM 1
AUDIO
7K00 1KA2
3B08 ISL24837IRZ
SOY0-AV1 Y0N AT29 81

Y
1C01
12 SC1_G 5C05 3C24 SY0P 3B07 Y0P AR28
SOY0

Y0P
MT5363 REF
VOLTAGE
GEN
VL/VH VGL_-6V
VGH_35V
79
78

SC1_B 5C04 3C23 SPB0P 3B09 PB0P AP29 72

9 PB0P
CVI-1 PB 3C21 SPR0P 3B11
SC1_CVBS_OUT 5C03 PR0P AU30 61
PR0P VH
7 50
PR TO DISPLAY
AK22 RLV(0-7)
PBR0N 13

SOY1-AV2 3B00 AP25 34

1C02 SOY1
33
3C25 3B01 VCC_3V3
12 SY1P_SC2 5C02 SY1P AU26 12
Y Y1P
3C22 3B03 11
PB1P_SC2 5C01 SPB1P AT27 VLS_15V6
9 PB1P 10
CVI-2 PB
PR1P_SC2 5C00 3C20 SPR1P 3B05 VL
AP27
PR1P 2
7
2C06

PR 3B02 1
SY1N AR26
Y1N
1C03

AVIN 2 CVBS_AV3 AP35

B04C CONTROL B05B USB
CVBS CVBS_2P 1D01
2C07

1
USB 2.0

1
GND_CVBS AR36 AR10 USB_DM 2
CVBS_0N CONNECTOR SIDE

3 2
USB_DM
AU10 USB_DP 3 SW UPLOAD
USB_DP JPEG
B06D VGA 4

4
MP3
1E01
1 VGA_R VGA_Rp RP AT25 RP
2 VGA_G VGA_Gp GP AU24
10

B04C CONTROLLER
15

GP
5

3 VGA_B VGA_Bp BP AT23

BP 7708
13 H-SYNC HSYNC AR22 H27U1G8F2BTR
HSYNC
1

6
11

14 V-SYNC VSYNC AU22

VSYNC
2E08

2E03

VGA SOG AP23 FLASH

CONNECTOR SOG PDD NAND_PDD(0-7)
AR24
1Gb
GN
COM

B05A HDMI & MUX B05 HDMI-LVDS

1902
B04B DRAM
1 M_RX2_2 AP19 B04B DDR
3 M_RX2_2B AT19
1

4 M_RX2_1 AR18
2

RDQ RDQ(0-31)
6 M_RX2_1B AU18

RDQ(16-31)
RDQ(0-15)

7 M_RX2_0 AP17 RX1 7600 7601

9 M_RX2_0B AT17 H5PS5162FFR H5PS5162FFR
18
19

10 M_RX2_C AR16
HDMI 2
12 M_RX2_CB AU16 SDRAM SDRAM
CONNECTOR 512Mb 512Mb
1901
1 M_RX1_2 AP15
VDD

VDD
3 M_RX1_2B AT15
1
2

4 M_RX1_1 AR14 A1 A1
6 M_RX1_1B AU14
RA RA(0-13)
7 M_RX1_0 AP13 RX2
9 M_RX1_0B AT13 +1V8_SW
18
19

10 M_RX1_C AR12
HDMI 1 (SIDE) 12 M_RX1_CB AU12
CONNECTOR 19130_020_110427.eps
110621

2012-Jul-20 back to
div. table
 Block Diagrams L11M1.1L LA 9. EN 50

9-6 Block Diagram Audio 3939 123 65052

AUDIO SBB 3139 123 6505.x
B02A TUNER B02B DIGITAL DEMOD B04 MT5363: B06B ANALOG I/O - AUDIO B03 CLASS-D & MUTING
+5VTUN_DIG
1201 7700
VA1E1BF2403

5207
7302 MT5363BHMG
8 TC90517FG
B04C MAC-CI
+B B06B ALI_ADAC
DIGITAL 58 TSO_VALID G34
RESET_DEMOD 42 CI_MIVAL
TUNER B04C DEMODULATOR
59 TSO_SYNC H33
CI_MISTRT
10 DIF_N 29
IF_OUT+ 61 TSO_CLK F35 7400
CI_MCLKI 7B01 1735
DIF_P TPA3123D2PWP
11 30
IF_OUT- 60 TSO_DATA0 H35 V37 PREAMPL 2 1 AOUTL 5 22 LEFT_SPEAKER 1
6 CI_MDIO AL_L
SCL AGCCNTI 9 SPEAKER
7 (I2C)
SDA B04C CONTROL u36 PREAMPR 6 7 AOUTR 6 2 LEFT
IF_AGC M31 AR_R
IF_AGC
9
AGC_IF CLASS D
POWER GND-AUDIO
3
3 7218 RF_AGC M33
RF_AGC AGC_RF AMPLIFIER SPEAKER
15 RIGHT_SPEAKER 4 RIGHT
MUTE 4
B04C
7217 RESET_AUDIO
RF_AGC_SW B04C A_STBY 2
B04C RF_AGC_SW STANDBY
SW_MUTE
B04C 7408
DC_PROT
B06C ANALOG I/O - VIDEO B06B ALI_DAC B04C DC-DETECTION

1C01

CVI-1
AV IN
AUDIO
L/R
5

3
AIN0_L-AV1

AIN0_R-AV1
AD33

AC34
AIN_AADC_0_L
MT5363
AIN_AADC_0_R

1C02
5 AIN1_L-AV2 AB31
AV IN AIN_AADC_1_L
CVI-2 AUDIO
L/R 3 AIN1_R-AV2 AC32
AIN_AADC_1_R
B04C CONTROL B05B USB
1D01
1
USB 2.0

1
1C03 AR10 USB_DM 2 CONNECTOR SIDE

3 2
USB_DM
AU10 USB_DP 3 SW UPLOAD
5 SAV_L_IN AA36 USB_DP JPEG
AIN_AADC_6_L 4

4
AV IN MP3
AVIN AUDIO
8 SAV_R_IN Y37
L/R AIN_AADC_6_R

B04C CONTROLLER
7708
B06B ANALOG I/O - AUDIO H27U1G8F2BTR
1B01
2 DVI_AUL_IN AC36
AIN_AADC_3_L
AV IN FLASH
3 DVI_AUR_IN AB37 PDD NAND_PDD(0-7)
AUDIO AIN_AADC_3_R 1Gb
L/R
1
+3V3
7S09
1B02 74LVC00
2
SPDIF 2 SPDIF_OUT 3 &
OUT 1 ASPDIF_OUT K33
ASPDIF B04B DRAM
4 B04B DDR
eHDMI+ 8 B05 GPIO
5 ARC_SW E28 GPIO_12
ASPDIF
RDQ RDQ(0-31)
B05A HDMI & MUX

RDQ(16-31)
RDQ(0-15)
1901 B05 HDMI 7600 7601
1 M_RX1_2 AP15 H5PS5162FFR H5PS5162FFR
3 M_RX1_2B AT15
SDRAM SDRAM
1
2

4 M_RX1_1 AR14
6 M_RX1_1B AU14 512Mb 512Mb
7 M_RX1_0 AP13 RX1
9 M_RX1_0B AT13
18

VDD

VDD
19

10 M_RX1_C AR12
HDMI 1 (SIDE) 12 M_RX1_CB AU12 A1 A1
CONNECTOR 14
RA RA(0-13)
+1V8_SW
1902
1 M_RX2_2 AP19
3 M_RX2_2B AT19
1

4 M_RX2_1 AR18
2

6 M_RX2_1B AU18
7 M_RX2_0 AP17 RX0
9 M_RX2_0B AT17
18
19

10 M_RX2_C AR16
12 M_RX2_CB AU16
HDMI 2
19130_038_110427.eps
CONNECTOR
110621

2012-Jul-20 back to
div. table
 Block Diagrams L11M1.1L LA 9. EN 51

9-7 Block Diagram Control & Clock Signals 3939 123 65052
CONTROL + CLOCK SIGNALS SBB 3139 123 6505.x
B04 MT5363 7700 B04B DDR T01B TCON CONTROL
MT5363BIMG 7H01
VPP1501BFG
B04B DRAM 7H00
RDQ RDQ(0-31) H5PS5162FFR TCON

RDQ(16-31)
CONTROL T01F

RDQ(0-15)
LLV(0-7)
7600 7601 SDRAM TDQ(0-15)
H5PS5162FFR H5PS5162FFR
512Mb TA(0-12)
SDRAM SDRAM TCK L2
T01F
RLV(0-7)

MT5363 512Mb 512Mb TCK# L1

A1
OSC_IN SLOPE
T16 GSLOP
T01C

J8 K8 J8 K8
1H00
27M
T01E MPD
B1
OSC_OUT 7L00
RA RA(0-13)
AD1 RCLK1 SL24016IRTZ
CLK
AD3 RCLK1# RESET T9 LEVEL
CLK T01D RST CS(1-12) T01F
50Hz_60Hz U9 CS ASIC_CS SHIFTER
B3 RCLK0 T01D RTC50_60
CLK
A2 RCLK0#
CLK

B04C GPIO
B04C CONTROLLER B04C FLASH & EJTAG & DISPLAY INTERFACE T01D P GAMMA & VCOM & NVM
BYPASS_MODE B23
B08C GPIO_32 EDID_WC
H29 7K00
RF_AGC_SW B29 GPIO_7 B06 B07E
B02A GPIO_9 ISL24837IRZ
A22 LCD-PWR-ONn
DC_PROT AG6 GPIO_35 B04C
B03 GPIO_42
USB_PWR_EN G30 AH3 LAMP-ON VH T01F
B06D GPIO_5 GPIO_43 B01A
USB_OCP E30 AG4 POWER-OK
B06D GPIO_6 GPIO_41 B01A VL T01F
RESET_DEMOD A30 E28 ARC_SW
GPIO_12 B06B
B02B GPIO_3 P
2701 B25
GAMMA
GPIO_26
SDM
2700 7708 25 OUTCOM
A26 OUTCOM
GPIO_21 H27U1G8F2BTR VCOM VCOM
T01F
PANEL 26 INCOM
OUT12 BUFER
B04C CONTROL
FLASH
PDD NAND_PDD(0-7)
1Gb
24 CS_L
OUT12 T01E

AJ36 1701
XTAL1
U0_RX AT21 3
1700 UART
54M AP21 2 SERVICE
AJ34 U0_TX
XTALO CONNECTOR
1

7710
AL20 STANDBY
OPWRSB B01
1M20
3 RC AN22
OIRI
2 AN14 HDMI_CEC
HDMI_CEC B05A
5 AM21 POWER_DOWN
TO IR/LED PANEL +3V3STBY OPCTRL_0 B04C
AND AU20 MUTE
OPCTRL_4 B03
KEYBOARD CONTROL
4 LED-2 AM37 AR20 SW_MUTE
ADIN_SRV_4 OPCTRL_3 B03
7 KEYBOARD AM35
ADIN_SRV_2 B06D USB
1 LIGHT-SENSOR AL36
ADIN_SRV_5 7D00
TPS2041BD
USB_PWR_EN
EN B04C
OUT USB_OCP
OC B04C
+3V3STBY
7701
BD45292G 1D01
5 1
VDD
1

4 ORESET AL22 AJ5 USB_DM0 2 USB 2.0

VOUT ORESET USB_DM0
3 2

AK5 USB_DP0 3 CONNECTOR

USB_DP0 SIDE
4
4

3
19130_045_110428.eps
110621

2012-Jul-20 back to
div. table
 Block Diagrams L11M1.1L LA 9. EN 52

9-8 Block Diagram I2C 3939 123 65052

I²C SBB 3139 123 6505.x
B04C CONTROLLER B06D VGA B04D LVDS DISPLAY
DC_5V
7700 +3V3_SW
MT5363BIMG

3E21

3E22
1E01

10

15
3718

3719
12 4E03 SDA_VGA 4818

5
B04C CONTROL
AP1 SDA-MAIN 4E02 4817
OSDA_0 15 SCL_VGA

6
11
AP3 SCL-MAIN
OSCL_0
VGA

3717

3716
CONNECTOR 5 6 7 8
5 6
7703 7E00 7801
AH1 SYS_EEPROM_WE 7 M24C02 PCA9540BDP
GPIO_44 7702 1G51
M24C64 4816 50
7708 EEPROM I2C SDA_VCOM
H27U1G8F2BTR 7E01 SWITCH TO
EEPROM 4814 49
SCL_VCOM
MT5363 (NVM) B04C
EDID_WC 7 TCON

FLASH ERR EDID

PDD NAND 35 SW
1Gb
MAIN NVM +3V3STBY
SW

3746

3747
1701
AT21 3727 3749
U0_RX 3
UART
3728 3748 SERVICE
AP21 2
U0_TX CONNECTOR
1

B2B DIGITAL DEMOD B02A TUNER

+3V3STBY T01A LVDS DISPLAY T01D P GAMMA & VCOM & NVM
3746

3747

VCC_3V3
N34 TUNER_SDA
TUNER_DATA

3K40

3K41
N36 TUNER_SCL 1N01 1KQB
TUNER_CLK
2 SDA-TCON 1
3352

3351

TO
B04B DRAM SSB 3 SCL-TCON 2
B4B DDR 46 45
BYPASS_MODE 4
RDQ RDQ(0-31) 7302 14 FE_SDA B04C
7600 7601 TC90517FG 12 13
H5PS5162FFR H5PS5162FFR 12 FE_SCL RES
DIGITAL 7K00

3228

3230
SDRAM SDRAM DEMODULATOR ISL24837IRZ
512Mb 512Mb 7 6
VOLTAGE
GENERATOR
1201
VA1E1BF2403

RA RA(0-13) MAIN
TUNER

ERR
B05A HDMI & MUX HDMI_PLUGPWR2 34
T01B TCON CONTROL VCC
3907

3908

1901

3K54

3K53
16 1KQA
AL14 SIDE_HDMI_SDA1
HDMI_SDA2 ROM_SDA 2
HDMI 1 (SIDE)
AL12 SIDE_HDMI_SCL1 15 CONNECTOR
HDMI_SCL2 1
ROM_SCL
HDMI_PLUGPWR2

3K56

3K55
3915

3916

1902 U8 T8 5 6
AN18 HDMI_SDA2 16
HDMI_SDA1 7 WP_TCON 3
HDMI 2 7H01 7K04
AM17 HDMI_SCL2 15 CONNECTOR VPP1501BFG M24C64
HDMI_SCL1 RESET 4
5 6 5 6 B08A
TCON EEPROM SW Programmable via USB
7900 7901 CONTROL RES SW Programmable via ComPair
M24C02 M24C02

EEPROM EEPROM
EDID EDID
SW SW
DEBUG ONLY 19130_011_110426.eps
110621

2012-Jul-20 back to
div. table
 Block Diagrams L11M1.1L LA 9. EN 53

9-9 Supply Lines Overview 3939 123 65052

SUPPLY LINES OVERVIEW SSB 3139 123 6505.X
B01 DC - DC B05A HDMI & MUX T01A LVDS DISPLAY
1N01
1M99 1M99 B02B DIGITAL Demod
B01
+3V3STBY +3V3STBY
+VDISP-INT
1 1 +12VDISP 47
+2V5_SW +2V5_SW T01c
B04d +5V_SW +5V_SW TO 1G51 48
B01 B01
6900 B04D 49
2 2 +1V25_SW +1V25_SW HDMI_PLUGPWR1 SSB 50
B01 6901
3 3 HDMI_PLUGPWR2
+3V3_SW +3V3_SW
4 4 B01

HDMI 2
1902
18 PWR5V_2
T01B TCON CONTROL
5 5 LAMP-ON
B04C CONNECTOR VCC_3V3 VCC_3V3
CONTROL T01c
6 6 BACKLIGHT-PWM 1901 5H02 VDD3V3LVRS
B04C PWR5V_1
CONTROL B03 CLASS-D & MUTING HDMI 1 SIDE
CONNECTOR
18
5H03
7 7 BACKLIGHT-BOOST VDD3V3IO
+3V3STBY +3V3STBY
B01 VCC_1V8 VCC_1V8
8 8 INV_STATUS +5V_SW +5V_SW T01c
B04C B01 5H00 VDD1V8
9 9 POWER-OK
CONTROL
B01
+12VS +12VS B05B USB
MAIN B06D
CONTROL B01
+24VAUDIO +24VAUDIO
B01
+5V_SW +5V_SW
5H01 VDD1V8PLL

5H05 DDR2VDD
POWER 1M99 1M95
5H06
1 1 +3V3STBY
SUPPLY 2 2 STANDBY
B03,B04a,c,d,
B05a B06A ANOLOG I/O - HEADPHONE 5H04
B04A B04A MTK POWER
3 3 CONTROL +3V3_SW +3V3_SW
+1V25_SW +1V25_SW B01 VGH_35V VGH_35V
4 4 B01 T01c
+1V1_SW +1V1_SW
5 5 B01
SENCE+1V1_MT5363 B01
+12VS
6 6
B03,B04c,B06b +3V3STBY +3V3STBY B06B ANALOG I/O - AUDIO
T01C TCON DC/DC
7 7 7122 B01
RT8283AHGSP B01 +3V3_SW +3V3_SW
5117 2 5121 +1V8_SW +1V8_SW
8 8 Synchronous 3 +3V3_SW B02b,B04a,c,d, B01 3B54 +3V3-ARC +VDISP-INT +VDISP-INT
Step-down 7119 B06a,b SENCE_1V8
Converter +1V25_SW B01 T01a
IN OUT +12VS +12VS
COM B02b,B04a +3V3_SW +3V3_SW B01 4J04 +VDISP
7123 B01 T01d,e
RT8283AHGSP 7J01 5J06 VLS_15V6_B
5120 2 Synchronous 3 5104 +5V5_TUN
B02a 4J01
Step-down B06D VGA VLS_15V6
T01f,d
Converter 6122 +5V_SW
B02a,B03.B04c,
B04B DDR 7J00
B01 +5V_SW +5V_SW ISL97653
B05a,b,B06d +1V8_SW +1V8_SW 3J10 3J26 VGL_-6V
1E01 10
7120 B01 VGA 9 3E13 6E05 5E03 DC_5V
6J02 4J02 T01f
+2V5_SW LCD 21 VGH_35V
IN OUT CONNECTOR
COM B02b SUPPLY T01b,f
7124 B04C CONTROLLER 3,4 5J00 VCC_3V3
RT8283AHGSP 3J12 T01b,d,f
5115 2 5123 39 VCC_1V8
Synchronous 3 +1V8_SW +3V3_SW +3V3_SW
B04a,b T01b
Step-down B01
Converter
7125
RT8283AHGSP +3V3STBY +3V3STBY
5105 2
Synchronous 3
5106 +1V1_SW B01
+5V_SW +5V_SW
T01D P GAMMA & VCOM & NVM
Step-down B04a
B01 1M20
Converter
6102 3130 EN_1 5 VCC_3V3 VCC_3V3
TO
IR/LED T01c
5706 8 VLS_15V6 VLS_15V6
9 9 +24VAUDIO PANEL
T01c
B03 +12VS +12VS 7K00
B01 ISL24837IRZ
10 10 32 VREF_15V2
VOLTAGE T01e
GND-AUDIO GENERA-
11 11 TOR
N.C. B04D LVDS DISPLAY +VDISP +VDISP
T01c
+12VDISP +12VDISP
1G51
B01
7800 5800 +VDISP-INT 1
2 TO 1N01
5801
SENSE+1V1_MT5363 SENSE+1V1_MT5363 3 T01A T01E MPD
B04a 7802 5802 4 TCON
LCD-PWR-ONn
SENSE_1V8 SENSE_1V8 VREF_15V2 VREF_15V2
B04a T01d
+3V3STBY +3V3STBY +VDISP +VDISP
B01 T01c
+3V3_SW +3V3_SW
B01
B02A TUNER

+5V5_TUN +5V5_TUN T01F MINI LVDS

B01
7216 VCC_3V3 VCC_3V3
IN OUT 5225 +5VTUN_DIGITAL T01c
COM VGL_-6V VGL_-6V
B08c
+5V_SW +5V_SW VGH_35V VGH_35V
B01
T01c
5222 VLS_15V6 VLS_15V6
+5VS
T01c

19130_005_110426.eps
110621

2012-Jul-20 back to
div. table
 Block Diagrams L11M1.1L LA 9. EN 54

9-10 Block Diagram Video 3939 123 65231

VIDEO SSB 3139 123 6523.x
B02A TUNER +5VTUN_DIGITAL B02A DIGITAL DEMOD B04 MT5363: B04D LVDS DISPLAY
1201 7302 7700
VA1E1BF2403

5208
TC90517FG MT5363BIMG
8 B04C MAC-CI
+B RESET_DEMOD 42 1KA1
B04C DIGITAL 58 TSO_VALID G34 B05A HDMI-LVDS
CI_MIVAL 60
TUNER DEMODULATOR
59 TSO_SYNC H33
CI_MISTRT
10 DIF_N 29
IF_OUT+ 61 TSO_CLK F35
CI_MCLKI
11 DIF_P 30
IF_OUT- 60 TSO_DATA0 H35 AO PX1
6 CI_MDIO
SCL AGCCNTI 9
7 (I2C)
SDA B04C CONTROL
9 IF_AGC M31
IF_AGC AGC_IF

3 7218 RF_AGC M33 AE PX2

RF_AGC AGC_RF

4
3
7217
RF_AGC_SW 2
B04C RF_AGC_SW
1
+VDISP-INT
B06B AUDIO-VIDEO
B06C ANALOG I/O - VIDEO B06B ANALOG I/O
AUDIO

SOY0-AV1 3B08 Y0N AT29

Y
1C01
12 SC1_G 5C05 3C24 SY0P 3B07 Y0P AR28
SOY0

Y0P
MT5363
SC1_B 5C04 3C23 SPB0P 3B09 PB0P AP29
9 PB0P
CVI-1 PB 3C21 SPR0P 3B11
SC1_CVBS_OUT 5C03 PR0P AU30
PR0P
7
PR
AK22
PBR0N

SOY1-AV2 3B00 AP25

1C02 SOY1
12 SY1P_SC2 5C02 3C25 SY1P 3B01 AU26
Y Y1P
PB1P_SC2 5C01 3C22 SPB1P 3B03 AT27
9 PB1P
CVI-2 PB
PR1P_SC2 5C00 3C20 SPR1P 3B05
AP27
PR1P
7
2C06

PR 3B02
SY1N AR26
Y1N
1C03

AVIN 2 CVBS_AV3 AP35

B04C CONTROL B05B USB
CVBS CVBS_2P 1D01
2C07

1
USB 2.0

1
GND_CVBS AR36 AR10 USB_DM 2
CVBS_0N CONNECTOR SIDE

3 2
USB_DM
AU10 USB_DP 3 SW UPLOAD
USB_DP JPEG
B05A B06D 4

4
HDMI & MUX 9710 VGA MP3
1E01
1903 SII9187BC
1 VGA_R RP AT25 RP
1 BRX2+ 8
2 VGA_G GP AU24
10

B04C
15

3 BRX2- 7 GP CONTROLLER
5

3 VGA_B BP AT23
1
2

4 BRX1+ 6 BP 7708
13 H-SYNC HSYNC AR22 H27U1G8F2BTR
6 BRX1- 5 HSYNC
1

6
11

R1 14 V-SYNC VSYNC AU22

7 BRX0+ 4 VSYNC
2E08

2E03

9 BRX0- 3
18

VGA AP23 FLASH

19

SOG
10 BRXC+ 2 CONNECTOR SOG PDD NAND_PDD(0-7)
HDMI 2 12 1 AR24
1Gb
BRXC- GN
COM
CONNECTOR HDMI
1902
1 CRX2+ 18
SWITCH B05 HDMI-LVDS
3 CRX2- 17
B04B DRAM
1

4 CRX1+ 16 B04B DDR

2

6 CRX1- 15
R2
7 CRX0+ 14
RDQ RDQ(0-31)
9 CRX0- 13

RDQ(16-31)
18

AR16 AR16

RDQ(0-15)
62
19

10 CRXC+ 12 TXC_P RX1_C 7600 7601

63 AU16 AU16
HDMI 1 12 CRXC- 11 TXC_N RX1_ CB H5PS5162FFR H5PS5162FFR
60 AP17 AP17
CONNECTOR TX0_P RX1_0
61 AT17 AT17
1901 TX0_N RX1_0B SDRAM SDRAM
1 58 AR18 AR18
DRX2+ 26 TX1_P RX1_1 512Mb 512Mb
3 59 AU18 AU18
DRX2- 25 TX1_N RX1_1B
1

AP19 AP19
2

4 24 56
DRX1+ TX2_P RX1_2

VDD

VDD
6 23 57 AT19 AT19
DRX1- TX2_N RX1_2B
R3
7 DRX0+ 22
A1 A1
9 21
18

DRX0-
19

10 DRXC+ 20 RA RA(0-13)
HDMI SIDE 12 DRXC- 19 +1V8_SW
CONNECTOR

9,27,64
+3V3_SW VCC33 19130_055_110620.eps
110620

2012-Jul-20 back to
div. table
 Block Diagrams L11M1.1L LA 9. EN 55

9-11 Block Diagram Audio 3939 123 65231

AUDIO SSB 3139 123 6523.x
B02A TUNER B02B DIGITAL DEMOD B04 MT5363: B06B ANALOG I/O - AUDIO B03 CLASS-D & MUTING
+5VTUN_DIG
1201 7700
VA1E1BF2403

5207
7302 MT5363BHMG
8 TC90517FG
B04C MAC-CI
+B B06B ALI_ADAC
DIGITAL 58 TSO_VALID G34
RESET_DEMOD 42 CI_MIVAL
TUNER B04C DEMODULATOR
59 TSO_SYNC H33
CI_MISTRT
10 DIF_N 29
IF_OUT+ 61 TSO_CLK F35 7400
CI_MCLKI 7B01 1D38
DIF_P TPA3123D2PWP
11 30
IF_OUT- 60 TSO_DATA0 H35 V37 PREAMPL 2 1 AOUTL 5 22 LEFT_SPEAKER 1
6 CI_MDIO AL_L
SCL AGCCNTI 9
7 (I2C) 2
SDA B04C CONTROL u36 PREAMPR 6 7 AOUTR 6
IF_AGC M31 AR_R
IF_AGC
9
AGC_IF CLASS D GND-AUDIO
POWER 15 RIGHT_SPEAKER 3 SPEAKERS
3 7218 RF_AGC M33
RF_AGC AGC_RF AMPLIFIER
MUTE 4
B04C
7217 RESET_AUDIO
RF_AGC_SW B04C A_STBY 2
B04C RF_AGC_SW STANDBY
SW_MUTE
B04C
7408
B06C ANALOG I/O - VIDEO B06B ALI_DAC
DC_PROT
B04C DC-DETECTION
1C01

CVI-1
AV IN
AUDIO
L/R
5

3
AIN0_L-AV1

AIN0_R-AV1
AD33

AC34
AIN_AADC_0_L
MT5363
AIN_AADC_0_R

1C02
5 AIN1_L-AV2 AB31
AV IN AIN_AADC_1_L
CVI-2 AUDIO
L/R 3 AIN1_R-AV2 AC32
AIN_AADC_1_R
B04C CONTROL B05B USB
1D01
1
USB 2.0

1
1C03 AR10 USB_DM 2 CONNECTOR SIDE

3 2
USB_DM
AU10 USB_DP 3 SW UPLOAD
5 SAV_L_IN AA36 USB_DP JPEG
AIN_AADC_6_L 4

4
AV IN MP3
AVIN AUDIO
8 SAV_R_IN Y37
L/R AIN_AADC_6_R

B04C CONTROLLER
7708
B05A HDMI & MUX 7910
B06B ANALOG I/O - AUDIO H27U1G8F2BTR
1903 SII9187BC 1B01
1 BRX2+ 8 2 DVI_AUL_IN AC36
AIN_AADC_3_L
3 BRX2- 7 AV IN FLASH
3 DVI_AUR_IN AB37 PDD NAND_PDD(0-7)
AUDIO 1Gb
1

AIN_AADC_3_R
2

4 BRX1+ 6
L/R
6 BRX1- 5 1
7 BRX0+ 4
9 BRX0- 3 R1
18
19

10 2 +3V3
BRXC+ 7S09
HDMI 2 12 BRXC- 1 1B02 74LVC00 B04B DRAM
CONNECTOR 2 B04B DDR
SPDIF 2 SPDIF_OUT 3 &
1901 OUT 1 ASPDIF_OUT K33
ASPDIF
1 DRX2+ 26 HDMI 4
B05 GPIO
RDQ RDQ(0-31)
eHDMI+ 8

RDQ(16-31)
RDQ(0-15)
3 DRX2- 25 SWITCH 5 ARC_SW E28 7600 7601
1

GPIO_12
2

4 DRX1+ 24 H5PS5162FFR H5PS5162FFR

6 DRX1- 23 R3
7 DRX0+ 22 SDRAM SDRAM
9 21 B05 HDMI
18

DRX0- 512Mb 512Mb

19

10 DRXC+ 20
HDMI SIDE 12 DRXC- 19
62 AR16 AR16
RX1_C

VDD

VDD
CONNECTOR TXC_P
63 AU16 AU16
9,27,64 TXC_N RX1_ CB
+3V3_SW VCC33 60 AP17 AP17
TX0_P RX1_0 A1 A1
1902 AT17 AT17
61 RX1_0B
1 TX0_N RA RA(0-13)
CRX2+ 18 58 AR18 AR18
TX1_P RX1_1
3 CRX2- 17 59 AU18 AU18 +1V8_SW
TX1_N RX1_1B
1

4 CRX1+ 16
2

56 AP19 AP19
TX2_P RX1_2
6 CRX1- 15 R2 57 AT19 AT19
TX2_N RX1_2B
7 CRX0+ 14
9 CRX0- 13
18
19

10 CRXC+ 12
HDMI 1 12 CRXC- 11
CONNECTOR 14
19130_056_110620.eps
110620

2012-Jul-20 back to
div. table
 Block Diagrams L11M1.1L LA 9. EN 56

9-12 Block Diagram Control & Clock Signals 3939 123 65231
CONTROL + CLOCK SIGNALS
B04 MT5363 7700 B04B DDR
MT5363BIMG

B04B DRAM
RDQ RDQ(0-31)

RDQ(16-31)
RDQ(0-15)
7600 7601
H5PS5162FFR H5PS5162FFR

SDRAM SDRAM

MT5363 512Mb 512Mb

J8 K8 J8 K8
RA RA(0-13)
AD1 RCLK1
CLK
AD3 RCLK1#
CLK
B3 RCLK0
CLK
A2 RCLK0#
CLK

B04C GPIO
B04C CONTROLLER B04C FLASH & EJTAG & DISPLAY INTERFACE
BYPASS_MODE B23
B08C GPIO_32 EDID_WC
RF_AGC_SW H29
B29 GPIO_7 B06 B07E
B02A GPIO_9
A22 LCD-PWR-ONn
DC_PROT AG6 GPIO_35 B04C
B03 GPIO_42
USB_PWR_EN G30 AH3 LAMP-ON
B06D GPIO_5 GPIO_43 B01A
USB_OCP E30 AG4 POWER-OK
B06D GPIO_6 GPIO_41 B01A
RESET_DEMOD A30 E28 ARC_SW
GPIO_3 GPIO_12 B06B
B02B
2701 B25
GPIO_26
SDM
2700 7708
A26
GPIO_21 H27U1G8F2BTR
PANEL
B04C CONTROL
FLASH
PDD NAND_PDD(0-7)
1Gb

AJ36 1701
XTAL1
U0_RX AT21 3
1700 UART
54M AP21 2 SERVICE
AJ34 U0_TX
XTALO CONNECTOR
1

7710
AL20 STANDBY
OPWRSB B01
1M20
3 RC AN22
OIRI
2 AN14 HDMI_CEC
HDMI_CEC B05A
5 AM21 POWER_DOWN
TO IR/LED PANEL +3V3STBY OPCTRL_0 B04C
AND AU20 MUTE
OPCTRL_4 B03
KEYBOARD CONTROL
4 LED-2 AM37 AR20 SW_MUTE
ADIN_SRV_4 OPCTRL_3 B03
7 KEYBOARD AM35
ADIN_SRV_2 B06D USB
1 LIGHT-SENSOR AL36
ADIN_SRV_5 7D00
TPS2041BD
USB_PWR_EN
EN B04C
OUT USB_OCP
OC B04C
+3V3STBY
7701
BD45292G 1D01
5 1
VDD
1

4 ORESET AL22 AJ5 USB_DM0 2 USB 2.0

VOUT ORESET USB_DM0
3 2

AK5 USB_DP0 3 CONNECTOR

USB_DP0 SIDE
4
4

3
19130_059_110623.eps
110623

2012-Jul-20 back to
div. table
 Block Diagrams L11M1.1L LA 9. EN 57

9-13 Block Diagram I2C 3939 123 65231

I²C SSB 3139 123 6523.x
B04C CONTROLLER B05A HDMI & MUX B04D LVDS DISPLAY B06D VGA

7700 +3V3_SW
MT5363BIMG

3718

3719
B04C CONTROL
AP1 SDA-MAIN
OSDA_0
AP3 SCL-MAIN
OSCL_0

3946

3945
3717

3716
5 6 53 54 1E01
7703

10

15
VGA_SDA 12

5
AH1 SYS_EEPROM_WE 7 47
GPIO_44 7702 7910 TO
M24C64 SII9187BCNU 48 VGA_SCL 15 TCON
7708

6
11
H27U1G8F2BTR BIN-5V

4D18

4D17
EEPROM HDMI
MT5363 (NVM) MUX
2 1
VGA
CONNECTOR

3931

3930
FLASH 1903
ERR
PDD NAND 35 ERR 16
1Gb 33 BRX-DDC-SDA 7801

1
2
23
PCA9540BDP
BRX-DDC-SCL 15 1G51
MAIN NVM 34
4D16 SDA-VCOM 50

18
SW I2C 7

19
CIN-5V
SWITCH TO
HDMI 4D14 SCL-VCOM 49
8 TCON
+3V3STBY CONNECTOR 2

3933

3932
1902
39 CRX-DDC-SDA 16

1
2
3746

3747

1701
3727 3749 40 CRX-DDC-SCL 15
AT21 3

18
19
U0_RX UART DIN-5V
3728 3748 SERVICE HDMI
AP21 2
U0_TX CONNECTOR CONNECTOR 1
1

3935

3934
1901
43 DRX-DDC-SDA 16

1
2
44 DRX-DDC-SCL 15

18
19
HDMI
CONNECTOR SIDE

B2B DIGITAL DEMOD B02A TUNER

+3V3STBY
3746

3747

N34 TUNER_SDA
TUNER_DATA
N36 TUNER_SCL
TUNER_CLK
3352

3351

B04B DRAM B4B DDR 46 45

RDQ RDQ(0-31) 7302 14 FE_SDA

7600 7601 TC90517FG
H5PS5162FFR H5PS5162FFR 12 FE_SCL
DIGITAL
3228

3230

SDRAM SDRAM DEMODULATOR

512Mb 512Mb 7 6

1201
VA1E1BF2403

MAIN SW Programmable via USB

RA RA(0-13)
TUNER SW Programmable via ComPair

ERR
34

19130_057_110620.eps
110620

2012-Jul-20 back to
div. table
 Block Diagrams L11M1.1L LA 9. EN 58

9-14 Supply Lines Overview 3939 123 65231

SUPPLY LINES OVERVIEW SSB 3139 123 6523.x
B01 DC - DC B05A HDMI & MUX

1M99
B02B DIGITAL Demod
B01
+3V3STBY +3V3STBY
1M95
+3V3STBY +2V5_SW +2V5_SW
1 1 B03,B04a,c,d, +5V_SW +5V_SW
B01 B01
2 2 STANDBY B05a 6900
B04A +1V25_SW +1V25_SW HDMI_PLUGPWR1
3 3 CONTROL B01 6901
+3V3_SW +3V3_SW HDMI_PLUGPWR2
4 4 B01
1902
5 5 +12VS PWR5V_2
HDMI 2 18
B03,B04c,B06b
CONNECTOR
6 6 +12VDISP
B04d
1901
7122 PWR5V_1
RT8283AHGSP B03 CLASS-D & MUTING HDMI 1 SIDE
CONNECTOR
18
5117 2 5121 +3V3_SW
Synchronous 3 B02b,B04a,c,d, +3V3STBY +3V3STBY
Step-down 7119 B06a,b B01
Converter +1V25_SW +5V_SW +5V_SW
IN OUT
COM B02b,B04a B01
7123
B01
+12VS +12VS B05B USB
MAIN RT8283AHGSP
5120 2 Synchronous 3 5104 +5V5_TUN
B01
+24VAUDIO +24VAUDIO
B01
+5V_SW +5V_SW
B02a
POWER Step-down
Converter 6122 +5V_SW
B02a,B03.B04c,
SUPPLY B05a,b,B06d
B06A ANOLOG I/O - HEADPHONE
7120 B04A MTK POWER
+2V5_SW
IN OUT +1V25_SW +1V25_SW +3V3_SW +3V3_SW
COM B02b B01
7124 B01
RT8283AHGSP +1V1_SW +1V1_SW
5115 2 5123 +1V8_SW B01
Synchronous 3 SENCE+1V1_MT5363
B04a,b B01
Step-down
Converter +3V3STBY +3V3STBY B06B ANALOG I/O - AUDIO
7125 B01
RT8283AHGSP B01 +3V3_SW +3V3_SW
5105 2 5106 +1V1_SW +1V8_SW +1V8_SW
Synchronous 3 B01 3B54
B04a +3V3-ARC
Step-down SENCE_1V8
Converter B01
6102 3130 +12VS +12VS
EN_1 +3V3_SW +3V3_SW B01
B01

7 7 +24VAUDIO
B03
8 8
B06D VGA
B04B DDR
B01 +5V_SW +5V_SW
GND-AUDIO
+1V8_SW +1V8_SW 1E01
9 9 LAMP-ON B01 VGA 9 3E13 6E05 5E03 DC_5V
B04C
CONNECTOR
CONTROL
10 10 BACKLIGHT-PWM
B04C B04C CONTROLLER
CONTROL
11 11 BACKLIGHT-BOOST +3V3_SW +3V3_SW
B01
12 12 POWER-OK
B06D
CONTROL +3V3STBY +3V3STBY
13 13 B01
N.C.
14 14 +5V_SW +5V_SW
B01 1M20
5
TO
5706 8 IR/LED
SENSE+1V1_MT5363 SENSE+1V1_MT5363 PANEL
B04a +12VS +12VS
SENSE_1V8 SENSE_1V8 B01
B04a

B04D LVDS DISPLAY

B02A TUNER +12VDISP +12VDISP

1G51
B01
+5V5_TUN +5V5_TUN 7800 5800 +VDISP-INT 1
B01
7216 2 TO 1N01
5801
IN OUT 5225 +5VTUN_DIGITAL 3 T01A
COM 7802 5802 4 TCON
+5V_SW +5V_SW LCD-PWR-ONn
B01
+3V3STBY +3V3STBY
5222 +5VS B01
+3V3_SW +3V3_SW
19130_058_110620.eps
B01
110620

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 59

10. Circuit Diagrams and PWB Layouts

10.1 A 272217190323 - 272217190353 PSL
10-1-1 Power Supply Unit with Integrated LED Driver

Power Supply Unit with Integrated Led Driver

A01 1
JW24
2
TP238
5 8
TP237

D402
SB3200
LED_CN3_A A01

2
! TP436 R454
• •• • • 51K
LED_CN2_A

1
• • •• D401 TP33

33uF/200V
• • •• ! SB3200 R424

1
R450 TP236 CN2-1316
• •• • • 51k

C414
VLED 5 8 TP32 51K LED_CN3_A
1
LED1A
R414

2
R421

TP235
TP219 TP218 TP207 TP193
R412 R451 VREF R473 TP181
R475 2
NC

TP229
51K ISEN1
TP441

1
1K R448 3

R413
8.2K

10K
100K 100K C416 UVLS 1.8K LED2A

C413

33uF
TP226
47K TP234

D
100nF 4

2
POK R423 NC
47K LED_CN2_K TP224 G Q407 C470 5
LED1K

TP222

TP230
R449 C433 10nF
GND1 Q401 2N7002
R441 D R415 3K 47n 6
NC
TP206 TP192
R422 C422

S
47K G
+12V 7002 2K 3K
JW74 JW4
LED_CN3_K 7
LED2K
47n 1 2 1 2

2
GND1
R411 R461 TP225 D

JW10
C409 VREF S G Q404 8
10 GND1 C410 GND1
MDHT3N40 TP439
R474 TP180
R476

1
R416 R470 TP239 D
TP212 TP205 1uF G GND1 1.5K ISEN2 LED_CN2_A 9
BL-ON-OFF 47n

R462 10k
56K Q403 S 1.8K 8.2K
LED3A
47

D
GND1 AOD450 C432 10
R410 Q402 TP240
S TP438
R477
TP194 NC

R463
1nF TP195

10k
10K
VREF
D
C419 G Q408 C472 11
C407 R409 R417 AOD450 LED4A

2.7 R467
TP228
C408 G 1n 10nF
10K 2N7002

R468G R468H
100nF 100K • • •• 12
NC
2.2u C471

R466
47

S
R408

R442

R464

R465
••
R445 R472

2.7

2.7

2.7
•
• • •• •• • ••
1n S 13

10k
TP191
LED3K

TP227
47K TP204 2.7

300 TP437
TP196
• ••• ••••
•• R471 100k 14
NC

R468C

R468D
R468A

R468B

R468E

R468F

OPEN
R468I
R468
TP190 GND1
R443 R444

100
• ••
1k

18

18

18

18

18
••• ••••
R446 LED_CN2_K 15
LED4K

18
VREF
VREF

2
JW63 TP20
R419

JW29
1 2 • •• 2.7 2.7 53426-1510
R438 TP203
•••• •••
1k 2.7 GND1

1
100K GND1 R426 • ••
R407 •• •• • • GND1
CN4_1M95
R452 10K TP202 TP299
56K • ••
1
BL-DIM1(VSYNC)
TP201
•••• • •••
GND1 LED_CN3_K TP440
ST3V3 TP300 3V3stdby
10k • ••
R491 2
C423
•• • • • • • ••
R492 C216 STANDBY TP301
Standby
open •
•• • • •• • • •
••
ISEN1 R457 D
100nF 3
GND1 TP200
TP184 TP233
G 10K 120k GND1
GND1 GND1
Q405 4
ADIM •
• • •• •• • •
••
1.5K F GND1

R456 10k
TP199 TP183
MDHT3N40 GND1
S
••
• •• • • • •••
••
+12V 5
TP198 TP182
TP302 +12V
••
• • •• • • • • • • ••
•• C434 BL-I-CTRL 6
+12V

R455G R455H
TP197 TP185
1nF R496 R490 TP303 +12V
12K 18K R494 7

0
•• •• TP223
• • •• • • • •• • • •
TP21
R434B R434C
JW3
OPEN OPEN R493 75K
+24V5 TP304 +Vsnd
C402 R402 R403 • • •••• ISEN2 1 2
OPEN ADIM GND1 8
1uF 10K 10K C493 GND_SND

R455C

R455D
R455A

R455B

R455E

R455F
R455

OPEN
•• • • • • • • • • • • • • • •

R455I
10nF 9

18

300

100
R434 R434A

18

18

18

18
R497 R495 BL-ON-OFF
TP209

TP208

BL-ON-OFF

18
GND1
JW79
OPEN 220k 10
C403 12K 18K BL-DIM1(VSYNC) BL-DIM1(Vsync)
C401 1 2
C404 C405 C406 0.47u +12V 11
1n BL-I-CTRL BL-I-CTRL
470nF 1n 470nF 12
GND1 POK POK

VCC
TP309
GND1 JW57
TP178
R432B TP22
R432C R630A GND1
1
JW17
2 13
TP210 1 2 +24V5 +24(AL2_DVBS)

R482 47K
1K TP213 100nF JW54
TP310
12K 18K !
UVLS 14

R630
1 2
C474 GND1 GND1

1K
R432 R432A PC601
R481 1-1735446-4
EL817MC

C
C473

TP418
12K 18K 10K
TP216
B Q406 GND1
R631
KST2222A 100nF
2.7k GND1

E
TP217
C440

TP417
TP416 R480
10n
100K F

HOT C622
100n
R632 TP419
4.7K
GND1

U602
COLD Q222

TP420
AS431AN / SMD AOD407
TP340 L501 TP390
C292 22nF
TP429 S D
+24V5

D
S
BFS3550A Q221 R228
D601 D601A

R221
TP401
SDURF1040CT

10K
JW46 JW41
!

G
• • ••• VLED KST2907

R223
56K
1 2 1 2 R229

G
EY38 TP241

E
3
4A 600V R511 TP393 R518 47 470K 16K
S3V60 S3V60

33uF/200V

C
TP430 TP341
D602 B

68K, 2W
D

12K R220
4 1 BQ220

C411

R431

2200pF
G
4.3KF 1uF D211 R240

R512

R222
C223
KST2222A

C
2.2K

15K
TP339

! C601 EY26 BYV29X-600 C506 U501 MMSD4148 10 Q501 2K C233 C233A

E
! T501

330k
BFS3550A

D220

R622
S EY40
2
1uF L6599 D503 R519 KF5N50 TP242
ZS 50V 47UF ZS 50V 47UF
L603

14
• • ••• 1 16
1

CSS VBOOT
! • ••• GND1 MMSD4148 R243
R510 2 15
13

ZD220
R233
27K
C504 C505 DELAY HVG 1

6.8V
• • • • • • • •• • • • • VCC

R520
10K
330k
R624 R623
750K C508 12 MBRF10100CT 7.5K
• • • • •• • • 0.22uF 3 CF OUT 14 EY43
EY17
100nF 2
11
TP263

4 13
! CY106 330pF TP262
RFMIN NC
470k
R615

330k
C644 68uF/450V

VCC
C645 68uF/450V

! CY105 220pF MVCC 5 12

3 10 GND1
10

STBY VCC R521 EY18

C610A 47p/1kV

C610B 47p/1kV

D210
C610 47p/1kV

EY30
220pF Q602

OPEN

OPEN
2
9

220uF

220uF
6 11

R211

R212
EY23
ISEN LVG D 4

C207A
C207

R284
R50712K

82K
MDF11N60D R628 47 10 G
470k

GND1
D

R617 R616

100
8
R609 100 7 10 Q510

330k
D504 R522

R625

1
LINE GND

R508
R501

3.3K
5

C602 100nF • • •IC-SOP-8

•
GG
0.1u 100K 8 9 S KF5N50 7

! • • ••• C510 C509 DIS PFC_STOP R523 EY31 TP278

470k

4 3
1 8
OPEN IC-SOP-16-L6599 MMSD4148W 6
D603 R608
S

S
10K
TSA601MA1

2
R610

TP330
EFD4549
10k

2 7
! ! Q604

JW78
L201

TP383
GND1
G R509

C5110.1uF
R604 C604 C608
SA101

MMSD4148 10 STK0160 R531

1N4148 C526 C208 C209 C215

R502
36K

1
2 1 3 6
SDB1060PI C222 C206 1.6uH
68K 100nF
s

R507A
10nF 100
470k

D512 100pF 12nF/1kV

R618

S OPEN 1000uF 1000uF 47u 47u 2.2uF

R513
0
4 5

56
• • •••••••
R605
120K

R629 C611 C501 C513 +12V

FA5591 C502
R602

R603

100K 1nF
TP432

22K

TP331
CY103 C603 C605 C699 10nF 2.2nF D212
43

TP414
! 470pF VCC D

! CY104 10nF 2.2nF R612

5.6K
! CY202

R251
120 1W

470nF G
MMSD4148W
R101

R527 220pF
R627 R626
10K

470pF 100 R621 Q603 D506

S
STK0160 GND1
1nF 100k

ZD503
GND1 33

5.6V
C607
4.3K

R256

R252
C507

10K
CX102 C626 ! PC501
2W 0.12

R6332W 0.12

TP407
! EL817MC TP251
R614

330nF 10nF 1nF/50V 1.5K

R255
R620 R619

1.5K
12k

TP408

1nF TP434 C210 R254

C606
120

1K GND1
!EY47 • • • • • EY48 JW36
1uF
EY12 EY11 TP244
4 3
1 2
! PC502 U203
EL817MC

R253
2.7K
EY15 EY46 EY49TP443EY16 AS431AZ
2 1
JW6 D101 TP431 JW5
JW30 1 2 1 2
1 2 ! T101 GND1
• • ••• •••• IN4007 C119 EFD2020 L301 GND1
D102 D103 TP24 ••• • TP352 EY41 EY42 TP281
D301 TP296 TP297
ST3V3
! 2
JW73
1
1nF 5 10
TP423
COLD
P6KE180A
TP363

! CY102 IN4007 IN4007 • • ••• 3 9 SB140

ZD101

TP355 4.7uH C306

OPEN 4 C301
GND1
8 47u/50V
R111
OPEN

R113 IN4007
STVCC1 JW7 2 D107 R105 TP282
1000uF
! CX101 EY8 EY7 1 7
200 D106A

2.7K
TP353
0

R305
0.68uF 1000V R302 GND1
TP362

2 6
EY24 EY25
+24V5
4 3 R122 ZD110 100F +12V
C121

0.1uF
C304
1.5K
C102

R303
! TP247
2
1

STVCC OPEN
JW42

JW35

Q112 450V 10uF ZS47uF/50V R304

S

NC

• • • •••

EY45 EY44
• • •••
TP356

D114
1
2

Q110 OPEN 750

• •••

2 1
VCC OPEN ! PC101

R235
OPEN

OPEN STVCC TP349 TP293

C303

1k
•• • • • • MMSD4148
R112

EL817MC
BP

FB
TP368

CAP002DG C E E C 2.2u TP288

Q110A OPEN

1.5K
ZD110A
1

R307 R306
TP26 TP27 TP350 TP294
JW18
OPEN

5 4 R101C Q111 MVCC OPEN TP365

R118

R120
10K

OPEN
R123

1 2
56K
B

9.1K
R122A Q112A

R231
TP30
B
2

510k 6 3 ! 510K BASE KST2907A U301

JW37

TP369

R227
18K
OPEN AZ431L

120
2

TP31 TP292
R308 TP295
1

JW77

7 2 R117 R119

R234
R101B

1k
TP364
R121

!
43K

R118A
OPEN

47F
R112A

8 1 ! PC102
OPEN OPEN D110
0.1uF
C107
ZD104

U110
TP351
R109 TP348
EL817MC GND1
OPEN R309
ZD103

TP290
5.6V

COLD
7.5V

D115
2

C115 OPEN R117A BASE

JW55

MMSD4148 1K TP347
TP370 4.7K
CY101
E
1

C101 ! 2200pF/ 630V OPEN R310 TP283

47pF C118 B AS431AZ
STANDBY K
1nF VCC Q301 1K U206 U207
GND1
OPEN TP384 D116 R126 R125 R124
C

U102 Q101 KST2907A AS431AZ R

0.1uF
AS431A R110 A

1.8K

1.8K
KST2222A

R230

R224
! VA101 51K 51K 220K C305 C220 C221
510K

C109
R128

RF101L4S
EY6 EY5
10K GND1 1nF 1nF
ZD102

ZS 22uF/50V
15V

EY1

! F101 750V 14A R127 C116 C117 GND1 GND1

47n 47n
510K 1W
T5AH 250V

TP428 TP422 EY3 EY4 TP421

TP427

Live 2722 171 90323 3 2011-05-02

1

Neutral
2

Power Supply Unit with 2722 171 90353

! CN1(1308)
Integrated Led Driver PLDE-P008A
PLDE-P008A_CKD
19132_006_111219.eps
111219

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 60

10-1-2 Layout top

2722 171 90323 3 2011-05-02

Layout top 2722 171 90353

PLDE-P008A
PLDE-P008A_CKD
19132_007_111219.eps
111219

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 61

10-1-3 Layout bottom

2722 171 90323 3 2011-05-02

Layout bottom 2722 171 90353

PLDE-P008A
PLDE-P008A_CKD
19132_008_111219.eps
111219

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 62

10.2 A 272217190354 PSL

10-2-1 Power Supply Unit with Integrated LED Driver

200UH
Power Supply Unit with !
TP138

A01 A01
TP228
D401
VLED 5 8 LED_CN1_A
L401 RF101L4S
Integrated Led Driver TP222
R416
100
1 2 R430
GATE TP233 TP234 D 82k

TP230
JW26 G

33uF/300V
Q401
R409 D402

C404
S KF5N50DS R432
10 MMSD4148 75k

TP221

TP231
CN2-1316
CS LED_CN1_A 1
R434 VREF Anode 1+
C405 75k

TP237
R414 OVP
2
NC
OPEN
10k

TP134
TP198 3
TP217 Cathode 1-

2
BL-ON-OFF R433

TP227
JW2
2 1 EN 4
C401JW34 TP212
C407
3k R494 NC

1
R401 1N

TP127
R402 1K
5 Anode 2+

2.2 R410C
2.2 R410D
2.2 R410A
2.2 R410B

2.2 R410E
2.2 R410F
10K 100nF R493

R410

2
TP238
100K

JW65

JW11
TP215
U401 100K TP229
6 NC
POK

1
1 EN FBN 14 FBN
TP235 GND1 R417 C410 GND1 LED_CN1_K 7 Cathode 2-

D
GND1

JW31

2.2
+12V 2 1 2 VCC FBP 13 FBP 33k 10N
TP44
R491 SD-53427-07

2
C402 GATE G Q492

1
R403

JW1
JW28 TP213
3 GATE COMP 12 GND1
10 R419 BL-DIM1(VSYNC)
TP131 1.5K 2N7002

TP63
1uF

1
TP59
GND1 4 GND PWMI 11 R442 LED_CN1_K C494

TP130

S
TP218 R488 R489

TP200
TP223
10k TP232 R492 C491 C492 R495 1uF
CS 2 1 5 CS OVP 10 820 Q491

TP128
PWMO R420 0 100K 100K 2.2uF 2.2uF 2K
R415 OVP PWMO D KST2222A

1
JW27 6 RT PWMO 9 C490

TP129
1 2

JW22

JW59
10K G R490
10 JW24
JW32 TP226 Q402 100PF
7 SYNC REF 8

2
2 1
C406 R423 D403 S
KF3N40W 680K
330p MAP3202 VREF open MMSD4148 GND1 CN4_1M95

TP211
TP220

TP124

TP214
1
R444 TP126 R443 TP210 TP135
ST3V3 3V3stdby
R405 R404 TP219 GND1 C408 C413 FBN 820 820 2
110K 270K 2.2u 1uF C409 C403 1 2
STANDBY Standby

R455G R455H
3
1nF 6.8n R446 R445 GND1 GND1

TP225
GND1 JW23

39
TP209
820 820 4

OPEN TP236
GND1 C420 R424 C419 GND1 GND1
1N 10k NC +12V 5
+12V

R455C

R455D
R455A

R455B

R455E

R455F
R455

R455I
150
56

56

56

56

56

56

5.1
TP125 6
+12V +12V
GND1 100KF 7
VREF +24V5 +Vsnd

TP122
GND1 8
R470A GND1 GND_SND

R468

R470
130KF
5.1KF
9
TP123
BL-ON-OFF TP116
BL-ON-OFF
R469 R472 10
EN FBP BL-DIM1(VSYNC) BL-DIM1(Vsync)

R460
10KF
11
+12V 150K 10k BL-I-CTRL BL-I-CTRL

D
VCC TP114

TP121

TP111
12
POK

R630A
R483 R464 POK

R458

R471
C416

10KF

39KF
2
G Q413

1k

JW35
10k NC +24V5 13
+24(AL2_DVBS)
C474 C473

TP119
R630 0 2N7002

TP136

D
! PC601 TP120

1
TP202
R482 100nF 14

TP115
GND1

100KF
1k R456 100nF GND1

AC
S
TP168

R465

1
47K R481

JW33
EL817MC G Q412
HOT BL-I-CTRL 1-1735446-4

D416
10K Q406
COLD C415 GND1GND1

NC
TP35

R459
100KF
1K 2N7002

2
R631 KST2222A OPEN

S
2.7k C414

C
A
TP36
TP167
TP37 C440 R480 OPEN
10n 100K GND1 GND1 GND1 GND1 GND1
GND1 GND1 GND1
C622 R632 GND1
100n 4.7K
U602 Q222
AS431AN / SMD C292
AOD407
L501 TP251 22nF K 50V
S D TP113 +24V5

D
S
EY21 TP41 jumper TP91 Q221 TP110
D601 D601A R228

R221
10K
! SDURF1040CT

R223

R229
G
BD601 VLED KST2907

2
2 1

G
56K

16K
TP109
EY36

100p/1kV
3

JW5
C514
RS405M JW3 R511
TP48 1 2 470K
TP9 S3V60 TP10 S3V60 TP27

TP172
D602 TP33

1
EY19 EY22

33uF/200V

2200pF K 50V
47K, 2W
R518 D Q220

R220
TP112

TP107
C411JW9
JW8

12K
4 1 1 2 G

R426
4.3K 1uF D211TP92

R512

R222
15K
KST2222A TP117

C323
TP8

2.2K

R240
1
EY24
! JW38
BYV29X-600 C506 U501 47TP177 TP28
TP93

2K
C601 Q501 ! C233 C233A

TP118
EY26 EY44 TP207 T501

330pF TP208
330k
D220

R622

1
EY20 S EY39
820n R510 L6599 KF5N50 ZS 50V 47UF OPEN

JW13
TH601 2 D503 R519

TP26
TP49
jumper

14
L603
5

750K 1 CSS VBOOT 16

3ohm 15D TP18
!

2
C505
EY25

TP187
10 13 MMSD4148

7.5K
EY35

R243
ZD220
R233
HVG 15 1

27K
2 1 2 DELAY EY41 GND1
C504

6.8V
L601 VCC TP47 MMSD4148W

R520
10K
330k
EY34

R624 R623
TP34
! CY106 12
2

! CY105 JW50 220nF EY45

JW40

TP94
3 CF OUT 14

1
EER3611 400uH C508 2

JW36

2
TP186
100pF COLD 100pF 11 MBRF10100CT

JW19
104
1

4 RFMIN NC 13 EY40 2 11 2
470k

TP19
R615

1 2
2 1

330k
C64568uF/450V

VCC
C64468uF/450V

MVCC 3 10

1
MK 220uF/35V

MK 220uF/35V
TP16

EY37 JW4 JW20

TP65 6

10

5 STBY VCC 12
JW46
R521 JW42
GND1
C610A 47p/1kV

C610B 47p/1kV
TP241

EY29 EY38
C610 47p/1kV

EY23 EY43 Q602 9

R211
2.2k

R212
2.2k
GND1 2 6 ISEN LVG 11 D 4 D210TP95

TP50
EY27

C207A
C207

R284
R507 12K
47

100p/1kV

NC
TP32
R628
D

TP66 TP206 MDF11N60 TP46 G TP96

470k

TP42
R617 R616

C515
8

100
D TP178
7 LINE GND 10

330k
R609 D504 R522

R625

R508
R501 5

3.3K
TP11

100nF GG 0.1u 7
TP242

! U601 EY30 EY32 C509 100K 8 DIS PFC_STOP 9 R523

S
EY46
TP25 LF103EY15 C510 Q510
1

EY16 C602 IC-SOP-8 100 MMSD4148W10

470k
JW57

TP30
1 8 TP21 6
! ! 1 2
TP17

TP179
4 3 IC-SOP-16-L6599 TP39 TP38
TP7

D603 R608 S 22uF 50V KF5N50

S

TP29 10K
TSA601MA1

EY31 EY33 D JW62

R610

2 7 EFD4549
10k

TP4 TP5 TP24 Q604 GND1 C208

TP243

EY17 EY18 G R509 L201 C209 C215

C608

TP43
SA101

R507ATP248
C604 MMSD4148 10 STK0160 D512 C526 R531

R502
36K
2 1 3 6 EY47 TP97 1.6uH 47u/50V 47u/50V 225J
TP40 SDB1060PI
s

1N4148
1

100nF 103 100pF/1kV 100/1W

470k

JW44
TP20

R605

R618

S 47
120K

TC930080S
TP31
R604 10nF

R513
4 5 EY48

120

C511
0.1uF
! ! CY103 1 2 103 C513 1 2 1 2
+12V
TP180

1 2
TP22

R629 C611 C501

TP100
CY104 6.8K FA5591 C502
COLD
TP12

470pF JW56 JW60 JW25

JW55
TP23
R602

R603

471 100K 102

R251
560
43K

C699 2.2nF C222 C206

TP15 43

TP99 D212
TP6

C603 C605
TP13 D
! CY202
2

2.2nF 1000uF 1000uF

120 1W

1
470nF R612 G

JW54
VCC

2
10nF 1 2 MMSD4148W
R101

470pF

TP175
JW6

JW7
R627 R626
1

10K

GND1 100 Q603 R527 1 2

R621
JW47

D506

2
JW58

TP45
GND1

1
EY14 EY13 S
1nF STK0160 JW45

1
ZD503
TP14

R252
2

TP216

33

10K
JW61
100k

5.6V
C607 1nF/50V
4.3K

TP102
C507 ! PC501

2
! CX102 C626 R256 GND1
2W 0.12

2W 0.12

1
TP98
1 2

JW14
330nF EL817MC
R614

R633

10nF
3.6K JW29

2 2
2
R620 R619

R255
1.5K
12k

JW48

JW15
TP104
C210TP176
TP181

2 1
1nF 1uF R254

1
1 2
! LF102EY11

JW51
EY12 C606
1K
0

TP103
4 3 JW21

1
TP77
TP2 TP3 U203
EY9
2
EY10
1 ! PC502 AS431AZ

R253
2.7K
EL817MC
CS2540110ME02C
TP51
D101 GND1
! GND1
! CY101 COLD ! CY102 T101
L301
IN4007 C119 EFD2020 TP82
NC D102 D103
TP247 10D9 TP57
EY53 EY28 D301 ST3V3
NC 1 2
1uF 5 10
P6KE180A

GND1
IN4007 IN4007 TH101 JW52 3 9 SB140
ZD101

TP60
R111
OPEN

EY8 0.68uFEY7 4.7uH C306

C301

TP90
4 47u/50V

2
R113 IN4007 8

JW16
TP53

TP62 TP64
D107 R105 1000uF
! STVCC
2

CX101
JW39

1 7

1
200 D106A GND1
!EY52LF101EY49

2.7K
1000V 1A 0

R305
1

TP58
R302
1

4 2 6
JW49

3 TP80
+24V5 2011-03-08
R122

TP81
TP72 +12V
2

EY51 EY50
TP244 TP55 ZD110TP54 100F

0.1uF
OPEN

C304
1.5K
C102

R303
S 8

S 7

NC 6

D 5

2 1 STVCC Q112 R304TP174

LT 450V 10uF
LNK362

C121 TP89
JW63 D114
U101

Q110 OPEN 750

2

CH040031 VCC 2 1 ZS47uF/50V !

JW41

OPEN
MMSD4148 PC101
OPEN

CAP002DG OPEN

1
STVCC R235
R112

3 BP

EL817MC
4 FB

JW18
TP246
1 S

2 S

5 4
1 2 TP203 2.2u 1K

1.5K
R307 R306
2

TP105
510k Q110A

TP83
TP250
jumper R122A ZD110A
TP61

6 3
OPEN

JW64 MVCC
R118

R120
10K

TP84
OPEN TP245 OPEN OPEN C303
R123

TP173
Q111
56K

7 2 Q112A U301 R231

! R101B ! R101C KST2907A
OPEN AZ431L 9.1K R227

120
TP71 R308
TP249

TP76

8 1

TP106
R117 R119 18K

TP108
R234
R121
43K

U110 R118A TP68 47F

!
TP67

OPEN

R117A PC102 1k
R112A

OPEN OPEN
1

D110
0.1uF
C107

OPEN
ZD104
JW37

R109
TP56
5.6V

OPEN EL817MC TP85

R309 GND1
TP75

ZD103

C101 47pF/1kV
7.5V

BASE D115
2

C115 OPEN BASE 1K

!EY5VA101EY6 MMSD4148 4.7K SMD

2
TP79 TP86 TP87

JW12

JW10
2200pF/ 630V 1 2JW53 R310 SMD

TP101

1
STANDBY
TP69

TP74 TP224 TP73 C118 VCC Q301

EY4 1nF 1K U206 U207
D116 R126 R125 R124
750V 14A ! 1 2 U102 Q101 KST2907A AS431AZ AS431AZ
F101
TP52

R110
TP88

T3.15AH 250V RF101L4S 51K 51K AS431A KST2222A R230 C220 C221
220K
510K

JW43
C109
R128

R224
JW17

EY1
0.1uF 1nF 1nF
TP78

TP70
10K 1.8K 1.8K
C305
ZD102

ZS 22uF/50V
15V

EY2 EY3 GND1 GND1 GND1

R127 C116 C117
47n 47n
510K 1W
Neutral Live
TP1
1

4 2011-03-08

CN1(1308)
Power Supply Unit with 2722 171 90354
! AC-inlet Integrated Led Driver PLDC-P015A

19132_003_111219.eps
111219

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 63

10-2-2 Layout top

4 2011-03-08

Layout top 2722 171 90354

PLDC-P015A

19132_004_111219.eps
111219

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 64

10-2-3 Layout bottom

4 2011-03-08

Layout bottom 2722 171 90354

PLDC-P015A

19132_005_111219.eps
111219

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 65

10.3 A 272217190355 - 272217190359 PSL

10-3-1 Power Supply Unit with Integrated LED Driver

Power Supply Unit with 200UH

A01 Integrated Led Driver

VLED
!
TP55
TP57

L401
8

R416
5

TP54
TP58

D401
RF101L4S
TP51
LED_CN1_A
A01
100 R430
GATE JW4 TP56 D 82k

TP50
1 2 G
Q401

33uF/300V
R409 D402

C404
S KF5N50DS
R432 CN2-1316
10 MMSD4148 82k LED_CN1_A 1
Anode 1+

TP53

TP49
2
1
JW8
2
R434 VREF TP60 NC
C405 CS 82k 3
R414 JW3
TP62
Cathode 1-

TP48
OPEN 1 2
OVP
10k 4
NC
BL-ON-OFF EN C407 TP8
R433
R494
5 Anode 2+
2.7k
R401 TP46
1N 6 NC

100nF
R402

C401
1K

2.2 R410C
2.2 R410D
R493

2.2 R410A
2.2 R410B

2.2 R410E
2.2 R410F
10K

R410
100K U401 TP52 100K JW59 LED_CN1_K 7 Cathode 2-
GND1

TP14
1 2
FBN POK
GND1 1 EN FBN 14 GND1 SD-53427-07

D
TP34 JW38 R417 C410

2.2
+12V 2 VCC FBP 13 1 2 FBP 33k 10N
TP64 R491 TP12

C402 GATE G Q492

R403 3 GATE COMP 12 GND1
10 R419 1.5K 2N7002
1uF TP47 JW29 TP19 BL-DIM1(VSYNC) TP42
TP33 TP11
GND1 4 GND PWMI 11 1 2 LED_CN1_K

S
R442 R488 R489 C494
TP35
10k JW10 R492 C491 C492 R495
CS TP44
820
TP43 Q491
5 CS OVP 10 1 2
0 1K 2K 1uF
TP36 PWMO R420 KST2222A 100K 2.2uF 2.2uF
R415 OVP PWMO JW9 TP45 D C490 CN4_1M95
6 RT PWMO 9 10K 1 2 G R490
10 Q402 100PF TP299 1
C406 7 SYNC REF 8 1
JW35
2 1
JW42
2
R423 D403 KF3N40W 680K TP69
ST3V3 3V3stdby
S TP300 2
330p MAP3202 VREF open MMSD4148 GND1 STANDBY Standby

TP41
TP37
C408A C408 C413 C403 GND1
TP301 3
GND1
C409
2

NC 2.2u OPEN R444 R443

JW11

1nF 6.8nF FBN GND1 4

GND1
R405 R404 GND1 TP38 820 F TP40 820 F
1

TP22 TP302
110K 270K +12V 5
+12V

R455C

R455E
GND1 R446 R445

R455G R455H
R455A
GND1 6

56

56
+12V +12V

0
820 F 820 F

56
TP39
C420 R424 C419 TP303 7
+Vsnd

43 TP61
10k NC +24V5
820p

OPEN
R455I
R455B

R455F
R455D
R455
TP304 8
GND1 GND_SND

100
56

56

56
TP15 9
GND1 100K BL-ON-OFF BL-ON-OFF
VREF
10
GND1 R470A C474 BL-DIM1(VSYNC) BL-DIM1(Vsync)

R468

R470
130K
5.1K
11
R472 100nF BL-I-CTRL BL-I-CTRL
TP23 R469 10K
TP67 12
POK POK

TP25
+12V EN JW17 TP309

R460
FBP 13

10K
1 2
R630A 150K +24V5 +24(AL2_DVBS)

VCC
JW26 TP415 1k R483 JW54 TP310

D
2
1 2 14

JW19
1 2
10k R464 TP63 GND1 GND1

R458

R471
COLD C416

10K

39K
Q413

TP32
G

1
C473 1-1735446-4

TP6
0 2N7002 1uF

TP5

TP9
R630 100nF

TP21
! PC601 R482 JW32 TP20 R456

100K

S
R465
1k G Q412

TP418
1 2
EL817MC 47K R481TP4

C
BL-I-CTRL C415
10K Q406

R459
1K 2N7002

100K
TP3 B OPEN
R631 KST2222A

S
R480 C414
2.7k C440

E
OPEN

TP7
TP417
TP416 10n GND1 GND1 GND1 GND1 GND1
100K GND1 GND1 GND1

2
JW63

HOT C622 R632 TP419 GND1

1
100n 4.7K
U602 Q222

TP420
AS431AN / SMD AOD407
TP340 22nF K 50V
TP390 L501 TP65 TP272 TP277
C292
TP279
+24V5
TP429 S D

D
S
BFS3550A Q221
D601 TP401 D601A

R221
10K
EY21 TP266 SDURF1040CT TP268 TP273
R228

R223

R229
!3

G
BD601 EY38 VLED KST2907

100p/1kV

G
TP267

2
56K

16K
TP271
E

JW25
RS405

C514
S3V60 S3V60 R511 TP393
B 470K

33uF/200V
EY19 EY22 JW43 JW50 JW65 JW64 TP341 D602

1
2200pF
47K, 2W
R518 TP403 D Q220

R220
12K
4 1

TP276
1 2 1 2 1 2 1 2 G

C411

R431
4.3KF 1uF TP265
D211

R512

R222
15K
KST2222A

C323

C
2.2K
TP339

R240
EY9

TP270
! BYV29X-600 C506 U501

2K
EY26 47 ! T501 C233 C233A

330k
BFS3550A

TP411 TP274

R622
EY20 S EY40
2 C601 R510 L6599 TP402 TP400 D503TP399 R519
TP275D220
Q501 14 ZS 50V 47UF ZS 50V 47UF

TP404
L603

TP430 EY10
TH601
1

TP269
750K 1 CSS VBOOT 16
TP433 EY34 EY35 TP344 JW47 820n ! L601 TP326 TP395
10 KF5N50 13 MMSD4148

7.5K
MMSD4148W

R243
ZD220
R233
HVG 15 1

27K
1 2 TP334 2 DELAY GND1
EER3611 150uH C504

6.8V
VCC

R520
10K
C505

330k
R624 R623
TP396 12
224 EY43
MBRF10100CT
3ohm 15D TP394
3 CF OUT 14 C508 2 TP263 TP264 TP280
TP342 330pF 11 JW13 JW49 TP249 JW56 JW62 JW48
TP327 4 RFMIN NC 13 100nF TP262 1 2 1 2 1 2 1 2 1 2
470k

CY106
R615

330k
CY105 VCC TP391 GND1
68uF/450V

68uF/450V

MVCC 3 10

MK 220uF/35V

MK 220uF/35V
COLD 101 EY39
10

101 EY29
5 STBY VCC 12 TP387 R521
C610A 47p/1kV

C610B 47p/1kV

TP397 EY30 D210

C610 47p/1kV

Q602 9

2
TP388

R211
2.2k

R212
2.2k
6 ISEN LVG 11 4

100p/1kV
EY23 D
GND1

C207A
TP325 TP328

C207

R284
R507 12K
MDF11N60D 47

NC
TP316 TP386

R628

C515
D

G
470k

22uF 50V JW57

R617 R616

100
1 2 7 LINE GND 10

330k
R609 TP336 D504 R522

R625

1
3.3KF
R508
U601 R501 TP392 TP18 5
100nF GG 0.1u S Q510 7
! C604 IC-SOP-8 EY36 EY32 C509 100K 8 DIS PFC_STOP 9 R523 TP278

2
EY31
LF103EY50
C644

C510
TP335

100 MMSD4148W10

JW78
EY51 C602 TP324
KF5N50
470k

1 8 TP329 6
! !
C645

TP409
4 3 TP313 TP319 D603TP337R608 IC-SOP-16-L6599
D512TP398 TP412

TP385
100nF S
S

JW55

1
10K
TSA601MA1

TP413
TP330 D
R610

2 71 2 1 2 EFD4549
10k

Q604 GND1

TP383
EY52 EY53 TP314 G R509 L201 47u/50V
C608 3
SA101

JW40 MMSD4148 10 EY37

STK0160 1N4148 C526 R531

R502
36K
2 1 R604 6 TP323 EY33 EY54 1.6uH C208 C209 C215
TP343

SDB1060PI
s

R507A
TP261
10nF 100pF/1kV 100/1W
470k

TP317
R605

R618
120K

6.8K S 47 10nF/1kV
TP260 JW21 JW22 JW23 47u/50V 225J

R513
TC930080S 4 5

C511
0.1uF
TP311 TP259
TP338

56
103 C513 EY55
1 2 1 2 1 2
+12V
470pF FA5591 R629 C611 C502 C501
TP321

! CY103
2

TP312
R602

R603

100K 1nF
TP432

JW37

JW27 TP331
22K

C605 C699 JW33 JW80 JW81 2.2nF JW51

43

D212

TP414
C603 TP322 D 1 2 1 2 1 2 1 2 1 2 C206
103 222 ! CY202 C222

R251
120 1W

R612

560
! CY104
COLD 470nF VCC G
MMSD4148W
R101

R626

TP406 JW45 220pF 1000uF

10K

470pF 100 R621 Q603 R527 D506 1 2

2
TP426

2
S

TP252

JW2
GND1 STK0160

JW16
TP318 1nF
TP332

ZD503
JW76 JW75
100k 33 GND1 MK 1000uF/25V
TP320

5.6V
1 2 1 2 C607 1nF/50V

1
1
TP250
R627
4.3K

R252
C507 ! PC501

10K
C626 R256

2
2W 0.12

2W 0.12

JW15
1 2

JW1
! TP407
EL817MC TP251
R614

R633

CX102EY13TP424 10nF
3.6K F

1
TP425EY14 680nF
R619
12k

TP408

R255
1.5K
TP245
C210 TP243 R254
TP435

1nF TP434 1uF

C606
R620

1K GND1
120

!EY47LF102EY48 TP244
4 3 ! PC502 U203
AS431AZ
EL817MC

R253
2.7K
EY46 EY49
TP443
2 1 JW6 D101 JW5 TP431

TP246
JW30 1 2 1 2
1 2 TC930080S ! T101 GND1 GND1
IN4007 C119 EFD2020 L301
D102 D103 TP24 10D9 TP352 EY41 EY42 TP281 D301 TP296 TP297 ST3V3
102 1KV 1
JW73
2 5 10
!
P6KE180A

! TP423 COLD
TP363

CY102 IN4007 IN4007 TH101 3 9 SB140

ZD101

100pF TP355 4.7uH C306

GND1 4 C301
47u/50V

TP284
R111

8
OPEN

R113 TP354IN4007
! CX101 STVCC1 JW7 2 TP359 D107TP358 R105 TP357
1 7
TP282 1000uF JW12 JW20
EY8 EY7 1 2 1 2 TP298 COMPANY:
200 D106A LG Innotek

2.7K
TP353 1000V 1A 0

R305
JW41
LT 450V 10uF JW28
TP362

1 2 1 2 2 6 R302
0.68uF GND1 +24V5 TITLE:
R122 +12V
4 3 ZD110 C121 100 BL GL40S PLDE-P016A
! OPEN

1.5K
TP373 TP367 C102 TP247

R303
2
1

2
DRAWN: DATED:
S 8

S 7

NC 6

D 5

STVCC
JW36

JW44

JW14
LF101 Q112 ZS47uF/50V R304 MH KIM 2011-03-08
LNK362

TP31
TP356

TP380 TP382
D114 TP287
750 TP289 C304
U101
1
2

1
2 1 Q110 VCC OPEN CHECKED: DATED: CODE: SIZE: DRAWING NO: REV:
!

2
OPEN

JW34
MMSD4148 PC101 TP293 0.1uF
OPEN

JUMPER OPEN STVCC TP349 2.2u R235

R112

3 BP

EL817MC
4 FB

1
OPEN TP368

QUALITY CONTROL:DATED:
1 S

2 S

MPR1.0

R307TP285 R306
C303 <Code> A0

1.5K
C E E C
Q110A TP288 1k
CAP002DG R122A ZD110A TP350 TP294 JW18

TP257
TP26 TP27 TP365
5 4 Q111 MVCC OPEN RELEASED: DATED:
R118

R120
10K

TP30 OPEN TP29OPENTP28

1 2
56K F
B

R123

Q112A R231 SCALE: 1

SHEET: 1 OF
B

6 3 jumper KST2907A U301

510k
TP369

43K TP381

OPEN 9.1K R227

2

BASE TP292 R308 TP295 AZ431L

JW77

120
7 2 R117 R119 18K
! TP286
TP364

R101B R234
R121

R118A
1

TP253
OPEN

R117A ! PC102 47
R112A

8 1 1k
! R101C OPEN OPEN TP372D110 OPEN
0.1uF
C107
TP371

OPEN TP351 R109 TP348

ZD104

U110 EL817MC TP290 R309 GND1

ZD103
5.6V

7.5V

TP255
OPEN D115
C115 TP370 BASE 1K TP347 TP248
MMSD4148 4.7K
C101 47pF/1kV JW39 JW46 JW58 SMD
E

2200pF/ 1000V 1 2 1 2 1 2 R310 TP283 SMD

B
STANDBY K AS431AZ TP254
C118 1nF VCC Q301
TP291

1K U206 U207
TP384 D116 TP378 R126TP379R125 TP376 R124 TP375
C

! VA101 U102 TP345

Q101 KST2907A 0.1uF AS431AZ R
EY6 EY5
RF101L4S 51K 51K AS431A R110 KST2222A C305 R230
A
C220 C221
220K
510K

C109
R128

R224
10K GND1 1.8K 1nF 1nF
750V 14A 1.8K
ZD102

CY101 ZS 22uF/50V TP258

15V

TP256
EY1
COLD 101
R127 C116 C117 TP346 GND1 GND1
JW53 JW31
GND1 47n 47n 1 2 1 2
510K 1W
EY2 !
F101
T5AH 250V TP422 EY3 EY4 TP421
TP427
TP428

Live Neutral
2

2011-03-08
2722 171 90355
Power Supply Unit with 2722 171 90359
! CN1(1308)
Integrated Led Driver PLDE-P016A_CKD
PLDE-P016A_CBU
19132_009_111219.eps
111219

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 66

10-3-2 Layout top

2722 171 90355 3 2011-03-08

Layout top 2722 171 90359

PLDE-P016A_CKD
PLDE-P016A_CBU
19132_010_111219.eps
111219

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 67

10-3-3 Layout bottom

2722 171 90355 3 2011-03-08

Layout bottom 2722 171 90359

PLDE-P016A_CKD
PLDE-P016A_CBU
19132_011_111219.eps
111219

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 68

10.4 B01 313912365052

10-4-1 DC-DC

DC-DC
B01A 12V/3V3 CONVERSION
5117
7122
RT8283AHGSP
3149 2170
1M99
B01A
I105 2 1 1 F102
VIN BOOT +12VDISP
1M99 2 F103
33R 3100 1R0 100n 5121 F133
7 3 PIN ON STBY 3 F104

10u 16V
EN_1 EN SW +3V3_SW

2163

2100
RES
2154
1 12V 0V 4

10u

10u
2158 100K I137 I117 10u LAMP-ON

100u 6.3V
8 5 5 3V 0V

4K7 1%
5 F105 3126 68R
SS FB

3140

2101
6 >1.5V 0V BACKLIGHT-PWM

2152

RES
F106

2162
6

22u

22u
3127 68R
22n BACKLIGHT-BOOST
10
VIA COMP
6 7 1.5V 0V 7 F107 3128 68R

2179

100n
GND 9 3V 0V 8 F108 INV_STATUS
GND HS I136 9 F109 POWER-OK
SS1_GND

2160

3138
4

RES

10R
3n3

1K5 1%
100K 5%
2041145-9

3146

3107

2198

10n
SS1_GND

I106

I118

100p

100p

100p

100p

100p

100p

10n
3135

4100

2126

100n
2125

100n
2150

470p

RES
RES
12K
SS1_GND SS1_GND

2127

2128

2131

2132

2133

2134

2135
SS1_GND

12V/5V CONVERSION 7123

SS1_GND
F135
+5V5_TUN +3V3STBY
RT8283AHGSP

2136

1n0
+12VS 5120 I123 3150 2123
+12VS 2 1
VIN BOOT 3129 STANDBY
33R 3101 1R0 100n I138 5104 6122 F132
EN_1 7 3 1M95 1M95
10u 16V

EN SW +5V_SW 68R
2102

2171

2153
RES
2168

10u PIN ON STBY 1 F113

10u

10u

10u

100K I120 SS36

2169

2199

2180

2146
2137
RES
8 5 1 3V3 3V3

RES
2157 22n 2 F114

10u

10u

1n0

2u2
100u 6.3V

1n0
27K 1%
SS FB

470R

470R

470R
3115
2161

3153

3154

RES 3155
2164

2159
2155
2 0V 3V 3 F115

22u

22u

10u
I122
10 6 6 12V 0V 4 F116
VIA COMP

100n
GND 7 12V 0V 5 F117
GND HS 8 12V 0V 6 F118 +12VS

2185
SS2_GND

RES
3136
4

9
9 25V 0V F119

10R
7

3n3
2177
8 F120
9 F121 +24VAUDIO

I140
I107

I119
10 F122 GND-AUDIO
SS2_GND 11 F123

3122

2186

470p
RES
1-2041145-1

10K
SS2_GND

5K1 1%
100K 1%

3125

2149

100n

2148

100n
2147

100n
3105

2141

2142

100n

2143

100n
2144

2145
RES

1n0

1n0

1n0
SS2_GND
SS2_GND SS2_GND
GND-AUDIO GND-AUDIO

12V/1V8 CONVERSION GND-AUDIO

7124
RT8283AHGSP
5115 I104 3151 2187
2 1
VIN BOOT
33R 3102 1R0 100n I131 5123 F125
7 3
10u 16V

EN_1 EN SW +1V8_SW
2172

2189
2188

10u

10u

100K 3u6

100u 6.3V
8 5

15K 1%
2190 22n
BZX384-C6V8

SS FB
3V3/1V2 CONVERSION

3112

2191

2138

2183

RES 2104

RES 2105
22u

22u

22u

22u
I132 I127
100n
6102

10 6
VIA COMP
GND RES 7119
GND HS LD1117DT
2178

2112

SS3_GND

3108
4

RES

10R
4n7

5124 I144 I143 5125 F131

+3V3_SW 3 2
IN OUT +1V25_SW
3116 33R 33R
3130

I141

22u 6.3V
SS3_GND COM
I135

I134
1K0

SENSE_1V8

2139

100n

2140

2197

2166

2193

2122
2165

RES
10n

22u

22u

10n
22u
15K

68K 1%

12K 1%

1
3114

3113

3118
2192

470p
RES
I139

12K

EN_1 SS3_GND

RES
3131

4K7

SS3_GND SS3_GND
SS3_GND

5V/2V5 CONVERSION
7120
12V/1V0 CONVERSION 5127 I125
LD1117DT25
I126 5128 F136
7125 3 2
+5V_SW IN OUT +2V5_SW
RT8283AHGSP
33R 33R

22u 6.3V
COM

47u 16V
5105 I108 3152 2124

2108

100n

2109

2110

100n

2111

100n
2107
2 1
VIN BOOT

1
33R 3103 1R0 100n I110 5106 F101
7 3
10u 16V

EN SW +1V1_SW
2175

2181
2176

10u

10u

2195 100K I109 3u6

12K 1%

100u 6.3V
8 5
SS FB
3106

2151

2106
2129

2130
22u

22u

22u

22n I111 DGND DGND DGND DGND DGND DGND

10 6
VIA COMP
GND
GND HS
2167

SS4_GND
3111
4

RES

10R
4n7

I142 3117
I112

I113

SENSE+1V1_MT5363
47K
3145

2113

470p
RES
3K6

470K 5%
27K 1%

SS4_GND
3109

3148

ROUND 4.02mm SCREW HOLE ROUND 4.50mm SCREW HOLE SLOT SCREW HOLE
1X02 1X03 1X05 1X04 1X01
REF EMC HOLE REF EMC HOLE REF EMC HOLE EMC HOLE REF EMC HOLE
SS4_GND SS4_GND SS4_GND

2 2011-01-31

PCB SB SSB 1 2011-01-13

3139 123 6505

THRILLER BRZ DIG

19130_016_110426.eps
110426

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 69

10.5 B02 313912365052

10-5-1 Tuner

Tuner
B02A B02A

7216
LD29150DT50R

I255 5225 F236

+5V5_TUN 1 3 +5VTUN_DIGITAL
IN OUT
0R
COM

RES

RES
4209

4210

100n
2277

2278

2280

2279

2281

2282
RES

RES

RES
RES
22u

1u0

10n

10u

22u
2
F242 AGND AGND AGND AGND AGND
RF_AGC_SW

10R

10R

10R

10R

10R

10R

10R

10R
+5VS

5
8

8
RES

RES

RES

RES
3264

10K

3272-1

3272-2

3272-3

3272-4

3271-1

3271-2

3271-3

3271-4
I221

4
3269 I222

3265 I220 1K0

7217
BC847BW
1K0 AGND

I254 5222 F235

+5V_SW +5VS
10u
F213 AGND 3270 F247
RF_AGC_EX RF_AGC

2283

2284
22u

10n
1201 10K
VA1E1BF2403
AGND
15

16

2293

2213
RES
47n

22u
MT

2295
1 F201 AGND 7218
ANT_PWR
2 F202 KTK5132E
NC1 100p AGND AGND
3 F203
RF_AGC
4 F204
NC2 AGND AGND
TUNER

5 F205 AGND 3230

AS
6 F206 FE_SCL
SCL
7 F207
SDA 10R

2226
8 F208 RES 5207 30R

15p
+B +5VTUN_DIGITAL
9 F209 5208 4u7 +5VTUN_DIGITAL
IF_AGC
10 A212 2258 100n
IF_OUT+ 2285

2286

180p
11 A213
IF_OUT-
12 A214 3228
IF_OUT_ANALOG AGND AGND 27p
2296

2294
RES

FE_SDA
22u

47u
MT

DIF_N 3262 5226 5227 2287

14

13

VIP_ATV
10R
2225

15p
75R 220n 220n 10n
RES
2297

1n0

AGND

5228

330n

2288
A225

33p
AGND 3261 F246
IF_AGC
AGND
10K
2262

100p

2263
RES

47n

AGND DIF_P 3263 5229 5230 2289

VIN_ATV
75R 220n 220n 10n
2290

2291

180p
AGND AGND
DIF_N
27p
DIF_P
Near Tuner Near MTK5363

2 2011-01-31

PCB SB SSB 1 2011-01-13

3139 123 6505

THRILLER BRZ DIG

19130_017_110426.eps
110426

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 70

10-5-2 Digital demodulator

Digital demodulator
B02B B02B
+2V5_SW +1V25_SW

5307 I300 I301 5302

30R 30R

2320

2321

100n

2322

2306

100n
2307

100n
2308

100n
2309

100n

2310
1u0

10n

1u0
+3V3_SW

5306 AGND AGND AGND I302 I303 DGND DGND DGND DGND DGND 5301

30R 30R

2318

2323

100n

2301

100n
2302

100n
2303

100n
2304

100n

2305
1u0

1u0
+1V25_SW

5304 AGND AGND I304 I305 DGND DGND DGND DGND DGND 5303

30R 30R

2314

2324

100n

2311

100n
2312

100n

2313
1u0

1u0
+2V5_SW

DGND DGND I306 DGND DGND DGND 5305

30R
1301 FOR DEVELOPMENT USE

2317

100n

2316
1 3

1u0
DEB DEB DEB
7301 6301
25.4M 3355
2333

2334
18p

18p

BC847BW
4
2

DEB +3V3_SW
3356 SML-310 1K0
7302 DGND DGND

32

22

20

16
36
56
63

13
35
49
64

34
48

43
TC90517FG
1K0

AD_DVDD

AD_AVDD

PLLVDD

DR2VDD
VDDC Φ VDDS

DR1VDD
AGND AGND I307
19 21 2335 1n5
I FIL
AGND
I308 X
18 58 I320 3354 33R TSO_VALID
O PBVAL DGND
3 53
0 RERR
DIF_P 2 XSEL
1
DGND 54
RLOCK
5308

2341

100n
RES

RES

2339 1u0 30
1n2

P
2340 1u0 29 ADI_AI 55 3353 33R
N RSEORF
DIF_N
2377 100n 28 59 3357 33R TSO_SYNC
P SBYTE
2378 100n 27 ADQ_AI
N
3331

3332

52
2K7

2K7

AGND SLOCK
2336 100n 24
P TSO_CLK
2337 100n 25 AD_VREF 61 3358 33R
N SRCK
AGND TSO_DATA0
2338 100n 26 60 3359 33R
AD_VREF SRDT
AGND
AGND AGND
39 38
DTCLK STSFLG1
DGND
40 9 I325 3339 20K IF_AGC
+3V3_SW DTMB AGCCNTI
8 10
S_INFO AGCCNTR
3349 10K 1 51
DGND 0 STSFLG0

2332

100n
41 TSMD
1
42
SYRSTN
3337 10K 7
AGCI
6
0
I316 11 SLADRS 5
CKI 1 AGND
AD_DVSS
AD_AVSS

TUNER_SCL F300 3351 100R I317 45 12

SCL SCL
PLLVSS

TUNER_SDA F301 3352 100R I318 46 TN 14 +3V3_SW

SDA SDA
VSS
23

31

17

4
15
33
37
44
47
50
57
62
2379

2380

3350
RES

RES

4K7
39p

39p

RES

AGND AGND F306

RESET_DEMOD
5309
DGND DGND DGND DGND
33R

3360

4K7
4306

4312
DGND
3335

3336
4307
10K

10K
DGND
4313

4308 4309 4314

+3V3_SW 4310 4311

AGND
5310 5311

I338
33R 33R
3344

3343
2K7

2K7

F302 FE_SCL
AGND DGND
F303 FE_SDA

2 2011-01-31

PCB SB SSB 1 2011-01-13

3139 123 6505

THRILLER BRZ DIG

19130_018_110426.eps
110426

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 71

10.6 B03 313912365052

10-6-1 Class-D & muting

Class-D & muting

B03 +24VAUDIO B03

220R

220R
5400

5401
3400 F400
+24VAUDIO
I411 I412 LEFT_SPEAKER
4R7 GND-AUDIO

220u 35V

220u 35V

22K

22K

22K

22K
2401

2400

220n

2403

2402

220n
10u 35V

V_NOM
2405

2404

220n

3452

3451

1402

2419
1K0

1K0

10n
5

2413

220n
2414

220n
1735
F404 1 LEFT +
F405 2

1
GND-AUDIO GND-AUDIO GND SND
3
GND SND

3405-4

3405-3

3405-2

3405-1
F406 4
GND-AUDIO RIGHT -

3454

3453

2420

2421
2041145-4

1K0

1K0
7400-1

10n

10n
F401 2406 I401

19
20

10
12
TPA3123D2PWP

1
3
AOUTR
47n AVCC L R
PVCC I413 2411
6 Φ BSR
16
I415 5402
I417
2415
RIGHT_SPEAKER
RIGHT_SPEAKER
R CLASS-D 15
220n

V_NOM
F402 2407 I403 IN R 22u 35V 220u
AUDIO AMP

1403
AOUTL 5
L OUT
22 5403 2416
47n L I416 I418
18 LEFT_SPEAKER
0 I414 2412
17 GAIN 21 35V 220u
1 BSL 22u
220n
2408 1u0 I405 11
GND-AUDIO VCLAMP
2409 1u0 I406 7
BYPASS
4
MUTE
2
F411 SD
MUTE I434

22K

22K

22K

22K
PGND 3422-4 F410 3422-3
F412 AGND L R

2433
A_STBY GND_HS

1u0
100K 100K

8
8
9

23
24

13
14

25
3422-2

2417

220n
2418

220n
DC_PROT
GND-AUDIO 100K
40
39
38

7400-2

1
TPA3123D2PWP 3422-1 2426 10u 7408

3406-4

3406-3

3406-2

3406-1
BC847BW
VIA GND-AUDIO 100K
26 37

2427
27 36

1u0
28 VIA
VIA VIA 35
GND-AUDIO
29 34
GND-AUDIO GND-AUDIO GND-AUDIO
VIA
GND-AUDIO GND-AUDIO
+12VS
DC-DETECTION
30
31
32
33

GND-AUDIO

3418

1K0
F415
+12VS I424
F408 3412 F416
+5V_SW RES RESERVED

RES

RES
2430

3430
I440

47K
4n7
1 6 1K0 3431
7402-1

I435
BC857BS(COL) 7403 47K
BC847BW 3 2
2 RES
BAS316

F409 7411 RES

RES
6400

I425 I433 4401 1 1 I436

3411 3413 BC857BW 3432 RES

RES
3433

10K
7412
3 2SD2653K
470u 16V

4K7 1K8 2 1K0

3410

2422
4K7

RES

RES
2424

3420
4 7402-2

47K
4n7
I423 HP_LOUT
3409 3426
I422

BC857BS(COL)
I430

5 6402 HP_ROUT
56K 47K
BAT54C

I442
2
3 I429

RES
3408

2431

3434
1
RES

RES
47K

47K
4n7
I431
3428
3419

10K

7406
7404 3 2SD2653K
6401 BC857BW 1K0
F413
+3V3STBY AOUTL
BAS316 RES 3435 I437 RES
100K
3416

7413
RES

AOUTR
100K
3414

RES 7405 2SD2653K

RES

3415 BSS84 1K0

I441

2 3
1R0
2425

3421
RES

47K
4n7

F414 1
SW_MUTE

3427 I432
2423

100n
3417

+3V3STBY
10K

7407
2SD2653K
1K0

RESET_AUDIO I445 3437 I443

3439

10K

F417 3K0
A_STBY
3438

2432
22K

1u0

7414
BC847BW
6403
BAT54C

2 2011-01-31

PCB SB SSB 1 2011-01-13

3139 123 6505

THRILLER BRZ DIG

19130_019_110427.eps
110427

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 72

10.7 B04 313912365052

10-7-1 MT5363 Power

MT5363 Power
B04A B04A

+3V3_SW

5506
7700-8

30R
MT5363BIMG
F503
F502 5500
H23 POWER-MAIN C8
H31 D9
+1V25_SW
30R J30 E8

100n

100n

100n

100n

100n

100n

100n

100n
V31 F9
VCCIO33

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n
+3V3_SW W32 G8

2514

4u7
DVSS

2567
W34 G10

4u7

2515

2516

2517

2518

2519

2520

2521

2522
W36 J4

2552

2553

2558

2559

2560

2561

2562

2563

2564

2565

2566
J6
AF13 L4
5501

AF15 VCCIO33-1 L6
30R

DVSS
N14
B1 P15
F500 3500 4u7
B13 R14
+1V8_SW
C2 R18
1R0 2598 VCC2IO
7700-7 C12 T15
DVSS
100n

2573 100n

100n

100n

100n

100n

MT5363BIMG D3 T17
2571 1u0

I504
2588

D13 T19
4u7

SENSE_1V8
POWER-MISC E4 U16
2568

2577

2576

2575

2574

E12 U18
VCC2IO

100n

100n

100n

100n

100n

100n
AM23 E14 V15

4u7
AVDD10_LDO DVSS

2507
F5 V17

22u
AVDD12 AVSS12 F13 V19

2500

2501

2502

2503

2504

2505

2506
AH33 P17 G6 W4
ADCPLL LVDS
AG30 T13 G14 W6
APLL MEMPLL VCC2IO
100n

100n

100n

100n

AP11 AH29 H7 W14

HDMI PLL_1 DVSS
N16 AH31 J14 W16
LVDS PLL_2
P13 AN26 R2 W18
2582

2581

2580
2584

MEMPLL RGB
AM25 AM9 R4 Y3
RGB USB
AG32 P19 R6 Y17
SYSPLL VPLL VCC2IO
AF29 AC6 Y19
TVDPLL DVSS
AL10 AD5 AA16
USB
N18 AD7 AA18
VPLL

100n

100n

100n

100n

100n
AE2 AB13
AVDD33 AVSS33 AE4 AB15
VCC2IO
Y31 Y33 AF1 AB17

2508

2509

2510

2512

2513
AADC AADC DVSS
5502 30R I505 AF33 AE34 AF3 AB19
ADAC0 ADAC0
5503 30R I506 T31 U30 AC14
ADAC1 ADAC1
AN32 AR32 R16 AC16
CVBS CVBS
AG34 AG36 U14 AC18
DEMOD1 DEMOD1
2569 100n

2570 100n

AK31 AJ30 V13 AD13

5504 30R DIG DIG DVSS
2597

2599

AM13 AN12 Y13 AE8

1u0

1u0

+3V3STBY 2592 1u0 HDMI HDMI

F15 J18 Y15 AF9
I502

LVDS_1 LVDS VCCK

2593 100n H15 Y29 AA14 B21
LVDS_2 REF_AADC
W30 AK29 AD15 D21
5505 30R REF_AADC SIF
AL30 AP9 AD17 E22
+3V3STBY SIF USB_1 DVSS
2595 10u AM11 AT9 AD19 G22
USB USB_2
2596 100n AN30 AT11 AE14 N20
VDAC USB_3 VCCK
AN24 AR30 AE16 P21
I507 VGA_STB VDAC
AK35 AL24 AE18 P23
XTAL_STB VGA_STB
AK37 AG12 P25
XTAL DVSS
AH7 R20
AJ6 R22
VCCK
2579

AJ8 R24
4u7

AK5 T21
AK7 T23
DVSS
AL2 U20
AL4 U22
SENSE+1V1_MT5363 VCCK
AL6 U24
F501 AL8 V21
+1V1_SW AM1 V23
DVSS
AM3 W20
100n

100n
100n

100n
100n
100n

100n

100n

100n
100n
100n

100n
100n
100n

100n
100n
100n

100n
100n
100n

100n
100n
100n
AM5 W22
100u 6.3V

4u7

VCCK
2551

AM7 Y21
AN2 Y23
2550

2549

2545
2544

2543
2542
2541

2540

2538

2537
2536
2535

2534
2533
2532

2531
2530
2529

2528
2527
2526

2525
2524
2523
AN4 AA20
DVSS
N22 AA22
N24 AB21
VCCK
T25 AB23
V25 AC20
W24 AC22
DVSS
Y25 AC24
AA24 AD21
VCCK
AB25 AD23
AE20 AD25
AE22 AE24

2 2011-01-31

PCB SB SSB 1 2011-01-13

3139 123 6505

THRILLER BRZ DIG

19130_021_110427.eps
110427

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 73

10-7-2 DDR

DDR
B04B B04B
+1V8_SW
+1V8_SW
3622 F602

1K0 1% 7700-3
MT5363BIMG

100n

100n

100n

100n

100n

100n

100n

100n

47u 16V
1K0 1%
2630

100n
3623

2608
DRAM 0
D7 RDQ(0)
H11 RDQ(1)

2600

2601

2602

2603

2604

2605

2606

2607
1
E6 RDQ(2)
2
G12 RDQ(3)
3
H13 RDQ(4)
4
N8 D5 RDQ(5)
1 5
P7 RVREF F11 RDQ(6)
2 6
F7 RDQ(7) 7600

M9
7

G1
G3
G7
G9
R1

C1
C3
C7
C9
A1
E1

A9

E9
J9

J1
RA(0) N4 B5 RDQ(8) H5PS5162FFR-G7C
0 8
RA(1)

VDDL
H5 D11 RDQ(9)
1 9 VDD VDDQ
RA(2) M3 A4 RDQ(10) RODT 3605-2 56R K9
2 10 ODT
RA(3)
RA(4)
G4
M5
3 11
B11
A12
RDQ(11)
RDQ(12)
RCKE
RWE#
3603-2
3603-1
56R
56R
K2
K3
CKE Φ A2
E2
4 12 WE 3604-1
RA(5) F1
5 13
C4 RDQ(13) RCS# 3605-4 56R L8
CS
SDRAM L1 RBA(2)
RA(6) M7 A10 RDQ(14) RRAS# 3605-3 56R K7 NC R3
6 14 RAS 56R
RA(7) F3 RA A6 RDQ(15) RCAS# 3600-1 56R L7 R7
7 RDQ 15 CAS 3600-3
RA(8) P1 AB1 RDQ(16) R8 RA(13)
8 16
RA(9) D1 U4 RDQ(17) RBA(0) 3603-4 56R L2
9 17 0 56R
RA(10) G2 AC4 RDQ(18) RBA(1) 3603-3 56R L3 BA G8 RDQ(0)
10 18 1 0
RA(11) N2 T1 RDQ(19) G2 RDQ(1)
11 19 1
RA(12) E2 T3 RDQ(20) RA(0) 3600-2 56R M8 H7 RDQ(2)
12 20 0 2
RA(13) M1 AC2 RDQ(21) RA(1) 3604-2 56R M3 H3 RDQ(3)
13 21 1 3
U2 RDQ(22) RA(2) 3602-4 56R M7 H1 RDQ(4)
22 2 4
RBA(0) H3 AB3 RDQ(23) RA(3) 3604-4 56R N2 H9 RDQ(5)
0 23 3 5
RBA(1) J2 Y5 RDQ(24) RA(4) 3602-2 56R N8 F1 RDQ(6)
1 RBA 24 4 6
RBA(2) H1 T7 RDQ(25) RA(5) 3601-4 56R N3 F9 RDQ(7)
2 25 5 7
AA6 RDQ(26) RA(6) 3602-3 56R N7 DQ C8 RDQ(8)
26 6 A 8
RCLK0 B3 V7 RDQ(27) RA(7) 3601-3 56R P2 C2 RDQ(9)
27 7 9
RCLK0# A2 RCLK0 V5 RDQ(28) RA(8) 3600-4 56R P8 D7 RDQ(10)
28 8 10
RCLK1 AD1 AA4 RDQ(29) RA(9) 3601-1 56R P3 D3 RDQ(11)
29 9 11
RCLK1# AD3 RCLK1 T5 RDQ(30) RA(10) 3604-3 56R M2 D1 RDQ(12)
30 10 12
RCKE K1 Y7 RDQ(31) RA(11) 3602-1 56R P7 D9 RDQ(13)
RCKE 31 11 13
RA(12) 3601-2 56R R2 B1 RDQ(14)
12 14
AB5 E10 RDQM(0) 3605-1 56R B9 RDQ(15)
REXTDN 0 3612 15
RODT N6 C10 RDQM(1) RCLK0 J8
RODT 1
RCS# P3 RDQM V1 RDQM(2) K8 CK B3 RDQM(1)
RCS 2 22R 1% UDM
RWE# K3 U6 RDQM(3) F3 RDQM(0)
RWE 3 LDM

100R
3614
RCAS# L2 F7
RCAS F600 3615
RRAS# P5 B9 RDQS(0) E8 LDQS J2 +1V8_SW
RRAS VREF
RDQS0 A8 RDQS(0)#
3613 1K0 1%

1K0 1%
B7 RDQS(1) RCLK0# B7

3616

2609
100R
3624

VSSDL

100n
RDQS1 C6 RDQS(1)# A8 UDQS
22R 1%
V3 RDQS(2)
VSS VSSQ
RDQS2 W2 RDQS(2)#

A3
E3
J3
N1
P9

J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
Y1 RDQS(3) RDQS(0)
RDQS3 AA2 RDQS(3)# RDQS(0)#
RDQS(1)
RDQS(1)#

+1V8_SW

100n

100n

100n

100n

100n

100n

100n

100n

47u 16V
2628
2620

2621

2622

2623

2624

2625

2626

2627
7601

M9

G1
G3
G7
G9
R1

C1
C3
C7
C9
A1
E1

A9

E9
J9

J1
H5PS5162FFR-G7C

VDDL
VDD VDDQ
RODT 3611-3 56R K9
ODT
RCKE
RWE#
3610-3
3610-4
56R
56R
K2
K3
CKE Φ A2
E2
WE SDRAM 3609-4
RCS# 3611-1 56R L8 L1 RBA(2)
CS
RRAS# 3611-2 56R K7 NC R3
RAS 56R
RCAS# 3606-1 56R L7 R7
CAS 3606-3
R8 RA(13)
RBA(0) 3610-1 56R L2
0 56R
RBA(1) 3610-2 56R L3 BA G8 RDQ(16)
1 0
G2 RDQ(17)
1
RA(0) 3606-2 56R M8 H7 RDQ(18)
0 2
RA(1) 3609-3 56R M3 H3 RDQ(19)
1 3
RA(2) 3608-1 56R M7 H1 RDQ(20)
2 4
RA(3) 3609-1 56R N2 H9 RDQ(21)
3 5
RA(4) 3608-3 56R N8 F1 RDQ(22)
4 6
RA(5) 3607-1 56R N3 F9 RDQ(23)
5 7
RA(6) 3608-2 56R N7 DQ C8 RDQ(24)
6 A 8
RA(7) 3607-2 56R P2 C2 RDQ(25)
7 9
RA(8) 3606-4 56R P8 D7 RDQ(26)
8 10
RA(9) 3607-4 56R P3 D3 RDQ(27)
9 11
RA(10) 3609-2 56R M2 D1 RDQ(28)
10 12
RA(11) 3608-4 56R P7 D9 RDQ(29)
11 13
RA(12) 3607-3 56R R2 B1 RDQ(30)
12 14
3611-4 56R B9 RDQ(31)
3617 15
RCLK1 J8
K8 CK B3 RDQM(3)
22R 1% UDM
F3 RDQM(2)
LDM
100R
3619

F7
F601 3620
E8 LDQS J2 +1V8_SW
VREF
RCLK1# 3618 B7 1K0 1%

1K0 1%
3621

2629

100n
VSSDL

A8 UDQS
22R 1%
VSS VSSQ
RDQS(2)
A3
E3
J3
N1
P9

J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

RDQS(2)# 2 2011-01-31
RDQS(3)
RDQS(3)# PCB SB SSB 1 2011-01-13

3139 123 6505

THRILLER BRZ DIG

19130_022_110427.eps
110427

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 74

10-7-3 Controller

Controller
B04C 7700-6
B04C
+3V3_SW +3V3_SW MT5363BIMG

F37 H33 TSO_SYNC

MOSTRT MISTRT

37A9
G36 G34

RES
TSO_VALID
3700

3701

10K
10K

10K
MOVAL MIVAL
7700-4 RES H37 CI CI H35 TSO_DATA0
MT5363BIMG 3726 MDO0 MDI0
F33 F35 TSO_CLK
4K7 MCLKO MCLKI
USB_PWR_EN 3704 100R I700 K35 GPIO J26
3705 I701
0 23 +3V3_SW
USB_OCP 100R K37 F25
1 24 D37 C36
EDID_WC J32 H25
2 25 +3V3_SW ETMDIO ETCRS

2729
RES
A30 B25

10p
RESET_DEMOD 3 26 F737 E36 G32

5700
C30 D25 4700 RES

30R
4 27 BYPASS_MODE ETMDC ETCOL

10K
10K
RF_AGC_SW G30 C24 LCD-PWR-ONn
5 28 F31
ARC_SW E30 G24
6 29 ETPHYCLK

3713
H29 E24

10K
5701 F704 2702 100n
3732 7 30
INV_STATUS 100R I758 F29 J24 D33 B33
8 31 3709 F760 3711 CLK CLK
30R B29 B23 LAMP-ON I741
9 32 3712

3715
3714
D29 F23 +3V3_SW F705 D31 D35
10 33 100R 7702 4K7 EN ER
2730

100n

C28 D23 +3V3_SW M24C64-WDW6

8
+3V3_SW 11 GPIO GPIO 34 F706 33R
E34 B37

3710
E28 A22

4K7
7703
12 35 Φ ER DV
J28 C22 BC847BW
13 36 ETTX ETRX
B31 C34

3703

3786
G28 AF5 7 (8K × 8)

10K

10K
+3V3_SW 14 37 F707 WC D3 D3
37AA

H27 AG2 E32 A34

4K7

15 38 EEPROM D2 D2
F708 I708 C32 B35
3707

F27 AE6 SCL-MAIN 6 1

4K7

3716 22R
16 39 F759 SCL 0 D1 D1
B27 AF7 VCOM_SW 2 A32 A36
17 40 ADR 1 D0 D0
D27
18 41
AG4 F738 3796 100R POWER-OK SDA-MAIN F736 3717 22R 5
SDA 2
3 MAC-CI
3706

+3V3_SW G26 AG6 F739 DC_PROT

4K7

F702
19 42

4
E26 AH3 F740
20 43 F761

2703

2704
F701 A26 AH1 SYS_EEPROM_WE

10p

10p
21 44
C26
22

RES 2705

10n
100n
RES

RES 2701
PANEL

100n

+3V3_SW
RES

2700

SDM

+3V3_SW FOR DEBUGGING

+3V3_SW +3V3_SW +3V3_SW ONLY

10K
10K
10K
10K
10K
+3V3_SW

4K7
4K7

10K
I731

3762
DEB

1K0
7708

DEB 3763-1
DEB 3763-2
DEB 3763-3
DEB 3763-4
DEB 3780
12

37
3740
H27U1G8F2B

3776

3777

3778
10K

RES
5705
+3V3_SW 1702
VCC
220R 1
BACKLIGHT-BOOST 3741
NAND_PDD(0) 29 1 2
I711 0

2713

100n
2712

100n
NAND_PDD(1) 30 2 JTRST F745 3
1K0 1
NAND_PDD(2) 31 3 JTDI F746 4
2
2706

NAND_PDD(3) 32 4 F747
1u0

1700 JTMS 5
3
NAND_PDD(4) 41 IO 5 JTCK F748 6
4
NAND_PDD(5) 42 10 F749 7
54M 5 F751 DEB 3765
2716

2717

NAND_PDD(6) 43 11 JTDO F750

10p

10p

8
3739 I713
6
BOOST_CONTROL NAND_PDD(7) 44 14 9
7 33R
15 10
1R0
3782
RES

NAND_PCLE I742 16 20
10K

11
CLE
NAND_PALE I743 17 21 F763 13 12
ALE
NAND_POCE I727 9 22
CE_

3760

3759
DEB

DEB
NAND_POOE 8 23 502382-1170

10K

10K
RE
NAND_POWE 18 24 DEB
WE
19 NC 25
WP
6 26
SE
NAND_PARB I726 7 27
R
28
+3V3STBY B
33

I732
4K7
4K7
7700-1
MT5363BIMG 34
35

RES
CONTROL

3779
AJ36 AR2 NAND_PDD(0) 38

4K7
XTALI 0
AP5 NAND_PDD(1) 39
BAS316

RES 3774
RES 3775
2710

2709

6706

3768

AJ34 AR6 NAND_PDD(2) 40

1K0
4u7

4u7

XTALO 2
7701 AU6 NAND_PDD(3) 45
BD45292G 3
T37 PDD AP7 NAND_PDD(4) 46
5

VCXO 4
VDD AT7 NAND_PDD(5) 47
5
AR8 NAND_PDD(6) 48
I725 1 Φ F721 6
4 ORESET AL22 AU8 NAND_PDD(7)
ER VOUT ORESET 7
I759 L30
BAS316

FSRC_WR VSS
100K
6707

3769

2711

100n
RES

I756 K5 AT1
MEMTN 0
37A5

13

36
SUB GND I757 K7 POCE AN6 NAND_POCE
4K7

MEMTP 1
2

M19
+3V3_SW TP_VPLL
AT5 NAND_PARB
PARB +3V3STBY
JTCK AK3 AR4 NAND_PALE
JTCK PAALE
4K7
4K7

RES 4K7
4K7

JTDO AH5 AU4 NAND_PCLE

JTDO PACLE
JTRST AK1 AT3 NAND_POWE
JTRST POWE
RES

3746

3747
AJ2 AU2 NAND_POOE 4K7

4K7
JTDI JTDI POOE
JTMS AJ4
JTMS
3761 AT21 I744 3727 100R
3718
3719

3720
3721

RX 1701
10K U0 AP21 I745 3728 100R 3748 33R F717 2
TX
SCL-MAIN AP3 R36 3
0 RX
SCL-DISP F741 R34 U1 T35 3749 33R F718 1
1 OSCL TX
P31 MSJ-035-29D PPO
2

F719
J34
0 UART (SERVICE) +3V3_SW
SDA-MAIN AP1 J36 I760 3783 4K7

BZX384-C6V8

BZX384-C6V8
0 OPWM 1
SDA-DISP F742 R32 T33
1 OSDA 2

6700

6701

1705

1706
P33
2 +3V3_SW
3722 10K AN22 I749
OIRI

3736
3758 10K 3723 10K

4K7
AL32 AM21 I746 3734 100R RES FOR ITV +3V3STBY
0 0
LED-1 RES 3788 100R I754 AK33 AM19 4707 RES +3V3STBY +3V3STBY
1 1 +3V3_SW +3V3_SW

100K
3790
I753 AM35 AN20

RES
KEYBOARD 3787 100R 4708 RES
2 OPCTRL 2
RESET_AUDIO
3702

AL34 ADIN_SRV AR20 I734 3738 100R

4K7

3 3 BACKLIGHT_CONTROL
3729

AM37 AU20 I739

I714
LED-2 3735 100R I733 3744 100R
10K

4 4 3791
3737 100R I747 AL36 7710 LIGHT-SENSOR
10K
10K
10K

LIGHT-SENSOR
5 BC847BW STANDBY
AL20 I750 3751 100R
OPWRSB 100R

2722
3753

3754

3724

1R0
4K7

4K7

1n0
3730 I755 I761 +3V3_SW
USB_DP AU10 AN14 PWM DIMMING
DP CEC
USB_DM AR10 AN18
3733
RES 37A6
RES 37A7

DM USB SDA1 10K

AN10 AM17
RES 3731 VRT HDMI SCL1 3792

680R
3742
I735
AL14 RC RC
+3V3STBY SDA2
10K AL12 7705
100R
SCL2

2723
POWER_DOWN BC847BW

1n0
37AB
RES

AL16 SDA-LCD 1M20

10K

I716 3745
PWR5V AM15 SCL-LCD F753 1
5K1 1%
3757

3789

SW_MUTE 2
RES

10K

4K7
N36 MUTE F754 3
CLK 3793

3743
N34 F755 4

1K0
RES
TUNER DATA F766 LED-2
AP37 HDMI_CEC I715 +3V3STBY F756 5
BYPASS F716 3781 100R F757

2724
6

1n0
+3V3STBY HDMI_SDA2 BACKLIGHT-PWM
AM31 HDMI_SCL2 F758 7
BYPASS0 100R
AH37 SIDE_HDMI_SDA1 +5V_SW 5706 F765 8
ADCINP 30R
DEMOD AH35 SIDE_HDMI_SCL1
ADCINN 3794
TRAP0 AOLRCK AOBCK ASPDIF F743 PWR5V_2 LED-1 2041145-8
+3V3STBY

2727

100n

2728

100n
M31 F744 PWR5V_1
IF RES100R

2725
ICE mode + Serial Boot 0 0 0 AGC M33

RES
TUNER_SCL

1n0
RF F725 3764 3798
ICE mode +ROM mode 0 0 1 TUNER_SDA POWER_DOWN
+3V3STBY
1K0 6K8
6 3767
BZX384-C3V3

15K 3795
VIP_ATV 7709-2 KEYBOARD
I737
6708

VIN_ATV 2 3 BC847BS(COL)
RES

TRAP1 OPCTRL3(0) 10R

2726

100n
3784 10K IF_AGC
PDWNC Normal 0 3785 10K RF_AGC 1 5
I738 3770 F724 6709
7709-1 +12VS
BC847BS(COL) 1K0 BZX384-C8V2
4
TRAP2 AOSDATA0 OPWM1

2721

3771
37A8

2719

2720

220n
2K2

47n

47n

1K0
XTAL 54MHZ 1 0
3756

4K7

+5V_SW 2 2011-01-31

PCB SB SSB 1 2011-01-13

3139 123 6505

THRILLER BRZ DIG

19130_023_110427.eps
110427

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 75

10-7-4 LVDS Display

LVDS Display
B04D B04D

+3V3_SW

SDA-DISP
RES 4812

4811
RES
4810
SCL-DISP

PCA5940 PCA9515 - (RES) 2802

4810 Y - 100n LVDS#1

RES 4823

RES 4815
7801
4814 Y - PCA9540B 3 1G51
RES 4813 F801
VDD SC0 5 60 61
4816 Y -
58 59
4817 Y - SC1 8 4814 56 57
SCL-VCOM 54 55
4818 Y - 4817 RES 4824
SCL_VGA 1 SCL SD0 4 52 53
4819 Y - I2 C SDA-VCOM 51
INP
4818 -BUS F833
SDA_VGA 2 SDA FIL SD1 7 4816 50
4820 - Y CTRL
F832 49
4812 - Y 4820

4822
48

RES
VSS
RES 6 47
4815 - Y 46
BYPASS_MODE
4813 - Y 4819 RES 4821 45
44
4821 - Y 43
4822 - Y VCOM_SW 42
- 41
4811 Y
PX1A- F805 40
PX1A+ F806 39
F807 38
PX1B- F808 37
PX1B+ F809 36
F810 35
PX1C- 34
+5V_SW +12VDISP F811 33
PX1C+
F812 32
PX1CLK- 31
PX1CLK+ F813 30
F814 29
28
RES 4800
RES 4801
RES 4802

PX1D- F815
27
4803
4804
4805

PX1D+ F816
26
RES
PX1E- 2803 10n F831 25
4806 RES PX1E+ F817 24
4807 RES F818 23
4808 RES F819 22
8 5800 21
PX2A- F820
3 7 33R PX2A+ F821 20
2 6 I801 5801
F822 19
I800 1 5 33R PX2B- 18
5802 +VDISP-INT 17
PX2B+ F823
33R F824 16
7800 PX2C- 15
SI4835DDY PX2C+ F825 14
3802
4

F826 13
PX2CLK- F827 12
47K
PX2CLK+ F828 11
6800
F834 10
PX2D- 9
BZX384-C6V8 8
PX2D+
7
3803 I802 2806
PX2E- 6
PX2E+ F829 5
47R 1u0 +VDISP-INT
3805

4
47K

3
+3V3STBY 2
1

100u 16V
2804

2805

100n
FI-RNE51SZ-HF-R1500
3806

15K

I806 3807 I807

7803 6
BC857BW I808
10K
7802-1 2 3
3808 BC847BS(COL) I809 F800
1 5 3809 LCD-PWR-ONn
10K 7802-2
BC847BS(COL)
1K0
2807

220n
3810

4
1K0

2 2011-01-31

PCB SB SSB 1 2011-01-13

3139 123 6505

THRILLER BRZ DIG

19130_024_110427.eps
110427

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 76

10.8 B05 313912365052

10-8-1 HDMI & Multiplexer

HDMI & Multiplexer

B05A B05A
RES
6913
IP4281CZ10
M_RX1_1B 1 2 M_RX1_1
3

8 HDMI_PLUGPWR1
M_RX1_2 5 4 M_RX1_2B
HDMI PORT 1
+3V3STBY
6 7 9 10
M_RX1_2 M_RX1_1B I906 1901
6902
M_RX1_2B M_RX1_1 M_RX1_2 1
+3V3STBY 2 7900
RB521S-30 M24C02-WMN6

3900
M_RX1_2B 3

10K
8
Φ

3906

2900

100n
M_RX1_1 4

27K
5
RES F901
6914
HDMI_PLUGPWR1
7908 M_RX1_1B 6 (256 × 8) 7
WC
IP4281CZ10 BSH111 M_RX1_0 7 EEPROM
RES F902 SIDE_HDMI_SCL1
M_RX1_CB 1 2 M_RX1_C 8 1 6
0 SCL
3 M_RX1_0B 9 2
1 ADR F903 SIDE_HDMI_SDA1
M_RX1_C 10 3 5
2 SDA

3908

3907
8 11

3K3

3K3

4
M_RX1_0 5 4 M_RX1_0B M_RX1_CB 12
HDMI_CEC_A F914
HDMI_CEC 4904 13
F915 F904
6 7 9 10 eHDMI+ 5900 30R ARC_eHDMI+ 14
M_RX1_0 M_RX1_CB SIDE_HDMI_SCL1 15
M_RX1_0B M_RX1_C SIDE_HDMI_SDA1 16
17 3901 I915
18 EDID_WC F905 7902
PWR5V_1
19 L : WP MMBT3904
10K

3912
20 21

1K0

CDS2C05HDMI2

3924

3902
22 23 H : WRITE

DEB

68K

4K7
RES

2902

6903

5.6V
10p
6915 I902
IP4281CZ10 4900 47266-9002
HDMI_PLUGPWR1
M_RX2_1B 1 2 M_RX2_1
3 RES
F900 RES +5V_SW
SIDE_HDMI_HPD1 4901 7905
8 MMBT3904

1
100K
3913
M_RX2_2 5 4 M_RX2_2B

3914
RES

4K7

BAT54C
HDMI_PLUGPWR1
6 7 9 10
M_RX2_2 M_RX2_1B
F913

6900
M_RX2_2B M_RX2_1 3

RES
6916

2
IP4281CZ10
M_RX2_CB 1 2 M_RX2_C PWR5V_1
3

M_RX2_0
8
5 4 M_RX2_0B
HDMI PORT 2 (SIDE) HDMI_PLUGPWR2

6 7 9 10
M_RX2_0 M_RX2_CB
M_RX2_0B M_RX2_C 1902
M_RX2_2 1
2 7901
M24C02-WMN6

3903
M_RX2_2B 3

10K
8
HDMI_CEC_A
Φ

2901

100n
M_RX2_1 4
5
HDMI_PLUGPWR2 (256 × 8) F906

CDS2C05HDMI2
M_RX2_1B 6 7
WC
M_RX2_0 7 EEPROM F907 HDMI_SCL2

5.6V
6917
RES
8 1 6
0 SCL
M_RX2_0B 9 2
1 ADR F908 HDMI_SDA2
M_RX2_C 10 3 5
7700-5 2 SDA

3916

3915
11

3K3

3K3
MT5363BIMG
M_RX2_CB

4
12
HDMI_CEC_A 13
HDMI-LVDS 0P
G16 PX2A+
14
F909
M_RX2_0 AP17 E16 PX2A-
0 0N HDMI_SCL2 15
M_RX2_0B AT17 H17 PX2B+
0B 1P HDMI_SDA2 16
M_RX2_1 AR18 F17 PX2B-
1 1N 17
M_RX2_1B AU18 G18 PX2C+ 3904 I916
1B 2P 18 EDID_WC 7903
M_RX2_2 AP19 RX1 E18 PX2C- PWR5V_2
2 2N 19 MMBT3904
M_RX2_2B AT19 AE G20 PX2D+ 10K
2B 3P
3919

20 21
1K0

M_RX2_C AR16 E20 PX2D-

C 3N

3923

3905
22 23

DEB

68K

4K7
M_RX2_CB AU16 H21 PX2E+
CB 4P
F21 PX2E-
4N 4902 I905 47266-9002
HDMI_HPD2 AL18 H19 PX2CLK+ HDMI_PLUGPWR2
HDMI_HPD1 CKP PX2CLK-
F19
CKN RES
F912 RES
M_RX1_0 AP13 D15 PX1A+ HDMI_HPD2 4903 7907
0 0P MMBT3904
M_RX1_0B AT13 B15 PX1A-
100K

0B 0N
3920

M_RX1_1 AR14 C16 PX1B+

1 1P
3921
RES

4K7

M_RX1_1B AU14 A16 PX1B-

1B 1N +5V_SW
M_RX1_2 AP15 RX2 D17 PX1C+
2 2P
M_RX1_2B AT15 B17 PX1C-

1
2B 2N PX1D+
M_RX1_C AR12 AO D19
C 3P
M_RX1_CB AU12 B19 PX1D-

BAT54C
CB 3N HDMI_PLUGPWR2
C20 PX1E+
4P
SIDE_HDMI_HPD1 AN16 A20 PX1E- F911
HDMI_HPD2 4N

6901
C18 PX1CLK+ 3
CKP
A18 PX1CLK-
CKN

2
PWR5V_2

2 2011-01-31

PCB SB SSB 1 2011-01-13

3139 123 6505

THRILLER BRZ DIG

19130_025_110427.eps
110427

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 77

10-8-2 USB

USB
B05B B05B

7D00
TPS2041BD
FD04
6 4 USB_PWR_EN
1 EN_
USB 7
2 OUT 1
2
+5V_SW
1D01
FD01 5D00 FD07 IN
1 5V 8 3
FD02
3 2
2
USB_DM 33R
3
USB_DP FD03 5
OC_ 2D14

GND
4 FD00 2D12
100n 100u
6 5 16V

BZX384-C6V8
1D03

1D04

1D05

6D00

2D11
USB-01-PBT-B-30-CU2

10u

1
FD06

FD05 USB_OCP

USB_DM

USB_DP

2 2011-01-31

PCB SB SSB 1 2011-01-13

3139 123 6505

THRILLER BRZ DIG

19130_026_110427.eps
110427

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 78

10.9 B06 313912365052

10-9-1 Analog I/O - Headphone

Analog I/O - Headphone

B06A B06A

RESERVED

RES
3A04
HP_LOUT LEFT FA03
1R0

PESD5V0S1BA
2A02

RES 1A03
RES

1n0

6A01
RES
HEADPHONE
1A01
2 RES
3
1
MSJ-035-12D-B-AG-PBT-BRF

FA04
RES
HP_ROUT 3A03
RIGHT FA02
1R0

PESD5V0S1BA
2A01

RES 1A02
RES

1n0

6A00
RES

RES
3A10

22K

+3V3_SW

RES
7A00 RES

2A10
RES

1u0
PBS_HPL TPA6111A2DGN 3A11
2A05
RES

4A02
47n

8
RES
RES
RES RES
Φ VDD
RES 33R
HPOUTL FA06 2A07 3A18 10K IA02 3A15 10K 2 AMPLIFIER 1 IA09 2A06 IA00 RES 3A12 FA08 HP_LOUT
1 1
FA07 RES RES 33R
HPOUTR 1u0 RES 2A08 IA03 3A16 10K IN- 100u 4V
3A19 10K 6
2 VO RES RES
1u0 RES 3A17 IA04 IA08 2A09 IA01 3A13 FA09
RESET_AUDIO 5 7 HP_ROUT
SHUTDOWN 2
10K RES 2A11 IA10 100u 4V 33R
PBS_HPR 4A03 3 10
BYPASS RES 3A14
RES VIA 11
1u0
2A12

2A13
RES

RES

GND GND_HS
1n0

1n0

33R
2A04
RES

9
47n

RES
3A09

22K

2 2011-01-31

PCB SB SSB 1 2011-01-13

3139 123 6505

THRILLER BRZ DIG

19130_027_110427.eps
110427

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 79

10-9-2 Analog I/O - Audio

Analog I/O - Audio

B06B 7700-2
B06B
MT5363BIMG

AUDIO-VIDEO AF
AM33

AN34
P
MPX AN36
N
AD33 IB10 AIN0_L-AV1
IB66 0_L
HSYNC AR22 AC34 FB02 AIN0_R-AV1
IB67 HSYNC 0_R
VSYNC AU22 AB31 IB12 AIN1_L-AV2
VSYNC 1_L IB13
AC32 AIN1_R-AV2
IB23 1_R
SOG AP23 AD35 IB02 IB01 2B34 IB00
SOG 2_L 3B31 3B32 FB00
RP IB24 AT25
RP 2_R
AB35
AC36 DVI_AUL_IN
AUDIO IN

PESD5V0S1BA
3_L 30K 10u 1R0
GP IB25 AU24 AIN_AADC AB37 DVI_AUR_IN
GP 3_R 1B01
IB26 2

6B00
AT23 AA32

RES
BP BP 4_L 3

2B35

2B36

1B03
RES

RES
AB33

1n0

1n0
IB27 4_R 1
GN AR24 AA34
COM 5_L
Y35 MSJ-035-29D PPO
IB39 5_R
SPR0P 3B11 68R 2B11 10n PR0PAU30 AA36 SAV_L_IN
IB29 0P 6_L FB06
SPR1P 3B05 68R 2B05 10n AP27 PR Y37 SAV_R_IN
IB41 1P 6_R
SPB0P 3B09 68R 2B09 10n PB0PAP29
3B03 IB31 0P
SPB1P 68R 2B03 10n AT27 PB AA30 IB03 2B37
IB43 1P VMID_AADC 3B34 IB09 IB08 3B33
SY0P 3B07 68R 2B07 10n Y0PAR28 0P
3B01 68R 2B01 10n IB33 AU26 Y

PESD5V0S1BA
SY1P 1P 30K 10u 1R0 FB01

2B41

2B40
100n
1u0
IB45 NEAR CONNECTOR

6B01
SY0N 3B08 100R 2B08 10n Y0NAT29

RES
IB35 0
3B35 4K7

2B38

2B39

1B04
RES
3B02 2B02 10n AR26 COM L34 IB14

RES
SY1N 100R

1n0

1n0
1 AOBCK IB15 3B36 4K7
M37
2B06 IB47 AOLRCK
3B06 1R0 1n5 SOY0AU28 M35
3B00 1R0 2B00 1n5 IB37 0 AOMCLK
SOY1-AV2 AP25 SOY
1 IB16 3B37
AP33 L36 +3V3_SW
0 0
SOY0-AV1 AR34 SY P35
1 1 4K7
AT33 P37
0 AOSDATA 2 3B38
AU34
1
SC
3
K31
N32
+3V3_SW SPDIF
FB08 2B15 4 4K7
GND_CVBS IB61 AR36 1B02
0N IB17 2B42
FB03 ASPDIF_OUT FB04 2
AT37 K33 SPDIF_OUT 3B15 240R
1u0 0P ASPDIF
3B14 2B14 AU36
1P CVBS 100n FB07
CVBS_AV3 IB63 AP35 L32 3B16 100R 1
2P ALIN RES 3B39

1B05
AT35 MTJ-032-21B-43-NI
100R 47n 3P 2B20 33p

2B19
AF37

33p
0 4K7
AP31 U32
OUT1 1
AT31 VDAC AL V35 RES 2B16 10u HPOUTL
OUT2 2
DEB 3
V37 IB18 2B17 10u IB19 PREAMPL
AM29
FS_VDAC
AE36
0
V33
1

DEB

560R
3B58

3B47
AR U34 RES 2B24 10u HPOUTR

75R
2 IB20 IB21
U36 2B25 10u PREAMPR
3
AF35 IB22
AVICM

3B17

3B18

3B48

3B49
RES
RES

47K

47K

47K

47K
2B43

2B44

100n
1u0
+3V3_SW
+3V3-ARC

3B40
3B54 IB70
22K
1R0
2B50

220p

2B60

100n
2B51 3B41 3B50
4

PREAMPL IB48
2B58
IB49 5K1 2 AOUTL
10u 10K
2B52

820p

1
+12VS 10u
3 7B05-1
8

LM833

14
3B51

74LVC00APW
47K

7B01-1 IB71
+12VS ASPDIF_OUT 1 & 2B61 IB72
3 SPDIF_OUT
3B42

2
30R

100n
IB50 +3V3_SW
3B43

7
47K

+3V3_SW

IB51
2B53

1u0

+3V3-ARC
2B54

3B44

3B55
+3V3-ARC
47K

10K
10u

7B05-2

14
74LVC00APW 7B05-3

14
4 & 74LVC00APW
6 9 & 2B62 3B56 IB74 2B63
ARC_SW FB09 eHDMI+
7B01-2 5 8
LM833 10
+3V3_SW 100n 180R 100n
8

7
5
2B59
7

7
2B55 IB52 AOUTR
IB53 3B45 3B52

3B57
PREAMPR 6

68R
10u
4

10u 10K 5K1

2B56

3B53
820p

47K
2B57

220p

+3V3-ARC

7B05-4

14
74LVC00APW
12 &
3B46
11
13
22K +3V3_SW

7
2 2011-01-31

PCB SB SSB 1 2011-01-13

3139 123 6505

THRILLER BRZ DIG

19130_028_110427.eps
110427

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 80

10-9-3 Analog I/O - Video

Analog I/O - Video

B06C B06C
NEAR CONNECTOR
NEAR CONNECTOR 2C24
3C28 IC09 3C12
AIN0_R-AV1
3C26 2C22 IC01 3C00 30K 10u 1R0

PESD5V0S1BA
AIN1_R-AV2

1C14
2C20

2C21
RES

RES
1n0

1n0
PESD5V0S1BA
30K 10u 1R0

6C19
2C00

2C01

1202

0001
6C00
RES

RES

RES
1n0

1n0
RES

3C29 2C25 3C13 FC15

AIN0_L-AV1 IC10

3C27 2C23 IC02 3C01 30K 10u 1R0

PESD5V0S1BA
AIN1_L-AV2

RES 6C20

1C15
2C18

2C19
RES

RES
PESD5V0S1BA

1n0

1n0
30K 10u 1R0
CVI 2 CVI 1

2C02

2C03

6C01

1C16
RES
RES

RES
1n0

1n0
1C02 1C01
FC09 FC10
MSP-636V1-01 1 MSP-636H1-01-NI
1 2
FC08 3
2
IC03 3 IC11 FC11
3C20 5C00 3C21 5C03
SPR1P SPR0P 4
4 60R
18R 60R FC07 18R
5

PESD5V0S1BA
2C04

3C02

1C17

2C17

3C14

RES 6C08

1C10
5

56R

56R
PESD5V0S1BA
15p

15p
6

6C02
6

RES
FC12
PR_CVI2 PR_CVI1 7
7
FC04
8
8
FC05 FC13
PB_CVI2 PB_CVI1 9
9

PESD5V0S1BA

PESD5V0S1BA
10

RES
11
2C05

3C04

6C03

1C18

2C16

3C16

6C09

1C09
10

RES
56R

56R
15p

15p
FC06 FC14
SY_CVI2 11 SY_CVI1 12
IC15 12
3C22 5C01 IC13 3C23 5C04
SPB1P SPB0P
18R 60R IC21 18R 60R
IC16 SOY0-AV1
SOY1-AV2 IC14 3C24 5C05
IC17 SY0P
SY1P 3C25 5C02
60R

PESD5V0S1BA
18R

1C08
60R

PESD5V0S1BA
18R

1C19

2C15

3C17

6C10
RES
56R
15p
2C06

3C05

6C04
56R

RES
15p

IC22 3C18
IC18 SY0N
SY1N 3C06
1R0
1R0

SIDE AV
CVBS
1C03-1
YELLOW2 FC03 3C07 IC04
RIGHT CVBS_AV3
PESD5V0S1BA

(YELLOW) 1R0 IC19

1 SAV_L_IN
1C05

6C05

3C08

2C08

2C07

MTJ-032-37BAA-432 NI
RES

75R
RES

15p

47p

IC20
SAV_R_IN

GND_CVBS

LEFT1C03-2
FC02 IC05 2C09
WHITE 3C09 3C10
5
PESD5V0S1BA

(WHITE) 1R0 10u 30K

4
6
MTJ-032-37BAA-432 NI
6C06

2C11

2C10
RES

RES

RES
1n0

1n0
1C06

NEAR CONNECTOR

1C03-3
FC01 3C11 IC07 2C14 3C19
RED
8
PESD5V0S1BA

(RED) 1R0 10u 30K

7
9
1C07

6C07

2C12

2C13
RES
RES

MTJ-032-37BAA-432 NI
RES
1n0

1n0

FC00
2 2011-01-31

PCB SB SSB 1 2011-01-13

3139 123 6505

THRILLER BRZ DIG

19130_029_110427.eps
110427

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 81

10-9-4 VGA

VGA
B06D B06D

6E06
+5V_SW
IE00 3E26 BAS316

10K
3E25 FE16
EDID_WC 7E01
BC847BW
10K

3E27
RES

68K
DC_5V

2E00 3E00 5E00

RP VGA_Rp VGA_R FE01
10n 68R 60R

PESD5V0S1BA
2E07

3E16

6E00

1E00
RES
75R
5p6
2E03 3E03
SOG
1n5 1R0
2E02 3E02 5E01
GP VGA_Gp VGA_G FE02

PESD5V0S1BA
10n 68R 60R

2E08

3E15

6E01

1E05
RES

0001
75R
5p6
2E04 3E04 3E10 FE11 DC_5V
GN VGA_Gn

10n 100R 1R0

RES
3E24
DC_5V
2E05 3E05 5E02
VGA_B 6K2 1%
BP VGA_Bp
2E16
4E04 FE15

PESD5V0S1BA
10n 68R 60R
100n

2E09

3E14

6E02

1E02
RES

0001
75R
5p6
7E00

3E21

3E22

3E23
M24C02-WMN6 8

33R
10K

10K
Φ
FE10
1E01 7 (256 × 8)
WC
1 EEPROM
5E03 6E05 3E13 FE13 FE08
2 4E02 SCL_VGA 6 1
DC_5V SCL 0
FE03 3 2
60R BAS316 150R FE09 ADR 1
4 4E03 SDA_VGA 5 3
SDA 2
2E10

2E11
100n

1n0 5
6 4

1%

1%
RES 3E19

2E14

2E15

RES 3E20
330p

330p
7
FE12
8

6K2

6K2
FE04 9
5E04 10
H_SYNC
HSYNC 11
12
PESD5V0S1BA

30R
FE05 13 FE14
2E12

RES 3E17

6E03

1E03

FE06 14
RES
2K2
5p6

15
FE07
16 17

5E05 VSYNC 1216-02D-15L-2EC

VSYNC
PESD5V0S1BA

30R
2E13

RES 3E18

6E04

1E04
RES
2K2
5p6

2 2011-01-31

PCB SB SSB 1 2011-01-13

3139 123 6505

THRILLER BRZ DIG

19130_030_110427.eps
110427

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 82

10.10 B07 313912365052

10-10-1 Hospitality

Hospitality
B07 B07

DMMC1 DMMC3
RES RES
1F00 1F01
FF12
1 FF00 RES 5F00 33R +3V3STBY 1 PBS_HPL
2 SDA_CLOCK FF01 RES 3F00 100R SDA-LCD 2 FF11 FF13
3 SCL_CLOCK FF02 RES 3F01 100R SCL-LCD 3 PBS_HPR
4 4 5
5 FF03 RES 5F01 33R +5V_SW
6 7 FF04 502382-0370

RES
2F00

2F01
RES
1n0

1n0
502382-0570

2 2011-01-31

PCB SB SSB 1 2011-01-13

3139 123 6505

THRILLER BRZ DIG

19130_031_110427.eps
110427

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 83

10.11 313912365052 SSB Layout

10-11-1 Overview top side

1X05

2608 2101
4817
4820

7123
4814

1702 1G51

4815
7122
4822

U4
7801 4816

7124
U5

4823
2140
4821

U2
4818

2105
4812 4819

5120 2168
2104 4810

2802
4824

4813
5117 2154

3765
3780
3760
3759
4811 2155

3763
5115 2188
2183

1X04
2152 2803
2161
2805

6122
2138 3762
2162

2171
2153
2163
2100
2191

2189
2172
5121
3615 2609
2804 5104
2135
2126 5123
1M99
2701
2125

2164
7600
3707
3706

2700
7120 2159

2551 2628

37A9

5506
2514
2127
2134

4700
3726

37AA
7125

1D05
3126

1D01
2128
2133

U23
3600

2106
3605 3602 3614
3127 3612 2729

2D14

1D04
2109
2131 3613
2132

5105 2176

3128 3607
2130 3B37
4100 3609
2129 3611 3606 3608 3610
3784 2720
2198 3785 2719
2151 3754
2175
2181

37A8

3B18
2146 3753 2B24
2136
2B16

3B17
2169
5106 2B25
1F01

2B41
7601
2199 2B17

2B40
1M95

2137
2180

3129

7700 2B43

2B44
2290
2416 2415 2422

2291

1C07
5228
2289 5230 5229 6C07

2288
2148
2287 5227 5226

2286
3619 2C12

3711 2702
7216
3617

2C13
5700
2147 2285

2717
3C11
3618

1700

2C14
3737 3757
2145
2405 5402

3735 3731
3758 3C19
2143

2149

2403
3788
2141 2144

7702
2716 3787
3796 3C10
7703

2C09
2142 3715

3712
3713
3709 3C09

2C10
3719 2C11

1C03
1M20 1735

3718

1C06
1402

6C06

7A00
2419

2E05

2E02

2E04

2E00

2B00

2B01

2B02

2B03

2B05

2B06

2B07

2B08

2B11

2B09
2402
5401

2704 2703

3E05

3E02

3E04

3E00

3B00

3B01

3B02

3B03

3B05

3B06

3B07

3B08

3B11

3B09
3717 3716
7400
2411
2421
2420
1403

2B56
3B49 2B55 3B45

2A06
2A09
2412

2297
3B52
3B46

2B57
4306
5400

2400
3791 3790 3C07

2722 2C08
7B01

1C20
3C08

2723 2C07
5403

3792

1C05
2294 5208
6C05

3A13

3A14

3A12

3A11
2724
3793
2727

2401 1X03 5311

6A01

3B34
5207

3B31
2725

2258
3794

2A02

3A04
2B37
2B34

1A03
2B50

2726
3B40

3B50

3B48

2296
3B32 3B33

2B38
2B35
3795 3798

3749
2A01 3A03
2B36 2B39
2728 3748

1A01
2B52

2B20

3B16

2B19
5706
6B00 6B01
6701 6700

3B15
6A00
1B05
1706

1A02
1B03
1C14 1C08
1B02 1705 1B04
1C09

1C15

1C01
1C10
1701 1B01
1201

6916 6915
5309

1902
6C08
5C03
6C20

6C10
5C05
6C19

3C13

2C19
2C21

3C12

3C21

3C14

2C17

3C24

3C17

2C15

3C18

2295
3C29
3C28

2C16

3C16

2C24 2C25
2C18

2C20
5C04

6C09

2E09

5E02
1X02
3C23

3E15
3E14

6E02
7B05 2E08

5E01
2B61
6C00

6C02

6C04
3C25

2C06

3C05

3C06
6C01

6C03

2C00 2C22
6E01
5C00

3B54
3C20

3C02

2C04

3C22
5C01
2C05

3C04

3E10
5F01

5F00

3B55

2C23
2C01

3C00

3C26

3C27
6917
2C02

3C01

2C03

3F01
3F00

5C02 5E03

3E16

2E07
6E00 5E00

6E05
1202 6914 6913

6E03

3E17

2E12
2E13
3E18

1C19

5E04
2B60 3E13

2E11 2E10
6E04 5E05

1C16 1C17
2B62

1F00 1E02 1E05 1E00

3B56

3B57

1C18 2B63

1X01

1E03
1E04
1901
1C02 1E01

2 2011-01-31

SSB Layout Top

3139 123 6505

19130_040_110428.eps
110428

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 84

10-11-2 Overview bottom side

3122 I107 2185 3101

2157
3125 I122 2177 3135 I106 2160 2179 3114 I135 2112 2178

2190
I144
3105 F750 F748 F746 3100 3102
I140 I120
F763
3107 I136 2158 3113

7119
F801 F832
3115 2139

F815

F813
F132 I127
F811 F809 F807 F805 3146 I137
3118

F749

F747
F831 I132

2165 3140

I141
F833
3116

F812

F810

F808

F806
F834 F816 F814

3112

5124
F135
I138
F751
I117
I105
F133

5125
2166
2193
I143

3136
F829
2123 3150 I131

2197

2122

3138
I123
2170 3149
2186

3108
2187 3151
2150 2192

5801
5802
5800
I119
F131
I118
I104
I134

3153 I801

3154
F125
FD00
3155

F818

F817
F824 F823

2602 F102

7800
3616 F600

5705
4803
4804
4805
2607

4800 4806
5127 4801 4807
4802 4808

3779
3778
3775
3774
2712

3776
3777
2706 F502
2601

2600
F103

3741
3782
I800 5500
F702
F819 I743 I727

FD05 FD04 F822 F821

2567
3740 F828 F827 F826 F825
2566

3700
3701
I732 I742 I731 I726

U1
F820

2604

F104
F701

3705 3145 I112 2167

2603 2605 2606

7D00
F800

3809

3103
I109 F105
3704 3109 I111

2195

2D12
3601 3148
3604 F106

3808
I142
FD03
3802
I711 3739 I713
3117
7803

2107
I125
3603

2108
I806

3721
3720
3B38 3106

3805
2806
6800
FD06

3B39
F107

3732 5701
FB03

IB17
I807
FD02 2B42

2807 3807
FD07
3803 F716

2730
IB16 F503 F737 F108

3781
7802

3810
I802

5D00
I809

1D03
I808 I715

7708
F109

7705
2502

3742
I758
I701
2506

3111
2124 3152

6D00
FD01

2D11
I126 3806 2501
2113

2521
F742

I110
2505
5128
I700

2110

2581
3736
F101 I113
I108
2504

5503
F741

3743
I716 3745 IB14
2522 2515 2503

2565
2523
2564
I756

2524
I759
2111 F136 3B35
I757
F113
2584

3783
I506
I760 F601

2623

2624
IB15

2627
3B36
37A5

2513 2630
4311 4314

3621
2629
3620
IB18 IB20 2536 3623 F602
F114

I714
2599 2570
3622

2512
2525 2622

4307
F501
F117

4309
2552

2516
2518
2526 F409

2553 2621

4401
2F00
FF11
2537 3131 F116

2569
I254 F416 3416

2533
2517
2277 5502
2577 2527 2620 2625
2626
6402

3130
I139

6401

3412
2F01 FF13 FF12
2538 F115

2532
IB22
2278 2597 2535 3624
5222

2531

2423
3417

7405
FC01

F414
3415

2558
2562
2563
2713

I424

F120
6102

2510
F500 I505 2534 2508 2509 I429
2500

2529
2545

2560
2528
F236
F413 3414

2582

6400
2580 2507

2530
2519
2520
3B47
2282 2579 2102

3432
F119
2561

2559
2541
3722 2574
I436

5225
F704

7411

3411
3413
3723 CXXX I423
7402 I425

4209 F118

2596
IC07 I747 I442
2543 F759

2595
I507

5505

2540
2542
I255

7412
I735
2573 F415
2284

4210

2550
3409 3410

2549
I422 F408
2544

3435
2430
3430
IC20

2575

2576
F121

3418
I733 I435 3431 3408

3B58
3789 F745
3761 7403
2283

2281
2279
U3
I754
2280

3433

3426
IC19

I753
I433

2571
2588

I440
4313 7404

2568
37AB I437 F122

2705 F738 3786 I741

7413

2431
3434
IB63 I502 I504 F706
3B14 2B14 IB61 F705 F123
IC05 3714 I708 3419 I430
3A18 2593 5504 3703 F761
4A02 3272 3271 4312
2B15
3710
F760
IA02 2592 5501 F739
3A15

FA06

2A07

2598 3500
F740 F707
IB37 F721
2A12

3A10

2A05

IB27 IB26 I744

F708
3405
FC00

I750
FC02
I739
4707 F736
I412
IA10 IB47 IB31 IB33
IA09 IB41 IB24 IB25 3452 F404

3744
4708
2414

37A7
2A11

IB39 IB45
I734
37A6
3451
IB43 IB29 IB35
2E03 IB23

2426
2711

3738

2408

3422
F417
3E03
I746
I405 I415
2413 I417
2A10

IA04 3756

3734
3751
3729
3702
3A17 IB21

6706 F411 I745 I761

F410 F405

I413
4A03

I749 F766

3724

7710
6707 C400 F406
IB53
3A16

F400 I434
FA07
2A08

3768

3727

3728

3730
I906
2A04 I406 I414
IC04 A214 2427 3453

4904 3906
3769 I725 6902

2409
3A09 IA03
3400

7408
IB52 I403 3454

2404
7701
I755

2407
IA08 3A19
I302

3746
3747
3764
5307 I401
2378
2337

2710
3733 2709
2A13

7908
3332 3331

5306

2406
2320

2333
3262

2B59
F402
5308
2341

A213

2425
3421
2340
1301
2334
FB08
2318 2321

3B53
2335
2377
2338
2336

F753

3263
2339 2323 2322 6708 F725
F401
2424
3420
IB50
FC03
I738
5304 2262
2324 2263
2314 3261

I300 I307 I308

7709 3B42

4308

2721
7407

2B53
I737

3771
3770
IA00 IA01 F246
A212

6709
F754

2306 3767 I411

3B43
I304 F724
I432
FA04 3344

F755
7406
2311 F303

3427
IB02
2301

2B54
I338 IB51
2303 2418

3B44
IB03 F209
I301 3343 IB19 F412 I416
F756
2309 IB48 I431 3428
3360

F302

2417
3339
2332 I418
3350

3B41
2B51

6403
2433 3439

7302
IB01 F757
IB49 I441
I306 F213
2313 3352 3351 2316
2312 2379 2380 2317

IB09 F306

7414
I325

3406
IB08

2B58
F208

FA08 IB00
5305 3337
F758
F300 3335

3B51
I317
FB00
FA09 3336 I445 F765

3349

3438
F301
I318 3437 I443
2432
5303

F207
FA02

I305
F717
2226 2225
3230 3228

I303
F206
I320
FA03 FB01 I316
F718
3354

3359

FB04
2307

2304 3353 2308

F205 2305 3356 2310
3357

3358
2302
7301

4310 5301 5302

3355
I220

6301
3265
7217

5310

F204 F719
F235

FB07
3264

F242
3915

3269

I221
F908
2213 7218

7901
F907 F203 I222
IB72
6901
3916

FE16 F904
FE12
7900
3E25
F911
3270 F247 FE11
FC14
IC22 IC14 IC11 FC10
7E01

I916 FC12 FC11 FC15

2293

F202
3E27 IC09
3E21

3E19

2E14

F909 FE09 IC10 IB10

FB06
3904
3905

7903 FB09
FC13 IC13
7907

7902
3923

I905

FB02
IC21 FC06 IC18

7E00
IC01 FC08
F743

IC17
3919

A225 FE08
3E22

3E20

2E15

F905
3903

F906

IC15
IC03 IB13
3921
4903

IB70
IC02 IB12
F201
FE10 IB71
IE00 3E23
2901 3901 I915
IC16 FC05 FC04 FC07
F912
4902 FE05 FE01 FE03

IB66 FE15 3924 3902

3920 FE07
FE02 FE04
F903 F901
IB67
3E26 4E04 2E16
2900
FE06 F902
3900
7905

3E24
3908
3907

6E06
I902

F900
F913
4901

FE14 F744
FF00 FF01 FF02 FF03

6900
3913

3914

4900
6903

4E03 F914 3912 IB74

5900

FF04
FE13 4E02 FC09
F915 2902

2 2011-01-31

SSB Layout Bottom

3139 123 6505

19130_041_110428.eps
110428

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 85

10.12 B01 313912365231

10-12-1 DC-DC

DC-DC
B01A 12V/3V3 CONVERSION +3V3STBY

B01A

2146
2136

2u2
1n0
7122
RT8283AHGSP
5117 I105 3149 2170
2 1
VIN BOOT 3129 STANDBY
33R 3100 1R0 100n 5121 F133
7 3

10u 16V
EN_1 EN SW +3V3_SW 68R

2163

2100
RES
2154

10u

10u
2158 100K I137 I117 10u

2169

2199

2180
100u 6.3V

2137
RES
8 5

4K7 1%

RES
10u

10u

1n0
1n0
SS FB

3140

2101
2152

RES
2162

22u

22u
22n
10 6
VIA COMP

2179

100n
GND 1M95
GND HS I136 F113
1 +12VS
SS1_GND

2160

3138
4

RES
F114

10R
2

3n3

2148

100n
2147

100n

2145
1K5 1%
3 F115

100K 5%

1n0
3146

3107
4 F116 F102
SS1_GND +12VDISP
F118 F103

I106

I118
5
6 F119
7 F121

3135

2150

470p
RES
F122

12K
8
SS1_GND SS1_GND 9 F105
SS1_GND
10 F106
11 F107 +24VAUDIO
12 F109

2149

100n
2143

100n

2144
13

1n0
12V/5V CONVERSION 7123
SS1_GND
F135
+5V5_TUN
14 F104

RT8283AHGSP 1-2041145-4

+12VS 5120 I123 3150 2123 GND-AUDIO GND-AUDIO

+12VS 2 1 GND-AUDIO
VIN BOOT
33R 3101 1R0 100n I138 5104 6122 F132
EN_1 7 3
10u 16V

EN SW +5V_SW GND-AUDIO
2102

2171

2153
RES
2168

10u
10u
10u

10u

100K I120 SS36

2141
RES
2157 22n 8 5

100u 6.3V

1n0
27K 1%
SS FB

470R

470R

470R
3115
2161

3153

3154

RES 3155
2164

2159
2155
22u

22u

10u
I122
10 6
VIA COMP

100n
GND
GND HS
3126

2185
SS2_GND

RES
LAMP-ON

3136
4

10R
3n3
2177
68R

2127

100p

2134

100p
I140
I107

I119
SS2_GND

3122

RES
2186

470p
10K
SS2_GND 3127
BACKLIGHT-PWM

5K1 1%
100K 1%

3125
3105
68R

2128

100p

2133

100p
SS2_GND
SS2_GND SS2_GND RES
3128 BACKLIGHT-BOOST

12V/1V8 CONVERSION 68R

2131

100p

2132

100p
7124
RT8283AHGSP
5115 I104 3151 2187
2 1
VIN BOOT
POWER-OK
33R 3102 1R0 100n I131 5123 F125
7 3
10u 16V

EN_1 EN SW +1V8_SW
2172

2189
2188

10u

10u

100K 3u6

2198
100u 6.3V
8 5

15K 1%
2190 22n

10n
BZX384-C6V8

SS FB

3112

2191

2138

2183

RES 2104

RES 2105
22u

22u

22u

22u
I132 I127
100n
6102

10 6
VIA COMP
GND RES
GND HS
2178

2112

SS3_GND

3108
4

RES

10R
4n7

3116
3130

SS3_GND I141
I135

I134
1K0

SENSE_1V8
15K

68K 1%

12K 1%
3114

3113

3118
2192
RES

470p
I139

12K

EN_1 SS3_GND

RES
3131

4K7

SS3_GND
SS3_GND SS3_GND
3V3/1V2 CONVERSION
7119
LD1117DT
5124 I144 I143 5125 F131
3 2
+3V3_SW IN OUT +1V25_SW
12V/1V0 CONVERSION 33R 33R

22u 6.3V
COM

2139

100n

2140

2197

2166

2193

2122
2165

RES
10n

22u

22u

10n
22u
7125
RT8283AHGSP

1
5105 I108 3152 2124
2 1
VIN BOOT
33R 3103 1R0 100n I110 5106 F101
7 3
10u 16V

EN SW +1V1_SW
2175

2181
2176

10u

10u

2195 100K I109 3u6

12K 1%

100u 6.3V
8 5
SS FB
3106

2151

2106
2129

2130
22u

22u

22u

22n I111
10 6
VIA COMP
GND
GND HS
5V/2V5 CONVERSION
2167

SS4_GND
3111
4

RES

10R
4n7

7120
LD1117DT25
3117 5127 I125 I126 5128 F136
I142 3 2
I112

I113

SENSE+1V1_MT5363 +5V_SW IN OUT +2V5_SW

47K 33R 33R

22u 6.3V
COM

47u 16V
3145

2108

100n

2109

2110

100n

2111

100n
2113

470p

2107
RES
3K6

470K 5%
27K 1%

SS4_GND
3109

3148

1
SS4_GND SS4_GND SS4_GND DGND DGND DGND DGND DGND DGND

ROUND 4.02mm SCREW HOLE ROUND 4.50mm SCREW HOLE SLOT SCREW HOLE
1X01
1X02 1X03 1X05 1X04 REF EMC HOLE
REF EMC HOLE REF EMC HOLE REF EMC HOLE EMC HOLE
1

1 2011-04-18

PCB SB SSB
3139 123 6523
BERLINALE BRZ DIG

19131_001_110615.eps
110615

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 86

10.13 B02 313912365231

10-13-1 Tuner

Tuner
B02A B02A

7216
LD29150DT50R
I255 5225 F236
+5V5_TUN 1 3 +5VTUN_DIGITAL
IN OUT
0R
COM

RES

RES
4209

4210

100n
2277

2278

2280

2279

2281

2282
RES

RES
RES

RES
22u

1u0

10n

10u

22u
2
F242 AGND AGND AGND AGND AGND
RF_AGC_SW

10R

3272-2 RES 10R

3272-3 RES 10R

10R

10R

10R

10R

10R
+5VS

5
8

8
RES
3264

RES
10K

3272-1

3272-4

3271-1

3271-2

3271-3

3271-4
I221

4
3269 I222
3

3265 I220 1K0

1 7217
BC847BW
1K0 AGND
2
I254 5222 F235
+5V_SW +5VS
10u
F213 AGND 3270 F247
RF_AGC_EX RF_AGC
2

2283

2284
22u

10n
1201 10K
VA1E1BF2403
AGND
15

16

2293

2213
RES
47n

22u
MT

2295
1 F201 AGND 7218
ANT_PWR
2 F202 KTK5132E
NC1 100p AGND AGND
3 F203 1 3
RF_AGC
4 F204
NC2 AGND AGND
TUNER

5 F205 AGND 3230

AS FE_SCL
6 F206
SCL
7 F207
SDA 10R

2226
8 F208 RES 5207 30R

15p
+B +5VTUN_DIGITAL
9 F209 5208 4u7 +5VTUN_DIGITAL
IF_AGC
10 A212 2258 100n
IF_OUT+ 2285

2286

180p
11 A213
IF_OUT-
12 A214 3228
IF_OUT_ANALOG AGND AGND 27p
2296

2294
RES

FE_SDA
22u

47u

5226 5227
MT

DIF_N 3262 2287

14

13

VIP_ATV
10R

2225

15p
75R 220n 220n 10n
RES
2297

1n0

AGND

5228

330n

2288

33p
A225 AGND 3261 F246
IF_AGC
AGND
10K
2262

100p

2263
RES

47n
AGND DIF_P 3263 5229 5230 2289
VIN_ATV
75R 220n 220n 10n
2290

2291

180p
AGND AGND
DIF_N
27p
DIF_P
Near Tuner Near MTK5363

1 2011-04-18

PCB SB SSB
3139 123 6523
BERLINALE BRZ DIG

19131_002_110615.eps
110615

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 87

10-13-2 Digital demodulator

Digital demodulator
B02B +2V5_SW +1V25_SW
B02B
5307 I300 I301 5302

30R 30R

2320

2321

100n

2322

2306

100n
2307

100n
2308

100n
2309

100n

2310
1u0

10n

1u0
+3V3_SW

5306 AGND AGND AGND I302 I303 DGND DGND DGND DGND DGND 5301

30R 30R

2318

2323

100n

2301

100n
2302

100n
2303

100n
2304

100n

2305
1u0

1u0
+1V25_SW

5304 AGND AGND I304 I305 DGND DGND DGND DGND DGND 5303

30R 30R

2314

2324

100n

2311

100n
2312

100n

2313
1u0

1u0
+2V5_SW

DGND DGND I306 DGND DGND DGND 5305

30R
1301 FOR DEVELOPMENT USE

2317

100n

2316
1 3

1u0
DEB DEB DEB
7301 6301
25.4M 3355
2333

2334

3
18p

18p

BC847BW
4
2

DEB +3V3_SW
3356 SML-310 1K0
7302 1
DGND DGND

32

22

20

16
36
56
63

13
35
49
64

34
48

43
TC90517FG
1K0

AD_DVDD

AD_AVDD

PLLVDD

DR2VDD
2
Φ

DR1VDD
AGND AGND I307 VDDC VDDS
19 21 2335 1n5
I FIL
AGND
I308 X I320
18 58 3354 33R TSO_VALID
O PBVAL DGND
3 53
0 RERR
DIF_P 2 XSEL
1
DGND 54
RLOCK
5308

2341

100n
RES

RES

2339 1u0 30
1n2

P
2340 1u0 29 ADI_AI 55 3353 33R
N RSEORF
DIF_N
2377 100n 28 59 3357 33R TSO_SYNC
P SBYTE
2378 100n 27 ADQ_AI
N
3331

3332

52
2K7

2K7

AGND SLOCK
2336 100n 24
P TSO_CLK
2337 100n 25 AD_VREF 61 3358 33R
N SRCK
AGND TSO_DATA0
2338 100n 26 60 3359 33R
AD_VREF SRDT
AGND
AGND AGND
39 38
DTCLK STSFLG1
DGND
40 9 I325 3339 20K IF_AGC
+3V3_SW DTMB AGCCNTI
8 10
S_INFO AGCCNTR
3349 10K 1 51
DGND 0 STSFLG0

2332

100n
41 TSMD
1
42
SYRSTN
3337 10K 7 5309
AGCI
6
0
I316 11 SLADRS 5 33R
CKI 1 AGND
4306
AD_DVSS
AD_AVSS

TUNER_SCL F300 3351 100R I317 45 12

SCL SCL
PLLVSS

TUNER_SDA F301 3352 100R I318 46 TN 14 +3V3_SW

SDA SDA
VSS 4307
4312
23

31

17

4
15

47
33
37
44

50
57
62
2379

2380

3350
RES

RES

RES

4K7
39p

39p

4308 4309 4313

AGND AGND F306

RESET_DEMOD 4314
4310 4311
DGND DGND DGND DGND
AGND

3360

4K7
5310 5311

I338
33R 33R
DGND
3335

3336
10K

10K
DGND

AGND DGND

+3V3_SW
3344

3343
2K7

2K7

F302 FE_SCL
F303 FE_SDA

1 2011-04-18

PCB SB SSB
3139 123 6523
BERLINALE BRZ DIG

19131_003_110615.eps
110615

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 88

10.14 B03 313912365231

10-14-1 Class-D & muting

Class-D & muting +24VAUDIO

B03 B03

220R

220R
5400

5401
3400 F400
+24VAUDIO
I411 I412 LEFT_SPEAKER
4R7 GND-AUDIO

1K0

1K0
220u 35V

220u 35V

22K

22K

22K

22K
2401

2400

220n

2403

2402

220n
10u 35V

V_NOM
2405

2404

220n

1402

2419

10n
5

2413

220n
2414

220n
1735 1D38

3452

3451
F404 1 1 LEFT +
F405 2 2

1
GND-AUDIO GND-AUDIO GND SND
3 3

1K0

1K0
RIGHT -

3405-4

3405-3

3405-2

3405-1
F406 4
GND-AUDIO
2041145-3

2420

2421
2041145-4

10n

10n
F401 2406 7400-1
I401

19
20

10
12
AOUTR TPA3123D2PWP

1
3

3454

3453
47n AVCC L R
PVCC I413 2411
6 Φ BSR
16
I415 5402
I417
2415
RIGHT_SPEAKER
RIGHT_SPEAKER
R CLASS-D 15
220n

V_NOM
F402 2407 I403 IN R 22u 35V 220u
AUDIO AMP

1403
AOUTL 5
L OUT
22 5403 2416
47n L I416
18 I418 LEFT_SPEAKER
0 I414 2412
17 GAIN 21 35V 220u
1 BSL 22u
220n
2408 1u0 I405 11
GND-AUDIO VCLAMP
2409 1u0 I406 7
BYPASS
4
MUTE
2
F411 SD
MUTE I434

22K

22K

22K

22K
PGND 3422-4 F410 3422-3
F412 AGND L R

2433
A_STBY GND_HS

1u0
100K 100K

8
8
9

23
24

13
14

25
3422-2

2417

220n
2418

220n
DC_PROT
3
GND-AUDIO 100K
40
39
38

7400-2

1
TPA3123D2PWP 3422-1 2426 10u 1 7408

3406-4

3406-3

3406-2

3406-1
BC847BW
VIA GND-AUDIO 100K
26 37 2

2427
27 36

1u0
28 VIA
VIA VIA 35
GND-AUDIO

29 34
GND-AUDIO GND-AUDIO GND-AUDIO
VIA
GND-AUDIO GND-AUDIO
+12VS
DC-DETECTION
30
31
32
33

GND-AUDIO

3418

1K0
F415
+12VS I424
F408 3412 F416
+5V_SW RES RESERVED

2430

3430
RES

RES
I440

47K
4n7
1 6 1K0 3431
7402-1

I435
BC857BS(COL) 7403 47K
BC847BW 3 2
2 RES
BAS316

F409 7411 RES

RES
6400

I425 I433 4401 1 1 I436 RES

3411 3413 BC857BW 3432

RES
3433

10K
7412
3 2SD2653K
470u 16V

4K7 1K8 2 1K0

3410

2422
4K7

RES

RES
2424

3420
4 7402-2

47K
4n7
I423 HP_LOUT
3409 3426
I422

BC857BS(COL)
I430

5 6402 HP_ROUT
56K 47K
BAT54C 2

I442
3 I429 3
3408

2431

3434
RES
1

RES
RES

47K

47K
4n7
3428 I431
3419

1
10K

7406
7404 3 2SD2653K
6401 BC857BW 1K0
F413 2
+3V3STBY AOUTL
BAS316 RES 3435 I437 RES
100K
3416
RES

7413
AOUTR
100K

RES 2SD2653K
3414
RES

7405
3415 BSS84 1K0
I441

1R0
2 3
2425

3421
RES

47K
4n7

F414 1
SW_MUTE 3
3427 I432
2423

100n
3417

+3V3STBY 1
10K

7407
2SD2653K
1K0
2
RESET_AUDIO I445 3437 I443
3439

10K

F417 3K0
2

A_STBY
3438

2432

3
22K

1u0

1 7414
BC847BW
3 2
6403
BAT54C

1 2011-04-18

PCB SB SSB
1

3139 123 6523

BERINALE BRZ DIG

19131_004_110615.eps
110615

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 89

10.15 B04 313912365231

10-15-1 MT5363 Power
+3V3_SW
MT5363 Power
B04A B04A

5506

30R
7700-8
MT5363BIMG
F503
F502 5500
H23 POWER-MAIN C8
+1V25_SW
H31 D9
30R J30 E8

100n

100n

100n

100n

100n

100n
100n

100n
V31 F9
VCCIO33

100n

100n

100n

100n

100n
100n

100n

100n

100n

100n

100n
+3V3_SW W32 G8

2514

4u7
DVSS

2567
W34 G10

4u7

2515

2516

2517

2520

2521

2522
2518

2519
W36 J4

2552

2553

2558

2559

2560

2561

2562

2563

2564

2565

2566
J6
AF13 L4
5501

AF15 VCCIO33-1 L6
30R

DVSS
N14
B1 P15
F500 3500 4u7
B13 R14
+1V8_SW
C2 R18
1R0 2598 VCC2IO
7700-7 C12 T15
DVSS
100n

2573 100n

100n

100n

100n

100n
MT5363BIMG D3 T17
2571 1u0

I504
2588

D13 T19
4u7

SENSE_1V8
POWER-MISC E4 U16
2568

2577

2576

2575

2574
E12 U18
VCC2IO

100n

100n

100n

100n

100n

100n
AM23 E14 V15

4u7
AVDD10_LDO DVSS

2507
F5 V17

22u
AVDD12 AVSS12 F13 V19

2500

2501

2502

2503

2504

2505

2506
AH33 P17 G6 W4
ADCPLL LVDS
AG30 T13 G14 W6
APLL MEMPLL VCC2IO
100n

100n

100n
100n

AP11 AH29 H7 W14

HDMI PLL_1 DVSS
N16 AH31 J14 W16
LVDS PLL_2
P13 AN26 R2 W18
2581

2580
2582
2584

MEMPLL RGB
AM25 AM9 R4 Y3
RGB USB
AG32 P19 R6 Y17
SYSPLL VPLL VCC2IO
AF29 AC6 Y19
TVDPLL DVSS
AL10 AD5 AA16
USB
N18 AD7 AA18
VPLL

100n

100n

100n

100n

100n
AE2 AB13
AVDD33 AVSS33 AE4 AB15
VCC2IO
Y31 Y33 AF1 AB17

2508

2509

2510

2512

2513
AADC AADC DVSS
5502 30R I505 AF33 AE34 AF3 AB19
ADAC0 ADAC0
5503 30R I506 T31 U30 AC14
ADAC1 ADAC1
AN32 AR32 R16 AC16
CVBS CVBS
AG34 AG36 U14 AC18
DEMOD1 DEMOD1
2569 100n

2570 100n

AK31 AJ30 V13 AD13

5504 30R DIG DIG DVSS
2597

2599

AM13 AN12 Y13 AE8

1u0

1u0

+3V3STBY 2592 1u0 HDMI HDMI

F15 J18 Y15 AF9
I502

LVDS_1 LVDS VCCK

2593 100n H15 Y29 AA14 B21
LVDS_2 REF_AADC
W30 AK29 AD15 D21
5505 30R REF_AADC SIF
AL30 AP9 AD17 E22
+3V3STBY SIF USB_1 DVSS
2595 10u AM11 AT9 AD19 G22
USB USB_2
2596 100n AN30 AT11 AE14 N20
VDAC USB_3 VCCK
AN24 AR30 AE16 P21
I507 VGA_STB VDAC
AK35 AL24 AE18 P23
XTAL_STB VGA_STB
AK37 AG12 P25
XTAL DVSS
AH7 R20
AJ6 R22
VCCK
2579

AJ8 R24
4u7

AK5 T21
AK7 T23
DVSS
AL2 U20
AL4 U22
SENSE+1V1_MT5363 VCCK
AL6 U24
F501 AL8 V21
+1V1_SW AM1 V23
DVSS
AM3 W20
100n

100n
100n

100n
100n
100n

100n

100n

100n
100n
100n

100n

100n

100n
100n

100n
100n

100n
100n

100n

100n

100n

100n
AM5 W22
100u 6.3V

4u7

VCCK
2551

AM7 Y21
AN2 Y23
2550

2549

2545
2544

2543
2542
2541

2540

2538

2537
2536
2535

2527
2534
2533
2532

2531

2529

2528
2530

2526

2524
2525

2523
AN4 AA20
DVSS
N22 AA22
N24 AB21
VCCK
T25 AB23
V25 AC20
W24 AC22
DVSS
Y25 AC24
AA24 AD21
VCCK
AB25 AD23
AE20 AD25
AE22 AE24

1 2011-04-18

PCB SB SSB 1 2011-01-13

3139 123 6523

BERLINALE BRZ DIG

19131_005_110615.eps
110615

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 90

10-15-2 DDR

DDR
B04B B04B
+1V8_SW
+1V8_SW
3622 F602

1K0 1% 7700-3
MT5363BIMG

100n

100n

100n

100n

100n

100n

100n

100n

47u 16V
1K0 1%
2630

100n
3623

2608
DRAM 0
D7 RDQ(0)
H11 RDQ(1)

2600

2601

2602

2603

2604

2605

2606

2607
1
E6 RDQ(2)
2
G12 RDQ(3)
3
H13 RDQ(4)
4
N8 D5 RDQ(5)
1 5
P7 RVREF F11 RDQ(6)
2 6
F7 RDQ(7) 7600

M9

G1
G3
G7
G9
7

R1

C1
C3
C7
C9
A1
E1

A9

E9
J9

J1
RA(0) N4 B5 RDQ(8) H5PS5162FFR-G7C
0 8

VDDL
RA(1) H5 D11 RDQ(9)
1 9 VDD VDDQ
RA(2) M3 A4 RDQ(10) RODT 3605-2 56R K9
2 10 ODT
RA(3)
RA(4)
G4
M5
3 11
B11
A12
RDQ(11)
RDQ(12)
RCKE
RWE#
3603-2
3603-1
56R
56R
K2
K3
CKE Φ A2
E2 3604-1
4 12 WE
RA(5) F1 C4 RDQ(13) RCS# 3605-4 56R L8 SDRAM L1 RBA(2)
5 13 CS
RA(6) M7 A10 RDQ(14) RRAS# 3605-3 56R K7 NC R3
6 14 RAS 56R
RA(7) F3 RA A6 RDQ(15) RCAS# 3600-1 56R L7 R7
7 RDQ 15 CAS 3600-3
RA(8) P1 AB1 RDQ(16) R8 RA(13)
8 16
RA(9) D1 U4 RDQ(17) RBA(0) 3603-4 56R L2
9 17 0 56R
RA(10) G2 AC4 RDQ(18) RBA(1) 3603-3 56R L3 BA G8 RDQ(0)
10 18 1 0
RA(11) N2 T1 RDQ(19) G2 RDQ(1)
11 19 1
RA(12) E2 T3 RDQ(20) RA(0) 3600-2 56R M8 H7 RDQ(2)
12 20 0 2
RA(13) M1 AC2 RDQ(21) RA(1) 3604-2 56R M3 H3 RDQ(3)
13 21 1 3
U2 RDQ(22) RA(2) 3602-4 56R M7 H1 RDQ(4)
22 2 4
RBA(0) H3 AB3 RDQ(23) RA(3) 3604-4 56R N2 H9 RDQ(5)
0 23 3 5
RBA(1) J2 Y5 RDQ(24) RA(4) 3602-2 56R N8 F1 RDQ(6)
1 RBA 24 4 6
RBA(2) H1 T7 RDQ(25) RA(5) 3601-4 56R N3 F9 RDQ(7)
2 25 5 7
AA6 RDQ(26) RA(6) 3602-3 56R N7 DQ C8 RDQ(8)
26 6 A 8
RCLK0 B3 V7 RDQ(27) RA(7) 3601-3 56R P2 C2 RDQ(9)
27 7 9
RCLK0# A2 RCLK0 V5 RDQ(28) RA(8) 3600-4 56R P8 D7 RDQ(10)
28 8 10
RCLK1 AD1 AA4 RDQ(29) RA(9) 3601-1 56R P3 D3 RDQ(11)
29 9 11
RCLK1# AD3 RCLK1 T5 RDQ(30) RA(10) 3604-3 56R M2 D1 RDQ(12)
30 10 12
RCKE K1 Y7 RDQ(31) RA(11) 3602-1 56R P7 D9 RDQ(13)
RCKE 31 11 13
RA(12) 3601-2 56R R2 B1 RDQ(14)
12 14
AB5 E10 RDQM(0) 3605-1 56R B9 RDQ(15)
REXTDN 0 3612 15
RODT N6 C10 RDQM(1) RCLK0 J8
RODT 1
RCS# P3 RDQM V1 RDQM(2) 22R 1% K8 CK B3 RDQM(1)
RCS 2 UDM
RWE# K3 U6 RDQM(3) F3 RDQM(0)
RWE 3 LDM

100R
3614
RCAS# L2 F7
RCAS F600 3615
RRAS# P5 B9 RDQS(0) E8 LDQS J2 +1V8_SW
RRAS VREF
RDQS0 A8 RDQS(0)# 1K0 1%
3613
B7 RDQS(1) RCLK0# B7

1K0 1%
3616

2609
100R
3624

VSSDL

100n
RDQS1 C6 RDQS(1)# 22R 1% A8 UDQS
V3 RDQS(2)
VSS VSSQ
RDQS2 W2 RDQS(2)#

A3
E3
J3
N1
P9

J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
Y1 RDQS(3) RDQS(0)
RDQS3 AA2 RDQS(3)# RDQS(0)#
RDQS(1)
RDQS(1)#

+1V8_SW

100n

100n

100n

100n

100n

100n

100n

100n

47u 16V
2628
2620

2621

2622

2623

2624

2625

2626

2627
7601

M9

G1
G3
G7
G9
R1

C1
C3
C7
C9
A1
E1

A9

E9
J9

J1
H5PS5162FFR-G7C

VDDL
VDD VDDQ
RODT 3611-3 56R K9
ODT
RCKE
RWE#
3610-3
3610-4
56R
56R
K2
K3
CKE Φ A2
E2
WE 3609-4
RCS# 3611-1 56R L8 SDRAM L1 RBA(2)
CS
RRAS# 3611-2 56R K7 NC R3
RAS 56R
RCAS# 3606-1 56R L7 R7
CAS 3606-3
R8 RA(13)
RBA(0) 3610-1 56R L2
0 56R
RBA(1) 3610-2 56R L3 BA G8 RDQ(16)
1 0
G2 RDQ(17)
1
RA(0) 3606-2 56R M8 H7 RDQ(18)
0 2
RA(1) 3609-3 56R M3 H3 RDQ(19)
1 3
RA(2) 3608-1 56R M7 H1 RDQ(20)
2 4
RA(3) 3609-1 56R N2 H9 RDQ(21)
3 5
RA(4) 3608-3 56R N8 F1 RDQ(22)
4 6
RA(5) 3607-1 56R N3 F9 RDQ(23)
5 7
RA(6) 3608-2 56R N7 DQ C8 RDQ(24)
6 A 8
RA(7) 3607-2 56R P2 C2 RDQ(25)
7 9
RA(8) 3606-4 56R P8 D7 RDQ(26)
8 10
RA(9) 3607-4 56R P3 D3 RDQ(27)
9 11
RA(10) 3609-2 56R M2 D1 RDQ(28)
10 12
RA(11) 3608-4 56R P7 D9 RDQ(29)
11 13
RA(12) 3607-3 56R R2 B1 RDQ(30)
12 14
3611-4 56R B9 RDQ(31)
3617 15
RCLK1 J8
K8 CK B3 RDQM(3)
22R 1% UDM
F3 RDQM(2)
LDM
100R
3619

F7
F601 3620
E8 LDQS J2 +1V8_SW
VREF
3618 1K0 1%
RCLK1# B7

1K0 1%
3621

2629

100n
VSSDL

A8 UDQS
22R 1%
RDQS(2) VSS VSSQ
A3
E3
J3
N1
P9

J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
RDQS(2)#
RDQS(3)
RDQS(3)#

1 2011-04-18

PCB SB SSB
3139 123 6523
BERLINALE BRZ DIG

19131_006_110615.eps
110615

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 91

10-15-3 Controller

Controller
B04C B04C
7700-6
+3V3_SW +3V3_SW MT5363BIMG

F37 H33 TSO_SYNC

MOSTRT MISTRT

37A9
G36 G34

RES
TSO_VALID
3700

3701

10K
10K

10K
MOVAL MIVAL
7700-4 RES H37 CI CI H35 TSO_DATA0
MT5363BIMG 3726 MDO0 MDI0
F33 F35 TSO_CLK
4K7 MCLKO MCLKI
USB_PWR_EN 3704 100R I700 K35 GPIO J26
3705 I701
0 23 +3V3_SW
USB_OCP 100R K37 F25
1 24 D37 C36
J32 H25
2 25 +3V3_SW ETMDIO ETCRS

2729
RES
A30 B25

10p
RESET_DEMOD
3 26 F737 E36 G32

5700
C30 D25 4700 RES

30R
4 27 BYPASS_MODE ETMDC ETCOL

10K
10K
RF_AGC_SW G30 C24 LCD-PWR-ONn
5 28 F31
ARC_SW E30 G24
6 29 ETPHYCLK

3713
R|L H29 E24

10K
F704 2702 100n
7 30 D33 B33
U|D F29 J24
8 31 3709 F760 3711 CLK CLK
SELLVDS B29 B23 LAMP-ON I741
9 32 3712

3715
3714
+3V3_SW F705 D31 D35
FRAME F767 D29 F23 100R 7702 4K7
10 33 +3V3_SW
EN ER
F768 C28 D23 M24C64-WDW6

8
+3V3_SW 11 GPIO GPIO 34 F706 33R
E34 B37

3710
E28 A22

4K7
7703
12 35 Φ ER DV
J28 C22 BC847BW
13 36 (8Kx8) B31 ETTX ETRX C34

3703

3786
G28 AF5 7

10K

10K
+3V3_SW 14 37 F707 WC D3 D3
37AA

H27 AG2 E32 A34

4K7

15 38 EEPROM D2 D2
F708 I708 C32 B35
3707

F27 AE6 SCL-MAIN 6 1

4K7

F759 3716 22R D1 D1

16 39 SCL 0 A32 A36
B27 AF7 VCOM_SW 2
+3V3_SW 17 40 ADR 1 D0 D0
D27
18 41
AG4 F738 3796 100R POWER-OK SDA-MAIN F736 3717 22R 5
SDA 2
3 MAC-CI
3706

F769 G26 AG6 F739 DC_PROT

4K7

F702
19 42

4
F770 E26 AH3 F740
20 43 F761

2703

2704
A26 AH1 SYS_EEPROM_WE

10p

10p
F701
21 44
C26
22

RES 2705

10n
100n
RES

RES 2701
PANEL

100n

+3V3_SW
RES

2700

SDM

+3V3_SW FOR DEBUGGING

+3V3_SW +3V3_SW +3V3_SW ONLY

10K
10K
10K
10K
10K
+3V3_SW

4K7
4K7

10K
I731

DEB
3762

1K0
7708

DEB 3763-1
DEB 3763-2
DEB 3763-3
DEB 3763-4
DEB 3780
12

37
3740
H27U1G8F2B

3776

3777

3778
10K

RES
5705
+3V3_SW 1702
VCC
220R 1
BACKLIGHT-BOOST 3741
NAND_PDD(0) 29 1 2
I711 0

2713

100n
2712

100n
NAND_PDD(1) 30 2 JTRST F745 3
1K0 1
NAND_PDD(2) 31 3 JTDI F746 4
2
2706

NAND_PDD(3) 32 4 JTMS F747 5

1u0

1700 3 IO
NAND_PDD(4) 41 5 JTCK F748 6
4
NAND_PDD(5) 42 10 F749 7
54M 5 F751 DEB 3765
2716

2717

NAND_PDD(6) 43 11 JTDO F750

10p

10p

8
3739 I713
6
BOOST_CONTROL NAND_PDD(7) 44 14 9
7 33R
15 10
1R0
3782
RES

NAND_PCLE I742 16 20
10K

11
CLE
NAND_PALE I743 17 21 F763 13 12
ALE
NAND_POCE I727 9 22
CE_

3760

3759
DEB

DEB
NAND_POOE 8 23 502382-1170

10K

10K
RE
NAND_POWE 18 24 DEB
WE NC
19 25
WP
6 26
SE
NAND_PARB I726 7 27
R
28
+3V3STBY B
33

I732
4K7
4K7
7700-1
MT5363BIMG 34
35
CONTROL

3779
RES
AJ36 AR2 NAND_PDD(0) 38

4K7
XTALI 0
AP5 NAND_PDD(1) 39
BAS316

RES 3774
RES 3775
2710

2709

6706

3768

AJ34 AR6 NAND_PDD(2) 40

1K0
4u7

4u7

XTALO 2
7701 AU6 NAND_PDD(3) 45
BD45292G 3
T37 PDD AP7 NAND_PDD(4) 46
5

VCXO 4
VDD AT7 NAND_PDD(5) 47
5
AR8 NAND_PDD(6) 48
I725 1 Φ F721 6
4 ORESET AL22 AU8 NAND_PDD(7)
ER VOUT ORESET 7
I759 L30
BAS316

FSRC_WR VSS
100K
6707

3769

2711

100n
RES

I756 K5 AT1
MEMTN 0
37A5

13

36
SUB GND I757 K7 POCE AN6 NAND_POCE
4K7

MEMTP 1
2

M19
+3V3_SW TP_VPLL
AT5 NAND_PARB
PARB +3V3STBY
JTCK AK3 AR4 NAND_PALE
JTCK PAALE
4K7
4K7

RES 4K7
4K7

JTDO AH5 AU4 NAND_PCLE

JTDO PACLE
JTRST AK1 AT3 NAND_POWE
JTRST POWE
RES

3746

3747
AJ2 AU2 NAND_POOE

4K7

4K7
JTDI
JTDI POOE
JTMS AJ4
JTMS
3761 AT21 I744 3727 100R
3718
3719

3720
3721

RX 1701
10K U0 AP21 I745 3728 100R 3748 33R F717 2
TX
AP3 R36 3
SCL-MAIN 0 RX
F741 R34 U1 T35 3749 33R F718 1
SCL-DISP 1 OSCL TX
P31 MSJ-035-29D PPO
2

F719
J34 UART (SERVICE)
0 +3V3_SW
AP1 J36 I760 3783 4K7

BZX384-C6V8

BZX384-C6V8
SDA-MAIN 0 OPWM 1
F742 R32 T33
SDA-DISP 1 OSDA 2

6700

6701

1705

1706
P33
2 +3V3_SW
3722 10K AN22 I749
OIRI

3736
3758 10K 3723 10K

4K7
AL32 AM21 RES FOR ITV +3V3STBY
I746 3734 100R
0 0
LED-1 3788 100R I754 AK33 AM19 4707 RES +3V3STBY +3V3STBY
1 1 +3V3_SW +3V3_SW

100K
3790
KEYBOARD 3787 100R I753 AM35 AN20

RES
4708 RES
RESET_AUDIO
2 OPCTRL 2
3702

AL34 ADIN_SRV AR20 I734 3738 100R

4K7

3 3 BACKLIGHT_CONTROL
3729

AM37 AU20 I739

I714
LED-2 3735 100R I733 3744 100R
10K

4 4 3791
3737 100R I747 AL36 7710 LIGHT-SENSOR
10K
10K
10K

LIGHT-SENSOR
5 BC847BW STANDBY
AL20 I750 3751 100R
OPWRSB 100R

2722
3753

3754

3724

1R0
4K7

4K7

1n0
3730 I755 I761 +3V3_SW
USB_DP AU10 AN14 PWM DIMMING
DP CEC
USB_DM AR10 AN18
3733
RES 37A6
RES 37A7

DM USB SDA1 10K

3731 AN10 AM17
VRT HDMI SCL1 3792

680R
3742
I735 AL14 RC RC
+3V3STBY SDA2
RES 10K AL12 7705
SCL2 100R

2723
POWER_DOWN BC847BW

1n0
37AB
RES

AL16 SDA-LCD 1M20

10K

I716 3745
PWR5V AM15 SCL-LCD F753 1
5K1 1%
3757

3789

SW_MUTE F771 2
RES

10K

4K7
N36 MUTE F754 3
CLK 3793

3743
N34 F755 4

1K0
LED-2

RES
TUNER DATA F766
AP37 CEC I715 +3V3STBY F756 5
BYPASS F716 3781 100R F757

2724
6

1n0
+3V3STBY BACKLIGHT-PWM
AM31 F758 7
BYPASS0 100R
AH37 +5V_SW 5706 F765 8
ADCINP RES
DEMOD AH35 30R
ADCINN 3794
LED-1 2041145-8
+3V3STBY

2727

100n

2728

100n
M31
IF RES 100R

2725
AGC M33 TUNER_SCL

RES

1n0
RF F725 3764 3798
TUNER_SDA POWER_DOWN
TRAP0 AOLRCK AOBCK ASPDIF +3V3STBY
1K0 6K8
6 3767
BZX384-C3V3

15K 3795
ICE mode + Serial Boot 0 0 0 VIP_ATV 7709-2 KEYBOARD
I737
ICE mode +ROM mode
RES

0 0 1
6708

VIN_ATV 2 3 BC847BS(COL)
10R

2726

100n
3784 10K IF_AGC
6709
I738 3770 F724
3785 10K RF_AGC 1 5
7709-1 +12VS
BC847BS(COL) 1K0 BZX384-C8V2
4
37A8

2721

3771
2719

2720

220n
2K2

47n

47n

1K0
TRAP1 OPCTRL3(0)
3756

4K7

PDWNC Normal 0
+5V_SW

TRAP2 AOSDATA0 OPWM1

XTAL 54 MHz 1 0 1 2011-04-18

PCB SB SSB
3139 123 6523
BERLINALE BRZ DIG

19131_007_110615.eps
110615

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 92

10-15-4 LVDS Display

LVDS Display
B04D B04D
RES RES 3811 10K
3812 +3V3_SW
R|L
RES 3813 10K
100R

RES RES 3814 10K

3815 +3V3_SW
U|D
PCA5940 PCA9515 - (RES) RES 3816 10K
100R
+3V3_SW
4810 Y - RES RES 3817 10K +3V3_SW
SELLVDS 3818
4814 Y -
3819 10K
4816 Y - SDA-DISP 100R
4817 Y - RES 4812 RES

4811
RES 3820 10K

RES
4810
3821 +3V3_SW
SCL-DISP
4818 - FRAME
Y RES 3822 10K
- 2802 100R
4819 Y
4820 - Y 100n LVDS#1

RES 4823
RES 4815
7801
4812 - Y PCA9540B 3 1G51
RES 4813 F801
VDD SC0 5 60 61
4815 - Y 58 59
4813 - Y SC1 8 4814 SCL-VCOM 56 57
54 55
4821 - Y 4817 RES 4824
VGA_SCL 1 SCL SD0 4 52 53
I 2C

F833
4822 - Y INP 51
4818 -BUS
VGA_SDA 2 SDA FIL SD1 7 4816 SDA-VCOM 50
4811 - Y CTRL
F832 49
4820 48

4822
RES
VSS
RES 6 F835 47
BYPASS_MODE F836 46
4819 RES 4821 F837 45
44
43
VCOM_SW F838 42
41
PX1A- F805 40
PX1A+ F806 39
F807 38
PX1B- F808 37
PX1B+ F809 36
F810 35
+5V_SW +12VDISP 34
PX1C-
PX1C+ F811 33
F812 32
PX1CLK- 31
PX1CLK+ F813 30
29
RES 4800
RES 4801
RES 4802

F814
28
4803
4804
4805

PX1D- F815
PX1D+ F816 27
26
RES
4806 RES PX1E- 2803 10n F831 25
4807 RES PX1E+ F817 24
4808 RES F818 23
8 5800 22
F819
3 7 33R PX2A- F820 21
I801 5801
2 6 PX2A+ F821 20
I800 1 5 33R F822 19
5802 +VDISP-INT 18
PX2B-
33R PX2B+ F823 17
7800 F824 16
SI4835DDY PX2C- 15
3802
4

PX2C+ F825 14
F826 13
47K
PX2CLK- F827 12
6800
PX2CLK+ F828 11
F834 10
BZX384-C6V8 9
PX2D-
PX2D+ 8
3803 I802 2806
7
PX2E- 6
47R 1u0 5
3805

47K

PX2E+ +VDISP-INT F829

4
+3V3STBY 3
2
1

100u 16V
2804

2805

100n
3

RES
3806

15K

I806 I807 FI-RNE51SZ-HF-R1500

3807
7803 1 6
BC857BW I808
10K
2 7802-1 2 3
3808 BC847BS(COL) I809 3809 F800
1 7802-2 5 LCD-PWR-ONn
10K
BC847BS(COL)
1K0
2807

220n
3810

4
1K0

1 2011-04-18

PCB SB SSB
3139 123 6523
BERLINALE BRZ DIG

19131_008_110615.eps
110615

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 93

10.16 B05 313912365231

10-16-1 HDMI & Multiplexer

HDMI & Multiplexer

B05A B05A
I2C Address
5910 F939 F940 MICOM-VCC33
+3V3_SW
30R
SII9187B = 0xB0

2914

100n

2915

2916

3950
RES
HDMI CONNECTOR 2

RES

10K
10u

1u0
220u 16V
2919
1903
1 BRX2+
2
FB20
3 BRX2-
4 BRX1+ BIN-5V
5
6 RES
BRX1- F941 5911
7 BRX0+ +3V3STBY
8
30R

2917

2918

100n
RES

RES
9

10u
BRX0-

3930

3931
10

47K

47K
BRXC+
11
12 BRXC-
13 HDMI_CEC
14 7910 +5V_DC

27
64

37

38
15 F920 SII9187B

9
BRX-DDC-SCL BRX-DDC-SCL

MICOM_VCC33

SBVCC33
16 F921 BRX-DDC-SDA BRX-DDC-SDA VCC33 6924
17
+5V_SW
18 F922 BIN-5V 31
(CBUS) HPD0 BAS316
19 F923 BRX-HOTPLUG 32
R0PWR5V
21 20
CDS2C05HDMI2

3948

3949
23 22 29

10K

10K
DSDA0
RES 6920

5.6V

30 49
DSCL0 R4PWR5V
F924
65 48 VGA_SCL
N DSCL4
66 R0XC 47 VGA_SDA
P DSDA4
67 51
N CEC_D
HDMI 1 68 R0X0
P
1902 69
N
1 CRX2+ 70 R0X1
P
2
3 CRX2- 71
N
4 CRX1+ 72 R0X2
P
5 BRX-HOTPLUG 57 AT19
CIN-5V N
6 CRX1- 3937 100K 35 TX2 56 AP19
3938 I920 (CBUS) HPD1 P
7 CRX0+ 36
BIN-5V R1PWR5V
8 2910 1u0 59 AU18
10R N
9 CRX0- BRX-DDC-SDA 33 TX1 58 AR18
DSDA1 P
10 CRXC+ BRX-DDC-SCL 34
DSCL1
3932

3933

61
47K

47K

11 N AT17
12 CRXC- BRXC- 1 TX0 60 AP17
N P
13 F925 HDMI_CEC BRXC+ 2 R1XC
P
14 F926 ARC-eHDMI+ 63 AU16
N
15 F927 CRX-DDC-SCL CRX-DDC-SCL BRX0- 3 TXC 62 AR16
N P
16 F928 CRX-DDC-SDA CRX-DDC-SDA BRX0+ 4 R1X0 3943 4K7
P
17 I923
18 F930 CIN-5V BRX1- 5 55 3944 4K7 RES MICOM-VCC33
N TPWR_CI2CA
19 F931 CRX-HOTPLUG BRX1+ 6 R1X1
P
21 20
CDS2C05HDMI2

F932
23 22 BRX2- 7 50
N CEC_A
RES 6921

5.6V

BRX2+ 8 R1X2
P
CRX-HOTPLUG
3939 100K 41 52
3940 I921 (CBUS) HPD2 INT
42
CIN-5V R2PWR5V
2911 1u0
10R
CRX-DDC-SDA 39
DSDA2
CRX-DDC-SCL 40
HDMI SIDE DSCL2

CRXC- 11
N
1901 CRXC+ 12 R2XC 54 I924 3945 SCL-MAIN
P CSCL
1 DRX2+ 53 I925 3946 SDA-MAIN
CSDA
2 CRX0- 13
N
3 DRX2- CRX0+ 14 R2X0
P
4 DRX1+ 10
5 CRX1- 15 RSVDL 28
N
6 DRX1- CRX1+ 16 R2X1
DIN-5V P
7 DRX0+
8 CRX2- 17
N
9 DRX0- CRX2+ 18 R2X2
P
10 DRXC+ DRX-HOTPLUG 7700-5
11 3941 100K 45 MT5363BIMG
3942 I922 (CBUS) HPD3
3934

3935

46 74
47K

47K

12 DRXC- DIN-5V R3PWR5V

13 HDMI_CEC
10R 2912 1u0 75 HDMI-LVDS 0P
G16 PX2A+
14 DRX-DDC-SDA 43 76 AP17 AP17 E16 PX2A-
DSDA3 0 0N
15 F933 DRX-DDC-SCL DRX-DDC-SCL DRX-DDC-SCL 44 77 AT17 AT17 H17 PX2B+
DSCL3 0B 1P PX2B-
16 F934 DRX-DDC-SDA DRX-DDC-SDA 78 AR18 AR18 F17
5912 1 1N
17 eHDMI+ DRXC- 19 79 AU18 AU18 G18 PX2C+
N 1B 2P PX2C-
18 F935 30R DRXC+ 20 R3XC 80 AP19 AP19 RX1 E18
DIN-5V P 2 2N
19 F936 DRX-HOTPLUG 81 AT19 AT19 AE G20 PX2D+
2B 3P PX2D-
21 20 ARC-eHDMI+ DRX0- 21 VIA 82 AR16 AR16 E20
N C 3N
CDS2C05HDMI2
F937

23 22 DRX0+ 22 R3X0 83 AU16 AU16 H21 PX2E+

P CB 4P
RES 6922

5.6V

84 F21 PX2E-
4N
2913

23 85 AL18 H19 PX2CLK+

10p

DRX1- N HDMI_HPD1 CKP

DRX1+ 24 R3X1 86 F19 PX2CLK-
P CKN
87
DRX2- 25 88 AP13 D15 PX1A+
+3V3STBY N 0 0P
DRX2+ 26 R3X2 89 AT13 B15 PX1A-
P 0B 0N
AR14 C16 PX1B+
1 1P
AU14 A16 PX1B-
1B 1N
EPAD AP15 RX2 D17 PX1C+
2 2P
PX1C-

73
AT15 B17
2B 2N
7911 AR12 AO D19 PX1D+
C 3P
BSH111 AU12 B19 PX1D-
RES F943 CB 3N
C20 PX1E+
4P
AN16 A20 PX1E-
HDMI_HPD2 4N
+3V3STBY C18 PX1CLK+
CKP PX1CLK-
A18
CKN
6923 I926 3936
4910 F938 HDMI_CEC

RB521S-30 27K
CEC
1 2011-04-18

PCB SB SSB
3139 123 6523
BERLINALE BRZ DIG

19131_009_110615.eps
110615

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 94

10-16-2 USB

USB
B05B B05B

7D00
TPS2041BD

FD04 USB_PWR_EN
6 4
1 EN_
USB 7
2 OUT 1
2
+5V_SW
1D01
5D00 FD07 IN
1 5V FD01 8 3
FD02
3 2
2 USB_DM 33R
3 USB_DP FD03 5
OC_ 2D14

GND
4 FD00 2D12
100n 100u
6 5 16V

BZX384-C6V8
1D03

1D04

1D05

6D00

2D11
USB-16-PBT-B-30-CU1-BRF

10u

1
FD06

FD05 USB_OCP

USB_DM

USB_DP

1 2011-04-18

PCB SB SSB
3139 123 6523
BERLINALE BRZ DIG

19131_010_110615.eps
110615

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 95

10.17 B06 313912365231

10-17-1 Analog I/O - Headphone

Analog I/O - Headphone

B06A B06A

RESERVED

RES
3A04
HP_LOUT LEFT FA03
1R0

PESD5V0S1BA
2A02

RES 1A03
RES

1n0

6A01
RES
HEADPHONE
1A01
2 RES
3
1
MSJ-035-12D-B-AG-PBT-BRF

FA04
RES
HP_ROUT 3A03
RIGHT FA02
1R0

PESD5V0S1BA
2A01

RES 1A02
RES

1n0

6A00
RES

RES
3A10

22K

+3V3_SW

RES
7A00 RES
2A10
RES

1u0
PBS_HPL TPA6111A2DGN 3A11
2A05
RES

4A02
47n

RES
RES
RES RES
Φ VDD
RES 33R
HPOUTL FA06 2A07 3A18 10K IA02 3A15 10K 2 AMPLIFIER 1 IA09 2A06 IA00 RES 3A12 FA08 HP_LOUT
1 1
FA07 RES RES 33R
HPOUTR 1u0 RES 2A08 IA03 3A16 10K IN- 100u 4V
3A19 10K 6
2 VO RES RES
1u0 RES 3A17 IA04 IA08 2A09 IA01 3A13 FA09
RESET_AUDIO 5 7 HP_ROUT
SHUTDOWN 2
10K RES 2A11 IA10 100u 4V 33R
PBS_HPR 4A03 3 10
BYPASS RES 3A14
RES VIA 11
1u0
2A12

2A13
RES

RES

GND GND_HS
1n0

1n0

33R
2A04
RES

9
47n

RES
3A09

22K

1 2011-04-18

PCB SB SSB
3139 123 6523
BERLINALE BRZ DIG

19131_011_110615.eps
110615

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 96

10-17-2 Analog I/O - Audio

Analog I/O - Audio

B06B B06B
7700-2
MT5363BIMG

AUDIO-VIDEO AF
AM33

AN34
P
MPX AN36
N
AD33 IB10 AIN0_L-AV1
IB66 0_L
HSYNC AR22 AC34 FB02 AIN0_R-AV1
IB67 HSYNC 0_R
VSYNC AU22 AB31 IB12 AIN1_L-AV2
VSYNC 1_L IB13
AC32 AIN1_R-AV2
IB23 1_R
SOG AP23 AD35 IB02 IB01 2B34 IB00
SOG 2_L 3B31 3B32 FB00
RP IB24 AT25
RP 2_R
AB35
AC36 DVI_AUL_IN
AUDIO IN

PESD5V0S1BA
3_L 30K 10u 1R0
GP IB25 AU24 AIN_AADC AB37 DVI_AUR_IN
GP 3_R 1B01
IB26 2

6B00
AT23 AA32

RES
BP BP 4_L 3

2B35

2B36

1B03
RES

RES
AB33

1n0

1n0
IB27 4_R 1
GN AR24 AA34
COM 5_L
Y35 MSJ-035-29D PPO
IB39 5_R
SPR0P 3B11 68R 2B11 10n PR0PAU30 AA36 SAV_L_IN
IB29 0P 6_L FB06
SPR1P 3B05 68R 2B05 10n AP27 PR Y37 SAV_R_IN
IB41 1P 6_R
SPB0P 3B09 68R 2B09 10n PB0PAP29
3B03 IB31 0P
SPB1P 68R 2B03 10n AT27 PB AA30 IB03 2B37
IB43 1P VMID_AADC 3B34 IB09 IB08 3B33
SY0P 3B07 68R 2B07 10n Y0PAR28 0P
3B01 68R 2B01 10n IB33 AU26 Y

PESD5V0S1BA
SY1P 1P 30K 10u 1R0 FB01

2B41

2B40
100n
1u0
IB45 NEAR CONNECTOR

6B01
SY0N 3B08 100R 2B08 10n Y0NAT29

RES
IB35 0
3B35 4K7

2B38

2B39

1B04
RES
3B02 2B02 10n AR26 COM L34 IB14

RES
SY1N 100R

1n0

1n0
1 AOBCK IB15 3B36 4K7
M37
2B06 IB47 AOLRCK
3B06 1R0 1n5 SOY0AU28 M35
3B00 1R0 2B00 1n5 IB37 0 AOMCLK
SOY1-AV2 AP25 SOY
1 IB16 3B37
AP33 L36 +3V3_SW
0 0
SOY0-AV1 AR34 SY P35
1 1 4K7
AT33 P37
0 AOSDATA 2 3B38
AU34
1
SC
3
K31
N32
+3V3_SW SPDIF
FB08 2B15 4 4K7
GND_CVBS IB61 AR36 1B02
0N IB17 2B42
FB03 ASPDIF_OUT FB04 2
AT37 K33 SPDIF_OUT 3B15 240R
1u0 0P ASPDIF
3B14 2B14 AU36
1P CVBS 100n FB07
CVBS_AV3 IB63 AP35 L32 3B16 100R 1
2P ALIN RES 3B39

1B05
AT35 MTJ-032-21B-43-NI
100R 47n 3P 2B20 33p

2B19
AF37

33p
0 4K7
AP31 U32
OUT1 1
AT31 VDAC AL V35 RES 2B16 10u HPOUTL
OUT2 2
DEB 3
V37 IB18 2B17 10u IB19 PREAMPL
AM29
FS_VDAC
AE36
0
V33
1

DEB

560R
3B58

3B47
AR U34 RES 2B24 10u HPOUTR

75R
2 IB20 IB21
U36 2B25 10u PREAMPR
3
AF35 IB22
AVICM

3B17

3B18

3B48

3B49
RES
RES

47K

47K

47K

47K
2B43

2B44

100n
1u0
+3V3_SW
+3V3-ARC

3B40
3B54 IB70
22K
1R0
2B50

220p

2B60

100n
2B51 3B41 3B50
4

PREAMPL IB48
2B58
IB49 5K1 2 AOUTL
10u 10K
2B52

820p

1
+12VS 10u
3 7B05-1
8

LM833

14
3B51

74LVC00APW
47K

7B01-1 IB71
+12VS ASPDIF_OUT 1 & 2B61 IB72
3 SPDIF_OUT
3B42

2
30R

100n
IB50 +3V3_SW
3B43

470K

7
+3V3_SW

IB51
2B53

1u0

+3V3-ARC
2B54

3B44

470K

3B55
+3V3-ARC

10K
10u

7B05-2

14
74LVC00APW 7B05-3

14
4 & 74LVC00APW
6 9 & 2B62 3B56 IB74 2B63
ARC_SW FB09 eHDMI+
7B01-2 5 8
LM833 10
+3V3_SW 100n 180R 100n
8

7
5
2B59
7

7
2B55 IB52 AOUTR
IB53 3B45 3B52

3B57
PREAMPR 6

68R
10u
4

10u 10K 5K1

2B56

3B53
820p

47K
2B57

220p

+3V3-ARC

7B05-4

14
74LVC00APW
12 &
3B46
11
13
22K +3V3_SW

7
1 2011-04-18

PCB SB SSB
3139 123 6523
BERLINALE BRZ DIG

19131_012_110615.eps
110615

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 97

10-17-3 Analog I/O - Video

Analog I/O - Video

B06C B06C
NEAR CONNECTOR
NEAR CONNECTOR 2C24
3C28 IC09 3C12
AIN0_R-AV1
3C26 2C22 IC01 3C00 30K 10u 1R0

PESD5V0S1BA
AIN1_R-AV2

1C14
2C20

2C21
RES

RES
1n0

1n0
PESD5V0S1BA
30K 10u 1R0

6C19
2C00

2C01

1202

0001
6C00
RES

RES
1n0

1n0
RES
RES

3C29 2C25 3C13 FC15

AIN0_L-AV1 IC10

3C27 2C23 IC02 3C01 30K 10u 1R0

PESD5V0S1BA
AIN1_L-AV2

RES 6C20

1C15
2C18

2C19
RES

RES
PESD5V0S1BA

1n0

1n0
30K 10u 1R0
CVI 2 CVI 1

2C02

2C03

6C01

1C16
RES
RES

RES
1n0

1n0
1C02 1C01
FC09 FC10
MSP-636V1-01 1 MSP-636H1-01-NI
1 2
FC08 3
2
IC03 3 IC11 FC11
3C20 5C00 3C21 5C03
SPR1P SPR0P 4
4 60R
18R 60R FC07 18R
5

PESD5V0S1BA
2C04

3C02

1C17

2C17

3C14

RES 6C08

1C10
5

56R

56R
PESD5V0S1BA
15p

15p
6

6C02
6

RES
FC12
PR_CVI2 PR_CVI1 7
7
FC04
8
8
FC05 FC13
PB_CVI2 PB_CVI1 9
9

PESD5V0S1BA

PESD5V0S1BA
10

RES
11
2C05

3C04

6C03

1C18

2C16

3C16

6C09

1C09
10

RES
56R

56R
15p

15p
FC06 FC14
SY_CVI2 11 SY_CVI1 12
IC15 12
3C22 5C01 IC13 3C23 5C04
SPB1P SPB0P
18R 60R IC21 18R 60R
IC16 SOY0-AV1
SOY1-AV2 IC14 3C24 5C05
IC17 SY0P
SY1P 3C25 5C02
60R

PESD5V0S1BA
18R

1C08
60R

PESD5V0S1BA
18R

1C19

2C15

3C17

6C10
RES
56R
15p
2C06

3C05

6C04
56R

RES
15p

IC22 3C18
IC18 SY0N
SY1N 3C06
1R0
1R0

SIDE AV
CVBS
1C03-1
YELLOW2 FC03 3C07 IC04
RIGHT CVBS_AV3
PESD5V0S1BA

(YELLOW) 1R0 IC19

1 SAV_L_IN
1C05

6C05

3C08

2C08

2C07

MTJ-032-37BAA-432 NI
RES

75R
RES

15p

47p

IC20
SAV_R_IN

GND_CVBS

LEFT1C03-2
FC02 IC05 2C09
WHITE 3C09 3C10
5
PESD5V0S1BA

(WHITE) 1R0 10u 30K

4
6
MTJ-032-37BAA-432 NI
6C06

2C11

2C10
RES

RES

RES
1n0

1n0
1C06

NEAR CONNECTOR

1C03-3
FC01 3C11 IC07 2C14 3C19
RED
8
PESD5V0S1BA

(RED) 1R0 10u 30K

7
9
1C07

6C07

2C12

2C13
RES
RES

MTJ-032-37BAA-432 NI
RES
1n0

1n0

FC00
1 2011-04-18

PCB SB SSB
3139 123 6523
BERLINALE BRZ DIG

19131_013_110615.eps
110615

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 98

10-17-4 VGA

VGA
B06D B06D

2E00 3E00 5E00

RP VGA_Rp VGA_R FE01
10n 68R 60R

PESD5V0S1BA
3E16

6E00
2E07

1E00
RES
75R
5p6
2E03 3E03
SOG
1n5 1R0
2E02 3E02 5E01
GP VGA_Gp VGA_G FE02

PESD5V0S1BA
10n 68R 60R

2E08

3E15

6E01

1E05

0001
RES
75R
5p6
2E04 3E04 3E10
GN VGA_Gn
10n 100R 1R0

2E05 3E05 5E02

BP VGA_Bp VGA_B

PESD5V0S1BA
10n 68R 60R

2E09

3E14

6E02

1E02

0001
RES
75R
5p6
1E01
1
5E03 6E05 3E13
2
+5V_DC FE03 3
60R BAS316 150R
4

2E10

2E11
100n
5

1n0
6
7
8
FE04 9
10
5E04 H_SYNC
HSYNC 11
FE14 12

PESD5V0S1BA
30R
FE05 13

2E12

RES 3E17

6E03

1E03
FE06 14

RES
2K2
5p6
FE13 15
FE07 16 17

5E05 VSYNC 1216-02D-15L-2EC

VSYNC

PESD5V0S1BA
30R
2E13

RES 3E18

6E04

1E04
RES
2K2
5p6

VGA_SDA
VGA_SCL

1 2011-04-18

PCB SB SSB
3139 123 6523
BERLINALE BRZ DIG

19131_014_110615.eps
110615

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 99

10.18 B07 313912365231

10-18-1 Hospitality

Hospitality
B07 B07

DMMC1 DMMC3
RES RES
1F00 1F01
FF12
1 FF00 RES 5F00 33R +3V3STBY 1 PBS_HPL
2 SDA_CLOCK FF01 RES 3F00 100R SDA-LCD 2 FF11 FF13
3 SCL_CLOCK FF02 RES 3F01 100R SCL-LCD 3 PBS_HPR
4 4 5
5 FF03 RES 5F01 33R +5V_SW
6 7 FF04 502382-0370

RES
2F00

2F01
RES
1n0

1n0
502382-0570

1 2011-04-18

PCB SB SSB
3139 123 6523
BERLINALE BRZ DIG

19131_015_110615.eps
110615

2012-Jul-20 back to
div. table
 Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 100

10.19 313912365231 SSB Layout

10-19-1 Overview top side

1X05 1M95

2608 2101
4817

2101

7123
4820

7123
2804
4814

7122
1702

U4
1G51

4815
7122
4822

U4
7801 4816

7124

U2
U5

4823
2140
4821

U2
4818

2105
4819

5120 2168
4812
2152

2140
5120 2168
2104 4810 2155

2802
4824

4813

5117 2154
5117 2154

3765
3780
3760
3759
4811 2155

3763
2162

5115 2188
2183 2161

1X04

6122
2152 2803
2161
2805

6122
2138 3762

2171
2153
2162

2163
2100

2171
2153
2163
2100
2191

5104

2189
2172

2608
5121
3615 2609
3615 2609
2804
5121 5104
2135
2126 5123 2701
1M99
2701

2164
7600 7600
2125 3707

2164
7120 2159
3707

7120 2159
3706
3706

U5
2700

2551 2628
7124
2700

37A9
2551 2628

5506
2514
37A9
2105

5506
2514

4700
3726
2127
2134

37AA
4700