1914 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO.

8, AUGUST 2010

Analytical Phase-Noise Modeling and Charge Pump

Optimization for Fractional-N PLLs
Frank Herzel, Sabbir A. Osmany, and J. Christoph Scheytt, Member, IEEE

Abstract—We present an analytical frequency-domain

phase-noise model for fractional- phase-locked loops (PLLs).
The model includes the noise of the crystal reference, the reference
input buffer, the voltage-controlled oscillator (VCO), the loop
filter, charge pump (CP) device noise, and sigma-delta modulator
(SDM) noise, including its effect on the in-band phase noise. The
thermal device noise of the CP and the turn-on time of the CP
output current are found to be limiting the in-band phase noise
of state-of-the-art synthesizers. Device noise considerations for
bipolar transistors and MOSFETs suggest the use of CMOS-only
CPs, even in BiCMOS technologies. We present a noise-optimized
CMOS CP specifically designed for a dual-loop PLL architecture
N synthesizer architecture.
Fig. 1. Schematic view of a fractional-

using two CPs. This PLL architecture keeps the dc output voltage
of the noise-relevant CP and the phase-noise spectrum constant,
regardless of temperature variations.
Index Terms—Charge pump (CP), fractional-
loops (PLLs), phase noise.
I. INTRODUCTION
In this paper, we consider only CP PLLs due to their pop-
phase-locked ularity in state-of-the-art synthesizer design. For the same
reason, we assume that the fractional- divider ratio is ob-
tained by using a sigma-delta modulator (SDM). The SDM in a
fractional- synthesizer inevitably results in large momentary
phase errors, even in the absence of noise. This makes the
description difficult within an analytical model. Our approach

P HASE noise limits the performance of wireless and high-

speed digital systems. Frequency synthesizers are com-
monly characterized in the frequency domain by phase-noise
spectra. Jitter is the corresponding time-domain equivalent and
is used for characterizing clock generation circuits, as well as
clock and data recovery (CDR) circuits. Several theoretical pub-
lications on phase noise and jitter modeling of phase-locked
loops (PLLs) have appeared during the last decade, e.g., [1]–[4].
An accurate prediction of phase noise requires simulation on
the transistor level. However, a complete transistor-level simu-
lation of a PLL is difficult or impossible, even in the absence
of noise sources. This is due to very different time scales of
the voltage-controlled oscillator (VCO) dynamics and the PLL
settling. To simulate the PLL including nonlinear effects, be-
havioral system-level simulations are helpful [5]–[11]. An even
more simplified approach is linear analytical phase-noise mod-
eling, where the main noise contributions are described by ad-
justable parameters. These models correctly reflect the depen-
dence of the phase-noise spectrum on design parameters such
as loop filter values, charge pump (CP) current, divider ratios,
etc., but they inevitably need some fit parameters. These can be
determined from theory, simulation, or measurements.
Manuscript received October 20, 2009; revised December 08, 2009; accepted
December 22, 2009. Date of publication February 17, 2010; date of current
version August 11, 2010. This paper was recommended by Associate Editor
J. Silva-Martinez.
The authors are with the IHP, 15236 Frankfurt (Oder), Germany (e-mail:
herzel@ihp-microelectronics.com).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSI.2009.2039832
1549-8328/$26.00 © 2010 IEEE
is based on the linear model presented in [12], where the
quantization noise spectrum for a multistage noise shaping
(MASH) SDM was included based on the expression given in
[13]. Another critical problem related to SDM noise, which has
been disregarded in [12], is the turn-on time of the CP, resulting
in nonlinearities in the phase detector (PD), as described in
[14]–[20]. The combination of an SDM with a nonlinear PD
may fold the SDM noise from large-frequency offsets down
to the in-band region of the spectrum. This effect has analyt-
ically been modeled in [18]–[20]. It can be interpreted as the
self-mixing of the SDM noise in the nonlinear PD, which is
composed of a phase-frequency detector (PFD) and CP. To
avoid confusion with CP device noise and linear SDM noise,
this noise contribution will be referred to as PD noise.
This paper presents an analytical phase-noise model for a
PLL including PD noise. The modeled phase-noise spectrum
and its components are visualized by MATLAB. Finally, a
simple CP architecture is suggested, which allows CP device
noise and PD noise to drastically be reduced.
II. PLL PHASE-NOISE SOURCES
In a CP PLL used in modern communication systems, the
output phase of the VCO is divided by and compared with
a reference phase in a PFD. A CP current proportional to the
phase error is produced, low-pass filtered, and applied to the
control input of the VCO, as shown in Fig. 1. In fractional-
PLLs, the divider ratio is controlled by an SDM.
The output voltage of a PLL can be described as
(1)
HERZEL et al.: ANALYTICAL PHASE-NOISE MODELING AND CP OPTIMIZATION FOR FRACTIONAL- PLLs 1915

Fig. 2. Linearized PLL model.

where is the amplitude, is the oscillation

frequency, and is the excess phase. In this paper, the
term phase-noise spectrum refers to the two-sided power spec- Fig. 3. Third-order loop filter.
tral density (PSD) of in units of square radians per hertz
or square decibel-radians per hertz, when expressed in deci-
bels. In the latter case, the phase noise is almost identical to For the third-order filter according to Fig. 3, we obtain the
the single-sideband phase noise $ in units of dBc per hertz, if transimpedance
and only if white noise sources dominate the PLL noise [4].
The presence of flicker noise results in the well-known (3)
shape of the close-in VCO phase-noise spectrum, whereas the
single-sideband phase-noise spectrum is a Voigt function, which where
resembles a Gauss function at very small offsets [21]. In this
paper, we will include the following seven noise sources: (4)
1) reference noise;
2) reference input buffer noise; (5)
3) VCO noise;
4) loop filter noise; Unlike in [12], we have incorporated a voltage divider at the
5) CP device noise; filter input here, which is useful in the context of a dual-loop
6) – quantization noise; PLL, as discussed in [23]. For a traditional single-loop PLL, R4
7) PD noise. and R5 should be omitted, or huge values should be used in the
The latter contribution represents the noise folding of the noise model.
SDM quantization noise in the nonlinear PD. Noise in the fre- In the next section, the noise sources mentioned in Section II
quency dividers is disregarded in this paper, which is focused will analytically be described.
on PD design. It could be added to the phase-noise model, if
the measured phase-noise spectra at the feedback divider output IV. PHASE NOISE PSD
and the reference divider output are available. As an alterna-
The noise sources discussed in this section are uncorrelated.
tive, the white spectrum of the input-referred divider noise can
Therefore, the phase-noise PSD at the PLL output is the super-
be modeled as a function of delay mismatch in the feedback
position of the seven mentioned noise contributions, each multi-
divider [15], [19]. Another type of noise is caused by digital cir-
plied by its specific noise transfer function. Emphasis is placed
cuits such as frequency dividers, SDM, and PFD, affecting the
on those components that are not, or only insufficiently, included
performance of noise-sensitive analog circuits through supply
in [12], i.e., input buffer noise, CP noise, and PD noise.
and substrate coupling. Supply- and substrate-induced jitter may
easily exceed device-noise-induced jitter in high-speed digital A. Reference Noise
systems [22].
The phase-noise contribution of the reference oscillator as a
function of the frequency offset is modeled by
III. LINEARIZED PLL MODEL
Fig. 2 shows the linearized model of a PLL, as presented in (6)
[12]. Of special interest in this paper is the PD composed of PFD
and CP, which converts a phase error at the input into an output where is the phase noise at a specific offset in
current averaged over one comparison period. For an ideal the 20-dB/dec region of the spectrum, and is the
PD, the gain is given by , where is noise floor of the reference. The reference noise spectrum at the
the CP current in the ON state. The loop filter transimpedance is output reads
denoted as , and the VCO gain is . is the divider
ratio of the PLL. Note that the VCO gain
refers to the angular frequency and is given in units of radians (7)
per second per volts. The forward path transfer function is
given by with the transfer function given by

(2) (8)
1916 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 8, AUGUST 2010

filter from the CP output to ground. The resulting noise spec-

trum at the output is given by

(13)

Fig. 4. (a) Proposed input buffer and (b) noise model.
B. Reference Input Buffer Noise
As discussed in [23], the noise of the reference buffer may
become a major contributor to the output phase noise. We use an
electrostatic-discharge-protected CMOS inverter chain as input
buffer shown in Fig. 4. The first CMOS inverter converts the
crystal oscillator signal into a rectangular signal on the chip.
Assuming a sinusoidal reference signal with peak amplitude ,
we obtain for the phase noise at the PLL output
(9)
where is the input-referred noise voltage PSD. The
transconductance of the MOSFETs must be large
enough to make this noise negligible.
C. VCO Noise
The phase noise of a free running oscillator is modeled by
E. CP Device Noise
For a PLL to work at a given bandwidth, a large CP current
is generally favorable in order to reduce the loop filter resis-
tance . The large current, however, produces significant cur-
rent noise. The time between two phase comparison instants is
referred to as , where is the frequency at the PFD
input at which the PLL phase error is sampled.
In order to qualitatively describe the thermal CP noise,
we write the two-sided thermal drain current noise PSD of a
MOSFET according to [24] as
(14)
where is the channel conductance with zero drain–source
voltage, and is between 2/3 and 1 for long-channel devices
and somewhat larger for short devices, i.e., typically ranging
from 1 to 3. This type of noise results in a white noise spec-
trum of the CP described by one parameter. This pa-
rameter can be fitted to measurements or simulated by periodic
steady-state analysis (PSSA) [8]. Thermal noise must be multi-
plied by the CP duty cycle , where is the
CP activation time.
In addition to thermal noise, CPs also exhibit flicker noise
( noise). The flicker noise PSD is proportional to [25].
This is due to the large autocorrelation time of this type of noise,
which is assumed to be much larger than . Adding the two
noise contributions, we obtain
(15)

(10) where is the noise corner frequency of the transistor.

Note that the flicker noise corner of the CP scales with ,
which usually makes flicker noise small, compared with thermal
where is the phase noise at a specific offset in
noise, unless a large CP duty cycle is used. For the white noise
the 20-dB/dec region of the spectrum, is the noise
current PSD normalized to the CP current , we
corner of the VCO, and is the noise floor of the VCO. The
found a value of for the cascode CP from [23].
PLL output noise due to VCO phase noise is given by
This value was obtained by a PSSA, followed by a periodic
(11) noise analysis using the Virtuoso Analog Design Environment.
More details will be given in Section VI. The noise spectrum at
where is given by (8). the PLL output reads

D. Loop Filter Noise (16)

We model the noisy loop filter by a noise current in parallel
with a noiseless admittance. The two-sided PSD of noise current
can be expressed as F. Sigma-Delta Quantization Noise
The quantization noise spectrum for an th-order MASH-
(12) type SDM is given by [13]

where is Boltzmann’s constant, is the absolute tempera-

(17)
ture, and is the complex admittance of the
HERZEL et al.: ANALYTICAL PHASE-NOISE MODELING AND CP OPTIMIZATION FOR FRACTIONAL- PLLs 1917

where is the order of the modulator. The SDM noise spectrum

at the PLL output is given by

(18)

G. PD Noise
If both the UP and DOWN currents are changing in the steady
state of the PLL, then the PD gain will be discontinuous, if
the UP and DOWN currents do not match. This case has been
discussed in [20]. For a low-noise PLL in fractional- mode,
an offset current at the CP output is highly recommended, as
shown in [16]. If the offset current is a sufficiently large DOWN Fig. 5. PD gain versus input phase error for cascode CP.
current, then only the UP current will respond to phase error
changes in the steady state. This improves the linearity of the
PD and significantly reduces phase noise. In this case, the output with the integrals
current of the CP is a continuous function of the phase error
at the PFD input, which is ideally a linear function. In reality, (23)
the limited turn-on time of the current will result in deviations
from this behavior. Taking the nonlinearities into account in the
lowest order, we can write the current as
(24)
(19)

where is the linear PD gain, and represents the first-order (25)

nonlinearity. It can be determined from

(20) The first term in (22) corresponds to the term discussed in

Section IV-F. The other terms describe noise-folding contribu-
resulting in . The linear term in tions. If the process is symmetric with respect to the sign,
(19) produces the quantization noise spectrum described positive and negative contributions in will cancel out. In order
in Section IV-F, and the quadratic term will cause the PD noise to calculate , we decompose into a Fourier integral
discussed in this section. Third-order nonlinearities in the PD
transfer function have been disregarded in this paper. Such
(26)
nonlinearities have been modeled in [10] in the zero-phase
offset region. Fig. 5 shows the simulated PD gain as a
function of the phase error at the PFD input for the cascode CP Equation (25) then reads
used in [23]. Here, the sampling frequency was 100 MHz,
and the CP current was as large as 8 mA for a low in-band
phase noise. As evident from Fig. 5, the PD gain is not constant
but depends on the phase error, which causes noise folding in
the PLL. More specifically, the quantization noise described
in Section IV-F is folded down to low-frequency offsets in the (27)
nonlinear PD. Note that the PD gain is a fairly linear function
of the input phase error over a wide range. In other words, the where all integrals are to be taken from to . Integration
parabolic approximation of the PD transfer function given by with respect to yields
(19) seems reasonable for this particular CP. In order to calcu-
late the two-sided spectrum of the CP current, we write it as the
Fourier transform of the autocorrelation function according to
the Wiener–Khintchine theorem, i.e.,

(21) (28)

Integration with respect to , , and results in

with and the brackets denoting the stochastic
(ensemble) average. Substituting (19) into (21), we obtain
(29)
(22)
1918 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 8, AUGUST 2010

Taking the average on both sides yields By substituting (36) and (37) into (35), we finally obtain

(30) (38)

Note that we have a close similarity to the analytical result of

The PD noise is basically a convolution of the SDM phase noise Mao [20], where corresponds to the mismatch parameter
with itself multiplied by the variance of the phase. In the context in [20] and corresponds to . The same result could
of close-in phase noise, the low-frequency limit is relevant. We not be expected since [20] considers the case of a discontinuous
obtain for PD gain due to mismatch between the UP and DOWN currents,
whereas we consider the case of a continuous PD gain realized
(31) by an offset current at the CP output. The phase noise is pro-
portional to , i.e., a reduction in by a factor of two will
lower the phase noise by 12 dB. Therefore, for a relatively poor
where we have exploited the property for the PD linearity as in [23], a single-loop SDM might be the better
real-valued process . For the PD noise, we obtain choice since the momentary phase error and are lower than
those for a MASH-type SDM [14]. A reduction in the nonlin-
(32) earity parameter by a factor of 10 will reduce the in-band PD
noise by 20 dB, as evident from (38). Therefore, a MASH-type
where the same transfer function as for the CP noise current was SDM might be the better choice for a highly linear PD, as pro-
used. posed in Section VI. It has the advantage of easy integration in
For Gaussian noise of , we can further simplify the result for CMOS or BiCMOS and is unconditionally stable.
the in-band phase noise due to the nonlinear PD. The net charge
delivered by the CP and the resulting squared phase error are V. PLL PHASE NOISE SPECTRUM
sampled at the rate of . From the Nyquist–Shannon Since the noise sources are uncorrelated, the corresponding
sampling theorem, we know that this sampled process can be noise spectra must be added to obtain the total phase-noise spec-
expressed by a continuous-time signal, the spectrum of which trum at the PLL output given by
has no Fourier components above the Nyquist frequency .
We assume similarly to [18] and [20] that the spectrum
of is white for . The variance of then (39)
follows by integration of and reads
where , , , , ,
, and are the phase-noise contributions of
(33) the previously discussed noise sources referred to the PLL
output. The rms phase error [degree] at the PLL output, which
The quadratic term in (19) results in the PD noise current spec- is sometimes called absolute phase jitter, is given by
trum

(34)
(40)
Substituting (33) into (34) and multiplying the result by the
noise transfer function, we obtain
Fig. 6 shows the simulated phase-noise spectrum and the
components for a 10-GHz frequency synthesizer, which em-
ploys a cascode CP. Here, the model parameters have been
adapted to measurements on the experimental dual-loop PLL
(35) presented in [23]. For space limitations, we only sketch this
process here. First, the noise of the 100-MHz crystal oscillator
For a high order of the SDM, the probability density of is mounted on the printed circuit board was measured by a spec-
approximately Gaussian. By using partial integration, we obtain trum analyzer. Subsequently, the noise of the input buffer was
the averages in (35) given by measured using small sinusoidal input signals to maximize
the reference buffer noise. The VCO noise spectrum was de-
termined from phase-noise measurements on the free-running
oscillator. For the noise contributions of the loop filter and the
(36) SDM, no parameters but the filter values and the SDM order are
required. In order to model the PD noise, the rms phase error
was estimated from MATLAB simulations, and the curvature
(37) parameter was obtained from transient circuit simulations
using the simulator Virtuoso Analog Design Environment. CP
HERZEL et al.: ANALYTICAL PHASE-NOISE MODELING AND CP OPTIMIZATION FOR FRACTIONAL-
Fig. 6. Modeled phase-noise spectrum for a 10-GHz synthesizer using a cas-
code CP.
device noise was also modeled by circuit simulation. Details of
these simulations will be given in Section VI-C.
Unlike in traditional PLLs, the VCO phase noise is band-
stop filtered due to the presence of the voltage divider R4/R5
at the CP output, as shown in Fig. 3. For the same reason, all
other noise transfer functions are modified at low frequencies.
These modifications are not critical, provided that the biasing
resistors are not too small. The relatively high level of PD noise
can be explained by the high PLL output frequency of 10 GHz
in conjunction with strong PD nonlinearity and the employment
of a MASH-type SDM, which results in a large rms phase error
in fractional- mode. In our example, the PD noise due to CP
nonlinearity and the CP device noise dominate the in-band phase
noise. This was the main motivation for improving the CP with
respect to linearity and device noise, as will be discussed in the
next section.
VI. SUGGESTED NOVEL CP
In this section, we will consider the output noise PSD of
a bipolar transistor and a MOSFET. The potential of MOS-
FETs with large gate–source voltages in the context of low-noise
CPs is outlined. This is followed by a brief description of a
low-noise dual-loop PLL architecture with CP output biasing.
Subsequently, we describe a simple CP architecture specifically
designed for VCO fine tuning using this PLL architecture. An
improvement by 10 dB over the existing design from [23] with
respect to CP thermal device noise and PD noise is predicted.
A. Transistor Noise Considerations
This paper was motivated by the desire to improve the syn-
thesizer for space applications in SiGe-BiCMOS technology.
BiCMOS technologies offer the opportunity to choose between
bipolar transistors and MOSFETs for the best design of each
building block. Generally, bipolar transistors have the reputation
to provide better high-frequency noise performance than MOS-
FETs, which is only partly true. This reputation mainly results
from the large transconductance of (hetero-) bipolar transistors,
compared with MOSFETs. While this advantage is crucial for
PLLs 1919
amplifiers, this is not necessarily the case for other circuits like
CPs. Here, the white device noise in the output circuit (drain
or collector) must be compared for the two devices. A transfor-
mation to the gate or base terminal as typically performed in
low-noise amplifiers is not meaningful here. In the following,
we compare the white output noise PSDs for the two types of
devices.
The two-sided thermal drain current noise PSD of a MOSFET
was according to (14)
(41)
In saturation, the transconductance is given by
(42)
where the gate–source overdrive voltage was
introduced. By substituting (42) in (41), we obtain
(43)
The two-sided shot noise PSD of a bipolar transistor is given
by
(44)
where is the dc collector current, and is the elementary
charge. Assuming the same dc current for the two transistors,
we obtain from (43) and (44) for the ratio between the output
current noise PSDs
(45)
Here, we assumed that and , resulting
in a thermal voltage of 26 mV. We conclude
that MOSFETs may show much less white output noise, com-
pared with their bipolar counterparts, provided that the over-
drive voltage is much larger than 200 mV. Obviously, the ad-
vantage of MOSFETs over bipolar transistors is particularly
pronounced for processes with a higher CMOS supply voltage.
This advantage reduces with technology scaling, which makes
MOSFETs less attractive for low-voltage applications. We have
disregarded flicker noise in this comparison. We believe that
flicker noise is less important than thermal noise for the fol-
lowing reason. The CP flicker noise corner is given by
according to (15). Assuming a transistor noise corner of 1 MHz
and a duty cycle of 10%, we obtain a CP flicker noise corner
of 100 kHz. The optimum loop bandwidth is typically larger in
a fractional- PLL, efficiently suppressing flicker noise in the
CP. We will show that the condition can be
fulfilled by employing the modern dual-loop PLL architecture
from Section VI-B in conjunction with the CP architecture from
Section VI-C. This architecture will allow the gate–source volt-
ages to be fully switched between ground (VSS) and CMOS
supply ( in our case). For the CP, MOSFETs
might be the better choice, compared to SiGe-HBTs, whereas
HBTs are better suited for low-noise VCOs and frequency di-
viders at high frequencies due to the large transconductance,
compared with MOSFETs. Moreover, the flicker noise perfor-
mance of SiGe-HBTs based on VCOs is much better [26].
1920 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 8, AUGUST 2010
Fig. 7. Schematic view of a dual-loop frequency synthesizer.
B. PLL Architecture for Low Phase Noise
A dual-loop architecture using two parallel CPs was de-
scribed in [23] and [27]. A slightly modified version is
suggested in Fig. 7. Here, the two CPs, i.e., CP1 and CP2,
for fine and coarse tuning, respectively, are composed of five
binary weighted CPs each, which are selectable by a common
five-bit control line. Two current sources (CSs) are added to
generate offset currents and in the fine-tuning loop
and the coarse-tuning loop, respectively. They are composed of
five binary weighted CSs each, which are controlled by another
five-bit control line. The advantage of an offset current at the
CP output is the opportunity to shift the steady-state operation
point of the PD in order to improve its linearity [16], [28].
Since the two CPs are driven by the same PFD, the condition
should be fulfilled in order to keep
the dc value of the fine-tuning voltage constant. The noise in
the low-current CP CP2 for coarse tuning is minimized by a
large capacitor to ground (100 nF in [23]). As a result, the
phase noise is dominated by the fast fine-tuning loop. Due to
the low fine-tuning gain of the VCO, the overall phase noise
is significantly reduced, compared to a single-loop PLL with
the same tuning range, as experimentally verified in [23]. This
improvement is particularly important for fractional- PLLs,
where the large CP duty cycle increases phase noise and spurs,
particularly, if a dc offset current is added to the CP output
current.
C. CP Architecture for Low Phase Noise
In most cases, CPs have been designed and optimized for
single-loop PLLs. A vast number of publications are devoted
to this topic (see [29], [30], and references therein). In order to
obtain a good matching between the UP and DOWN currents
over the whole PLL tuning range, a large output resistance of
the CP is generally mandatory for single-loop PLLs. The situa-
tion is completely different, if a CP is used for fine tuning of the
VCO only, where its output dc voltage is almost fixed as in [23].
In this case, emphasis can be placed on fast current switching
of the CP and on a low device noise by simplifying the CP ar-
chitecture. In this paper, we confine ourselves to this dual-loop
PLL architecture and consider only the CP for fine tuning. For
Fig. 8. CP architecture used in CP1.
coarse tuning, a traditional low-current CP with a higher output
impedance could be used.
As shown in Section VI-A, MOSFET-based CPs can provide
a low white noise, if their gate–source voltages are large. In ad-
dition, they also exhibit flicker noise. However, the flicker noise
corner frequency of the CP given by according to (15) is
lower than the transistor noise corner by the factor . Since
is typically lower than 10%, flicker noise is usually less
important than thermal noise in the context of CP design. The
CP current is usually determined from system simulations
and results in a given drain current of the CP output tran-
sistors. In order to generate the drain current , either large
MOSFETs with moderate gate-source voltages or moder-
ately sized MOSFETs with large can be used. From (43),
we conclude that the latter option results in a lower device noise.
The next step in the design of a low-noise CP is to find an ar-
chitecture, where the gate–source voltages are maximized. The
simplest CP with this property consists of a pMOSFET M1 de-
livering the UP current and an nMOSFET M2 delivering the
DOWN current. Such a circuit is shown in Fig. 8. Unlike con-
ventional CPs, it does not use cascode transistors or current mir-
rors, which avoids additional potential noise sources. A switch-
able CS realized by the transistor M3 between the output and
ground was also introduced to improve the PD linearity. At first
sight, this CP seems unacceptable for low-noise PLL design
since the output resistance is rather low, and the matching be-
tween the UP and DOWN currents extremely depends on the
HERZEL et al.: ANALYTICAL PHASE-NOISE MODELING AND CP OPTIMIZATION FOR FRACTIONAL- PLLs 1921

output voltage. In traditional single-loop PLLs, this would in-

evitably result in large spurs and a strong dependence of the
PLL phase-noise spectrum on the output frequency. However,
these problems are solved, if this CP is used for fine tuning
of the VCO (CP1 in Fig. 7), whereas a traditional low-current
CP is used for coarse tuning (CP2 in Fig. 7). The noise of the
latter can be reduced to a negligible level by loading it with
a large capacitor [23]. A voltage divider composed of two re-
sistors R4 and R5 on the order of 1 is added at the output
of CP1 to stabilize the dc output voltage at a desired value
given by . This eliminates the need
for a high output impedance of CP1 and improves its perfor- Fig. 9. Simulated UP and DOWN currents of CP1 and offset current I for
mance. At the same time, the VCO fine-tuning gain is kept al- two offset current levels.
most constant, which makes the PLL phase-noise spectrum ro-
bust with respect to device parameter variations with process,
supply voltage, and temperature (PVT variations). Note that the
PVT dependence of the CP itself is larger than that of a typical
cascode CP. However, the loop bandwidth in a CP PLL is pro-
portional to the product . In an integrated VCO, the
gain can easily vary by a factor of three or more over the tuning
range. By contrast, variations in the threshold voltage of magni-
tude cause relative changes of the CP current on the order
of only, as evident from (42). This
is much smaller than relative changes in a single-loop
PLL. The relatively constant loop bandwidth over a wide tuning
range in a dual-loop PLL using a cascode CP with output biasing Fig. 10. PD gain versus input phase error for new CP.
has experimentally been demonstrated in [27] and [23]. The low
output impedance of our new CP will reduce supply rejection.
However, we believe this drawback to be less significant than 200 ps, respectively, which is approximately one inverter delay.
the advantage of having a highly linear CP with a low thermal The turn-on time is about four times shorter than the value of
device noise. To minimize the effect of CP supply noise on the 1 ns reported for a CP in 0.35- m CMOS technology using a
VCO, an on-chip voltage regulator and a separate CP supply cascode architecture [31]. Cascode architectures can provide a
would be helpful. high output resistance and good current matching, but the swing
The CP draws an additional dc current due of the gate–source voltages of the switching MOSFETs is sig-
to output biasing. This results in a tradeoff between power con- nificantly smaller than VDD, limiting their turn-on times and,
sumption and phase noise. The fractional- PLL in [23] uses thereby, the PD linearity. Fig. 10 shows the simulated PD gain
to stabilize the output dc voltage of the CP as a function of the phase error at the PFD input for the
generating a current up to 8 mA. This choice was motivated by new CP. It was calculated by simulating the average CP output
the desire to minimize the phase noise, whereas power consump- current as a function of the input phase error and numerically
tion was considered less critical in satellite applications. By con- differentiating the result with respect to the phase error. The PD
trast, the integer- PLL for 60-GHz wireless communications gain mA is almost
in [27] used . Generally, R4 and R5 should the same as in Fig. 5 to make the two CPs comparable. The slope
be larger for integer- PLLs, compared with fractional- PLLs of this gain curve is essentially the curvature of the PD charac-
due to the lower CP duty cycle of the former. Moreover, CMOS teristic according to (20) and below. The average slope is
VCOs require larger resistors R4 and R5 than bipolar oscillators lower by a factor of 18, compared to the cascode CP gain in
to guarantee sufficient flicker noise suppression in the loop. Fig. 5. This improvement of the linearity is expected to have a
Fig. 9 shows the simulated CP currents in the fine-tuning loop significant effect on the in-band phase noise and spurs of the
for two different offset currents. Obviously, the short DOWN fractional- PLL.
current pulse is not affected by the offset current, whereas the In addition to improving the PD linearity, the new CP reduces
UP current pulse becomes broader with increasing offset cur- thermal device noise. Fig. 11 shows the simulated device noise
rent. This allows the PD to be linearized by shifting the opera- of the new CP and of the cascode CP used in [23]. Note that the
tion point into a region, where only the UP current responds to large duty cycle of 30% represents a worst case with respect to
the inevitable phase error changes in fractional- mode [16]. CP device noise. For a 100-MHz reference as in [23], this duty
In order to obtain a high linearity of the PD, the current pulses cycle corresponds to a CP activation time of 3 ns, which
should be as steep as possible. This is achieved in our CP ar- is sufficiently large to linearize the PD, even if a MASH SDM
chitecture by the large swings and the steep waveforms of the with its large rms phase error is employed. The noise plateau
gate–source voltages toggling between VSS and VDD. As a re- is reduced by 10 dB as a result of the larger gate–source volt-
sult, the turn-on time and turn-off time are as low as 250 and ages and the small number of transistors. Remember that the
1922 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 8, AUGUST 2010

loop. Assuming a duty cycle of 20%, we obtain an

input-referred white phase noise of
. This corresponds to a phase noise of
or 159 dBc/Hz, following the remark after
(1). At the 10-GHz PLL output, this noise appears amplified by
MHz dB, resulting in an in-band
phase noise due to thermal CP noise of 119 dBc/Hz. This
noise level is negligible, compared to other noise sources, as
evident from Fig. 6.

VII. INTEGRATED PHASE ERROR AND TIMING JITTER

Fig. 11. Simulated output noise current PSD for new CP (lower curve) and
cascode CP.
Timing jitter and phase noise describe the same physical ef-
fect. Timing jitter describes the fluctuations of the zero crossings
of the output signal around the ideal values, whereas phase noise
is the corresponding frequency-domain equivalent. In radio-fre-
quency synthesizer design, the rms phase error is often used as
a metric to quantify the overall phase-noise performance. We
calculate the integrated rms phase error (in degrees) at the
PLL output by using

(46)

where we employ and MHz as

integration limits.
In high-speed digital design, the absolute PLL jitter (or
tracking jitter) is often used for noise characterization. It de-
scribes the deviation of the zero crossings of the output clock
from the ideal positions, where a clean input clock is assumed.
Absolute PLL jitter is given by

Fig. 12. Simulated output current PSD at 10 MHz as a function of CP duty
cycle  for I =4 mA.
noise corner of the CP is proportional to according to (15).
This long-term correlation effect is not correctly reflected by the
simulation, which overestimates the noise by a factor of
. For typical values of , this corresponds
to 10–20 dB. However, the white noise plateau is correctly mod-
eled. Therefore, we can expect a reduction in the in-band noise
contribution in the phase-noise plateau by 10 dB for the new CP.
As assumed in (15), the noise current PSD due to thermal
device noise is expected to be proportional to the CP duty cycle.
In order to confirm this assumption and to determine the ratio
, we have simulated the high-frequency
noise PSD over a wide range of . Fig. 12 shows the sim-
ulated device noise for different phase errors corresponding to
different CP duty cycles. For the white noise current PSD nor-
malized to the CP current , we found a value of
for this CP, which is an order of magnitude
lower than that for the cascode CP.
As an illustration, we consider a 10-GHz PLL driven by
a 100-MHz reference using a 4-mA CP in the fine-tuning
(47)
where is the ideal period of the PLL output signal. In
CDR circuits, the output signal is often referred to itself shifted
by a delay . For a very long delay , the autocorrelation of the
output signal converges to zero, and the self-referenced jitter
approaches a steady-state value . If white noise
sources dominate the phase noise, then we find for the long-term
jitter , as shown in [32].
In conclusion, the improvement of the CP will reduce not
only the phase noise but also the rms phase error, absolute jitter,
and long-term jitter. In order to predict the expected improve-
ment, we assume a reduction in white CP device noise by 10
dB and a reduction in by a factor of 10. These numbers are
consistent with the simulations presented in Section VI. Fig. 13
shows the simulated phase-noise spectrum and its components
for this case. The PD noise due to CP nonlinearity is now al-
most negligible, which can be understood from (38). Since the
PD phase noise is proportional to , the linearity improvement
by a factor of 10 will lower this phase-noise contribution by
20 dB. As a result, the integrated phase error is reduced from
1.43 to 0.75 . The latter value corresponds to an absolute jitter
of ps for our 10-GHz
HERZEL et al.: ANALYTICAL PHASE-NOISE MODELING AND CP OPTIMIZATION FOR FRACTIONAL-
Fig. 13. Modeled phase-noise spectrum for a 10-GHz synthesizer using the
novel CP for fine tuning.
PLL. This value is much lower than the best reported values for
CMOS clock generators [33].
VIII. CONCLUSION
We have presented analytical expressions for the phase-noise
spectrum of PLLs. The results have been visualized by
MATLAB. For an existing design, the thermal noise and non-
linearity of the CP have been found to be critical with respect to
phase noise. A method has been proposed to drastically reduce
these noise contributions. By using a dual-loop PLL topology
in conjunction with the novel CP, a very low PLL jitter is
predicted, which is robust with respect to PVT variations.
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1924 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 8, AUGUST 2010
Frank Herzel was born in Güstrow, Germany, in
1963. He received the M.S. degree from Berlin, Ger-
many, in 1989 and the Ph.D. degree from Rostock,
Germany, in 1993, both in theoretical physics.
Since 1993, he has been with the IHP, Frankfurt
(Oder), Germany, where he was mainly involved in
semiconductor device modeling until 1996. Since
then, he has been working on the design of silicon
ICs for RF communications. He is currently focusing
on SiGe BiCMOS frequency synthesizers for space
applications.
Sabbir A. Osmany was born in Bangladesh in 1975.
He received the M.S. degree in communications tech-
nology from the University of Ulm, Ulm, Germany,
where he is working toward the Ph.D. degree.
Since 2005, he has been with the IHP, Frankfurt
(Oder), Germany. His research interests include
mixed-signal and RF IC design for wireless or
optical communication, with emphasis on integer-N
N
and fractional- frequency synthesizers.
J. Christoph Scheytt (M’01) received the Diploma
degree (M.S.) and the Ph.D. degree (with highest
honors) from Ruhr-University, Bochum, Germany,
in 1996 and 2000, respectively.
In 2000, he cofounded advICo Microelectronics
GmbH, which is a German IC design house. For six
years, he served as CEO at advICo, where he was re-
sponsible for various projects in the area of wireless
and fiber-optic IC design. Since 2006, he has been
with the IHP, Frankfurt (Oder), Germany, where he
is the Head of the Circuit Design Department, which
is a group of about 30 researchers working on high-frequency and broadband IC
design. He has authored and coauthored more than 40 papers. He is the holder
of six patents. His research interests include RFIC and broadband IC design,
PLL techniques, and design with SiGe BiCMOS technologies.