5 views

Uploaded by Ma Seenivasan

Nanowire Mosfet

- 1M0565R
- MOSFET IRFZ44
- MOSFET
- Contoh Assignment PO11
- cmos01_1up
- AO7410
- FDN5618P-888996
- cadtutorial_03
- LinearAppNote363-ReplaceOringDiodesWithMosfets
- datasheet_6
- 62-6536602
- Tk40j60u Transistor n Mosfet
- 7445.pdf
- inyeccion mosfet
- BS170 N-Channel DMOS Transistor Datasheet
- 2N7000-D
- DSA00266672.pdf
- 0hwte31242z7a5lekkeuakcopfky.pdf
- Comparative Analysis of Technology Advancement From Single Gate to Multi-gate Mosfet
- 2SK3298.pdf

You are on page 1of 10

4, APRIL 2010

Schottky Gate-All-Around Si-Nanowire MOSFETs

Guojun Zhu, Student Member, IEEE, Xing Zhou, Senior Member, IEEE, Yoke-King Chin,

Kin Leong Pey, Senior Member, IEEE, Junbin Zhang, Guan Huei See,

Shihuan Lin, Yafei Yan, and Zuhui Chen, Member, IEEE

els and a unique subcircuit approach to physically and accurately

model the dopant-segregated Schottky (DSS) gate-all-around

(GAA) Si-nanowire (SiNW) MOSFETs. The direct current char-

acteristics of the DSS GAA SiNW MOSFETs are investigated

through numerical simulations and fabricated devices. Transport

mechanisms are studied and explained with numerical devices

from ambipolar thermionic tunneling to unipolar drift–diffusion

and a combination of both as the dopant segregation doping

and thickness are varied. The convex curvature in the Ids –Vds

characteristics is accurately reproduced by the subcircuit compact

model, and it is shown for the first time that such a unique gds –Vds

characteristic in DSS devices is only feasible to be modeled by the

subcircuit approach.

Fig. 1. Schematic of an ideal DSS GAA SiNW MOSFET: cross sections (left)

Index Terms—Ambipolar, compact model, dopant-segregated along S/D and (upper right) along radial. The n-channel DSS subcircuit model

Schottky (DSS), drift–diffusion (DD), gate-all-around (GAA), is shown in the lower right side. The nominal device parameters are Lg =

gate-induced drain leakage (GIDL), MOSFET, Schottky barrier 100 nm, R = 10 nm, Tox = 2 nm, Nseg = 1020 cm−3 , and Lseg = 10 nm,

(SB), subcircuit, thermionic tunneling (TT), unipolar. which are the default physical parameters values, unless otherwise stated. The

work function ΦM at S/D is 4.7 eV, corresponding to a barrier height ΦB of

0.53 eV for electrons.

I. I NTRODUCTION

terparts, and the OFF-state leakage current is larger due to

A S CONVENTIONAL bulk MOSFETs are approaching

the end of the technology roadmap, various alternatives

are being explored. MOSFETs with Schottky barrier (SB)

hole injection from the drain-side SB junction. To improve

the performance of SB MOSFETs, various methods have been

proposed, e.g., the use of thin interfacial layers [8], [9] or

source/drain (S/D) are viewed as very promising candidates due

group VI valence-mending adsorbates [10]–[14] and dopant

to their low parasitic S/D resistance and superior scalability [1],

segregation (DS) techniques [15]–[25], among which the

with additional advantages such as low thermal budget since

DS technique is most widely used.

metal silicides are formed at low temperatures and the high-

The concept of DS technique, which employs a very thin

temperature activation of S/D dopants is eliminated. In recent

but high dopant concentration layer at the metal/Si interface,

years, SB MOSFETs with various kinds of structures have been

is shown in Fig. 1. In this paper, we assume that the S/D is

fabricated, e.g., SB silicon-on-insulator (SOI) [2], SB-FinFET

perfectly aligned with the gate without any overlap/underlap.

[3], and SB Si-nanowire (SiNW) MOSFETs [4]–[7]. However,

Experimental studies [22] have shown that the DS changes the

due to the existence of the SB at the S/D junctions, the ON-state

leakage mechanism from SB tunneling (SBT) to gate-induced

current of SB MOSFETs is lower than its conventional coun-

drain leakage (GIDL) current due to band-to-band tunneling

(BTBT); at the same time, the ON-state transport changes from

Manuscript received September 21, 2009; revised January 4, 2010. First the ambipolar thermionic tunneling (TT) current to the unipo-

published February 22, 2010; current version published April 2, 2010. This lar drift–diffusion (DD) current. From numerical simulations,

work was supported in part by the Institute for Sustainable Nanoelectronics,

Nanyang Technological University, and in part by Semiconductor Research

we find that the characteristics of dopant-segregated Schottky

Corporation under Contract 2004-VJ-1166G. The review of this paper was (DSS) MOSFETs are very sensitive to the physical parameters

arranged by Editor M. Reed. such as the length and dopant concentration in the segregation

G. Zhu, X. Zhou, Y.-K. Chin, K. L. Pey, J. Zhang, S. Lin,

Y. Yan, and Z. Chen are with the School of Electrical and Electronic region. Carrier transport could be DD or TT dominant, or a

Engineering, Nanyang Technological University, Singapore 639798 (e-mail: combination of both, which depends on the DS-related parame-

zhug0002@ntu.edu.sg; exzhou@ntu.edu.sg; chin0102@ntu.edu.sg; eklpey@ ters. For either DD- or TT-dominant carrier transport, compact

ntu.edu.sg; e070054@ntu.edu.sg; lins0026@ntu.edu.sg; yanyf@ntu.edu.sg;

zhchen@ntu.edu.sg). models have been developed, respectively, by the authors to

G. H. See is with GLOBALFOUNDRIES Singapore Pte. Ltd., Singapore fully characterize the corresponding devices [26], [27]. For

738406 (e-mail: seegh@globalfoundries.com). DSS devices whose carrier transport is coupled with both DD

Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org. and TT mechanisms, formulation of analytical device models

Digital Object Identifier 10.1109/TED.2010.2041513 is nontrivial. Analytical formulations to solve the coupled

0018-9383/$26.00 © 2010 IEEE

ZHU et al.: DOPANT-SEGREGATED SCHOTTKY GATE-ALL-AROUND Si-NANOWIRE MOSFETs 773

(circles) SiNW MOSFETs at (solid) Vds = −0.05 V and (open) −1 V. The

inset shows the p-channel DSS subcircuit model conceptualized as a Schottky

diode in conjunction with the intrinsic Si channel MOSFET and a resistor at the

drain end.

is only possible when very simple equations are used, and

therefore, it is not able to include major short-channel effects.

Moreover, for SB MOSFETs, the carrier transport is dominated

by TT, and the DD inside the channel actually plays a neg-

ligible role.

In this paper, the characteristics of DSS gate-all-around

(GAA) SiNW MOSFETs are first investigated through 2-D nu-

merical simulations and fabricated devices. For devices whose

carrier transport involves both DD and TT mechanisms, we

demonstrate analytical device models and a unique subcircuit

approach, which shows very good agreement with both numer-

ical simulations and experimental data and is able to accurately

reproduce the convex curvature in the Ids –Vds characteristics Fig. 3. Extracted energy-band diagrams from Medici simulations for

[29]. There is no attempt to calibrate Medici to match experi- (a) conventional MOSFET, (b) SB MOSFET, and (c) DSS MOSFET at various

Vgs from −0.4 to 2 V with a step of 0.2 V and Vds = 1.2 V. The subcircuit

mental device characteristics. components for each structure are indicated by the corresponding subcircuit

symbols.

II. D EVICE FABRICATION AND N UMERICAL S IMULATION at the SiNW surface from source to drain) are extracted for

gate voltages ranging from −0.4 to 2 V (with a 0.2-V step), as

Experimental DSS SiNW MOSFETs have been fabricated shown in Fig. 3. From the potential profiles across the channel,

on 200-mm p-type (100) SOI wafers. The detailed fabrication transport mechanisms for each device can be identified. For the

process has been reported in [30]. A sample result for the p-n junction S/D MOSFET in Fig. 3(a), conventional diffusion

p-channel DSS device (with BF2 implant at 1 × 1015 cm−2 and drift currents at low and high gate biases, respectively, are

dose and 10 keV energy for the DS layer) and the SB device apparent from the potential gradients. For the SB MOSFET

(without BF2 implant) is shown in Fig. 2 [29], which shows that without DS in Fig. 3(b), the potential distributions inside the

DSS devices have superior performance. Due to the existence channel are very flat for all gate biases, indicating no drift cur-

of the SB at S/D sides, SB MOSFETs suffer from low ON-state rent, and the carrier transport is dominated by TT current. For

current and high OFF-state leakage current. With ultrathin DS, the DSS MOSFET in Fig. 3(c), the channel potential profiles are

the carrier transport demonstrates DD-like behaviors, and the similar to conventional DD counterparts while carrier injection

leakage current becomes GIDL-like. into the channel from the source is obviously due to TT, similar

Recently, we have used pulsed excimer laser anneal (ELA), to the SB counterpart. The drain side, however, is different from

prior to silicidation, to achieve diffusion-less activation and that in Fig. 3(b) without hole injection from the SB, which can

improved segregation as an approach to further reduce the be modeled by a resistor (Rd ) as a first-order approximation.

effective Schottky barrier height (SBH) in GAA DSS SiNW It may have BTBT due to the high gate field in the drain-side

transistors [31]. ELA-DSS MOSFETs outperform DSS coun- DS region, which is modeled by the GIDL current.

terparts in both drive currents and short-channel effects.

Three numerical GAA n-channel MOSFETs (with the nom-

III. M ODEL F ORMULATION

inal parameters shown in Fig. 1) are simulated by Medici,

each representing the conventional, SB, and DSS MOSFET, The DSS device has two types, namely, n-channel and

respectively. Energy-band diagrams (from the intrinsic band p-channel, depending on the type of dopant in the DS layer.

774 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 4, APRIL 2010

For model formulations, we follow the nMOS convention, B. Schottky Diode Model

and pMOS equations can be readily available by terminal-

The Schottky diode at the source end, which plays a very

bias polarity changes. The n-channel DSS MOSFET can be

important role in DSS MOSFETs, must be physically modeled.

conceptually separated into three components, namely, a gated

The diode current consists of both thermionic (Ith ) and tunnel-

Schottky diode (GSD) at the source junction whose anode

ing (Itun ) currents.

potential (Vs ) is dependent on the gate voltage Vg , an intrin-

The thermionic current is given as [36]

sic Si channel, and a resistor at the drain end, as shown in

the lower right of Fig. 1 as well as in Fig. 3(c) for n-type ΦB,s VA − Rs Ith

Ith = AA∗n T 2 exp − exp −1

DSS devices. The polarity of the GSD is forward biased, vth nvth

different from the normal SB diode, since the electrons are (4)

injecting from the silicide to the (n-type) semiconductor in nor-

where VA = Vs − Vs is the voltage drop across the GSD. A is

mal operations. Internal nodes are introduced, whose voltages

the area of the SB/intrinsic-channel interface. A∗n is the electron

(Vs and Vd ) can be solved by a circuit simulator in the subcircuit

Richardson constant. ΦB,s is the effective SBH at the source

model. The key model formulations for the current components

junction. n is the ideality factor, which is an adjustable model

will be given in the ensuing sections.

parameter. Vs is the internal node voltage between the source

SB junction and intrinsic Si channel. For more accurate model-

A. DD Model ing, an internal resistor Rs for the GSD is included in the right-

hand side of (4), which is the underestimated approximation

The DD current in conventional nMOSFETs is given as known as the “Bethe diode” equation [37]. Ith can be further

[32], [33] expressed using the L{w} function based on (4)

L {Ath Bth exp(−Bth Is )}

Ids = Idrift + Idiﬀ Ith = Is − (5)

Bth

dφs dQi (y)

= − μs W Qi (y) + μs W vth . (1) where

dy dy

∗ ΦB,s

In the case of SiNW MOSFETs, following the DD formu- Is = AA T exp −

2

(5a)

vth

lation, the surface-potential-based drain current model for the

Vs − Vs

intrinsic Si channel is given by [26], [34], [35] Ath = Is exp − (5b)

nvth

πR Rs

Ids = 2μCox (Vgf − φs + 2vth )Δφs Bth =

nvth

. (5c)

L

≈ 2μCox

πR

(Vgf − φs + 2vth )Vds,eﬀ (2) At low currents when Rs Ith (Vs − Vs ), Ith has the diode

L exponential form. At high currents, Ith becomes linear and

behaves like a resistor.

where μ is the carrier mobility, Vgf ≡ Vg − VFB is the flatband- The tunneling current is given as [28]

shifted gate voltage, Cox = εox /[R ln(1 + Tox /R)] is the cylin-

drical gate capacitance, and vth = kB T /q is the thermal q 2 Fs2 8π

Itun = A exp − 2m∗n (qΦB,s )3 (6)

voltage. Vds,eﬀ is the effective terminal drain–source voltage 8πhΦB,s 3hq|Fs |

including velocity saturation/overshoot effects. φs in (2) is the

Vg -dependent surface potential without the lateral-field effect, where h is the Planck constant. m∗n is the electron ef-

which is given as fective mass. Fs is the electric field at the source-end

metal/semiconductor interface, which is expressed as

φs = Vgf − 2vth L

Υi (Vgf −Vc (y))/2vth

√ e (3) Vs − Vs

2 vth Fs = (7)

λdep,s

where Υi = (2qεSi ni )1/2 /Cox is the intrinsic body factor. in which λdep,s is the depletion width induced by the source-

Vc (y) is the channel voltage, which equals the internal Vs at end SB and is approximately given by

the source end and Vd at the drain end. L{w} is the Lambert W

function. λdep,s = 2εSi ΦB,s /qNseg,s (8)

All major second-order effects, such as S/D series resistance,

where Nseg,s is the dopant concentration in the source-end

channel-length modulation, drain-induced barrier lowering, ve-

segregation region.

locity saturation/overshoot, and vertical/lateral-field mobility

The current-continuity condition requires that the total GSD

degradation, have been built into the core model as given in [26]

TT current, given by

and [34]. The detailed model validation with experimental data

can be found in [35], which shows that the unified model can Isb = Ith + Itun (9)

excellently match the drain current as well as its higher order

derivatives. be equal to the transistor DD current (Ids ) in (2).

ZHU et al.: DOPANT-SEGREGATED SCHOTTKY GATE-ALL-AROUND Si-NANOWIRE MOSFETs 775

For DSS MOSFETs, the DS layer creates a very narrow The aforementioned GIDL model can quite accurately repro-

tunneling width due to the high concentration, which leads to a duce the measured GIDL current in DSS MOSFETs, as shown

high tunneling current. At the same time, the ultrahigh electric in Fig. 2. Models for SBT-induced leakage can be found in [27]

field induced by the DS layer causes a large Schottky barrier and will not be discussed in detail.

lowering (SBL) effect due to the image force [38] and leads to a

larger thermionic current. Physical modeling of the SBL effect IV. R ESULTS AND D ISCUSSION

usually requires self-consistent iterations [23]. For simplicity,

we did not include the SBL effect in the model. The inaccuracy In this section, we show the compact subcircuit model

can be compensated by the adjustable model parameters (e.g., (Xsim) results in comparison with both (Medici) numerical

ΦB ) during actual data fitting. Ith usually dominates over Itun simulations and experimental data. Numerical investigation on

in the subthreshold (low Vgs ) and linear (low Vds ) regions the leakage mechanism of DSS MOSFETs is also presented.

since the barrier width is relatively wide. This can be justified For SB MOSFETs without DS, the carrier transport is dom-

from Fig. 2, which shows that the subthreshold region of a inated by TT current, which is evident from the energy-band

DSS MOSFET is very similar to the diffusion transport in diagram shown in Fig. 3(b) and the drain current has been

conventional MOSFETs. In the strong-inversion and saturation very well modeled by the quasi-2-D compact model [27].

regions, channel drift current plays a more important role in Electron tunneling occurs from source-side SB for positive

DSS devices. In this study, we adopt a subcircuit approach Vgs , whereas hole tunneling occurs from drain-side SB for

rather than pursuing analytical derivations for the coupled TT negative Vgs . After introducing the DS, the dc characteristic

and DD solutions. Both the GSD TT and intrinsic-channel DD is changed from ambipolar to unipolar transport, as shown

models are separately implemented in Hspice using Verilog-A, in Fig. 2. Fig. 3(b) shows the extracted energy-band diagram

which is simulated to obtain the internal node voltage Vs . of a DSS device with Lseg,s(d) = 10 nm and Nseg,s(d) =

1 × 1020 cm−3 . Electrons first tunnel from source-side SB

into the intrinsic Si channel, where the carrier transport is

C. GIDL dominated by DD. Hole injection from drain-side SB is ba-

When Nseg,d is high or Lseg,d is long in the drain-end sically blocked, and the leakage is mainly due to BTBT in

segregation region, a high electric field is induced by the gate the gate–drain overlap region. Therefore, the carrier transport

in the gate-to-drain overlap region, leading to GIDL, which can of the DSS device can be viewed as a combination of TT

be due to BTBT or trap-assisted tunneling. Normally, BTBT is from the source-side SB and DD inside the intrinsic Si chan-

assumed to be dominant. The BTBT current in the drain-end nel, together with a drain-side resistor to model the drain-end

overlap region can be approximated by [39] DS region.

To understand the leakage mechanism of DSS MOSFETs so

BGIDL as to optimize the device performance, numerical simulations

IGIDL ∝ 2πRLseg,d Eseg,d

2

exp − (10)

Eseg,d are performed, and the results are shown in Figs. 4 and 5.

The physical parameters for the source-side segregation layer

where BGIDL is a physics-based parameter with a theoretical

(Nseg,s and Lseg,s ) are fixed at relatively large values to ensure

value of 21.3 MV/cm. Eseg,d is the electric field in the drain

partial depletion and therefore maintain high ON-state current.

overlap region, given as

Nseg,d and Lseg,d at the drain side are varied separately to study

Cox 2 their impact on the leakage current. The BTBT model used by

Eseg,d = Vseg,d + (CGIDL Vds )2 (11) Medici has the form of Kane’s model [41]. The effective masses

εSi

used in the SBT model have the following values: 0.22m0

in which CGIDL is a fitting parameter. Vseg,d is the gate–drain for electrons and 0.35m0 for holes, where m0 is the electron

voltage across the oxide, given by rest mass.

Fig. 4 shows the effect of Nseg,d on the leakage current.

Vseg,d = Vg − VFB_seg,d − φs_seg,d (12) For Nseg,d greater than 5 × 1019 cm−3 , the segregation layer

is partially depleted, hole injection from drain-side SB is

where VFB_seg,d and φs_seg,d are the flatband voltage and

blocked, and the leakage current is mainly due to BTBT. For

surface potential, respectively, in the drain overlap region; the

BTBT-dominated leakage, it is undesirable to have a very high

latter can be obtained using the unified regional approach [40].

Nseg,d since higher Nseg,d induces larger electric field, which

The final expression for the GIDL current is written as

leads to larger leakage (GIDL) current. Nseg,d can neither be

BGIDL too small, which will make the segregation layer fully depleted,

2

IGIDL = AGIDL Vds Eseg,d exp − (13) and the leakage current will be dominated by the hole injection

Eseg,d

from the SB. As shown in Fig. 4(b), once Nseg,d is below

where AGIDL is a model parameter proportional to 2πRLseg,d . 1 × 1018 cm−3 , the energy-band diagram becomes independent

The above analytical equations clearly show the relationship of Nseg,d . Because of the dual role of the segregation layer,

between IGIDL and Nseg,d and Lseg,d . A longer segregation which requires higher dopant concentration to improve drive

length gives a larger overlap region, which increases the GIDL current and slightly lower dopant concentration to suppress

current. A higher Nseg,d leads to a larger electric field, which leakage, asymmetric structure [22] could be advantageous for

can also increase the GIDL current. practical applications.

776 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 4, APRIL 2010

for DSS nMOSFET (Lg = 100 nm, R = 10 nm, Tox = 2 nm, Nseg =

1020 cm−3 , and Lseg = 10 nm). Output conductance at Vgs = 1.2 V is given

in the inset, which shows the convex curvature.

neither be too short, which will make the segregation layer

fully depleted, and the leakage current will be dominated by

hole injection from the drain-side SB. These observations can

be further supported by the extracted energy-band transitions at

different Lseg,d , as shown in Fig. 5(b). For DSS devices with

Fig. 4. (a) Leakage current characteristics of DSS MOSFETs with various

dopant concentrations in the drain-side segregation region. (b) Corresponding

different SBH at S/D, although the optimal values for Nseg,d

energy-band diagrams, which explains the transition from BTBT-induced GIDL and Lseg,d could be different since the onset of partial depletion

current to SBT-induced leakage current. is changed, the aforementioned analysis still holds.

Although the Ids –Vgs characteristic of a DSS MOSFET

behaves similarly to the conventional counterpart, as shown in

the previous figures, its Ids –Vds characteristic shows a convex

curvature in the linear region while resembling the conventional

MOSFETs in the saturation region, as shown in Fig. 6. Similar

convex curvature can also be observed in SB MOSFET due

to Schottky diode at the source end, which can be accurately

reproduced by the quasi-2-D model [27]. For DSS MOSFETs,

such characteristics cannot be captured by either the conven-

tional DD-MOSFET model [26] or SB-MOSFET model [27],

but it can be very well reproduced by the subcircuit model pre-

sented in this paper. Fig. 6 shows the subcircuit model in com-

parison with the numerical device. The calibrated subcircuit

model shows good agreement with the numerical simulation,

in particular, the convex curvature, as shown in the inset by the

output-conductance characteristic.

To gain deeper insights into the convex curvature, we play

back the individual components of the subcircuit model, as

shown in Fig. 7(a), with the same parameters and bias con-

ditions as the one in Fig. 6 at Vgs = 1.2 V. The analysis is

similar to the 2-D numerical study [42] for the investigation of

the potential distribution inside the SB MOSFETs. The result

from the complete subcircuit model (schematic in Fig. 1) is

Fig. 5. (a) Leakage current characteristics of DSS MOSFETs with various DS shown by the circles. Each component of the subcircuit is

lengths in the drain-side segregation region. (b) Corresponding energy-band

diagrams, which explains the gradual transition from BTBT-induced GIDL calculated with the other two short circuited, all plotted as a

current to SBT-induced leakage current. function of Vds . At any given current level, the sum of the

voltage drops across the drain resistance (Vd − Vd , diamonds),

Fig. 5 shows the effects of Lseg,d on the leakage current. intrinsic channel (Vd − Vs , triangles), and SB diode (Vs − Vs ,

For Lseg,d longer than 4 nm (with Nseg,d = 1 × 1020 cm−3 ), squares) is always equal to Vds , the total voltage across the three

the segregation layer is partially depleted, hole injection from subcircuit elements. This is further confirmed by the zoomed-

drain-side SB is blocked, and the leakage current is contributed in plot in Fig. 7(b), as indicated at two current levels. The dc

by BTBT. For BTBT-dominated leakage, it is undesirable to resistance (Vds /Ids ) for each component is calculated, and their

have a long Lseg,d since longer Lseg,d gives a larger overlap sum is shown by the dashed line in Fig. 7(c), which tallies with

ZHU et al.: DOPANT-SEGREGATED SCHOTTKY GATE-ALL-AROUND Si-NANOWIRE MOSFETs 777

(c) Vd − Vs versus terminal Vds from the subcircuit model at different Vgs ,

as indicated. (d) Voltage distribution across the whole channel at Vgs = 0.3 V.

the thermionic current Ith , modeled by the Lambert W function

(5), as shown by the circle in Fig. 7(e). With a further increase in

Vds , the tunneling current Itun from (6), shown by the triangle

in Fig. 7(e), starts to contribute to the GSD current Isb , which

may have a minor influence on the total ac output resistance

but no effect on the dc current and dc resistance as the intrinsic

Fig. 7. (a) Model playback of the (circle) subcircuit model and the individual channel is pinched off. Fig. 7(e) clearly shows three distinct

components: (square) Schottky diode including internal Rs ; (triangle) intrin-

sic channel; and (diamond) drain-end resistance Rd . (b) Zoomed-in plot at regions of the GSD current (square), namely, exponential or

low Vds < 0.6 V, showing that the total voltage drop across the subcircuit thermionic dominant at low Vds , resistive at medium Vds , and

model (Vds ) is the sum of the voltage drops across the drain resistance tunneling dominant at high Vds .

(Vd − Vd ), intrinsic channel (Vd − Vs ), and GSD (Vs − Vs ) at any given

drain current (two indicated), as calculated by the circuit simulator. (c) DC The internal voltage distributions, Vs − Vs , Vd − Vd , and

resistance (Vds /Ids ) of the individual components in (a). (d) AC (differential) Vd − Vs , obtained from the circuit simulator, are shown in

conductance (dIds /dVds ) of the individual components in (a). (e) Thermionic Fig. 8(a)–(c), respectively. The source-side internal Vs in-

(Ith ) and tunneling (Itun ) components of the GSD total current (Isb ).

N-DSS: Lg = 100 nm, R = 10 nm, Tox = 2 nm, Nseg = 1020 cm−3 , and creases initially when the intrinsic channel is in the linear region

Lseg = 10 nm. with a small voltage drop, and it saturates once the channel

is pinched off and the current starts to be controlled by the

intrinsic channel. Similarly, the drain-side voltage drop Vd − Vd

the dc resistance from the subcircuit model (circle). It can be across the resistor increases initially when the intrinsic channel

seen that the DSS terminal current is dominated by the SB diode is in the linear region and it saturates once the channel is

at low Vds and by the intrinsic-channel MOSFET at high Vds . pinched off. Fig. 8(c) shows the voltage drop across the intrinsic

This is a unique feature of DSS devices [as in Fig. 3(c)], which channel. At low Vds , most of the voltage drops across the GSD

gives rise to the unique convex curvature in Ids at low Vds at the source side due to its large differential resistance com-

and high Vgs , not observable in conventional MOSFETs pared to the intrinsic-channel MOSFET, as shown in Fig. 8(d).

[as in Fig. 3(a)]. Finally, the subcircuit model is verified with the experimental

The small-signal ac conductance for each component is short-channel devices, as shown in Fig. 9. Two devices from

shown in Fig. 7(d), which explains the observed convex curva- the same wafer are selected. The first one shows the con-

ture at very low Vds . At low Vds and high Vgs , the current is low ventional behavior, whereas the second one shows a convex

and the intrinsic channel is linear, and most of the applied bias curvature at low Vds and high Vgs . The saturation currents for

Vds is dropped across the SB diode, which takes the exponential both devices have the same magnitude, which rules out the

form since the voltage drop across its internal resistor (Rs ) is possibility that the second device is a pure SB MOSFET whose

also small. This gives rise to the convex curvature in Ids or the saturation current is usually much smaller than its conventional

decreasing gds as Vds approaches zero. The exact shape of gds counterparts. Neither the SB-MOSFET model [27] nor the

should also depend on the drain-side DSS layer, which may not conventional MOSFET model [26] is able to capture such

be fully captured by our simple Rd subcircuit model. behaviors. However, by using the subcircuit approach, the drain

778 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 4, APRIL 2010

Fig. 10. Model playback of a long-channel device (Lg = 1 μm). (a) Impact

of the saturation current Is on the dc characteristics of DSS MOSFETs. The

smaller the value of Is is, the more convex the curvature becomes, as can be

justified from the output conductance shown in the inset. (b) Impact of ideality

factor n on the dc characteristics of DSS MOSFETs. The larger the value of n

is, the more convex the curvature becomes, as can be justified from the output

conductance shown in the inset.

SBH would greatly boost the device performance. However,

in practice, due to Fermi-level pinning, the SBH is always

Fig. 9. (Lines) Model comparison with (symbols) measurement data for two quite large regardless of the metal or silicide work function

DSS devices in (a) and (b), respectively. Output conductance of the two devices [43]–[48]. Similarly, Fig. 10(b) shows that for larger ideality

is given in (c).

factor n, the curvature in the linear region turns out to be

more convex. As n approaches zero, the curvature gradually

current as well as the convex curvature for the second device returns to the conventional (concave) behavior. This can also

can be accurately reproduced, which is further justified from the be justified from the output conductance shown in the inset.

characteristics of the output conductances of the two devices, The practical value of the ideality factor is usually between 1

as shown in Fig. 9(c). This interesting difference between the and 2. Therefore, the fluctuation of SBH at the S/D junction is

two devices is believed to be due to process variations, which believed to be the dominant cause for the device performance

are normally very severe in SB/DSS MOSFETs. One major variations. During model calibration, n and Is can be tuned

source of fluctuations is the SBH, which is highly sensitive together to better fit the data and to compensate for other

to the interface states/traps at the silicide/silicon junction. Due possible process fluctuations, such as variations in the length

to the exponential dependence on the SBH, even a very small and doping concentration in the segregation region.

variation in the SBH can lead to a huge variation in reverse The presented subcircuit modeling approach is, however, not

saturation current Is . In practice and model calibration, since limited to DSS MOSFETs and can be readily applied to model

the SBH and electron effective mass can hardly be determined, the convex curvature observed in some FinFET devices [49],

the reverse saturation current Is is considered as an adjustable [50], which is believed to be caused by the nonideal ohmic

fitting parameter for flexibility, which can be related to the SBH contact at the S/D junctions.

by (5a) if other parameters are known. The ideality factor n is

another source of variation that would distort the I–V behavior

V. C ONCLUSION

of DSS MOSFETs. Fluctuations in these model parameters

could have great impact on the dc characteristics, as shown In conclusion, we have demonstrated analytical device mod-

in Fig. 10 from the model playback of a long-channel device. els and a unique subcircuit approach to physically and accu-

The effect of saturation current Is (and the corresponding rately model the DSS GAA SiNW MOSFETs. The proposed

SBH ΦB,s ) is shown in Fig. 10(a), which shows that the larger subcircuit device model shows very good agreement with both

Is is, the less convex the curvature becomes. According to (5a), numerical simulations and experimental data with physical

a larger Is corresponds to a smaller SBH, which is expected to parameter scalability. The convex curvature in the Ids –Vds

ZHU et al.: DOPANT-SEGREGATED SCHOTTKY GATE-ALL-AROUND Si-NANOWIRE MOSFETs 779

characteristics at low drain and high gate biases has been engineering with dopant segregation technique,” in VLSI Symp. Tech.

explained and accurately reproduced via the subcircuit compact Dig., 2004, pp. 168–169.

[17] A. Kinoshita, C. Tanaka, K. Uchida, and J. Koga, “High-performance

model. Although the detailed curvature in that region, which 50 nm-gate-length Schottky-source/drain MOSFETs with dopant-

has not been physically modeled so far to the best of our segregation junctions,” in VLSI Symp. Tech. Dig., 2005, pp. 158–159.

knowledge, may not have practical importance for analog and [18] M. Zhang, J. Knoch, Q. T. Zhao, S. Lenk, U. Breuer, and

S. Mantl, “Schottky barrier height modulation using dopant

digital circuits, its physical modeling is of paramount impor- segregation in Schottky-barrier SOI-MOSFET,” in Proc. ESSDERC,

tance. Without the subcircuit model to solve for the coupled TT 2005, pp. 457–460.

and DD carrier transport, the conventional DD model would [19] B. Y. Tsui and C. Lin, “Process and characteristics of modified

Schottky barrier (MSB) p-channel FinFETs,” IEEE Trans. Electron De-

overestimate saturation current (that has to be tuned unphysi- vices, vol. 52, no. 11, pp. 2455–2462, Nov. 2005.

cally to match the actual data), whereas the ambipolar TT model [20] Z. Qiu, Z. Zhang, M. Östling, and S. L. Zhang, “A comparative study

would give incorrect tunneling-dominant current in strong- of two different schemes to dopant segregation at NiSi/Si and PtSi/Si

interfaces for Schottky barrier height lowering,” IEEE Trans. Electron

inversion and saturation regions. The proposed subcircuit com- Devices, vol. 55, no. 1, pp. 396–403, Jan. 2008.

pact modeling approach represents a unique way for solving [21] S. Matsumoto, M. Nishisaka, and T. Asano, “CMOS application of Schot-

coupled equations and a trend for future transistor compact tky source/drain SOI MOSFET with shallow doped extension,” Jpn. J.

Appl. Phys., vol. 43, no. 4B, pp. 2170–2175, Apr. 2004.

modeling. [22] T. Hoffmann, G. Doornbos, I. Ferain, N. Collaert, P. Zimmerman,

M. Goodwin, R. Rooyackers, A. Kottantharayil, Y. Yim, A. Dixit,

K. De Meyer, M. Jurczak, and S. Biesemans, “GIDL (gate-induced

R EFERENCES drain leakage) and parasitic Schottky barrier leakage elimination in ag-

[1] J. M. Larson and J. P. Snyder, “Overview and status of metal S/D Schottky gressively scaled HfO2 /TiN FinFET devices,” in IEDM Tech. Dig., 2005,

barrier MOSFET technology,” IEEE Trans. Electron Devices, vol. 53, pp. 725–728.

no. 5, pp. 1048–1058, May 2006. [23] R. A. Vega and T.-J. K. Liu, “A comparative study of dopant-

[2] J. Knoch, M. Zhang, S. Mantl, and J. Appenzeller, “On the performance segregated Schottky and raised source/drain double-gate MOSFETs,”

of single-gated ultrathin-body SOI Schottky-barrier MOSFETs,” IEEE IEEE Trans. Electron Devices, vol. 55, no. 10, pp. 2665–2677,

Trans. Electron Devices, vol. 53, no. 7, pp. 1669–1674, Jul. 2006. Oct. 2008.

[3] T. P. Lee, E. J. Lim, K. M. Tan, T. Y. Liow, G. Q. Lo, G. S. Samudra, [24] F. F. Huang and B. Y. Tsui, “Short-channel metal-gate TFTs with modified

D. Z. Chi, and Y. C. Yeo, “N-channel FinFETs with 25-nm gate length Schottky-barrier source/drain,” IEEE Electron Device Lett., vol. 27, no. 1,

and Schottky-barrier source and drain featuring ytterbium silicide,” IEEE pp. 43–45, Jan. 2006.

Electron Device Lett., vol. 28, no. 2, pp. 164–167, Feb. 2007. [25] Z. Zhang, Z. J. Qiu, P. E. Hellstrom, G. Malm, J. Olsson, J. Lu, M. Östling,

[4] Y. K. Chin, K. L. Pey, N. Singh, G. Q. Lo, L. Chan, L. H. Tan, and and S. L. Zhang, “SB-MOSFETs in UTB-SOI featuring PtSi source/drain

E. J. Tan, “Effect of nickel silicide intrusion on Schottky barrier nanowire with dopant segregation,” IEEE Electron Device Lett., vol. 29, no. 1,

MOSFET fabricated using top-down technology,” in Proc. SSDM, 2008, pp. 125–127, Jan. 2008.

pp. 436–437. [26] G. J. Zhu, G. H. See, S. H. Lin, and X. Zhou, ““Ground-referenced” model

[5] J. W. Peng, S. J. Lee, G. C. A. Liang, N. Singh, S. Y. Zhu, G. Q. Lo, and for three-terminal symmetric double-gate MOSFETs with source/drain

D. L. Kwong, “Improved carrier injection in gate-all-around Schottky symmetry,” IEEE Trans. Electron Devices, vol. 55, no. 9, pp. 2526–2530,

barrier silicon nanowire field-effect transistors,” Appl. Phys. Lett., vol. 93, Sep. 2008.

no. 7, p. 073 503, Aug. 2008. [27] G. J. Zhu, X. Zhou, T. S. Lee, L. K. Ang, G. H. See, S. H. Lin,

[6] E. J. Tan, K. L. Pey, N. Singh, G. Q. Lo, D. Z. Chi, Y. K. Chin, K. M. Hoe, Y. K. Chin, and K. L. Pey, “A compact model for undoped silicon

G. Cui, and P. S. Lee, “Demonstration of Schottky barrier NMOS tran- nanowire MOSFETs with Schottky barrier source/drain,” IEEE Trans.

sistors with erbium silicided source/drain and silicon nanowire channel,” Electron Devices, vol. 56, no. 5, pp. 1100–1109, May 2009.

IEEE Electron Device Lett., vol. 29, no. 10, pp. 1167–1170, Oct. 2008. [28] M. Jang, K. Kang, S. Lee, and K. Park, “Simulation of Schottky barrier

[7] E. J. Tan, K. L. Pey, N. Singh, G. Q. Lo, D. Z. Chi, Y. K. Chin, L. J. Tang, tunneling transistor using simple boundary condition,” Appl. Phys. Lett.,

P. S. Lee, and C. K. F. Ho, “Nickel-silicided Schottky junction CMOS vol. 2, no. 16, pp. 2718–2720, Apr. 2003.

transistors with gate-all-around nanowire channels,” IEEE Electron De- [29] G. J. Zhu, X. Zhou, Y. K. Chin, K. L. Pey, G. H. See, S. H. Lin,

vice Lett., vol. 29, no. 8, pp. 902–905, Aug. 2008. J. B. Zhang, and Z. H. Chen, “Subcircuit compact model for dopant-

[8] D. Connelly, C. Faulkner, D. E. Grupp, and D. J. S. Harris, “A new route segregated Schottky silicon-nanowire MOSFETs,” in Proc. SSDM, 2009,

to zero-barrier metal source/drain MOSFETs,” IEEE Trans. Nanotechnol., pp. 402–403.

vol. 3, no. 1, pp. 98–104, Mar. 2004. [30] Y. K. Chin, K.-L. Pey, N. Singh, G.-Q. Lo, K. H. Tan, C.-Y. Ong, and

[9] D. Connelly, C. Faulkner, P. A. Clifton, and D. E. Grupp, “Fermi-level L. H. Tan, “Dopant-segregated Schottky silicon-nanowire MOSFETs with

depinning for low-barrier Schottky source/drain transistors,” Appl. Phys. gate-all-around channels,” IEEE Electron Device Lett., vol. 30, no. 8,

Lett., vol. 88, no. 1, pp. 012 105–012 108, Jan. 2006. pp. 843–845, Aug. 2009.

[10] Q. T. Zhao, E. Rije, U. Bruer, S. Lenk, and S. Mantl, “Tuning of [31] Y. K. Chin, K. L. Pey, N. Singh, G. Q. Lo, G. Zhu, X. Zhou,

silicide SBHs by segregation of sulfur atoms,” in Proc. ICSICT, 2004, X. C. Wang, H. Y. Zheng, and L. H. Tan, “Excimer laser-annealed dopant

pp. 456–459. segregated Schottky Si nanowire gate-all-around pFET with near zero

[11] M. Tao, D. Udeshi, N. Basti, E. Maldonado, and W. P. Kirk, “Removal of effective Schottky barrier height (SBH),” in IEDM Tech. Dig., 2009,

dangling bonds and surface states on silicon (001) with a monolayer of pp. 935–938.

selenium,” Appl. Phys. Lett., vol. 82, no. 10, pp. 1559–1561, May 2003. [32] H. C. Pao and C. T. Sah, “Effects of diffusion current on characteristics of

[12] M. Tao, S. Agarwal, D. Udeshi, N. Basit, E. Maldonado, and W. P. Kirk, metal–oxide (insulator)–semiconductor transistors,” Solid State Electron.,

“Low Schottky barriers on n-type silicon (001),” Appl. Phys. Lett., vol. 83, vol. 9, no. 10, pp. 927–937, Oct. 1966.

no. 13, pp. 2593–2595, Sep. 2003. [33] J. R. Brews, “A charge-sheet model of the MOSFET,” Solid State Elec-

[13] G. Song, M. Y. Ali, and M. Tao, “A high Schottky-barrier of 1.1 eV tron., vol. 21, no. 2, pp. 345–355, Feb. 1978.

between AL and S-passivated p-type Si (100) surface,” IEEE Electron [34] G. H. See, X. Zhou, K. Chandrasekaran, S. B. Chiah, Z. M. Zhu,

Device Lett., vol. 28, no. 1, pp. 71–73, Jan. 2007. C. Q. Wei, S. H. Lin, G. J. Zhu, and G. H. Lim, “A compact model

[14] R. Saiz-Pardo, R. Perez, F. J. Garcia-Vidal, R. Whittle, and F. Flores, “Sys- satisfying Gummel symmetry in higher order derivatives and applicable

tematic theoretical studies of the Schottky barrier control by passivating to asymmetric MOSFETs,” IEEE Trans. Electron Devices, vol. 55, no. 2,

atomic intralayers,” Surf. Sci., vol. 426, no. 1, pp. 26–37, May 1999. pp. 624–631, Feb. 2008.

[15] S. J. Choi, J. W. Han, S. H. Kim, M. G. Jang, J. S. Kim, K. H. Kim, [35] G. J. Zhu, X. Zhou, G. H. See, S. H. Lin, C. Q. Wei, and J. B. Zhang, “A

G. S. Lee, J. S. Oh, M. H. Song, Y. C. Park, J. W. Kim, and Y. K. Choi, unified compact model for FinFET and silicon nanowire MOSFETs,” in

“Enhancement of program speed in dopant-segregated Schottky-barrier Proc. NSTI Nanotech, 2009, pp. 588–591.

(DSSB) FinFET SONOS for NAND-type Flash memory,” IEEE Electron [36] D. A. Neamen, Semiconductor Physics and Devices—Basic Principles.

Device Lett., vol. 30, no. 1, pp. 78–81, Jan. 2009. New York: McGraw-Hill, 2003, p. 338.

[16] A. Kinoshita, Y. Tsuchiya, A. Yagishita, K. Uchida, and J. Koga, “Solution [37] C.-T. Sah, Fundamentals of Solid-State Electronics. Singapore: World

for high performance Schottky-source/drain MOSFETs: Schottky barrier Scientific, 1991, p. 495.

780 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 4, APRIL 2010

[38] R. F. Pierret, Semiconductor Device Fundamentals. Reading, MA: mixed-signal circuit modeling and simulation. In November and December

Addison-Wesley, 1996, p. 492. of 1997 as well as in February and March 2001, he was a Visiting Fellow

[39] R. van Langevelde, A. J. Scholten, and D. B. M. Klaassen, Physical with the Center for Integrated Systems, Stanford University, Stanford, CA.

Background of MOS Model 11, p. 44, Apr. 2003. [Online]. Available: In January 2003, he was a Visiting Professor with Hiroshima University,

http://www.nxpcom/acrobat_download/other/philipsmodels/nl_tn2003_ Hiroshima, Japan. In May 2007, he was a Visiting Professor with Universiti

00239.pdf Teknologi Malaysia, Johor Bahru, Malaysia. He is currently with the School

[40] X. Zhou, G. H. See, G. J. Zhu, S. H. Lin, C. Q. Wei, and J. B. Zhang, of Electrical and Electronic Engineering, Nanyang Technological University as

“Unified regional modeling approach to emerging multiple-gate/nanowire a tenured Associate Professor, teaching and researching deep-submicrometer

MOSFETs,” in Proc. ICSICT, 2008, pp. 262–267. CMOS technology and device modeling. His current research interests include

[41] E. O. Kane, “Zener tunneling in semiconductors,” J. Phys. Chem. Solids, the area of semiconductor device physics and modeling, novel device struc-

vol. 12, no. 2, pp. 181–188, 1959. tures, compact model development for advanced devices, technology modeling

[42] J. P. Snyder, C. R. Helms, and Y. Nishi, “Analysis of the potential distribu- and simulation, mixed-signal CAD tools, hot-carrier transport, and ultrafast

tion in the channel region of a platinum silicided source/drain metal oxide phenomena.

semiconductor field effect transistor,” Appl. Phys. Lett., vol. 74, no. 22, Dr. Zhou is an Elected Member of the IEEE Electron Devices Society (EDS)

pp. 3407–3409, May 1999. Administrative Committee, the Chair of the EDS Asia Pacific Subcommittee

[43] S. Zhu, H. Y. Yu, S. J. Whang, J. H. Chen, C. Shen, C. Zhu, S. J. Lee, for Regions/Chapters, a Member of the EDS Compact Modeling Technical

M. F. Li, D. S. H. Chan, W. J. Yoo, A. Du, C. H. Tung, J. Singh, Committee as well as the Educational Activities, Publications, and Membership

A. Chin, and D. L. Kwong, “Schottky-barrier S/D MOSFETs with Committees, an EDS Distinguished Lecturer, and an Editor of the IEEE E LEC -

high-k gate dielectrics and metal-gate electrode,” IEEE Electron Device TRON D EVICE L ETTERS . He received the 2006 Nano Science and Technology

Lett., vol. 25, no. 5, pp. 268–270, May 2004. Institute (NSTI) Fellowship Award. He is listed in the Marquis Who’s Who in

[44] S. Zhu, J. Chen, M.-F. Li, S. J. Lee, J. Singh, C. X. Zhu, A. Du, the World and Who’s Who in Science and Engineering. Since 2002, he has been

C. H. Tung, A. Chin, and D. L. Kwong, “N-type Schottky barrier the Founding Chair of the Workshop on Compact Modeling in association with

source/drain MOSFET using ytterbium silicide,” IEEE Electron Device the NSTI Nanotech Conference.

Lett., vol. 25, no. 8, pp. 565–567, Aug. 2004.

[45] J. Kedzaerski, P. Xuan, H. Anderson, J. Bokor, T. J. King, and C. Hu,

“Complementary silicide source/drain thin-body MOSFETs for the 20 nm Yoke-King Chin received the B.E. degree in elec-

gate length regime,” in IEDM Tech. Dig., 2000, pp. 57–60. trical and electronics engineering in 2006 from

[46] L. E. Calvet, H. Leubben, M. A. Reed, C. Wang, J. P. Snyder, the Nanyang Technological University, Singapore,

and J. R. Tucker, “Suppression of leakage current in Schottky bar- where he is currently working toward the Ph.D.

rier metal–oxide–semiconductor field-effect transistors,” J. Appl. Phys., degree in the Division of Microelectronics, School

vol. 91, no. 2, pp. 757–759, Jan. 2002. of Electrical and Electronic Engineering.

[47] M. Fritze, L. Chen, S. Calawa, D. Yost, B. Wheeler, P. Wyatt, C. L. Keast, His research interests include the fabrication

J. Snyder, and J. Larson, “High-speed Schottky-barrier pMOSFET with and characterization of silicon-nanowire transistors,

fT = 280 GHz,” IEEE Electron Device Lett., vol. 25, no. 4, pp. 220–222, Schottky MOSFETs, advanced junction engineer-

Apr. 2004. ing, and channel engineering for future CMOS

[48] G. Larrieu and E. Dubois, “Schottky-barrier source/drain MOSFETs on applications.

ultrathin SOI body with a tungsten metallic midgap gate,” IEEE Electron

Device Lett., vol. 25, no. 12, pp. 801–803, Dec. 2004.

[49] H. Cho, P. Kapur, P. Kalavade, and K. C. Saraswat, “A low-power, highly Kin Leong Pey (S’86–M’95–SM’02) received the

scalable, vertical double-gate MOSFET using novel processes,” IEEE

B.Eng. and Ph.D. degrees in electrical engineer-

Trans. Electron Devices, vol. 55, no. 2, pp. 632–639, Feb. 2008.

ing from the National University of Singapore,

[50] H.-S. P. Wong, K. K. Chan, and T. Yuan, “Self-aligned (top and bottom)

Singapore, 1989 and 1994, respectively.

double-gate MOSFET with a 25 nm thick silicon channel,” in IEDM Tech. He has held various research positions in the Insti-

Dig., 1997, pp. 427–430.

tute of Microelectronics, Chartered Semiconductor

Manufacturing, Agilent Technologies, and National

University of Singapore. He is currently a Professor,

the Head of the Microelectronics Division, and the

Guojun Zhu (S’08) was born in China in 1984. Director of the Nanyang Nanofabrication Center at

He received the B.E.(Hons.) degree in electrical and the School of Electrical and Electronic Engineering,

electronic engineering in 2007 from the Nanyang College of Engineering, Nanyang Technological University, and holds a con-

Technological University, Singapore, where he is current Fellowship appointment in the Singapore—MIT Alliance (SMA).

currently working toward the Ph.D. degree at the Dr. Pey is an IEEE Electron Devices Society Distinguished Lecturer and has

School of Electrical and Electronic Engineering. been the Organizing Committee Member of the International Symposium on

From July to December 2005, he was an Intern the Physical and Failure Analysis of Integrated Circuits (IPFA) since 1995. He

with Chartered Semiconductor Manufacturing Ltd., was the General Chair of IPFA 2001, Singapore, and a Co-General Chair of

Singapore, where he worked on electrical testing. IPFA 2004, Hsinchu, Taiwan. He was an Editor of the IEEE T RANSACTIONS

His current research interests include unified com- ON D EVICES AND M ATERIALS R ELIABILITY and the Chair of the Singapore

pact modeling of bulk/SOI/DG/GAA and Schottky- Chapter of the IEEE Reliability Society, the IEEE Components, Packaging, and

barrier MOSFETs. Manufacturing Technology Society, and the IEEE Electron Devices Society

in 2004/2005 and 2009. He served on the 2006–2009 International Reliability

Physics Symposium Technical Subcommittee, the IPFA 2002–2006 and 2008

Technical Committee, and the 2007 International Electron Devices Meeting

Xing Zhou (S’88–M’91–SM’99) received the B.E.

(IEDM) CMOS and Interconnect Reliability and the 2008 IEDM Characteri-

degree in semiconductor physics from Tsinghua Uni-

zation, Reliability and Yield Subcommittees.

versity, Beijing, China, in 1983, and the M.S. and

Ph.D. degrees in electrical engineering from the Uni-

versity of Rochester, Rochester, NY, in 1987 and

1990, respectively. Junbin Zhang received the B.E.(Hons.) degree in

From 1990 to 1991, he was a Research Associate electrical and electronic engineering in 2007 from

with the Department of Electrical Engineering, Uni- the Nanyang Technological University, Singapore,

versity of Rochester, where he worked on hot-carrier where he is currently working toward the Ph.D.

injection phenomena in MOS devices and on the degree at the School of Electrical and Electronic

development of computer-aided design (CAD) tools Engineering.

for mixed-signal circuit simulation. From 1992 to 1995, he was a Research His current research interests include compact

Fellow with the School of Electrical and Electronic Engineering, Nanyang modeling and device physics of next-generation de-

Technological University, Singapore, where he worked on Monte Carlo and vices such as SOI, double-gate, and LD MOS.

numerical modeling of semiconductor and optoelectronic devices as well as

ZHU et al.: DOPANT-SEGREGATED SCHOTTKY GATE-ALL-AROUND Si-NANOWIRE MOSFETs 781

Guan Huei See received the B.E. degree in Yafei Yan received the B.S. and M.S. degrees

electrical/telecommunication engineering and the in electrical engineering from Tsinghua University,

M.Eng. degree in electrical engineering from Beijing, China, in 2000 and 2003, respectively.

the Universiti Teknologi Malaysia, Johor Bahru, From 2003 to 2008, he was with Cadence. He

Malaysia, in 2002 and 2004, respectively, and the is currently a Research Associate with the School

Ph.D. degree in electrical and electronic engineer- of Electrical and Electronic Engineering, Nanyang

ing from the Nanyang Technological University, Technological University, Singapore. His research

Singapore, in 2009. interests include semiconductors and physics, mainly

He was a Postgraduate Intern at Silterra Malaysia focusing on compact modeling.

from 2002 to 2003, where he was responsible for

developing RF SPICE model for on-chip passive

devices, i.e., inductors, capacitors and resistors. He is currently a Senior

Integration Engineer for mixed-signal/RFCMOS with GLOBALFOUNDRIES

Singapore Pte. Ltd., Singapore. His current research interests include compact

modeling of CMOS transistors.

Zuhui Chen (S’05–M’06) received the B.S. degree

in physics from Fujian Normal University, Fujian,

China, the M.S. degree in solid-state physics from

Shihuan Lin received the B.Sc. degree in electronic

Xiamen University, Fujian, and the Ph.D. degree in

engineering from the Beijing Institute of Technology,

engineering science from the University of Florida,

Beijing, China, in 2001 and the M.Sc. degree in

Gainesville, in 1998, 2001, and 2005, respectively.

microelectronics from the Nanyang Technological

In 2006, he joined the Pen-Tung Sah MEMS Re-

University, Singapore, in 2006, where he is currently

search Center of Xiamen University as an Instruc-

working toward the Ph.D. degree at the School of

tor. In 2007, under the Lee Kuan Yew Postdoctoral

Electrical and Electronic Engineering.

Fellowship, he joined Nanyang Technological Uni-

His current research interests include nanoscale

versity, Singapore, as a Research Fellow, where he is

device modeling.

currently with the School of Electrical and Electronic Engineering. His current

interests include NBTIs and interface-trap modeling in silicon MOSFETs.

- 1M0565RUploaded bysifap
- MOSFET IRFZ44Uploaded byhuynhsang1979
- MOSFETUploaded byGaurav
- Contoh Assignment PO11Uploaded byFaridah Hassan
- cmos01_1upUploaded byKritika Nimesh
- AO7410Uploaded byCarlosClaros
- FDN5618P-888996Uploaded byAlan jorge
- cadtutorial_03Uploaded byAnil Kulshrestha
- LinearAppNote363-ReplaceOringDiodesWithMosfetsUploaded bythesp
- datasheet_6Uploaded byJoão Lucas Fortuna
- 62-6536602Uploaded byKrishnaveni Subramani S
- Tk40j60u Transistor n MosfetUploaded byAtep Praja
- 7445.pdfUploaded byhatem
- inyeccion mosfetUploaded byJoseph Santana
- BS170 N-Channel DMOS Transistor DatasheetUploaded byNandagopal Sivakumar
- 2N7000-DUploaded bymaxwell_euler
- DSA00266672.pdfUploaded byOrlando Manuel Capote Luna
- 0hwte31242z7a5lekkeuakcopfky.pdfUploaded byMichael CH
- Comparative Analysis of Technology Advancement From Single Gate to Multi-gate MosfetUploaded byesatjournals
- 2SK3298.pdfUploaded bywilmerk_159990
- Lecture 01 UploadUploaded bybhanunaga11
- btech vi sem 1Uploaded byshanker
- FDD5N50Uploaded byprimero marnez
- 2NS04ZUploaded byNazım Dallas
- question 1 and 4.docxUploaded byShakik
- KA1M0565RUploaded byricardinhobhmg
- FDS6679.pdfUploaded byC Orporacion Print Ec
- DS_AM4835EP_C1.pdfUploaded bygrecu0
- Chap5.pptUploaded byNuraddeen Magaji
- 09 Mosfet IntroUploaded bySeanGoonShengTang

- VLSI Design RulesUploaded bysiddharthmohta
- mp[1]Uploaded byMa Seenivasan
- VLSI Lab ManualUploaded byMa Seenivasan
- 1 Mosfet-1 BasicsUploaded byMa Seenivasan
- Digital WatermarkingUploaded byMa Seenivasan
- Full AdderUploaded byMa Seenivasan
- Test 3 Prob ListUploaded byMa Seenivasan
- l Edit Class Example TutorialUploaded byAditya Candra Kristanto
- LUploaded byMa Seenivasan
- SUploaded byMa Seenivasan
- VLSI ENGINEER careers.docxUploaded byMa Seenivasan
- jitter_complete.pdfUploaded byAbhishek Sharma
- Research Opportunites in VLSI Testing Testability Mr. M. Jebin VijayUploaded byMa Seenivasan
- solnewpdfUploaded byMa Seenivasan
- Scmos Layout Rules - AllUploaded byjigarsampat
- Multigate DeviceUploaded byMa Seenivasan
- Hci SlidesUploaded byMa Seenivasan
- Solutions Assignment 1Uploaded byMa Seenivasan
- Solutions Assignment3Uploaded byMa Seenivasan
- MOS Assignment 2Uploaded byMa Seenivasan
- Assignment 3Uploaded byMa Seenivasan
- Assignment 1Uploaded byMa Seenivasan
- MOS.pdfUploaded byMa Seenivasan
- Modelling of Power MOSFET for the Analysis of Switching Chara in Half-bridge ConvertersUploaded byMa Seenivasan
- The Superjunction Insulated Gate Bipolar Transistor Optimization and ModelingUploaded byMa Seenivasan
- The Impact of NBTI Effect on Combinational Circuit-Modeling, Simulation, And AnalysisUploaded byMa Seenivasan
- The Electrothermal Large-Signal Model of Power MOS Transistors for SPICEUploaded byMa Seenivasan
- Switching Process of Power MOSFETs-An Improved Analytical Losses ModelUploaded byMa Seenivasan
- Statistical Modeling With the PSP MOSFET ModelUploaded byMa Seenivasan

- Ideal Diode Circuit Analysis StepsUploaded byPhaniendra Kundeti
- General Semiconductor Products catalogUploaded byEdd Whatley
- NEC ZenerUploaded byuthram
- ir3315Uploaded byTrương Thiên Vũ
- FGA60N65SMDUploaded bybookreader1968
- Water Level IndicatorUploaded bysubir_seal
- Power DiodeUploaded byRadix Aditya
- design-and-development-of-pic-microcontrollerbased-3-phase-energy-meter.pdfUploaded byArshad Ali
- 1sxu000023c0202_08_components_modular_30mm.pdfUploaded byWilmer Quishpe Andrade
- EKV26_QUCSUploaded byCharanraj Mohan
- 7-Segment Display and Driving a 7-Segment DisplayUploaded byvpsampath
- If 002 Second SemesterUploaded by100_example_100
- An 6182Uploaded bysaket4081
- Mixers Phase DetectorsUploaded bydhirajkhanna
- by228Uploaded byRey Tiburon
- Catalogo Extech enero2013Uploaded byINTRAVEcom Industrial Automation
- lm2596 power supply driverUploaded byTomass123
- Fds 6875Uploaded bydreyes3773
- Electronics Engineering Pre-Board 1 EBFUploaded bycloud
- Remote Controlled Home AppliancesUploaded byMayur Thakur
- Data SheetUploaded byHatake Kakashi
- Pulse OximetryUploaded byCarlota Sotelo
- LIST OF FIGURE.docxUploaded bySahil Sethi
- Paper_Reconfigurable_Antenna.pdfUploaded byrajendrasoloni
- EC 1209-EDCUploaded bymadhan_ins
- 1209B (11E).pdfUploaded bymohammed
- 2015 Oudside Delhi Boards PapersUploaded bykeerthy
- C152 AlternatorUploaded bybry nolas
- Kubara Lamina d22!10!01-n0Uploaded byFaulhaber Adrian
- BYW95C Datasheet[2]Uploaded bychichedemoreno