PNR Steps

Below are the main steps for PNR complete flow:

Step1: Design Setup

Step2: Floor Plan/Design Plan (DP)
Step3: Power Plan
Step4: Placement
Step5: CTS
Step6: Routing
Step7: Export
Step8: Side Flows

Design Setup:

This is the first step in PNR flow, Inside design setup we have to peform below
steps.

Step1: Load/Read all the input files:

a) Technology ndm files (or) .TF files, TLU + files , Layer Mapping files.
b) Reference files: Tech ndm files , Std cells ndm files and macros ndm files.
c) Verilog GLNL (Topcell name .V)
d) SCANDEF(Topcell name.SCANDEF)
e) Load UPF, Commit UPF and Connect PG net.
f) MCMM /SDC.
g) SAIF or VCD files.

Tech.ndm: Contains tech.tf,TLU+ and Layer mapping files,Tech.ndm is in binary

format and is unreadable format.Foundry provided

Tech.tf: Contains information about Metal layers, via's etc..like min width,min
spacing,max width,pitch etc.Foundry provided

TLU+: Used for extraction of nets in ICC2, Contains metal layer

dielectric,thickness, Resistance, Capacitance etc which are needed for paracytic
extraction of nets.Foundry provided

Layer Map: Contains layer matching/mapping information between Tech.Tf and TLU+
files.Foundry provided

Std cells Ndm: are in binary format and unredable.Foundry provided

Macro Ndm: are in binary format and unredable.Foundry provided

Verilog Netlist (.V) : Name of this file has Top cell name .V, Inside this verilog
NL we will be having top cell module which is the mother if all modules and
contains ports information , memories etc. This files gave many modules and
instances defined.Synthesis provided

SCANDEF: This file contains no.of scan chains and Start and stop of each scan chain
including elements of each scan chain.DFT provided

UPF(Unified Power Format): UPF contains information about power domains,supply

nets,supply ports,special cells like isolation cells, Level shifters etc and power
state tables etc.Synthesis provided
MCMM(Mutli Corner Mutli Mode):

Corners – RC Corners (RC best, RC worst), Timing Corner(SS,FF lib)

MCMM --
Modes (SDC)- Functional, Test

SS– More cell delay– P – 1, V – low and T – high

FF- Less cell delay– P -1, V-high and T-low
SS Inversion – P-1 , V- low and T-low
FF Inversion – P-1, V-low and T-high

In MCMM we define corners and modes and associate them to scenarios.

-Associate Setup releated scenarios to Setup
-Associate Hold related scenarios to Hold

SDC: Functionla SDC contains regular clk's which are of higher freqency compared to
test SDC

During MCMM we load funcional and Test SDC at the same time for the tool to
optimize the timming for both modes at the sametime.Here tool switches from
functional to test mode and Viceversa using the set case analysis defined in SDC's.

In functional mode setcase analysis defined as :

Set_case_Analysis 0 test-mode
Set_case_Analysis 0 Scan-enabled

In Test mode the set case analysis condition defined as:

Set_case_Analysis 1 test-mode
Scan enabled related case is not defined.

SDC contains:
create_clk,create_generated_clk,definitions
set_driving_cell for i/p ports
set_load for o/p ports
set_clk_uncertainity for clk's
set i/p delay for ip ports w.r.t clk
set o/p delay for op ports w.r.t clk
clks can be real or virtual clk
Timing exception which includes set_false_path,set_multi cycle path, Set_max delay
and set_min delay.

VCD (OR) SAIF: these files are provided by GLS (Gate Level Simulation) contains
switching activity information of the design.

Step2: Define Min, Max layers and routing direction for metal layers using Tech.TF
files.

Step3: Report QOR to check Zero wire load timming.

Step4: Check design (Sanity check)

Step5: Save Block or Save Library

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Floor Plan/ Design Plan:

Step1: Die size calculation and defining die size.

Step2: Placing macros , voltage areas
Step3: Doing quick placement of Std cells and place IO ports and data flow flylines
Step4: Doing routing congestion analysis and re-arranging floor plan if needed to
reduce congestion and connectivity.

Objective : Objective of floor plan is to get least possible die area which
satisfies routing congestion and timming.
Timing quality is measured using wire lenght of each metal layer after floor plan

Questions:

Q1) How will you calculate die size?

Ans)