VLSI Lab Manual

K.L.N.
COLLEGE OF ENGINEERING, POTTAPALAYAM
(An ISO 9001:2000 certified institution)
ELECTRONICS AND COMMUNICATION ENGINEERING

DEPARTMENT
(Accredited by NBA)
Janakiram Digitally signed by Janakiraman

DN: cn=Janakiraman, o=K.L.N.
College of Engineering, ou=VLSI
an
Lab, email=janakiraman.n@klnce.
edu, c=IN
Date: 2010.01.13 12:03:52 +05'30'
VLSI Design LABORATORY
VI Semester ECE Branch
COMPILED BY
Mr. N. JANAKIRAMAN M.E., M.B.A., I.T.I.L., M.I.S.T.E., (A.C.S.,)

SELECTION GRADE LECTURER / ECE
Mrs. R. THIVYA PRABHA M.E., LECTURER / ECE
LIST OF EXPERIMENTS:
1) Study of Simulation tools

2) Study of Synthesis tools
3) Study of Place and Root and Back annotation for FPGAs
4) Study of development tool for FPGAs for schematic entry & VHDL
5) Design of traffic light controller using VHDL and above tools
6) Design and simulation of pipelined serial and parallel adder
7) Design and Simulation of Signed 8 bit Multiplier
8) Study of FPGA board and testing on board LEDs and switches
9) Testing the traffic controller design on the FPGA board
10) Design a Real Time Clock and its working on the FPGA board
Manual Contents:
Introduction --------------------------------------------------------- (1)
Programmable Logic Device: FPGA ------------------------------ (1)
VLSI Design Flow for FPGA --------------------------------------- (2)
Creating a New Project ------------------------------------------------ (3)
Opening a project --------------------------------------------------------- (3)
Creating a Verilog HDL input file for a combinational logic design (5)
Editing the Verilog source file --------------------------------------- (7)
Chapter (1) Simulation of the coding ------------------------------ (10)

Chapter (2) Synthesis of the coding ------------------------------ (14)
Chapter (3) Place and Route and Back Annotation for FPGA --------- (16)
Chapter (4) Development through Schematic Entry ------------ (24)
Chapter (5) Compilation and Implementation of the Design ------------ (29)
Chapter (6) Testing a Digital Logic Circuit in FPGA ------------ (35)
Chapter (7) Traffic Light controller using FPGA --------------------- (40)
Chapter (8) Consolidated UCF for the Complete Board ------------ (43)
Chapter (9) Observation & Record notebook writing method --- (47)
Chapter (10) Verilog Hardware Modeling ------------------------------- (47)
Chapter (11) VHDL Hardware Modeling ------------------------------- (54)
Chapter (12) Sample Coding (VHDL) ------------------------------- (80)
Chapter (13) Sample Coding (Verilog HDL) ------------------------------- (87)
Traffic Light Controller (VHDL) ------------------------------- (90)
Traffic Light Controller (Verilog HDL) ------------------------------- (97)
Verilog Code for Ripple Carry Adder ------------------------------- (107)
Verilog Code for Real Clock Timer ------------------------------- (108)
Possible University Practical Questions ------------------------------- (113)
Compiled by ECE Department Faculties of K.L.N. College of Engineering
EC1404 – VLSI Design Laboratory
Introduction
Xilinx Tools is a suite of software tools used for the design of digital circuits
implemented using Xilinx Field Programmable Gate Array (FPGA) or Complex
Programmable Logic Device (CPLD). The design procedure consists of (a) design entry, (b)
compilation and implementation of the design, (c) functional simulation and (d) testing and
verification. Digital designs can be entered in various ways using the above CAD tools: using
a schematic entry tool, using a hardware description language (HDL) – Verilog or VHDL or a
combination of both.
The CAD tools enable you to design combinational and sequential circuits starting
with Verilog HDL design specifications. The steps of this design procedure are listed below:
1. Create Verilog design input file(s) using template driven editor.

2. Compile and implement the Verilog design file(s).
3. Create the test-vectors and simulate the design (functional simulation) without using a
PLD (FPGA or CPLD).
4. Assign input/output pins to implement the design on a target device.
5. Download bitstream to an FPGA or CPLD device.
6. Test design on FPGA/CPLD device
A Verilog input file in the Xilinx software environment consists of the following segments:
• Header: module name, list of input and output ports.
• Declarations: input and output ports, registers and wires.
• Logic Descriptions: equations, state machines and logic functions.
• End: endmodule
All your designs for this lab must be specified in the above Verilog input format. Note that
the state diagram segment does not exist for combinational logic designs.
Programmable Logic Device: FPGA

In this lab digital designs will be implemented in the Pegasus board which has a
Xilinx Spartan FPGA XC3S400. This FPGA part belongs to the Spartan family of FPGAs.
These devices come in a variety of packages. We will be using devices that are packaged in
208 pin package with the following part number: XC3S400-PQ208. This FPGA is a device
with about 400K gates.
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Mr.N.Janakiraman M.E.,M.B.A.,I.T.I.L.,M.I.S.T.E., (A.C.S.,) S.G.L./ECE Ms.R.ThivyaPrabha M.E.,L/ECE
VLSI Design Flow for FPGA:
• DESIGN ENTRY
• SIMULATION
• SYNTHESIS
• IMPLEMENTATION
• DEVICE PROGRAMMING
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1. Creating a New Project

Xilinx Tools can be started by clicking on the Project Navigator Icon on the Windows
desktop. This should open up the Project Navigator window on your screen.
2. Opening a project
Select File->New Project to create a new project. This will bring up a new project window
on the desktop. Fill up the necessary entries as follows:
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• Project Name: Write the name of your new project

• Project Location: The directory where you want to store the new project
Leave the top level module type as HDL.
Example: If the project name were “or_gate”, enter “or_gate” as the project name and then
click “Next”.
Clicking on NEXT should bring up the following window:
• For each of the properties given below, click on the ‘value’ area and select from the list
of values that appear.
o Device Family: Family of the FPGA/CPLD used. In this laboratory we will
be using the Spartan3 FPGA’s.
o Device: The number of the actual device. For this lab you may enter
XC3S400 (this can be found on the attached prototyping board)
o Package: The type of package with the number of pins. The Spartan FPGA
used in this lab is packaged in PQ208 package.
o Speed Grade: The Speed grade is “-4”.
o Synthesis Tool: XST [VHDL/Verilog]
o Simulator: The tool used to simulate and verify the functionality of the
design. ISE simulator is integrated in the Xilinx ISE. Hence choose “ISE
Simulator” as the simulator.
o Then click on NEXT to save the entries.
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All project files such as schematics, netlists, Verilog files, VHDL files, etc., will be
stored in a subdirectory with the project name. A project can only have one top level HDL
source file (or schematic). Modules can be added to the project to create a modular,
hierarchical design. In order to open an existing project in Xilinx Tools, select File->Open
Project to show the list of projects on the machine.
Choose the project you want and click OK.
Clicking on NEXT on the above window brings up the following window:

(New Source Window)
If creating a new source file, Click on the NEW SOURCE.
3. Creating a Verilog HDL input file for a combinational logic design
First we will enter a design using a structural or RTL description using the Verilog
HDL. You can create a Verilog HDL input file (.v file) using the HDL Editor available in the
Xilinx ISE Tools (or any text editor).
If adding an already existing source file (.v file) to the project, in the project Navigator
window, select Project -> Add Copy Source and browse through the disk for the source file.
If creating a new source file, in the Project Navigator window, select Project -> New
Source. A window pops up. (Note: “Add to project” option is selected by default. If you do
not select it then you will have to add the new source file to the project manually.)
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Select Verilog Module and in the “File Name:” area, enter the name of the Verilog
source file you are going to create. Also make sure that the option Add to project is selected
so that the source need not be added to the project again. Then click on Next to accept the
entries. This pops up the following window:
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In the Port Name column, enter the names of all input and output pins and specify the
Direction accordingly. A Vector/Bus can be defined by entering appropriate bit numbers in
the MSB/LSB columns.
Then click on Next to get a window showing all the new source information. If any
changes are to be made, just click on Back to go back and make changes. If everything is
acceptable, click on Finish to continue.
Once you click on Finish, the source file will be displayed in the sources window in
the Project Navigator.
If a source has to be removed, just right click on the source file in the Sources in Project
window in the Project Navigator and select Remove in that. Then select Project -> Delete
Implementation Data from the Project Navigator menu bar to remove any related files.
4. Editing the Verilog source file
The source file will now be displayed in the Project Navigator window. The source
file window can be used as a text editor to make any necessary changes to the source file. All
the input/output pins will be displayed. Save your Verilog program periodically by selecting
the File->Save from the menu. You can also edit Verilog programs in any text editor and add
them to the project directory using “Add Copy Source”.
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• Adding Logic in the generated Verilog Source code template:
The Verilog source code template generated shows the module name, the list of ports
and also the declarations (input/output) for each port. Combinational logic code can
be added to the verilog code after the declarations and before the endmodule line.
For example, an output z in an OR gate with inputs a and b can be described as,
assign z = a | b;
Remember that the names are case sensitive.
• Other constructs for modeling the logic function:
A given logic function can be modeled in many ways in verilog. Here is another
example in which the logic function is implemented as a truth table using a case
statement:
module or_gate(a,b,z);
input a;
input b;
output z;
reg z;
always @(a or b)
begin
case ({a,b})
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00: z = 1'b0;
01: z = 1'b1;
10: z = 1'b1;
11: z = 1'b1;
endcase
end
endmodule
Suppose we want to describe an AND gate. It can be done using the logic equation as
shown in Figure or using the case statement (describing the truth table) as shown in second
Figure. These are just two example constructs to design a logic function. Verilog offers
numerous such constructs to efficiently model designs.
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1. Simulation of the coding:-

Run the Check syntax Æ Process window > synthesize > double click check syntax > and
remove errors, if present, with proper syntax & coding.
Click on the symbol of FPGA device and then right click > click on new source
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Select the Test Bench Waveform and give the file name select entity click next and finish
Select the desired parameters for simulating your design. In this case combinational circuit
and simulation time click finish
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Assign all input signal using just click on this and save file.
From the source process window. Click Behavioral simulation from drop-down menu
Select the test bench file (.tbw)and click process button double click the Simulation
Behavioral Model
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Verify your design in wave window by seeing behavior of output signal with respect to input
signal.
EXPERIMENTAL RESULTS USING SIMULATION TOOLS CAN BE INFERRED FOR:
1) FUNCTIONAL SIMULATION
2) GATE-LEVEL SIMULATION
3) POST-PAR SIMULATION
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2. Synthesis of the coding:-

Synthesis is the process of constructing a gate level netlist from a register-transfer
level model of the circuit described in VHDL, Verilog, or mixed language designs. The
netlist files contain both logical design data and constraints.
Synthesis your design, from the source window select, synthesis/implementation

from the window Now double click the Synthesis – XST
RTL Schematic:
After the HDL synthesis phase of the synthesis process, you can display a schematic
representation of your synthesized source file. This schematic shows a representation
of the pre-optimized design in terms of generic symbols, such as adders, multipliers,
counters, AND gates, and OR gates double click View RTL Schematic.
1) Double click the schematic to internal view
2) Double click the schematic for internal view
3) Double click outside the schematic to move one-level back
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Technology Schematic:
This schematic shows a representation of the design in terms of logic elements

optimized to the target device. For example, in terms of LUTs(Look Up Table), carry
logic, I/O buffers, and other technology-specific components.
double click View Technology Schematic
1) Double click the schematic to inner view
2) Double click the LUT to inner view
3) This is Gate Level view of LUT
4) Display of Truth Table and K-Map for your design just click the respective tabs.
Design summary:
After finishing the synthesis, you can view number of Slices, LUT (Look Up
Table), I/Os are taken by your deign in Device using Design summary.
EXPERIMENTAL RESULTS USING SYNTHESIS TOOLS CAN BE INFERRED FOR:
1) UTILIZATION OF LUTS & SLICES
2) I/O BUFFER ASSIGNMENT
3) RTL SCHEMATIC IN GATE LEVEL
4) TECHNOLOGY SCHEMATIC IN LUT LEVEL
5) TIME DELAY BETWEEN I/Os & PATH
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3. Place and Route and Back Annotation for FPGA

Back annotation is the translation of a routed or fitted design to a timing simulation
netlist.
¾ To define the behavior of the FPGA, a hardware description language (HDL) or a
schematic design methods are used. Common HDLs are VHDL and Verilog. Then,
using an electronic design automation (EDA) tool, a technology-mapped netlist is
generated.
¾ The netlist can then be fitted to the actual FPGA architecture using a process called
place-and-route, usually performed by the FPGA vendor’s proprietary place-and-route
software.
¾ The user will validate the map, place and route results via timing analysis, simulation,
and other verification methodologies. Once the design and validation process is
complete, the binary file generated is used to (re)configure the FPGA.
¾ In an attempt to reduce the complexity of designing in HDLs, which have been
compared to the equivalent of assembly.
¾ In a typical design flow, an FPGA application developer will simulate the design at
multiple stages throughout the design process.
¾ Initially the RTL description in VHDL or Verilog is simulated by creating test
benches to simulate the system and observe results.
¾ Then, after the synthesis engine has mapped the design to a netlist, the netlist is
translated to a gate level description where simulation is repeated to confirm the
synthesis proceeded without errors.
¾ Finally the design is laid out in the FPGA at which point propagation delays can be
added and the simulation run again with these values backannotated onto the netlist.
After Synthesis, assign the Pin Value; double click the Assign Package Pins.
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Enter the Pin value for your input and output signals. if you want see your Pin assignment in
FPGA zoom in Architecture View or Package View
You see the Pins in FPGA Æ save file
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Save file as XST Default click ok and close the window.
Design Implementation begins with the mapping or fitting of a logical design file to a specific
device and is complete when the physical design is successfully routed and a bitstream is
generated. Double Click Implementation Design
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After implementation you see Design Summary, you get the all details about your design. If
you want edit the place and route, double click View/Edit placed design
You see where your IOs are placed in FPGA. And zoom to view how Pins are placed in
FPGA.
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You can see where your pins are placed
Just double click View/Edit Routed Design to view interconnection wires and blocks
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Click the pin to see where its placed in FPGA. And Zoom particular area to see Place and
Routing.
If you want to change the place of the design, click and trace to another slice
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See!!! You changed place and route of the design
Double click Back annotated Pin Location
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Once back annotation is completed, constraint file is generated.
EXPERIMENTAL RESULTS CAN BE INFERRED FOR:
Place & Route, the process of optimization of logic cells for effective utilization of
FPGA area and the speed of operation, is used to modify and infer the following:
1) RE-ASSIGNMENT OF PINS
2) RE-LOCATION OF SLICES
3) RUN TIME MINIMIZATION
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4. Development through Schematic Entry

This topic gives the overview of schematic entry using ISE .Here we give the
explanation with an example of full adder. The step to generate a full adder is given in this
chapter. We generate Truth Table for the required functionality. Solve the Equation and we
get the gates required to implement the design.
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Procedure:
¾ Started by clicking on the Project Navigator Icon on the Windows desktop.
¾ Select File->New Project to create a new project.
¾ Fill the necessary information’s based on previous chapters.
¾ Then click on NEXT.
¾ Click on the NEW SOURCE.
Select the Categories and symbols or type the symbol name in this case just type xor2, and2, or2.
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Click Add I/O markers
Double click the I/O pin
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Enter the Name and click ok
Click Add wire button
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Final schematic diagram. Then synthesis or simulation process
To view the VHF file generated Clock on View HDL functional model in design utilities
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5. Compilation and Implementation of the Design

The design has to be compiled and implemented before it can be checked for correctness,
by running functional simulation or downloaded onto the prototyping board. With the top-
level Verilog / VHDL file opened (can be done by double-clicking that file) in the HDL
editor window in the right half of the Project Navigator, and the view of the project being in
the Module view , the implement design option can be seen in the process view. Design
entry utilities and Create Programming File options can also be seen in the process view.
To compile the design, expand the Implement design option by clicking on the ‘add’
sign (+) in front of the implement design tab. Now click on the option Compile Design in the
Processes window. It will go through steps like Check Syntax, Compile Logic, Interpret
Feedbacks, Reformat Logic and Optimize Hierarchy. If any of these steps could not be
done or done with errors, it will place a X mark in front of that, otherwise a tick mark will be
placed after each of them to indicate the successful completion. If everything is done
successfully, a tick mark will be placed before the Compile Design option. If there are
warnings, one can see mark in front of the option indicating that there are some warnings.
One can look at the warnings or errors in the Console window present at the bottom of the
Navigator window. Every time the design file is saved; all these marks disappear asking for
a fresh compilation.
To implement the design, double-click on the Implement Design option. It has many
steps in it e.g., Translation, Fitter, Timing Analysis and Launch Tools. One can use the
timing analyzer and post fit chipviewer from the Launch Tools section once the
implementation is completed successfully. If the implementation is done successfully, a tick
mark will be placed in front of the Implement Design option.
The above two steps can be done in a single step by just double-clicking on the Implement
Design option straightaway. This will do the compilation first and then the implementation.
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A bitstream file needs to be prepared for each design and downloaded onto the
Pegasus prototyping board. This is done as follows:
User Constraint File:
1. Connect the 5V DC power cable to the power input on the demo board (J4).
2. Connect the download cable between the PC and demo board (J7).
3. Select Synthesis/Implementation from the drop-down list in the Sources window.
4. Select design file in the Sources window.
5. In the Processes window, click the “+” sign to expand the Generate Programming
File processes.
6. Double-click the Configure Device (iMPACT) process.
7. The Xilinx WebTalk Dialog box may open during this process. Click Decline.
8. Select Disable the collection of device usage statistics for this project only and
click OK. iMPACT opens and the Configure Devices dialog box is displayed.
9. In the Welcome dialog box, select Configure devices using Boundary-Scan (JTAG).
10. Verify that Automatically connect to a cable and identify Boundary-Scan chain is
selected.
11. Click Finish.
12. If you get a message saying that there are two devices found, click OK to continue.
The devices connected to the JTAG chain on the board will be detected and displayed
in the iMPACT window.
13. The Assign New Configuration File dialog box appears. To assign a configuration file
to the xc3s400 device in the JTAG chain, select the counter.bit file and click Open.
14. If you get a Warning message, click OK.
15. Select Bypass to skip any remaining devices.
16. Right-click on the xc3s400 device image, and select Program. The Programming
Properties dialog box opens.
17. Click OK to program the device.
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When programming is complete, the Program Succeeded message is displayed.

On the board, LEDs 0, 1, 2, and 3 are lit, indicating that the counter is running.
18. Close iMPACT without saving.
Note that you can assign pin numbers only to top-level Verilog / VHDL file.
¾ For the OR_GATE example, the user constraint file used is as follows:
# Pin 88 and 89 are FPGA pins connected to SW0 and SW1 in the Pegasus Board
# Pin 46 of the FPGA is connected to LED0 in the Pegasus Board.
NET a LOC="P88";
NET b LOC="P89";
NET z LOC="P46";
¾ Click on the Module View, choose the main design file and in the Process View -> User
Constraints –> Edit Constraints option; add the user constraint file for the design.
¾ Then, in the Process View window (left-bottom), double click on the ‘Generate
Programming file’.
¾ Wait for the programming file to be generated and then click on the “Generate
Programming File” Æ “Configure Device” option.
Once this is done, the following image pops up (JTAG Programmer Window). Choose
the ‘Select boundary scan’ option and click on NEXT.
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On clicking Next, the following image comes up: Choose the option ‘Automatically
connect to cable and identify device’ and click on Finish.
Once this is done, a window pops up where you will see two devices connected in the
Boundary scan. The first one xc3s400 is the Spartan FPGA. Right click on the xc3s400
device and select “Assign New configuration file”. Once this is done, click on Ok on the
following pop up which will take you to the Select bit file window as shown – Choose
or_gate.bit
Now Right click on the xs3s400 device and select program as shown below:
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Once you select program, the following window will pop up. Click on OK [There is
no need to check the Verify option].
Once you click OK, you can see the status of the bitstream download in the lower half
of the window.
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Ensure that the “Programmed Successfully” message appears in the message window.
If this doesn’t appear, it could be due to the following reasons:
1. The JTAG cable is not connected between the FPGA board and the PC
parallel port.
2. You did not select the proper device for download in the JTAG chain.
3. The bitstream generated was not for the device: XC2S50-PQ208
In order to use the respective input/output device on the board, the pin number of the
device must be connected properly to the designs input/output. If the Programmed
Successfully message appears in the message window, you can start testing your design in the
FPGA board using the input and output devices on the board.
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6. Testing a Digital Logic Circuit in FPGA

Testing a downloaded design requires connecting the inputs of the design to switches
or ports and the outputs of the design to LEDs or 7-segment displays. In case of sequential
circuits, the clock input(s) must also be connected to clock sources. These inputs and outputs
can be connected to appropriately on the Digital Lab workbench.
Model of the XC3S400 VLSI development board:
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Features which can be used to test the digital logic in the design:
• SPARTAN -3 FPGA : 400 k logic cell SPARTAN -3 FPGA in PQ208 Plastic Quad Flat
Package (MXS3FK-PQ208-IM )
Ð Three families Spartan 3 /Spartan 3L/Spartan 3 XA.
Ð Very low cost, high-performance logic solution for high-volume, consumer-oriented
applications.
- Densities as high as 74,880 logic cells.
- Three power rails for core (1.2V), I/O’s (1.2V to 3.3V) and Auxiliary purposes
(2.5V).
- 326 MHz system clock rate.
- 90 nm process technology.
Ð Select IO Signaling.
- Up to 784 I/O pins.
- 622 Mb/s data transfer rate per IO.
- 18 single-ended signal standards.
Ð Logic Resources
- Abundant Logic cells with shift register capability.
- Wide Multiplexers.
- Fast look-ahead carry logic.
- Dedicated 18 x 18 Multipliers.
Ð Select RAM Hierarchical Memory.
- Up to 1,872 Kbits of total block RAM.
- Up to 520 Kbits of Distributed RAM.
Ð Digital Clock Manager (up to 4DCMs)
- Clock skew elimination.
- Frequency synthesis
- High resolution phase shifting.
Ð Eight global clock lines and abundant routing.
• Seven Segment Display: Six-character multiplexed seven-segment LED display.
• Serial Interface: One RS-232 channel using MAX3223, 9 pin two channel serial
interfaces.
Ð DB9 9-pin female connector (DCE connector).
Ð RS-232 transceiver/level translator using MAX3223 in SSOP package.
Ð Uses straight-through serial cable to connect to computer or workstation serial port.
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• LCD Interface: - 16 Character/ Digit 2 Row LCD.

• Traffic Light Control Interface:-16 green LEDS, 8 Red LEDS, 4 Yellow LEDS.
Ð Traffic Light Interface module will be connected using 60 pin Connector (J5).
• RTC:- Six 7 Segment Displays.
• Analog Interface: – 12 bit AD7891 ADC and 12 bit AD7541 DAC.
Ð Analog Input – Eight channels using ADC using AD7891, (500Ksps, 12 bit).
Ð Analog Output- Two channels using Two DAC’s-AD7541. (12 bit, 100 ns conversion
time)
• DIP Switches: 16 DIP switches.
• LEDs: 23 onboard LEDS
Ð 16 output LEDs (OL 0 – OL 15).
Ð Done LED.(DONE)
Ð 6 Power ON LEDs (LED12VN, LED12V, LED5V, LED3.3V, LED2.5V, LED1.2V).
• Push Button Switches: 16 momentary-contact push button switches in 4x4 matrix.
• User selectable configuration modes - Boundary scan, Master serial.
• User selectable Interface hardware – Traffic Light, RTC, ADC-DAC.
• Free IOs: 34 pin FRC Connector (J7) provided for free I/Os.
• Clock Oscillator: 4 MHz crystal clock oscillator. Socket for an auxiliary crystal
oscillator clock source.
• JTAG port: JTAG download cable (parallel III) interface.
• Power Supplies: 5 volts regulated power supply provided along with the board.
Ð On board 3.3V, 2.5V, 1.2V regulators.
Ð FPGA supplies viz. Vccint (1.2V) & Vcco (3.3V) are generated on board
In order to use the respective input/output device on the board, the pin number of the
device must be connected properly to the design’s input/output. In the Pegasus board, the pin
number of these inputs/outputs are mentioned in the board manual and also mentioned in the
components of the board.
Observing outputs using the on-board LEDs and Seven Segment Displays
The Pegasus boards have six on-board 7-segment displays, which is connected to the
corresponding on-board Spartan FPGA chip. This display can be used to observe the outputs
of your design without using any additional wires if the design conforms to the pin
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assignments for the on-board 7-segment display. The figure below shows the 7-segment
display with the conventional labeling of individual segments.
The Pegasus board contains a 6-digit common anode seven-segment LED display.
The display is multiplexed, so only seven cathode signals (CA, CB, CC, CD, CE, CF, CG)
exist to drive all 28 segments in the display. Six digit-enable signals (AN1, AN2, AN3, AN4,
AN5, AN6) drive the common anodes, and these signals determine which digit the cathode
signals illuminate.
LCD Interface
SPARTAN-3 -IM includes a LCD Module, which is a dot matrix liquid crystal
display that displays alphanumeric, Kana (Japanese) characters and symbols. Built in
controller provides connectivity between LCD and FPGA.
This LCD has a built in Dot Matrix controller, with font 5 X 7 or 5 X 10 dots, display
data RAM for 80 characters ( 80 x 8 bit) and a character generator ROM which provides 160
characters with 5x7 font and 32 characters with font of 5x10.
All the functions required for LCD are provided internally. Internal refresh is
provided by the Controller.
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Data Lines Connection
LCD has 8 bit bidirectional data bus interface to FPGA. When Enable signal is at low
level, this data bus remains in high impedance state. Interface details of the data lines with
SPARTAN-3 FPGA are as in Table.
Control Line Interface:
The control lines of LCD comprises of RS, R/W# and E The significance of the
above mentioned control signals is as follows
• RS : Register select signal used to select Data register or a Command/Status register.

Ð High on RS selects the data register.
Ð Low on RS selects the Command/Status register.
• R/W# : Read/Write select control line.

Ð High on R/W # selects the read operation
Ð Low on R/W # selects the write operation.
• E : Enable signal used to enable or disable the data bus.
Ð Low on the enable signal puts the data bus into a high impedance state.
Ð High on the enable signal selects the data bus
Control Bit FPGA Pin
"LCD_E" 168
"LCD_RS" 171
"LCD_RW_BAR" 169
Note: PR1 is used to adjust the contrast of LCD Display
ASCII CODE
The ASCII code for 5x 7 LCD Display is given in Figure
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7. Traffic Light controller using FPGA

Spartan-3 FPGA development board, which is available in college, includes a
TRAFFIC LIGHT Interface Module. This module is interfaced to the Trainer using 60 pin
FRC cable. Traffic Light controller is implemented in FPGA and verified using Traffic Light
Interface Module.
There are simple rules for traffic lights on one node, and complex ways of regulating
a whole infrastructure of them. It is necessary to adjust general algorithms.
Design Description:
• Initially all Red Lights will be “ON” (South, west, North, East, Pedestrian)
• Green Lights of will be “ON”, Right, Left & Straight paths are free for Traffic.
• Yellow Phase is split as yellow1 & yellow2. In yellow1 phase yellow lights will be on
and respective left & pedestrian paths are free for traffic.
• In Yellow2 Phase only yellow lights will be “ON”
• Same flow is repeated for all four paths. (South, west, north, east).
¾ Flowchart:-
40
¾ To implement Traffic Light controller refer the waveform given below.
Abbreviation used:-
South West
PSG – Pedestrian South Green PWR – Pedestrian West Red
PSR – Pedestrian South Red PWG – Pedestrian West Green
RS – Right South RW – Right West
LS – Left South LW – Left West
SS – Straight South SW – South West
YS – Yellow South YW – Yellow West
REDS – Red South REDW – Red West
North East
PNR- Pedestrian North red PEG – Pedestrian East green
PNG – Pedestrian North green PER – Pedestrian Ease Red
RN – Right North RE – Right East
LN – Left North LE – Left East
SN – Straight North SE – Straight East
YN - Yellow North YE – Yellow East
REDN – Red North REDE – Red East
41
Experimental Set up:
Traffic Light Interface to SPARTAN-3 FPGA
Component Diagram
42
8. Consolidated UCF for the Complete Board

Clock and Reset
net "CLK_4M" Loc= "p181";
net "CLK_OPT" Loc= "p180";
net "RESET" Loc= "p182";
KEYS
net "RL<0>" Loc= "p96";
net "RL<1>" Loc= "p95";
net "RL<2>" Loc= "p94";
net "RL<3>" Loc= "p85";
net "SL<0>" Loc= "p86";
net "SL<1>" Loc= "p87";
net "SL<2>" Loc= "p90";
net "SL<3>" Loc= "p93";
LCD Interface
net "LCD_D<0>" Loc= "p167";
net "LCD_E" Loc= "p168";
net "LCD_RS" Loc= "p171";
net "LCD_RW_BAR" Loc= "p169";
Seven Segment Interface

net "SEGA" Loc= "p144";
net "SEGB" Loc= "p143";
net "SEGC" Loc= "p141";
net "SEGD" Loc= "p140";
net "SEGE" Loc= "p139";
net "SEGF" Loc= "p138";
net "SEGG" Loc= "p137";
net "SEGDP" Loc= "p135";
Display
net "DIS<0>" Loc= "p97";
43

Input Switches
net "IL<0>" Loc= "p57";
net "IL<1>" Loc= "p52";
net "IL<2>" Loc= "p51";
net "IL<3>" Loc= "p50";
net "IL<4>" Loc= "p48";
net "IL<5>" Loc= "p46";
net "IL<6>" Loc= "p45";
net "IL<7>" Loc= "p44";
net "IL<8>" Loc= "p43";
net "IL<9>" Loc= "p42";
net "IL<10>" Loc= "p40";
net "IL<11>" Loc= "p39";
net "IL<12>" Loc= "p37";
net "IL<13>" Loc= "p36";
net "IL<14>" Loc= "p35";
net "IL<15>" Loc= "p34";
Test LEDs
net "OL<0> Loc= "p68";
net "OL<10>" Loc= "p78";
net "OL<11>" Loc= "p77";
net "OL<12>" Loc= "p76";
net "OL<13>" Loc= "p74";
net "OL<14>" Loc= "p72";
net "OL<15>" Loc= "p71";
44
RTC
net "RTC_DIS<0>" LOC = "p16"; #J6-1
net "RTC_SEGA" LOC = "p24"; #J6-7
net "RTC_SEGB" LOC = "p20"; #J6-8
net "RTC_SEGC" LOC = "p27"; #J6-5
net "RTC_SEGD" LOC = "p26"; #J6-6
net "RTC_SEGE" LOC = "p29"; #J6-3
net "RTC_SEGF" LOC = "p28"; #J6-4
net "RTC_SEGG" LOC = "p33"; #J6-1
net "RTC_SEGDP" LOC = "p31"; #J6-2
Traffic Control
net "TRC_LE" LOC = "p107"; #J3-20
net "TRC_LN" LOC = "p125"; #J3-9
net "TRC_LS" LOC = "p150"; #J3-25
net "TRC_LW" LOC = "p130"; #J3-6
net "TRC_SE" LOC = "p115"; #J3-17
net "TRC_SN" LOC = "p123"; #J3-11
net "TRC_SS" LOC = "p152"; #J3-26
net "TRC_SW" LOC = "p146"; #J3-4
net "TRC_RE" LOC = "p114"; #J3-18
net "TRC_RN" LOC = "p122"; #J3-12
net "TRC_RS" LOC = "p111"; #J3-23
net "TRC_RW" LOC = "p147"; #J3-3
net "TRC_PEG" LOC = "p116"; #J3-16
net "TRC_PNG" LOC = "p128"; #J3-7
net "TRC_PSG" LOC = "p12"; #J3-28
net "TRC_PWG" LOC = "p148"; #J3-2
net "TRC_PER" LOC = "p117"; #J3-15
net "TRC_PNR" LOC = "p124"; #J3-10
net "TRC_PSR" LOC = "p13"; #J3-27
net "TRC_PWR" LOC = "p149"; #J3-1
net "TRC_REDE" LOC = "p109"; #J3-22
net "TRC_REDN" LOC = "p120"; #J3-13
net "TRC_REDS" LOC = "p108"; #J3-21
net "TRC_REDW" LOC = "p126"; #J3-8
net "TRC_YE" LOC = "p106"; #J3-19
45
net "TRC_YN" LOC = "p119"; #J3-14

net "TRC_YS" LOC = "p113"; #J3-24
net "TRC_YW" LOC = "p131"; #J3-5
IOs
net "IO<1>" LOC = "p184"; #J7-1
net "IO<2>" LOC = "p183"; #J7-2
net "IO<3>" LOC = "p187"; #J7-3
net "IO<4>" LOC = "p185"; #J7-4
net "IO<5>" LOC = "p190"; #J7-5
net "IO<6>" LOC = "p189"; #J7-6
net "IO<7>" LOC = "p194"; #J7-7
net "IO<8>" LOC = "p191"; #J7-8
net "IO<9>" LOC = "p197"; #J7-9
net "IO<10>" LOC = "p196"; #J7-10
net "IO<11>" LOC = "p199"; #J7-11
net "IO<12>" LOC = "p198"; #J7-12
net "IO<13>" LOC = "p203"; #J7-13
net "IO<14>" LOC = "p200"; #J7-14
net "IO<15>" LOC = "p205"; #J7-15
net "IO<16>" LOC = "p204"; #J7-16
net "IO<17>" LOC = "p3"; #J7-17
net "IO<18>" LOC = "p2"; #J7-18
net "IO<19>" LOC = "p5"; #J7-19
net "IO<20>" LOC = "p4"; #J7-20
net "IO<21>" LOC = "p9"; #J7-21
net "IO<22>" LOC = "p7"; #J7-22
net "IO<23>" LOC = "p11"; #J7-23
net "IO<24>" LOC = "p10"; #J7-24
46
9. Observation & Record notebook writing method:
Aim:
Write the short objective of your program in your own wordings.
Required Packages:
1) Software details
2) Hardware details
Procedure:
Write all the theoretical procedure given in the corresponding operations like
Simulation, Synthesis, Place & Route, Back-annotation, Schematic & Implementation in
FPGA.
Circuit Diagram:
Draw the logic gates design diagram of your circuit.
Truth Table:
Draw the truth table of your circuit.
Program:
Write the HDL program (VHDL / Verilog HDL) for your design.
Model Result:
Write the expected result for your program.
Experimental Result:
Write the actual result of your design works.
Conclusion:
Write the conclusion of your experiment, based on the model & experimental result.
47
10. Verilog Hardware Modeling:
This is just an introductory level tutorial to the Verilog language. The reader is
encouraged to go through the various Verilog tutorials to understand the language better:
1. Module:
A module is the basic building block in Verilog. It is defined as follows:

module <module_name> (<portlist>);
.
. // module components
.
endmodule
The <module_name> is the type of this module. The <portlist> is the list of
connections, or ports, which allows data to flow into and out of modules of this type.
Verilog models are made up of modules. Modules, in turn, are made of different types of
components. These include
• Parameters
• Nets
• Registers
• Primitives and Instances
• Continuous Assignments
• Procedural Blocks
• Task/Function definitions
2. Ports:
Ports are Verilog structures that pass data between two or more modules. Thus, ports can
be thought of as wires connecting modules. The connections provided by ports can be
either input, output, or bi-directional (inout).
Module instantiations also contain port lists. This is the means of connecting signals in
the parent module with signals in the child module.
48
3. Nets:
Nets are the things that connect model components together. They are usually thought of as
wires in a circuit. Nets are declared in statements like this:
net_type [range] [delay3] list_of_net_identifiers ;
Example:
wire w1, w2;

tri [31:0] bus32;
wire wire_number_5 = wire_number_2 & wire_number_3;
4. Registers:
Registers are storage elements. Values are stored in registers in procedural assignment
statements. Registers can be used as the source for a primitive or module instance (i.e.
registers can be connected to input ports), but they cannot be driven in the same way a net
can.
Registers are declared in statements like this:
reg [range] list_of_register_identifiers ;
Example:
reg r1, r2;

reg [31:0] bus32;
5. Operators in Verilog:
Logical, arithmetic and relational operators available in Verilog are described in Table
49
Verilog Unary Operators:
6. Continuous assignments:
Continuous assignments are sometimes known as data flow statements because they
describe how data moves from one place, either a net or register, to another. They are usually
thought of as representing combinational logic. In general, any logic functionality which can
be implemented by means of a continuous assignment can also be implemented using
primitive instances.
A continuous assignment looks like this:
assign [delay3] list_of_net_assignments ;
Examples:
assign w1 = w2 & w3;

assign #1 mynet = enable; // mynet is assigned the value after 1 time unit.
7. Procedural Blocks:
Procedural blocks are the part of the language which represents sequential behavior.
A module can have as many procedural blocks as necessary. These blocks are sequences of
executable statements. The statements in each block are executed sequentially, but the blocks
themselves are concurrent and asynchronous to other blocks.
There are two types of procedural blocks, initial blocks and always blocks.
initial <statement> always <statement>
There may be many initial and always blocks in a module. Since there may be many modules
in a model, there may be many initial and always blocks in the entire model. All initial and
always blocks contain a single statement, which may be a compound statement, e.g.
initial
begin statement1 ; statement2 ; ... end
50
a. Initial Block:
All initial blocks begin at time 0 and execute the initial statement. Because the
statement may be a compound statement, this may entail executing lots of statements.
There may be time or event controls, as well as all of the control constructs in the
language. As a result, an initial block may cause activity to occur throughout the
entire simulation of the model.
When the initial statement finishes execution, the initial block terminates. If
the initial statement is a compound statement, then the statement finishes after its last
statement finishes.
Example:
initial x = 0; // a simple initialization
initial begin
x = 1; // an initialization
y = f(x);
#1 x = 0; // a value change 1 time unit later
y = f(x);
end
b. Always Block:
Always blocks also begin at time 0. The only difference between an always
block and an initial block is that when the always statement finishes execution, it
starts executing again. Note that if there is no time or event control in the always
block, simulation time can never advance beyond time 0. Example,
always
#10 clock = ~clock;
8. Behavioral modeling constructs:
a. Conditional if-else construct:
The if - else statement controls the execution of other statements in a

procedural block.
Syntax:
if (condition)
statements;
if (condition)
statements;
else
statements;
if (condition)
statements;
else if (condition)
statements;
................
else
statements;
Example:
// Simple if statement
51
if (enable)
q <= d;
// One else statement
if (reset == 1'b1)
q <= 0;;
else
q <= d;
// Nested if-else-if statements
if (reset == 1'b0)
counter <= 4'b0000;
else if (enable == 1'b1 && up_en == 1'b1)
counter <= counter + 1'b1;
else if (enable == 1'b1 && down_en == 1'b1);
counter <= counter - 1'b0;
else
counter <= counter; // Redundant code
b. Case statement:
The case statement compares an expression to a series of cases and executes

the statement or statement group associated with the first matching case. Case
statement supports single or multiple statements. Multiple statements can be grouped
using begin and end keywords.
Syntax:
case (<expression>)
<case1> : <statement>
<case2> : <statement>
.....
default : <statement>
endcase
Example:
module mux (a,b,c,d,sel,y);

input a, b, c, d;
input [1:0] sel;
output y;
reg y;
always @ (a or b or c or d or sel)
case (sel)
0 : y = a;
1 : y = b;
2 : y = c;
3 : y = d;
default : $display("Error in SEL");
endcase
endmodule
9. Module instantiations and hierarchies:
Verilog allows you to represent the hierarchy of a design. A more common way of
depicting hierarchical relationships is:
52
We say that a parent instantiates a child module. That is, it creates an instance of it to
be a submodel of the parent. In this example,
system instantiates comp_1, comp_2

comp_2 instantiates sub_3
Modules in a hierarchy have both a type and a name. Module types are defined in
Verilog. There can be many module instances of the same type of module in a single
hierarchy. The module definition by itself does not create a module. Modules are created by
being instantiated in another module, like this:
module <module_name_1> (<portlist>);

.
<module_name_2> <instance_name> (<portlist>);
.
endmodule
11. VHDL Hardware Modeling:
53
This is just an introductory level tutorial to the VHDL language. The reader is
encouraged to go through the various VHDL tutorials to understand the language better:
VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware
Description Language. This tutorial deals with VHDL, as described by the IEEE standard
1076-1993.
A hardware description language is inherently parallel, i.e. commands, which

correspond to logic gates, are executed (computed) in parallel, as soon as a new input arrives.
A HDL program mimics the behavior of a physical, usually digital, system. It also allows
incorporation of timing specifications (gate delays) as well as to describe a system as an
interconnection of different components.
Levels of representation and abstraction

A digital system can be represented at different levels of abstraction. This keeps the
description and design of complex systems manageable.
The highest level of abstraction is the behavioral level that describes a system in
terms of what it does (or how it behaves) rather than in terms of its components and
interconnection between them. A behavioral description specifies the relationship between
the input and output signals. This could be a Boolean expression or a more abstract
description such as the Register Transfer or Algorithmic level.
As an example, let us consider a simple circuit that warns car passengers when the
door is open or the seatbelt is not used whenever the car key is inserted in the ignition lock At
the behavioral level this could be expressed as,
Warning = Ignition_on AND ( Door_open OR Seatbelt_off)
The structural level, on the other hand, describes a system as a collection of gates
and components that are interconnected to perform a desired function. A structural
description could be compared to a schematic of interconnected logic gates. It is a
representation that is usually closer to the physical realization of a system.
For the example above, the structural representation is shown in Figure below.
54
Structural representation of a “buzzer” circuit.
VHDL allows one to describe a digital system at the structural or the behavioral level.
The behavioral level can be further divided into two kinds of styles: Data flow and
Algorithmic. The dataflow representation describes how data moves through the system.
This is typically done in terms of data flow between registers (Register Transfer level). The
data flow model makes use of concurrent statements that are executed in parallel as soon as
data arrives at the input. On the other hand, sequential statements are executed in the
sequence that they are specified. VHDL allows both concurrent and sequential signal
assignments that will determine the manner in which they are executed.
Basic Structure of a VHDL file
A digital system in VHDL consists of a design entity that can contain other entities
that are then considered components of the top-level entity. Each entity is modeled by an
entity declaration and an architecture body. One can consider the entity declaration as the
interface to the outside world that defines the input and output signals, while the architecture
body contains the description of the entity and is composed of interconnected entities,
processes and components, all operating concurrently, as schematically shown in Figure. In a
typical design there will be many such entities connected together to perform the desired
function.
VHDL uses reserved keywords that cannot be used as signal names or identifiers.
Keywords and user-defined identifiers are case insensitive. Lines with comments start with
two adjacent hyphens (--) and will be ignored by the compiler. VHDL also ignores line
breaks and extra spaces. VHDL is a strongly typed language which implies that one has
always to declare the type of every object that can have a value, such as signals, constants
and variables.
a. Entity Declaration
55
The entity declaration defines the NAME of the entity and lists the input and output ports.
The general form is as follows,
entity NAME_OF_ENTITY is [ generic generic_declarations);]

port (signal_names: mode type;
signal_names: mode type;
:
signal_names: mode type);
end [NAME_OF_ENTITY] ;
An entity always starts with the keyword entity, followed by its name and the
keyword is. Next are the port declarations using the keyword port. An entity declaration
always ends with the keyword end, optionally [ ] followed by the name of the entity.
• The NAME_OF_ENTITY is a user-selected identifier

• signal_names consists of a comma separated list of one or more user-selected
identifiers that specify external interface signals.
• mode: is one of the reserved words to indicate the signal direction:
o in – indicates that the signal is an input
o out – indicates that the signal is an output of the entity whose value
can only be read by other entities that use it.
o buffer – indicates that the signal is an output of the entity whose value
can be read inside the entity’s architecture
o inout – the signal can be an input or an output.
• type: a built-in or user-defined signal type. Examples of types are bit,

bit_vector, Boolean, character, std_logic, and stc_ulogic.
o bit – can have the value 0 and 1
o bit_vector – is a vector of bit values (e.g. bit_vector (0 to 7)
o std_logic, std_ulogic, std_logic_vector, std_ulogic_vector: can have 9
values to indicate the value and strength of a signal. Std_ulogic and
std_logic are preferred over the bit or bit_vector types.
o boolean – can have the value TRUE and FALSE
o integer – can have a range of integer values
o real – can have a range of real values
o character – any printing character
o time – to indicate time
• generic: generic declarations are optional and determine the local constants
used for timing and sizing (e.g. bus widths) the entity. A generic can
have a default value. The syntax for a generic follows,
generic (
constant_name: type [:=value] ;
constant_name: type [:=value] ;
:
constant_name: type [:=value] );
For the example shown above, the entity declaration looks as follows.
-- comments: example of the buzzer circuit of fig. 2
entity BUZZER is
port (DOOR, IGNITION, SBELT: in std_logic;
56
WARNING: out std_logic);

end BUZZER;
The entity is called BUZZER and has three input ports, DOOR, IGNITION and
SBELT and one output port, WARNING. Notice the use and placement of semicolons! The
name BUZZER is an identifier. Inputs are denoted by the keyword in, and outputs by the
keyword out. Since VHDL is a strongly typed language, each port has a defined type. In this
case, we specified the std_logic type. This is the preferred type of digital signals. In
contrast to the bit type that can only have the values ‘1’ and ‘0’, the std_logic and std_ulogic
types can have nine values. This is important to describe a digital system accurately including
the binary values 0 and 1, as well as the unknown value X, the uninitialized value U, “-” for
don’t care, Z for high impedance, and several symbols to indicate the signal strength (e.g. L
for weak 0, H for weak 1, W for weak unknown - see section on Enumerated Types). The
std_logic type is defined in the std_logic_1164 package of the IEEE library. The type defines
the set of values an object can have. This has the advantage that it helps with the creation of
models and helps reduce errors. For instance, if one tries to assign an illegal value to an
object, the compiler will flag the error.
A few other examples of entity declarations follow:
Four-to-one multiplexer of which each input is an 8-bit word.
entity mux4_to_1 is
port (I0,I1,I2,I3: in std_logic_vector(7 downto 0);
OUT1: out std_logic_vector(7 downto 0));
end mux4_to_1;
An example of the entity declaration of a D flip-flop with set and reset inputs is
entity dff_sr is
port (D,CLK,S,R: in std_logic;
Q,Qnot: out std_logic);
end dff_sr;
b. Architecture body
The architecture body specifies how the circuit operates and how it is implemented.
As discussed earlier, an entity or circuit can be specified in a variety of ways, such as
behavioral, structural (interconnected components), or a combination of the above.
The architecture body looks as follows,
architecture architecture_name of NAME_OF_ENTITY is

-- Declarations
-- components declarations
-- signal declarations
-- constant declarations
-- function declarations
-- procedure declarations
-- type declarations
:
begin
-- Statements
57
:
end architecture_name;
Behavioral model
The architecture body for the example shown above, described at the behavioral level,
is given below,
architecture behavioral of BUZZER is

begin
WARNING <= (not DOOR and IGNITION) or (not SBELT and
IGNITION);
end behavioral;
The header line of the architecture body defines the architecture name,
e.g. behavioral, and associates it with the entity, BUZZER. The architecture name can be
any legal identifier. The main body of the architecture starts with the keyword begin and
gives the Boolean expression of the function. We will see later that a behavioral model can be
described in several other ways. The “<= ” symbol represents an assignment operator and
assigns the value of the expression on the right to the signal on the left. The architecture body
ends with an end keyword followed by the architecture name.
A few other examples follow. The behavioral description of a two-input AND gate is
shown below.
entity AND2 is
port (in1, in2: in std_logic;
out1: out std_logic);
end AND2;
architecture behavioral_2 of AND2 is

begin
out1 <= in1 and in2;
end behavioral_2;
An example of a two-input XNOR gate is shown below.
entity XNOR2 is
port (A, B: in std_logic;
Z: out std_logic);
end XNOR2;
architecture behavioral_xnor of XNOR2 is

-- signal declaration (of internal signals X, Y)
signal X, Y: std_logic;
begin
X <= A and B;
Y <= (not A) and (not B);
Z <= X or Y;
End behavioral_xnor;
The statements in the body of the architecture make use of logic operators. Logic
operators that are allowed are: and, or, nand, nor, xor, xnor and not. In
addition, other types of operators including relational, shift, arithmetic are allowed as well
58
(see section on Operators). For more information on behavioral modeling see section on
Behavioral Modeling.
Structural description
The circuit of above example can also be described using a structural model that
specifies what gates are used and how they are interconnected. The following example
illustrates it.
architecture structural of BUZZER is

-- Declarations
component AND2
end component;
component OR2
end component;
component NOT1
port (in1: in std_logic;
end component;
-- declaration of signals used to interconnect gates
signal DOOR_NOT, SBELT_NOT, B1, B2: std_logic;
begin
-- Component instantiations statements
U0: NOT1 port map (DOOR, DOOR_NOT);
U1: NOT1 port map (SBELT, SBELT_NOT);
U2: AND2 port map (IGNITION, DOOR_NOT, B1);
U3: AND2 port map (IGNITION, SBELT_NOT, B2);
U4: OR2 port map (B1, B2, WARNING);
end structural;
Following the header is the declarative part that gives the components (gates) that are
going to be used in the description of the circuits. In our example, we use a two- input AND
gate, two-input OR gate and an inverter. These gates have to be defined first, i.e. they will
need an entity declaration and architecture body (as shown in the previous example). These
can be stored in one of the packages one refers to in the header of the file (see Library and
Packages below). The declarations for the components give the inputs (e.g. in1, in2) and the
output (e.g. out1). Next, one has to define internal nets (signal names). In our example these
signals are called DOOR_NOT, SBELT_NOT, B1, B2 (see Figure 2). Notice that one always
has to declare the type of the signal.
The statements after the begin keyword gives the instantiations of the components
and describes how these are interconnected. A component instantiation statement creates a
new level of hierarchy. Each line starts with an instance name (e.g. U0) followed by a colon
and a component name and the keyword port map. This keyword defines how the
components are connected. In the example above, this is done through positional association:
DOOR corresponds to the input, in1 of the NOT1 gate and DOOR_NOT to the output.
Similarly, for the AND2 gate where the first two signals (IGNITION and
DOOR_NOT) correspond to the inputs in1 and in2, respectively, and the signal B1 to the
59
output out1. An alternative way is to use explicit association between the ports, as shown
below.
label: component-name port map (port1=>signal1, port2=> signal2,… port3=>signaln);
U0: NOT1 port map (in1 => DOOR, out1 => DOOR_NOT);
U1: NOT1 port map (in1 => SBELT, out1 => SBELT_NOT);
U2: AND2 port map (in1 => IGNITION, in2 => DOOR_NOT, out1 => B1);
U3: AND2 port map (in1 => IGNITION, in2 => SBELT_NOT, B2);
U4: OR2 port map (in1 => B1, in2 => B2, out1 => WARNING);
Notice that the order in which these statements are written has no bearing on the
execution since these statements are concurrent and therefore executed in parallel. Indeed, the
schematic that is described by these statements is the same independent of the order of the
statements.
Structural modeling of design lends itself to hierarchical design, in which one can
define components of units that are used over and over again. Once these components are
defined they can be used as blocks, cells or macros in a higher level entity. This can
significantly reduce the complexity of large designs. Hierarchical design approaches are
always preferred over flat designs. We will illustrate the use of a hierarchical design approach
for a 4-bit adder, shown in Figure 4 below. Each full adder can be described by the Boolean
expressions for the sum and carry out signals,
sum = (A ⊕ B) ⊕ C
carry = AB + C(A ⊕ B)
Figure 4: Schematic of a 4-bit adder consisting of full adder modules.
In the VHDL file, we have defined a component for the full adder first. We used
several instantiations of the full adder to build the structure of the 4-bit adder. We have
included the library and use clause as well as the entity declarations.
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Four Bit Adder – Illustrating a hierarchical VHDL model

-- Example of a four bit adder
library ieee;
use ieee.std_logic_1164.all;
-- definition of a full adder
entity FULLADDER is
port (a, b, c: in std_logic;
sum, carry: out std_logic);
end FULLADDER;
architecture fulladder_behav of FULLADDER is
begin
sum <= (a xor b) xor c ;
carry <= (a and b) or (c and (a xor b));
end fulladder_behav;
-- 4-bit adder
library ieee;
entity FOURBITADD is
port (a, b: in std_logic_vector(3 downto 0);
Cin : in std_logic;
sum: out std_logic_vector (3 downto 0);
Cout, V: out std_logic);
end FOURBITADD;
architecture fouradder_structure of FOURBITADD is

signal c: std_logic_vector (4 downto 0);
component FULLADDER
port(a, b, c: in std_logic;
end component;
begin
FA0: FULLADDER
port map (a(0), b(0), Cin, sum(0), c(1));
FA1: FULLADDER
port map (a(1), b(1), C(1), sum(1), c(2));
FA2: FULLADDER
port map (a(2), b(2), C(2), sum(2), c(3));
FA3: FULLADDER
port map (a(3), b(3), C(3), sum(3), c(4));
V <= c(3) xor c(4);
Cout <= c(4);
end fouradder_structure;
Notice that the same input names a and b for the ports of the full adder and the 4-bit
adder were used. This does not pose a problem in VHDL since they refer to different levels.
However, for readability, it may be easier to use different names. We needed to define the
internal signals c(4:0) to indicate the nets that connect the output carry to the input carry of
the next full adder. For the first input we used the input signal Cin. For the last carry we
defined c(4) as an internal signal since the last carry is needed as the input to the xor gate. We
could not use the output signal Cout since VHDL does not allow the use of outputs as
internal signals! For this reason we had to define the internal carry c(4) and assign c(4) to the
output carry signal Cout.
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c. Library and Packages:
library and use keywords
A library can be considered as a place where the compiler stores information about a
design project. A VHDL package is a file or module that contains declarations of commonly
used objects, data type, component declarations, signal, procedures and functions that can be
shared among different VHDL models.
We mentioned earlier that std_logic is defined in the package ieee.std_logic_1164 in

the ieee library. In order to use the std_logic one needs to specify the library and package.
This is done at the beginning of the VHDL file using the library and the use keywords as
follows:
library ieee;
The .all extension indicates to use all of the ieee.std_logic_1164 package.
The Xilinx Foundation Express comes with several packages.
ieee Library:
• std_logic_1164 package: defines the standard datatypes

• std_logic_arith package: provides arithmetic, conversion and comparison functions
for the signed, unsigned, integer, std_ulogic, std_logic and std_logic_vector types
• std_logic_unsigned
• std_logic_misc package: defines supplemental types, subtypes, constants and
functions for the std_logic_1164 package.
To use any of these one must include the library and use clause:
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
One can add other libraries and packages. The syntax to declare a package is as follows:
-- Package declaration
package name_of_package is
package declarations
end package name_of_package;
-- Package body declarations
package body name_of_package is
package body declarations
end package body name_of_package;
For instance, the basic functions of the AND2, OR2, NAND2, NOR2, XOR2, etc.
components need to be defined before one can use them. This can be done in a package, e.g.
basic_func for each of these components, as follows:
-- Package declaration
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library ieee;
package basic_func is
-- AND2 declaration
component AND2
generic (DELAY: time :=5ns);
port (in1, in2: in std_logic; out1: out std_logic);
end component;
-- OR2 declaration
component OR2
generic (DELAY: time :=5ns);
end component;
end package basic_func;
-- Package body declarations

library ieee;
package body basic_func is
-- 2 input AND gate
entity AND2 is
generic (DELAY: time);
end AND2;
architecture model_conc of AND2 is
begin
out1 <= in1 and in2 after DELAY;
end model_conc;
-- 2 input OR gate
entity OR2 is
generic (DELAY: time);
end OR2;
architecture model_conc2 of AND2 is
begin
out1 <= in1 or in2 after DELAY;
end model_conc2;
end package body basic_func;
Notice that we included a delay of 5 ns. However, it should be noticed that delay
specifications are ignored by the Foundation synthesis tool. We made use of the predefined
type std_logic that is declared in the package std_logic_1164. We have included the
library and use clause for this package. This package needs to be compiled and placed in
a library. Lets call this library my_func. To use the components of this package one has to
declare it using the library and use clause:
library ieee, my_func;

use ieee.std_logic_1164.all, my_func.basic_func.all;
One can concatenate a series of names separated by periods to select a package. The
library and use statements are connected to the subsequent entity statement. The library
and use statements have to be repeated for each entity declaration.
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Constant
A constant can have a single value of a given type and cannot be changed during the
simulation. A constant is declared as follows,
constant list_of_name_of_constant: type [ := initial value] ;
where the initial value is optional. Constants can be declared at the start of an
architecture and can then be used anywhere within the architecture. Constants declared
within a process can only be used inside that specific process.
constant RISE_FALL_TME: time := 2 ns;

constant DELAY1: time := 4 ns;
constant RISE_TIME, FALL_TIME: time:= 1 ns;
constant DATA_BUS: integer:= 16;
Variable
A variable can have a single value, as with a constant, but a variable can be updated
using a variable assignment statement. The variable is updated without any delay as soon as
the statement is executed. Variables must be declared inside a process. The variable
declaration is as follows:
variable list_of_variable_names: type [ := initial value] ;
A few examples follow:
variable CNTR_BIT: bit :=0;

variable VAR1: boolean :=FALSE;
variable SUM: integer range 0 to 256 :=16;
variable STS_BIT: bit_vector (7 downto 0);
The variable SUM, in the example above, is an integer that has a range from 0 to 256
with initial value of 16 at the start of the simulation. The fourth example defines a bit vector
or 8 elements: STS_BIT(7), STS_BIT(6),… STS_BIT(0).
A variable can be updated using a variable assignment statement such as
Variable_name := expression;
Signal
Signals are declared with the following statement:
signal list_of_signal_names: type [ := initial value] ;
signal SUM, CARRY: std_logic;

signal CLOCK: bit;
signal TRIGGER: integer :=0;
signal DATA_BUS: bit_vector (0 to 7);
signal VALUE: integer range 0 to 100;
Signals are updated when their signal assignment statement is executed, after a certain
delay, as illustrated below,
SUM <= (A xor B) after 2 ns;
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One can also specify multiple waveforms using multiple events as illustrated below,
signal wavefrm : std_logic;

wavefrm <= ‘0’, ‘1’ after 5ns, ‘0’ after 10ns, ‘1’ after 20 ns;
It is important to understand the difference between variables and signals, particularly

how it relates to when their value changes. A variable changes instantaneously when the
variable assignment is executed. On the other hand, a signal changes a delay after the
assignment expression is evaluated. If no delay is specified, the signal will change after a
delta delay. This has important consequences for the updated values of variables and signals.
Lets compare the two files in which a process is used to calculate the signal RESULT [7].
Example of a process using Variables
architecture VAR of EXAMPLE is

signal TRIGGER, RESULT: integer := 0;
begin
process
variable variable1: integer :=1;
begin
wait on TRIGGER;
variable1 := variable2;
variable2 := variable1 + variable3;
variable3 := variable2;
RESULT <= variable1 + variable2 + variable3;
end process;
end VAR
Example of a process using Signals
architecture SIGN of EXAMPLE is

signal TRIGGER, RESULT: integer := 0;
signal signal1: integer :=1;
begin
process
begin
wait on TRIGGER;
signal1 <= signal2;
signal2 <= signal1 + signal3;
signal3 <= signal2;
RESULT <= signal1 + signal2 + signal3;
end process;
end SIGN;
In the first case, the variables “variable1, variable2 and variable3” are computed
sequentially and their values updated instantaneously after the TRIGGER signal arrives.
Next, the RESULT is computed using the new values of the variables. This results in the
following values (after a time TRIGGER): variable1 = 2, variable2 = 5 (=2+3), variable3= 5.
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Since RESULT is a signal it will be computed at the time TRIGGER and updated at the time
TRIGGER + Delta. Its value will be RESULT=12.
On the other hand, in the second example, the signals will be computed at the time
TRIGGER. All of these signals are computed at the same time, using the old values of
signal1, 2 and 3. All the signals will be updated at Delta time after the TRIGGER has arrived.
Thus the signals will have these values: signal1= 2, signal2= 4 (=1+3), signal3=2 and
RESULT=7.
Enumerated Types
An enumerated type consists of lists of character literals or identifiers. The
enumerated type can be very handy when writing models at an abstract level. The syntax for
an enumerated type is,
type type_name is (identifier list or character literal);
Here are some examples,
type my_3values is (‘0’, ‘1’, ‘Z’);

type PC_OPER is (load, store, add, sub, div, mult, shiftl, shiftr);
type hex_digit is (‘0’, ‘1’, ‘2’, ‘3’, ‘4’, ‘5’, ‘6’, ‘7’, 8’, ‘9’, ‘A’, ‘B’, ‘C’, ‘D’, ‘E’, ‘F’);
type state_type is (S0, S1, S2, S3);
Examples of objects that use the above types:
signal SIG1: my_3values;

variable ALU_OP: pc_oper;
variable first_digit: hex_digit :=’0’;
signal STATE: state_type :=S2;
If one does not initialize the signal, the default initialization is the leftmost element of the list.
Enumerated types have to be defined in the architecture body or inside a package as

shown in the section above.
An example of an enumerated type that has been defined in the std_logic_1164

package is the std_ulogic type, defined as follows
type STD_ULOGIC is (
‘U’, -- uninitialized
‘X’, -- forcing unknown
‘0’, -- forcing 0
‘1’, -- forcing 1
‘Z’, -- high impedance
‘W’, -- weak unknown
‘L’, -- weak 0
‘H’. -- weak 1
‘-‘); -- don’t care
In order to use this type one has to include the clause before each entity declaration.
library ieee; use ieee.std_logic_1164.all;
66
signal OUT1: resolved: std_ulogic;
Array Type
An array type is declared as follows:
type array_name is array (indexing scheme) of element_type;
type MY_WORD is array (15 downto 0) of std_logic;

type YOUR_WORD is array (0 to 15) of std_logic;
type VAR is array (0 to 7) of integer;
type STD_LOGIC_1D is array (std_ulogic) of std_logic;
In the first two examples above we have defined a one-dimensional array of elements
of the type std_logic indexed from 15 down to 0, and 0 up to 15, respectively. The last
example defines a one-dimensional array of the type std_logic elements that uses the type
std_ulogic to define the index constraint. Thus this array looks as follows:
Index: ‘U’ ‘X’ ‘0’ ‘1’ ‘Z’ ‘W’ ‘L’ ‘H’ ‘-‘
Element:
We can now declare objects of these data types. Some examples are given
signal MEM_ADDR: MY_WORD;

signal DATA_WORD: YOUR_WORD := B“1101100101010110”;
constant SETTING: VAR := (2,4,6,8,10,12,14,16);
In the first example, the signal MEM_ADDR is an array of 16 bits, initialized to all
‘0’s. To access individual elements of an array we specify the index. For example,
MEM_ACCR(15) accesses the left most bit of the array, while DATA_WORD(15) accesses
the right most bit of the array with value ‘0’. To access a subrange, one specifies the index
range, MEM_ADDR(15 downto 8) or DATA_WORD(0 to 7).
Multidimensional arrays can be declared as well by using a similar syntax as above,
type MY_MATRIX3X2 is array (1 to 3, 1 to 2) of natural;

type YOUR_MATRIX4X2 is array (1 to 4, 1 to 2) of integer;
type STD_LOGIC_2D is array (std_ulogic, std_ulogic) of std_logic;
variable DATA_ARR: MY_MATRIX :=((0,2), (1,3), (4,6), (5,7));
The variable array DATA_ARR will then be initialized to,
0 2
1 3
4 6
5 7
To access an element one specifies the index, e.g. DATA_ARR(3,1) returns the value 4.
The last example defines a 9x9 array or table with an index the elements of the std_ulogic
type.
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Sometimes it is more convenient not to specify the dimension of the array when the
array type is declared. This is called an unconstrained array type. The syntax for the array
declaration is,
type array_name is array (type range <>) of element_type;
Some examples are
type MATRIX is array (integer range <>) of integer;

type VECTOR_INT is array (natural range <>) of integer;
type VECTOR2 is array (natural range <>, natural range <>) of std_logic;
The range is now specified when one declares the array object,
variable MATRIX8: MATRIX (2 downto -8) := (3, 5, 1, 4, 7, 9, 12, 14, 20, 18);
variable ARRAY3x2: VECTOR2 (1 to 4, 1 to 3)) := ((‘1’,’0’), (‘0’,’-‘), (1, ‘Z’));
Record Type
A second composite type is the records type. A record consists of multiple elements
that may be of different types. The syntax for a record type is the following:
type name is
record
identifier :subtype_indication;
:
identifier :subtype_indication;
end record;
As an example,
type MY_MODULE is
record
RISE_TIME :time;
FALL_TIME : time;
SIZE : integer range 0 to 200;
DATA : bit_vector (15 downto 0);
end record;
signal A, B: MY_MODULE;
To access values or assign values to records, one can use one of the following methods:
A.RISE_TIME <= 5ns;

A.SIZE <= 120;
B <= A;
Type Conversions
Since VHDL is a strongly typed language one cannot assign a value of one data type
to a signal of a different data type. In general, it is preferred to the same data types for the
68
signals in a design, such as std_logic (instead of a mix of std_logic and bit types). Sometimes
one cannot avoid using different types. To allow assigning data between objects of different
types, one needs to convert one type to the other. Fortunately there are functions available in
several packages in the ieee library, such as the std_logic_1164 and the std_logic_arith
packages. As an example, the std_logic_1164 package allows the following conversions:
Conversions supported by std_logic_1164 package

Conversion Function
std_ulogic to bit to_bit(expression)
std_logic_vector to bit_vector to_bitvector(expression)
std_ulogic_vector to bit_vector to_bitvector(expression)
bit to std_ulogic To_StdULogic(expression)
bit_vector to std_logic_vector To_StdLogicVector(expression)
bit_vector to std_ulogic_vector To_StdUlogicVector(expression)
std_ulogic to std_logic_vector To_StdLogicVector(expression)
std_logic to std_ulogic_vector To_StdUlogicVector(expression)
The IEEE std_logic_unsigned and the IEEE std_logic_arith packages allow additional
conversions such as from an integer to std_logic_vector and vice versa.
An example follows.
entity QUAD_NAND2 is
port (A, B: in bit_vector(3 downto 0);
out4: out std_logic_vector (3 downto 0));
end QUAD_NAND2;
architecture behavioral_2 of QUAD_NAND2 is

begin
out4 <= to_StdLogicVector(A and B);
end behavioral_2;
The expression “A and B” which is of the type bit_vector has to be converted to the type
std_logic_vector to be of the same type as the output signal out4.
The syntax of a type conversion is as follows:
type_name (expression);
In order for the conversion to be legal, the expression must return a type that can be
converted into the type type_name. Here are the conditions that must be fulfilled for the
conversion to be possible.
• Type conversions between integer types or between similar array types are possible
• Conversion between array types is possible if they have the same length and if they have
identical element types or convertible element types.
• Enumerated types cannot be converted.
Signal attributes
The following table gives several signal attributes.
69
Attribute Function
signal_name’event returns the Boolean value True if an event on the
signal occurred, otherwise gives a False
signal_name’active returns the Boolean value True there has been a
transaction (assignment) on the signal, otherwise
gives a False
signal_name’transaction returns a signal of the type “bit” that toggles (0 to 1
or 1 to 0) every time there is a transaction on the
signal.
signal_name’last_event returns the time interval since the last event on the
signal
signal_name’last_active returns the time interval since the last transaction
on the signal
signal_name’last_value gives the value of the signal before the last event
occurred on the signal
signal_name’delayed(T) gives a signal that is the delayed version (by time
T) of the original one. [T is optional, default T=0]
signal_name’stable(T) returns a Boolean value, True, if no event has
occurred on the signal during the interval T,
otherwise returns a False. [T is optional, default
T=0]
signal_name’quiet(T) returns a Boolean value, True, if no transaction has
occurred on the signal during the interval T,
otherwise returns a False. [T is optional, default
T=0]
An example of an attribute is
if (CLOCK’event and CLOCK=’1’) then …
This expression checks for the arrival of a positive clock edge. To find out how much time
has passed since the last clock edge, one can use the following attribute:
CLOCK’last_event
Scalar attributes
Several attributes of a scalar type, scalar-type, are supported. The following table shows
some of these attributes.
Attribute Value
scalar_type’left returns the first or leftmost value of scalar-
type in its defined range
scalar_type’right returns the last or rightmost value of scalar-
type in its defined range
scalar_type’low returns the lowest value of scalar-type in its
defined range
scalar_type’high returns the greatest value of scalar-type in
its defined range
scalar_type’ascending True if T is an ascending range, otherwise
70
False
scalar_type’value(s) returns the value in T that is represented by
s (s stands for string value).
Here are a few examples.
type conductance is range 1E-6 to 1E3

units mho;
end units conductance;
type my_index is range 3 to 15;
type my_levels is (low, high, dontcare, highZ);
conductance’right returns: 1E3

conductance’high 1E3
conductance’low 1E-6
my_index’left 3
my_index’value(5) “5”
my_levels’left low
my_levels’low low
my_levels’high highZ
my_levels’value(dontcare) “dontcare”
Operators
VHDL supports different classes of operators that operate on signals, variables and constants.
The different classes of operators are summarized below.
Class
1. Logical operators and or nand nor xor xnor
2. Relational operators = /= < <= > >=
3. Shift operators sll srl sla sra rol ror
4.Addition operators + = &
5. Unary operators + -
6. Multiplying op. * / mod rem
7. Miscellaneous op. ** abs not
The order of precedence is the highest for the operators of class 7, followed by class 6 with
the lowest precedence for class 1. Unless parentheses are used, the operators with the highest
precedence are applied first. Operators of the same class have the same precedence and are
applied from left to right in an expression. As an example, consider the following
std_ulogic_vectors, X (=’010’), Y(=’10’), and Z (‘10101’). The expression
not X & Y xor Z rol 1
is equivalent to ((not X) & Y) xor (Z rol 1) = ((101) & 10) xor (01011) =(10110) xor
(01011) = 11101. The xor is executed on a bit-per-bit basis.
Behavioral Modeling: Sequential Statements
As discussed earlier, VHDL provides means to represent digital circuits at different
levels of representation of abstraction, such as the behavioral and structural modeling. In this
section we will discuss different constructs for describing the behavior of components and
71
circuits in terms of sequential statements. The basis for sequential modeling is the process
construct. As you will see, the process construct allows us to model complex digital systems,
in particular sequential circuits.
a. Process
A process statement is the main construct in behavioral modeling that allows you to use
sequential statements to describe the behavior of a system over time. The syntax for a process
statement is
[process_label:] process [ (sensitivity_list) ] [is]

[ process_declarations]
begin
list of sequential statements such as:
signal assignments
variable assignments
case statement
exit statement
if statement
loop statement
next statement
null statement
procedure call
wait statement
end process [process_label];
An example of a positive edge-triggered D flip-flop with asynchronous clear input follows.
library ieee;
entity DFF_CLEAR is
port (CLK, CLEAR, D : in std_logic;
Q : out std_logic);
end DFF_CLEAR;
architecture BEHAV_DFF of DFF_CLEAR is

begin
DFF_PROCESS: process (CLK, CLEAR)
begin
if (CLEAR = ‘1’) then
Q <= ‘0’;
elsif (CLK’event and CLK = ‘1’) then
Q <= D;
end if;
end process;
end BEHAV_DFF;
A process is declared within architecture and is a concurrent statement. However, the

statements inside a process are executed sequentially. Like other concurrent statements, a
process reads and writes signals and values of the interface (input and output) ports to
communicate with the rest of the architecture. One can thus make assignments to signals that
are defined externally (e.g. interface ports) to the process, such as the Q output of the flip-
72
flop in the above example. The expression CLK’event and CLK = ‘1’ checks for a
positive clock edge (clock event AND clock high).
The sensitivity list is a set of signals to which the process is sensitive. Any change in
the value of the signals in the sensitivity list will cause immediate execution of the process. If
the sensitivity list is not specified, one has to include a wait statement to make sure that the
process will halt. Notice that one cannot include both a sensitivity list and a wait statement.
Variables and constants that are used inside a process have to be defined in the
process_declarations part before the keyword begin. The keyword begin signals the start of
the computational part of the process. The statements are sequentially executed, similarly as
a conventional software program. It should be noted that variable assignments inside a
process are executed immediately and denoted by the “:=” operator. This is in contrast to
signal assignments denoted by “<=” and which changes occur after a delay. As a result,
changes made to variables will be available immediately to all subsequent statements within
the same process. For an example that illustrates the difference between signal and variable
assignments see the section on Data Types (difference between signals and variables).
The previous example of the D flip-flop illustrates how to describe a sequential circuit
with the process statement. Although the process is mainly used to describe sequential
circuits, one can also describe combinational circuits with the process construct. The
following example illustrates this for a Full Adder, composed of two Half Adders. This
example also illustrates how one process can generate signals that will trigger other processes
when events on the signals in its sensitivity list occur [3]. We can write the Boolean
expression of a Half Adder and Full Adder as follows:
S_ha = (A⊕B) and C_ha = AB
For the Full Adder:
Sum = (A⊕B)⊕Cin = S_ha ⊕Cin

Cout = (A⊕B)Cin + AB = S_ha.Cin + C_ha
Figure 5 illustrates how the Full Adder has been modeled.
Figure 5: Full Adder composed of two Half Adders, modeled with two processes P1 and P2.
library ieee;
entity FULL_ADDER is
port (A, B, Cin : in std_logic;
Sum, Cout : out std_logic);
end FULL_ADDER;
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architecture BEHAV_FA of FULL_ADDER is

signal int1, int2, int3: std_logic;
begin
-- Process P1 that defines the first half adder
P1: process (A, B)
begin
int1<= A xor B;
int2<= A and B;
end process;
-- Process P2 that defines the second half adder and the OR --
gate
P2: process (int1, int2, Cin)
begin
Sum <= int1 xor Cin;
int3 <= int1 and Cin;
Cout <= int2 or int3;
end process;
end BEHAV_FA;
Of course, one could simplify the behavioral model significantly by using a single process.
Wait statement
The wait statement will halt a process until an event occurs. There are several forms
of the wait statement,
wait until condition;

wait for time expression;
wait on signal;
wait;
The Xilinx Foundation Express has implemented only the first form of the wait statement.
The syntax is as follows,
wait until signal = value;

wait until signal’event and signal = value;
wait until not signal’stable and signal = value;
The condition in the “wait until” statement must be TRUE for the process to resume. A
few examples follow.
wait until CLK=’1’;

wait until CLK=’0’;
wait until CLK’event and CLK=’1’;
wait until not CLK’stable and CLK=’1’;
Example of a Mealy Machine
The sequence following detector recognizes the input bit sequence X: "1011". The
machine will keep checking for the proper bit sequence and does not reset to the initial state
74
after it recognizes the string. In case we are implementing a Mealy machine, the output is
associated with the transitions as indicated on the following state diagram (Figure 6).
Figure 6: Sequence detector (1011), realized as a Mealy Machine.
The VHDL file is given below.
VHDL file for a sequence detector (1011) implemented as a Mealy Machine

library ieee;
entity myvhdl is
port (CLK, RST, X: in STD_LOGIC;
Z: out STD_LOGIC);
end;
architecture myvhdl_arch of myvhdl is

-- SYMBOLIC ENCODED state machine: Sreg0
type Sreg0_type is (S1, S2, S3, S4);
signal Sreg0: Sreg0_type;
begin
--concurrent signal assignments
Sreg0_machine: process (CLK)
begin
if CLK'event and CLK = '1' then
if RST='1' then
Sreg0 <= S1;
else
case Sreg0 is
when S1 =>
if X='0' then
Sreg0 <= S1;
elsif X='1' then
Sreg0 <= S2;
end if;
when S2 =>
if X='1' then
Sreg0 <= S2;
elsif X='0' then
Sreg0 <= S3;
end if;
when S3 =>
if X='1' then
Sreg0 <= S4;
elsif X='0' then
Sreg0 <= S1;
end if;
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when S4 =>
if X='0' then
Sreg0 <= S3;
elsif X='1' then
Sreg0 <= S2;
end if;
when others =>
null;
end case;
end if;
end if;
end process;
-- signal assignment statements for combinatorial outputs
Z_assignment:
Z <= '0' when (Sreg0 = S1 and X='0') else
'0' when (Sreg0 = S1 and X='1') else
'1';
end myvhdl_arch;
Dataflow Modeling – Concurrent Statements

Behavioral modeling can be done with sequential statements using the process
construct or with concurrent statements. The first method was described in the previous
section and is useful to describe complex digital systems. In this section, we will use
concurrent statements to describe behavior. This method is usually called dataflow modeling.
The dataflow modeling describes a circuit in terms of its function and the flow of data
through the circuit. This is different from the structural modeling that describes a circuit in
terms of the interconnection of components.
Concurrent signal assignments are event triggered and executed as soon as an event
on one of the signals occurs. In the remainder of the section we will describe several
concurrent constructs for use in dataflow modeling.
Simple Concurrent signal assignments:
We have discussed several concurrent examples earlier in the tutorial. In this section
we will review the different types of concurrent signal assignments.
A simple concurrent signal assignment is given in the following examples,
Sum <= (A xor B) xor Cin;

Carry <= (A and B);
Z <= (not X) or Y after 2 ns;
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The syntax is as follows:
Target_signal <= expression;
in which the value of the expression transferred to the target_signal. As soon as an

event occurs on one of the signals, the expression will be evaluated. The type of the
target_signal has to be the same as the type of the value of the expression.
Another example is given below of a 4-bit adder circuit. Notice that we specified the
package: IEEE.std_logic_unsigned in order to be able to use the “+” (addition) operator.
Example of a Four bit Adder using concurrent/behavioral modeling

library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ADD4 is
port (
A: in STD_LOGIC_VECTOR (3 downto 0);
B: in STD_LOGIC_VECTOR (3 downto 0);
CIN: in STD_LOGIC;
SUM: out STD_LOGIC_VECTOR (3 downto 0);
COUT: out STD_LOGIC
);
end ADD4;
architecture ADD4_concurnt of ADD4 is
-- define internal SUM signal including the carry

signal SUMINT: STD_LOGIC_VECTOR(4 downto 0);
begin
-- <<enter your statements here>>
SUMINT <= ('0' & A) + ('0' & B) + ("0000" & CIN);

COUT <= SUMINT(4);
SUM <= SUMINT(3 downto 0);
end ADD4_concurnt;
Structural Modeling
Structural modeling was described briefly in the section Structural Modeling in
“Basic Structure of a VHDL file”. A structural way of modeling describes a circuit in terms
of components and its interconnection. Each component is supposed to be defined earlier
(e.g. in package) and can be described as structural, a behavioral or dataflow model. At the
lowest hierarchy each component is described as a behavioral model, using the basic logic
operators defined in VHDL. In general structural modeling is very good to describe complex
digital systems, though a set of components in a hierarchical fashion.
A structural description can best be compared to a schematic block diagram that can
be described by the components and the interconnections. VHDL provides a formal way to
do this by
• Declare a list of components being used
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• Declare signals which define the nets that interconnect components

• Label multiple instances of the same component so that each instance is
uniquely defined.
The components and signals are declared within the architecture body,
architecture architecture_name of NAME_OF_ENTITY is
-- Declarations
component declarations
signal declarations
begin
-- Statements
component instantiation and connections
:
end architecture_name;
Component declaration
Before components can be instantiated they need to be declared in the architecture

declaration section or in the package declaration. The component declaration consists of the
component name and the interface (ports). The syntax is as follows:
component component_name [is]
[port (port_signal_names: mode type;
port_signal_names: mode type;
:
port_signal_names: mode type);]
end component [component_name];
The component name refers to either the name of an entity defined in a library or an
entity explicitly defined in the VHDL file (see example of the four bit adder).
The list of interface ports gives the name, mode and type of each port, similarly as is
done in the entity declaration.
A few examples of component declaration follow:
component OR2
end component;
component PROC
port (CLK, RST, RW, STP: in std_logic;
ADDRBUS: out std_logic_vector (31 downto 0);
DATA: inout integer range 0 to 1024);
component FULLADDER
port(a, b, c: in std_logic;
end component;
As mentioned earlier, the component declaration has to be done either in the
architecture body or in the package declaration. If the component is declared in a package,
one does not have to declare it again in the architecture body as long as one uses the
library and use clause.
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Component Instantiation and interconnections:
The component instantiation statement references a component that can be
• Previously defined at the current level of the hierarchy or

• Defined in a technology library (vendor’s library).
The syntax for the components instantiation is as follows,
instance_name : component name

port map (port1=>signal1, port2=> signal2,… port3=>signaln);
The instance name or label can be any legal identifier and is the name of this
particular instance. The component name is the name of the component declared earlier using
the component declaration statement. The port name is the name of the port and signal is the
name of the signal to which the specific port is connected. The above port map associates the
ports to the signals through named association. An alternative method is the positional
association shown below,
port map (signal1, signal2,…signaln);
in which the first port in the component declaration corresponds to the first signal, the second
port to the second signal, etc. The signal position must be in the same order as the declared
component’s ports. One can mix named and positional associations as long as one puts all
positional associations before the named ones. The following examples illustrates this,
component NAND2
end component;
signal int1, int2, int3: std_logic;
architecture struct of EXAMPLE is
U1: NAND2 port map (A,B,int1);
U2: NAND2 port map (in2=>C, in2=>D, out1=>int2);
U3: NAND3 port map (in1=>int1, int2, Z);
…..
12. Sample Coding (VHDL):-

1) Half Adder:-
library IEEE;
79
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity halfadder is
Port ( a : in std_logic;
b : in std_logic;
s : out std_logic;
c : out std_logic);
end halfadder;
architecture Behavioral of halfadder is
begin
s <= a xor b;
c <= a and b;
end Behavioral;
2) Full Adder:-
library IEEE;
entity fa is
b : in std_logic;
cin : in std_logic;
sum : out std_logic;
cout : out std_logic);
end fa;
architecture Behavioral of fa is
begin
sum <= a xor b xor cin;
cout <= (a and b) or (b and cin) or (cin and a);
end Behavioral;
3) 1 - Bit Full Adder:-
library IEEE;
entity fa is
b : in std_logic;
cin : in std_logic;
end fa;
architecture Behavioral of fa is
begin
sum <= a xor b xor cin;
cout <= (a and b) or (b and cin) or (cin and a);
end Behavioral;
80
3) 8 - Bit Full Adder:
library IEEE;
entity adder_8 is
Port ( a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
cin : in std_logic;
cout : out std_logic;
sum : out std_logic_vector(7 downto 0));
end adder_8;
architecture Behavioral of adder_8 is
component fa is
b : in std_logic;
cin : in std_logic;
end component;
signal c : std_logic_vector(6 downto 0);
begin
Inst0 : fa port map (a => a(0), b => b(0), cin => cin, cout
=> c(0), sum => sum(0));
Inst1 : fa port map (a => a(1), b => b(1), cin => c(0), cout
=> c(1), sum => sum(1));
=> c(2), sum => sum(2));
=> c(3), sum => sum(3));
=> c(4), sum => sum(4));
=> c(5), sum => sum(5));
=> c(6), sum => sum(6));
=> cout, sum => sum(7));
end Behavioral;
4) 4 – BIT MULTIPLIER:
library IEEE;
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entity multiplier is
port( clk : in std_logic;
a, b : in std_logic_vector(3 downto 0);
product : out std_logic_vector(9 downto 0));
end multiplier;
architecture Behavioral of multiplier is
signal cin : std_logic:='0';
signal s1,s2,s3,s4 : std_logic_vector(7 downto 0);
signal a1,a2,a3,a4 : std_logic_vector(7 downto 0);
signal sum1 : std_logic_vector(8 downto 1);
signal sum2 : std_logic_vector(8 downto 1);
signal carry1 : std_logic_vector(8 downto 1);
signal carry2 : std_logic_vector(8 downto 1);
signal out1,out2 : std_logic_vector(8 downto 0);
signal sum3,carry3 : std_logic_vector(9 downto 1);
begin
process(clk)
begin
if clk 'event and clk='1' then
s1<= "0000" & a ;
s2<= "000" & a & '0';
s3<= "00" & a & "00";
s4<= '0' & a & "000";
if b(0)='1' then
a1<=s1;
else
a1<= "00000000";
end if;
if b(1)='1' then
a2<=s2;
else
a2<="00000000";
end if;
if b(2)='1' then
a3<=s3;
else
a3<="00000000";
end if;
if b(3)='1' then
a4<=s4;
else
a4<="00000000";
end if;
--------------------------------------------------------------
carry1(1)<=(a1(0) and a2(0)) or (a2(0) and cin) or (cin and
a1(0));
carry1(2)<=(a1(1) and a2(1)) or (a2(1) and carry1(1)) or
(carry1(1) and a1(1));
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out1<=carry1(8) & sum1;
sum1(1)<=a1(0) xor a2(0) xor cin;
sum1(2)<=a1(1) xor a2(1) xor carry1(1);
--------------------------------------------------------------
carry2(1)<=(a3(0) and a4(0)) or (a4(0) and cin) or (cin and
a3(0));
out2<=carry2(8) & sum2;
sum2(1)<=a3(0) xor a4(0) xor cin;
--------------------------------------------------------------
carry3(1)<=(out1(0) and out2(0)) or (out2(0) and cin) or (cin and
out1(0));
carry3(2)<=(out1(1) and out2(1)) or (out2(1) and carry3(1)) or
(carry3(1) and out1(1));
83

sum3(1)<=out1(0) xor out2(0) xor cin;
sum3(2)<=out1(1) xor out2(1) xor carry3(1);
--------------------------------------------------------------
product<=carry3(9) & sum3;
--------------------------------------------------------------
end if;
end process;
end Behavioral;
5) J-K Flip Flop:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity JKff is
port( clk, reset : in std_logic; ---inputs----
j, k : in std_logic;
q : out std_logic); ---outputs---
end JKff;
Architecture behavioural of JKff is
signal q_r :std_logic;
BEGIN
process(j, k, reset, clk)
BEGIN
if reset=’0’ then
q_r <= ‘0’;
elsif(clk’event and clk=’1’) then
if(j=’0’ and k=’0’) then
q_r <= q_r;
elsif(j=’0’ and k=’1’) then
q_r <= ‘0’;
q_r <= ‘1’;
q_r <= not(q_r);
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end if;
end if;
end process;
q<=q_r;
end behavioural;
6) RAM design:
library IEEE;
entity ram_8x32 is
Port ( clk : in std_logic;
wen : in std_logic;
addr : in std_logic_vector(2 downto 0);
di_wr : in std_logic_vector(31 downto 0);
do_wr : out std_logic_vector(31 downto 0));
end ram_8x32;
architecture Behavioral of ram_8x32 is
type ram_type is array (7 downto 0) of std_logic_vector(31 downto
0);
signal dpram8b32_storage : ram_type := (others=> (others => '0'));
begin
process(clk)
begin
if(clk'event and clk='1')then
if(wen = '1') then
dpram8b32_storage(conv_integer(addr)) <= di_wr;
end if;
end if;
end process;
do_wr <= dpram8b32_storage(conv_integer(addr));
end Behavioral;
STATE MACHINES - Mealy Machine
7) TO DETECT THE SEQUENCE “11” WITH OVERLAPPING:

library IEEE;
entity sm_mealy_11_ol is
rst : in std_logic;
x : in std_logic;
z : out std_logic);
end sm_mealy_11_ol;
architecture Behavioral of sm_mealy_11_ol is
begin
process(clk, rst)
type state_type is (A,B);
85
variable NS : state_type;
begin
if(rst = '1')then
NS := A;
elsif(clk'event and clk = '1')then
case NS is
when A =>
z <= '0';
if(x = '1') then
NS := B;
else
NS := A;
end if;
when B =>
if(x = '1')then
NS := B;
z <= '1';
else
NS := A;
z <= '0';
end if;
end case;
end if;
end process;
end Behavioral;
Moore Machine
8) TO DETECT A SEQUENCE “11” WITH OVERLAPPING:
library IEEE;
entity sm_moore_11_ol is
rst : in std_logic;
x : in std_logic;
z : out std_logic);
end sm_moore_11_ol;
architecture Behavioral of sm_moore_11_ol is
type state is (A,B,C);
signal temp : state;
begin
process(rst, clk)
begin
if(rst = '1') then
temp <= A;
elsif(clk'event and clk = '1')then
case temp is
when A =>
86
if(x='0')then
temp <= A;
else
temp <= B;
end if;
when B =>
if (x = '0') then
temp <= A;
else
temp <= C;
end if;
when others =>
if (x = '0') then
temp <= A;
else
temp <= C;
end if;
end case;
end if;
end process;
with temp select
z <= '0' when A | B,
'1' when others;
end Behavioral;
13. Sample Coding (Verilog HDL):-
1) NAND Latch:
module ffNand;
wire q, qBar;
reg preset, clear;
nand #1
g1 (q, qBar, preset),
g2 (qBar, q, clear);
initial
begin
// two slashes introduce a single line comment
$monitor ($time,,
"Preset = %b clear = %b q = %b qBar = %b",
preset, clear, q, qBar);
//waveform for simulating the nand flip flop
#10 preset = 0; clear = 1;
#10 preset = 1;
#10 clear = 0;
#10 clear = 1;
#10 $finish;
87
end
endmodule
2) Top Level of the Fibonacci Number Generator:
module top();
wire flag, numProduced, numConsumed;
wire [15:0] number, numberOut;
nandLatch ready (flag, , numConsumed, numProduced);

numberGen ng (number, numProduced, flag);
fibNumberGen fng (number, flag, numConsumed, numberOut);
endmodule
3) A One-Bit Full Adder:
module fullAdder(cOut, sum, aIn, bIn, cIn);

output cOut, sum;
input aIn, bIn, cIn;
wire x2;
nand (x2, aIn, bIn),

(cOut, x2, x8);
xnor (x9, x5, x6);
nor (x5, x1, x3),
(x1, aIn, bIn);
or (x8, x1, x7);
not (sum, x9),
(x3, x2),
(x6, x4),
(x4, cIn),
(x7, x6);
endmodule
4) A User-Defined Combinational Primitive:
primitive carry(carryOut, carryIn, aIn, bIn);

output carryOut;
input carryIn,
aIn,
bIn;
table
0 00 : 0;
0 01 : 0;
0 10 : 0;
0 11 : 1;
1 00 : 0;
1 01 : 1;
1 10 : 1;
1 11 : 1;
88
endtable
endprimitive
5) A Carry Primitive With Shorthand Notation:
primitive carryAbbrev(carryOut, carryIn, aIn, bIn);

output carryOut;
input aIn,
bIn,
carryIn;
table
0 0? : 0;
0 ?0 : 0;
? 00 : 0;
? 11 : 1;
1 ?1 : 1;
1 1? : 1;
endtable
endprimitive
6) A User-Defined Sequential Primitive:
primitive latch (q, clock, data);

output q;
reg q;
input clock, data;
table
// clock data state output
0 1 : ? : 1;
0 0 : ? : 0;
1 ? : ? : -;
endtable
endprimitive
7) A Static RAM Cell:
//description of a MOS static RAM cell

module sram(dataOut, address, dataIn, write);
output dataOut;
input address, dataIn, write;
tri w1, w3, w4, w43;
bufif1
g1(w1, dataIn, write);
tranif1
g2(w4, w1, address);
not (pull0, pull1)
g3(w3, w4), g4(w4, w3);
buf
g5(dataOut, w1);
89
endmodule
Traffic Light Controller (VHDL):
library IEEE;
---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity traffic_fsm is
Port ( CLK_4M,RESET : in std_logic;
TRC_LS,TRC_LW,TRC_LN,TRC_LE: out std_logic;
TRC_SS,TRC_SW,TRC_SN,TRC_SE: out std_logic;
TRC_RS,TRC_RW,TRC_RN,TRC_RE : out std_logic;
TRC_REDS,TRC_REDW,TRC_REDN,TRC_REDE : out
std_logic;
TRC_YS,TRC_YW,TRC_YN,TRC_YE : out std_logic;
TRC_PSR,TRC_PWR,TRC_PNR,TRC_PER : out std_logic;
TRC_PSG,TRC_PWG,TRC_PNG,TRC_PEG : out std_logic);
end traffic_fsm;
architecture Behavioral of traffic_fsm is

type state is (start,south_g,south_orange,south_r,west_g,west_orange,
west_r,east_g,east_orange,east_r,north_g,north_orange,north_r);
signal ps , ns : state;
signal div : std_logic_vector(30 downto 0);
signal clk_s : std_logic;
signal cnt : std_logic_vector(3 downto 0) ;
begin
--*************************** Divider **************************
process(CLK_4M,RESET)
begin
if(RESET = '1') then
div <= (others => '0');
elsif(CLK_4M'event and CLK_4M = '1') then
div <= div + 1;
end if;
end process;
clk_s <= div(20);
--*************************** Counter **************************

process(clk_s ,RESET)
begin
if(RESET = '1') then
90
cnt <= (others => '0');

elsif(clk_s'event and clk_s = '0') then
cnt <= cnt + 1;
end if;
end process;
--*************************** Memory_logic *********************

process(clk_s,RESET)
begin
if (RESET = '1')then
ps <= start;
elsif(clk_s'event and clk_s = '1') then
ps <= ns;
end if;
end process;
--*************************** Input_logic **********************

process(ps)
begin
case ps is
when start =>
ns <= south_g;
when south_g =>
if(cnt = 10)then
ns <= south_orange;
else
ns <= south_g;
end if;
when south_orange =>

if(cnt = 14) then
ns <= south_r;
else
ns <= south_orange;
end if;
when south_r =>
if(cnt = 15)then
ns <= west_g;
else
ns <= south_r;
end if;
when west_g =>
if(cnt = 10) then
ns <= west_orange;
else
ns <= west_g;
end if;
when west_orange =>
if(cnt = 14) then
ns <= west_r;
else
ns <= west_orange;
91
end if;
when west_r =>
if(cnt = 15 )then
ns <= north_g;
else
ns <= west_r;
end if;
when north_g =>
if(cnt = 10)then
ns <= north_orange;
else
ns <= north_g;
end if;
when north_orange =>
if(cnt = 14)then
ns <= north_r;
else
ns <= north_orange;
end if;
when north_r =>
if(cnt = 15)then
ns <= east_g;
else
ns <= north_r;
end if;
when east_g =>
if(cnt = 10)then
ns <= east_orange;
else
ns <= east_g;
end if;
when east_orange =>
if(cnt = 14)then
ns <= east_r;
else
ns <= east_orange;
end if;
when east_r =>
if(cnt = 15)then
ns <= south_g;
else
ns <= east_r;
end if;
when others =>
ns <= start;
end case;
end process;
--*************************** Output_logic **************************
process(ps)
begin
92
TRC_REDS <= '0';

TRC_REDW <= '0';
TRC_REDN <= '0';
TRC_REDE <= '0';
TRC_RS <= '0';
TRC_RW <= '0';
TRC_RN <= '0';
TRC_RE <= '0';
TRC_SS <= '0';
TRC_SW <= '0';
TRC_SN <= '0';
TRC_SE<= '0';
TRC_LS <= '0';
TRC_LW <= '0';
TRC_LN <= '0';
TRC_LE <= '0';
TRC_PSG <= '0';
TRC_PWG <= '0';
TRC_PNG <= '0';
TRC_PEG <= '0';
TRC_YS <= '0';
TRC_YW <= '0';
TRC_YN <= '0';
TRC_YE <= '0';
TRC_PSR <= '0';
TRC_PWR <= '0';
TRC_PNR <= '0';
TRC_PER <= '0';
case ps is
when start =>
TRC_REDS <= '1';
TRC_REDW <= '1';
TRC_REDN <= '1';
TRC_REDE <= '1';
when south_g =>
TRC_LS <= '1';
TRC_RS <= '1';
TRC_SS <= '1';
TRC_LE <= '1';
TRC_REDW <= '1';
TRC_REDN <= '1';
TRC_REDE <= '1';
TRC_PSR <= '1';
TRC_PWR <= '1';
TRC_PNR <= '1';
TRC_PER <= '1';
when south_orange =>
TRC_PNG <= '1';
TRC_LE <= '1';
TRC_LS <= '1';
TRC_YS <= '1';
TRC_REDW <= '1';
93
TRC_REDN <= '1';

TRC_REDE <= '1';
TRC_PSR <= '1';
TRC_PWR <= '1';
TRC_PER <= '1';
when south_r =>
TRC_LS <= '1';
TRC_REDW <= '1';
TRC_REDN <= '1';
TRC_REDE <= '1';
TRC_PSR <= '1';
TRC_PWR <= '1';
TRC_PNR <= '1';
TRC_PER <= '1';
when west_g =>
TRC_LW <= '1';
TRC_LS <= '1';
TRC_RW <= '1';
TRC_SW <= '1';
TRC_REDS <= '1';
TRC_REDN <= '1';
TRC_REDE <= '1';
TRC_PSR <= '1';
TRC_PWR <= '1';
TRC_PNR <= '1';
TRC_PER <= '1';
when west_orange =>
TRC_LW <= '1';
TRC_LS <= '1';
TRC_PEG <= '1';
TRC_YW <= '1';
TRC_REDS <= '1';
TRC_REDN <= '1';
TRC_REDE <= '1';
TRC_PSR <= '1';
TRC_PWR <= '1';
TRC_PNR <= '1';
when west_r =>
TRC_LW <= '1';
TRC_REDS <= '1';
TRC_REDN <= '1';
TRC_REDE <= '1';
TRC_PSR <= '1';
TRC_PWR <= '1';
TRC_PNR <= '1';
TRC_PER <= '1';
when north_g =>
TRC_LN <= '1';
TRC_RN <= '1';
TRC_SN <= '1';
TRC_LW <= '1';
TRC_REDS <= '1';
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TRC_REDW <= '1';

TRC_REDE <= '1';
TRC_PSR <= '1';
TRC_PWR <= '1';
TRC_PNR <= '1';
TRC_PER <= '1';
when north_orange =>
TRC_LN <= '1';
TRC_LW <= '1';
TRC_PSG <= '1';
TRC_YN <= '1';
TRC_REDS <= '1';
TRC_REDW <= '1';
TRC_REDE <= '1';
TRC_PWR <= '1';
TRC_PNR <= '1';
TRC_PER <= '1';
when north_r =>
TRC_LN <= '1';
TRC_REDS <= '1';
TRC_REDW <= '1';
TRC_REDE <= '1';
TRC_PSR <= '1';
TRC_PWR <= '1';
TRC_PNR <= '1';
TRC_PER <= '1';
when east_g =>
TRC_RE <= '1';
TRC_SE<= '1';
TRC_LE <= '1';
TRC_LN <= '1';
TRC_REDS <= '1';
TRC_REDW <= '1';
TRC_REDN <= '1';
TRC_PSR <= '1';
TRC_PWR <= '1';
TRC_PNR <= '1';
TRC_PER <= '1';
when east_orange =>
TRC_LN <= '1';
TRC_LE <= '1';
TRC_PWG <= '1';
TRC_YE <= '1';
TRC_REDS <= '1';
TRC_REDW <= '1';
TRC_REDN <= '1';
TRC_PSR <= '1';
TRC_PNR <= '1';
TRC_PER <= '0';
when east_r =>
TRC_LE <= '1';
TRC_REDS <= '1';
95
TRC_REDW <= '1';

TRC_REDN <= '1';
TRC_PSR <= '1';
TRC_PWR <= '1';
TRC_PNR <= '1';
TRC_PER <= '1';
when others =>
TRC_REDS <= '0';
TRC_REDW <= '0';
TRC_REDN <= '0';
TRC_REDE <= '0';
TRC_RS <= '0';
TRC_RW <= '0';
TRC_RN <= '0';
TRC_RE <= '0';
TRC_SS <= '0';
TRC_SW <= '0';
TRC_SN <= '0';
TRC_SE<= '0';
TRC_LS <= '0';
TRC_LW <= '0';
TRC_LN <= '0';
TRC_LE <= '0';
TRC_PSG <= '0';
TRC_PWG <= '0';
TRC_PNG <= '0';
TRC_PEG <= '0';
TRC_YS <= '0';
TRC_YW <= '0';
TRC_YN <= '0';
TRC_YE <= '0';
TRC_PSR <= '0';
TRC_PWR <= '0';
TRC_PNR <= '0';
TRC_PER <= '0';
end case;
end process;
end Behavioral;
Description of above Code:-

To Start the Traffic light controller
1. Initially the Red light of all the directions is ON.
2. Traffic starts from the South Direction, hence the green light of South direction goes ON.
The signals that are ON, now are :-
Ð TRC_LS ( left south ) –‘1’.
Ð TRC_RS ( right south ) –‘1’.
Ð TRC_SS ( straight south ) –‘1’.
Ð TRC_LE ( left east ) –‘1’.
Ð TRC_REDW ( red west ) –‘1’.
Ð TRC_REDN (red north ) –‘1’.
Ð TRC_REDE(red east ) –‘1’.
Ð TRC_PSG ( pedestrian south red) –‘1’.
96
Ð TRC_PWG ( pedestrian west red) –‘1’.

Ð TRC_PNG ( pedestrian north red) –‘1’.
Ð TRC_PEG ( pedestrian east red) –‘1’.
Similarly when Orange light of South direction is ON then the signals that are ON, now
are
Ð TRC_YS ( yellow south ) –‘1’.
Ð TRC_LE ( left east ) –‘1’.
Ð TRC_REDE (red east ) –‘1’.
Ð TRC_PSR ( pedestrian south red) –‘1’.
Ð TRC_PWR ( pedestrian west red) –‘1’.
Ð TRC_PNR ( pedestrian north red) –‘1’.
Ð TRC_PER ( pedestrian east red) –‘1’.
Similarly when Red light of South direction is ON then the signals that are ON, now are
Ð TRC_REDE (red east ) –‘1’.
Ð TRC_PSR ( pedestrian south red) –‘1’.
Ð TRC_PWR ( pedestrian west red) –‘1’.
Ð TRC_PNR ( pedestrian north red) –‘1’.
Ð TRC_PER ( pedestrian east red) –‘1’.
During this time all ways are Blocked for 1 second except left south ( ls -‘1’ ) and so on.
After that it goes clockwise for all Direction (i.e.:- South then West then North then East)
similarly.
Traffic Light Controller (Verilog HDL):

`timescale 1ns / 1ps
module traffic_controller_verilog(clk, rst, ls,lw,ln,le, ss,sw,sn,se,
rs,rw,rn,re, red_s,red_w,red_n,red_e, ys,yw,yn,ye, ps_r,pw_r,pn_r,pe_r,
ps_g,pw_g,pn_g,pe_g,l_n,y_n,redn,png,l_w,y_w,redw,pwg,l_e,y_e,rede,peg,l_
s,y_s,reds,psg);
input clk;
input rst;
output ls,lw,ln,le;
output ss,sw,sn,se;
output rs,rw,rn,re;
output red_s,red_w,red_n,red_e;
output ys,yw,yn,ye;
output ps_r,pw_r,pn_r,pe_r;
output ps_g,pw_g,pn_g,pe_g;
output l_n,y_n,redn,png ;
output l_w,y_w,redw,pwg ;
output l_e,y_e,rede,peg ;
output l_s,y_s,reds,psg ;
97
reg l_n,y_n,redn,png ;
reg l_w,y_w,redw,pwg ;
reg l_e,y_e,rede,peg ;
reg l_s,y_s,reds,psg ;
reg ls,lw,ln,le;
reg ss,sw,sn,se;
reg rs,rw,rn,re;
reg red_s,red_w,red_n,red_e;
reg ys,yw,yn,ye;
reg ps_r,pw_r,pn_r,pe_r;
reg ps_g,pw_g,pn_g,pe_g;
reg [3:0]ps,ns;
reg [30:0] div;
reg [3:0] cnt;
wire clk_s;
parameter [3:0]start = 4'b0000;
parameter [3:0]south_g = 4'b0001;
parameter [3:0]south_orange = 4'b0010;
parameter [3:0]south_r = 4'b0011;
parameter [3:0]west_g = 4'b0100;
parameter [3:0]west_orange = 4'b0101;
parameter [3:0]west_r = 4'b0110;
parameter [3:0]east_g = 4'b0111;
parameter [3:0]east_orange = 4'b1000;
parameter [3:0]east_r = 4'b1001;
parameter [3:0]north_g = 4'b1010;
parameter [3:0]north_orange = 4'b1011;
parameter [3:0]north_r = 4'b1100;
always@ (posedge clk or posedge rst)
begin
if (rst)
div <= 2'b00;
else
div <= div + 1;
end
assign clk_s = div[20];
//*************************** Counter **************************
always@(posedge clk_s or posedge rst)
begin
if (rst)
cnt <= 4'b0;
else
cnt <= cnt + 1;
end
//*************************** Memory_logic *********************
always@(posedge clk_s or posedge rst)
begin
if (rst)
ps <= start;
else
ps <= ns;
end
98
always @(ps)
case (ps)
start : ns <= south_g;
south_g: begin
if(cnt == 10)
ns <= south_orange;
else
ns <= south_g;
end
south_orange: begin
if(cnt == 14)
ns <= south_r;
else
ns <= south_orange;
end
south_r : begin
if(cnt == 15)
ns <= west_g;
else
ns <= south_r;
end
west_g : begin
if(cnt == 10)
ns <= west_orange;
else
ns <= west_g;
end
west_orange : begin
if(cnt == 14)
ns <= west_r;
else
ns <= west_orange;
end
west_r : begin
if(cnt == 15 )
ns <= north_g;
else
ns <= west_r;
end
north_g : begin
if(cnt == 10)
ns <= north_orange;
else
ns <= north_g;
end
north_orange : begin
if(cnt == 14)
ns <= north_r;
else
ns <= north_orange;
end
north_r : begin
99
if(cnt == 15)
ns <= east_g;
else
ns <= north_r;
end
east_g : begin
if(cnt == 10)
ns <= east_orange;
else
ns <= east_g;
end
east_orange : begin
if(cnt == 14)
ns <= east_r;
else
ns <= east_orange;
end
east_r : begin
if(cnt == 15)
ns <= south_g;
else
ns <= east_r;
end
default : ns <= start;
endcase
//*************************** Output_logic **************************
always@(ps)
begin
red_s <= 0;
red_w <= 0;
red_n <= 0;
red_e <= 0;
redn <= 0;
redw <= 0;
rede <= 0;
reds <= 0;
rs <= 0;
rw <= 0;
rn <= 0;
re <= 0;
ss <= 0;
sw <= 0;
sn <= 0;
se <= 0;
ls <= 0;
lw <= 0;
ln <= 0;
le <= 0;
l_n <= 0;
l_w <= 0;
l_e <= 0;
l_s <= 0;
100
ps_g <= 0;
pw_g <= 0;
pn_g <= 0;
pe_g <= 0;
png <= 0;
pwg <= 0;
peg <= 0;
psg <= 0;
ys <= 0;
yw <= 0;
yn <= 0;
ye <= 0;
y_n <= 0;
y_w <= 0;
y_e <= 0;
y_s <= 0;
ps_r <= 0;
pw_r <= 0;
pn_r <= 0;
pe_r <= 0;
case (ps)
start : begin
red_s <= 1;
red_w <= 1;
red_n <= 1;
red_e <= 1;
redn <= 1;
redw <= 1;
rede <= 1;
reds <= 1;
end
south_g : begin
ls <= 1;
l_s <= 1;
rs <= 1;
ss <= 1;
le <= 1;
l_e <= 1;
red_w <= 1;
red_n <= 1;
red_e <= 1;
redw <= 1;
redn <= 1;
rede <= 1;
ps_r <= 1;
pw_r <= 1;
pn_r <= 1;
pe_r <= 1;
end
south_orange : begin
pn_g <= 1;
png <= 1;
101
le <= 1;
ls <= 1;
l_s <= 1;
ys <= 1;
y_s <= 1;
red_w <= 1;
red_n <= 1;
red_e <= 1;
redw <= 1;
redn <= 1;
rede <= 1;
ps_r <= 1;
pw_r <= 1;
pe_r <= 1;
end
south_r : begin
ls <= 1;
l_s <= 1;
red_w <= 1;
red_n <= 1;
red_e <= 1;
ps_r <= 1;
pw_r <= 1;
pn_r <= 1;
pe_r <= 1;
end
west_g : begin
lw <= 1;
ls <= 1;
rw <= 1;
sw <= 1;
l_w <= 1;
l_s <= 1;
red_s <= 1;
red_n <= 1;
red_e <= 1;
redw <= 1;
redn <= 1;
rede <= 1;
ps_r <= 1;
pw_r <= 1;
pn_r <= 1;
pe_r <= 1;
end
west_orange : begin
lw <= 1;
ls <= 1;
l_w <= 1;
l_s <= 1;
pe_g <= 1;
peg <= 1;
yw <= 1;
102
y_w <= 1;
red_s <= 1;
red_n <= 1;
red_e <= 1;
reds <= 1;
redn <= 1;
rede <= 1;
ps_r <= 1;
pw_r <= 1;
pn_r <= 1;
end
west_r : begin
lw <= 1;
l_w <= 1;
red_s <= 1;
red_n <= 1;
red_e <= 1;
reds <= 1;
redn <= 1;
rede <= 1;
ps_r <= 1;
pw_r <= 1;
pn_r <= 1;
pe_r <= 1;
end
north_g : begin
ln <= 1;
l_n <= 1;
rn <= 1;
sn <= 1;
lw <= 1;
l_w <= 1;
red_s <= 1;
red_w <= 1;
red_e <= 1;
reds <= 1;
redw <= 1;
rede <= 1;
ps_r <= 1;
pw_r <= 1;
pn_r <= 1;
pe_r <= 1;
end
north_orange : begin
ln <= 1;
lw <= 1;
l_n <= 1;
l_w <= 1;
ps_g <= 1;
psg <= 1;
yn <= 1;
y_n <= 1;
103
red_s <= 1;
red_w <= 1;
red_e <= 1;
reds <= 1;
redw <= 1;
rede <= 1;
pw_r <= 1;
pn_r <= 1;
pe_r <= 1;
end
north_r : begin
ln <= 1;
l_n <= 1;
red_s <= 1;
red_w <= 1;
red_e <= 1;
reds <= 1;
redw <= 1;
rede <= 1;
ps_r <= 1;
pw_r <= 1;
pn_r <= 1;
pe_r <= 1;
end
east_g : begin
re <= 1;
se <= 1;
le <= 1;
ln <= 1;
l_n <= 1;
l_e <= 1;
red_s <= 1;
red_w <= 1;
red_n <= 1;
reds <= 1;
redw <= 1;
rede <= 1;
ps_r <= 1;
pw_r <= 1;
pn_r <= 1;
pe_r <= 1;
end
east_orange : begin
ln <= 1;
le <= 1;
l_n <= 1;
l_e <= 1;
pw_g <= 1;
pwg <= 1;
ye <= 1;
y_e <= 1;
red_s <= 1;
104
red_w <= 1;
red_n <= 1;
reds <= 1;
redw <= 1;
rede <= 1;
ps_r <= 1;
pn_r <= 1;
pe_r <= 0;
end
east_r : begin
le <= 1;
l_e <= 1;
red_s <= 1;
red_w <= 1;
red_n <= 1;
reds <= 1;
redw <= 1;
rede <= 1;
ps_r <= 1;
pw_r <= 1;
pn_r <= 1;
pe_r <= 1;
end
default : begin
red_s <= 0;
red_w <= 0;
red_n <= 0;
red_e <= 0;
rs <= 0;
rw <= 0;
rn <= 0;
re <= 0;
ss <= 0;
sw <= 0;
sn <= 0;
se <= 0;
ls <= 0;
lw <= 0;
ln <= 0;
le <= 0;
ps_g <= 0;
pw_g <= 0;
pn_g <= 0;
pe_g <= 0;
ys <= 0;
yw <= 0;
yn <= 0;
ye <= 0;
ps_r <= 0;
pw_r <= 0;
pn_r <= 0;
pe_r <= 0;
105
l_n <= 0;
l_w <= 0;
l_e <= 0;
l_s <= 0;
png <= 0;
pwg <= 0;
peg <= 0;
psg <= 0;
y_n <= 0;
y_w <= 0;
y_e <= 0;
y_s <= 0;
redn <= 0;
redw <= 0;
rede <= 0;
reds <= 0;
end
endcase
end
endmodule
--******************************************************
Description of above Code:-

To Start the Traffic light controller
1. Initially the Red light of all the directions is ON.
2. Traffic starts from the South Direction; hence the green light of South direction goes ON.
The signals that are ON, now are :-
ls ( left south ) –‘1’.
rs ( right south ) –‘1’.
ss ( straight south ) –‘1’.
le ( left east ) –‘1’.
red_w ( red west ) –‘1’.
red_n (red north ) –‘1’.
red_e (red east ) –‘1’.
ps_r ( pedestrian south red) –‘1’.
pw_r ( pedestrian west red) –‘1’.
pn_r ( pedestrian north red) –‘1’.
pe_r ( pedestrian east red) –‘1’.
Similarly when Orange light of South direction is ON then the signals that are ON, now are
ys ( yellow south ) –‘1’.
le ( left east ) –‘1’.
Similarly when Red light of South direction is ON then the signals that are ON, now are
106

During this time all ways are Blocked for 1 second except left south ( ls -‘1’ ) and so on.
After
that it goes clockwise for all Direction (i.e.:- South then West then North then East) similarly.
Verilog Code for Ripple Carry Adder:

-- * Pipelined adder structures
-- * parameterized pipelining stage
-- * ripple carry adder
-- **************************************************
//Define a 1-bit full adder
module fulladd(sum,c_out,a,b,c_in);
//I/O port declarations
Output sum,c_out;
Input a,b,c_in;
//Internal nets
wire s1,c1,c2;
//Instantiate logic gate primitives
xor (s1,a,b);
and (c1,a,b);
xor (sum,s1,c_in);
and (c2,s1,c_in);
xor (c_out,c2,c1);
endmodule
//Define a 4-bit full adder
Module fulladd4(sum,c_out,a,b,c_in);
//I/O PORT DECLARATIONS
output [3:0] sum;
output c_out;
input [3:0]a,b;
input c_in;
//Internal nets
wire c1,c2,c3;
//Instantiate four 1-bit full adders
Fulladd fa0 (sum[0],c1,a[0],b[0],c_in);
Fulladd fa1 (sum[1],c2,a[1],b[1],c1);
Fulladd fa2 (sum[2],c3,a[2],b[2],c2);
Fulladd fa3 (sum[3],c_out,a[3],b[3],c3);
endmodule
Verilog Code for Real Clock Timer:

`timescale 1ns / 1ps
//--This is real time clock in this we use
//4mhz clock
//to generate 1 sec clock we use enable signal high for last 1 count
107
// sec1 counter for reading sec

// sec2 counter for reading sec
// min1 counter for reading min
// min2 counter for reading min
// hr1 counter for reading hr
// hr2 counter for reading hr
module
finalclock_verilog(sgout,dis,hr2,hr1,min2,min1,sec1,sec2,load,tc1,tc2,tc3,tc4,tc5,tc6,enable,
reset,clock);
output [3:0]sec1,sec2,min1,min2,hr1,hr2;
output [7:0]sgout;
output [5:0]dis;
output tc1,tc2,tc3,tc4,tc5,tc6,enable;
input reset,clock,load;
reg [3:0]sec1_rg,sec2_rg,min1_rg,min2_rg,hr1_rg,hr2_rg;
reg [21:0] pulsegen ;
reg [2:0]cnk2;
reg [3:0]mout;
reg [7:0]sgout_rg;
reg [5:0]dis_sig;
//reg tc,tc1,tc2,tc3,tc4,tc5,tc6,enable;
//reg sec1_rg(3:0),sec2_rg(3:0),min1_rg(3:0),min2_rg(3:0),hr1_rg(3:0);
//reg hr2_rg(3:0),pulsegen(21:0),sel(2:0);
//reg mout(3:0),sgout(7:0),ck1(22:0),cnk2(2:0);
//*************************** Pulse Generator ******************
always@(posedge clock or posedge reset)
begin
if (reset)
pulsegen <= 22'b0;
else
begin
if (pulsegen == 22'b1111010000100100000000)
pulsegen <= 22'b0;
else
pulsegen <= pulsegen + 1;
end
end
//Enable signal to generate 1-sec pulse for sec1 counter
assign enable = (pulsegen == 22'b1111010000100100000000) ; //enable signal for
sec1 counter
//************************ Second_cntr1 *************************
begin
if (reset )
sec1_rg <= 4'b0000;
else if (load) begin
sec1_rg <= 4'b0100;
end
else
begin
if (enable)
begin
108
if (sec1_rg == 4'b1001)
sec1_rg <= 4'b0000;
else
sec1_rg <= sec1_rg + 1;
end
end
end
assign sec1 = sec1_rg;
//------------------tc1 signal to start sec2 counter---------------------------
assign tc1 = (sec1_rg == 4'b1001) && (enable == 1);
//--************************* Second_cntr2 ***********************
begin
if (reset )
sec2_rg <= 4'b0000;
sec2_rg <= 4'b0100;
end
else
begin
if (tc1)
begin
if (sec2_rg == 4'b0101) begin
sec2_rg <= 4'b0000;
end
else begin
sec2_rg <= sec2_rg + 1;
end
end
end
end
assign sec2 = sec2_rg;
//-------------------------tc2 signal to start min1 counter-------------------
assign tc2 = (sec2_rg == 4'b0101) && (tc1 == 1);
//--************************ Minute_cntr1 *************************
begin
if (reset )
min1_rg <= 4'b0000;
min1_rg <= 4'b0100;
end
else
begin
if (tc2)
begin
if (min1_rg == 4'b1001) begin
min1_rg <= 4'b0000;
end
else begin
min1_rg <= min1_rg + 1;
end
109
end
end
end
assign min1 = min1_rg;
//------------------------tc3 signal to start min2 counter--------------------
assign tc3 = (min1_rg == 4'b1001) && (tc2 == 1);
//--************************ Hour_cntr1 *************************
begin
if (reset)
min2_rg <= 4'b0000;
min2_rg <= 4'b0100;
end
else
begin
if (tc3)
begin
if (min2_rg == 4'b0101) begin
min2_rg <= 4'b0000;
end
else
begin
min2_rg <= min2_rg + 1;
end
end
end
end
assign min2 = min2_rg;
//---------------------tc4 signal to start hr1 counter--------------------------
assign tc4 = (min2_rg == 4'b0101) && (tc3 == 1);
//--************************ Hour_cntr1 *************************
begin
if (reset)
hr1_rg <= 4'b0000;
hr1_rg <= 4'b0001;
end
else
begin
if (tc6)
begin
hr1_rg <= 4'b0000;
end
else
begin
if (tc4)
begin
if (hr1_rg == 4'b1001) begin
hr1_rg <= 4'b0000;
end
110
else
begin
hr1_rg <= hr1_rg + 1;
end
end
end
end
end
assign hr1 = hr1_rg;
//---------------------tc5 signal to start hr2 counter--------------------------
assign tc5 = (hr1_rg == 4'b1001) && (tc4 == 1);
//------------------------tc6 signal to reset at
23:59:59--------------------------
assign tc6 = (hr2_rg == 4'b0010) && (hr1_rg == 4'b0011) && (tc4 == 1);
//--************************ Hour_cntr2 *************************
begin
if (reset)
hr2_rg <= 4'b0000;
hr2_rg <= 4'b0000;
end
else
begin
if (tc6)
begin
hr2_rg <= 4'b0000;
end
else
begin
if (tc5)
begin
if (hr2_rg == 4'b0010) begin
hr2_rg <= 4'b0000;
end
else
begin
hr2_rg <= hr2_rg + 1;
end
end
end
end
end
assign hr2 = hr2_rg;
always@(posedge pulsegen[9] or posedge reset)
begin
if (reset)
cnk2 <= 3'b0;
else
begin
if (cnk2 == 3'b101)
cnk2 <= 3'b0 ;
111
else
cnk2 <= cnk2 + 1;
end
end
always@(cnk2)
case (cnk2)
3'b000 : mout <= sec1;
3'b001 : mout <= sec2;
3'b010 : mout <= min1;
3'b011 : mout <= min2;
3'b100 : mout <= hr1;
3'b101 : mout <= hr2;
endcase
always@(mout)
case (mout)
4'b0000 : sgout_rg <= 8'b11000000;
4'b0001 : sgout_rg <= 8'b11111001;
4'b0010 : sgout_rg <= 8'b10100100;
4'b0011 : sgout_rg <= 8'b10110000;
4'b0100 : sgout_rg <= 8'b10011001;
4'b0101 : sgout_rg <= 8'b10010010;
4'b0110 : sgout_rg <= 8'b10000010;
4'b0111 : sgout_rg <= 8'b11111000;
4'b1000 : sgout_rg <= 8'b10000000;
4'b1001 : sgout_rg <= 8'b10011000;
endcase
always@(cnk2)
case (cnk2)
3'b000 : dis_sig <= 6'b111110;
3'b001 : dis_sig <= 6'b111101;
3'b010 : dis_sig <= 6'b111011;
3'b011 : dis_sig <= 6'b110111;
3'b100 : dis_sig <= 6'b101111;
3'b101 : dis_sig <= 6'b011111;
endcase
assign sgout = ~ sgout_rg;
assign dis = ~ dis_sig;
endmodule
Possible University Practical Questions

Verilog & VHDL
(Behavior, Structural & Dataflow Modeling)
1) Full Adder using 2 Half-Adders.
112
2) Full Adder using only NAND gates.

3) Full Adder using only NOR gates.
4) Full Subtractor using 2 Half-Subtractors.
5) Full Subtractor using only NAND gates.
6) Full Subtractor using only NOR gates.
7) D - Flip-Flop using +ive clock cycle.
8) D - Flip-Flop using -ive clock cycle.
9) T - Flip-Flop using +ive clock cycle.
10) T - Flip-Flop using -ive clock cycle.
11) D - Latch using positive enable.
12) D - Latch using negative enable.
13) T - Latch using positive enable.
14) T - Latch using negative enable.
15) S-R - Flip-Flop using +ive clock cycle.
16) S-R - Flip-Flop using -ive clock cycle.
17) J-K - Flip-Flop using +ive clock cycle.
18) J-K - Flip-Flop using -ive clock cycle.
19) 8:1 MUX
20) 16:1 MUX
21) 1:8 DEMUX
22) 1:16 DEMUX
23) 8:3 Encoder
24) 3:8 Decoder
25) 4:2 Encoder
26) 2:4 Decoder
27) Conversion of D to T Flip Flop function
28) Conversion of T to D Flip Flop function
29) Conversion of J-K to T Flip Flop function
30) Conversion of T to J-K Flip Flop function
31) Conversion of S-R to T Flip Flop function
32) Conversion of J-K to D Flip Flop function
33) Conversion of S-R to D Flip Flop function
34) Conversion of Binary to BCD converter.
35) Conversion BCD to Excess3.
36) Conversion Excess-3 to BCD code converter.
37) Conversion Binary to Gray Code converter.
38) Conversion Gray to Binary Converter.
39) Conversion BCD to Gray code converter.
40) Design a logic XOR gate using NAND gates only
41) Design a logic XNOR gate using NAND gates only
42) Design logic XOR gate using NOR gates only
43) Design logic XNOR gate using NOR gates only
44) 2 - bit Magnitude Comparator
45) 4 - bit Universal Shift Register (Behaviour Only)
46) 4 - bit Synchronous Counter (Behaviour Only)
47) 2 to 1 Multiplexer with Three-State Buffer (Dataflow only)
48) Traffic light controller for 4-way traffic.
49) Traffic light controller for 2-way traffic.
50) 4 - bit Pipeline parallel adder.
51) 2 - bit Pipeline parallel adder.
52) 8 - bit Multiplier
[write the Program for the truth table] (UDP)
113
53) Realize the circuit using NAND gates:

54) Realize the circuit using NAND gates:
55) Realize the circuit using NOR gates:
56) Realize the circuit using NOR gates:
57) Realize the circuit: f
58) Realize the circuit: g
59) Draw the logic diagram of the digital circuit for the following specifications and check
the output in the FPGA board.
module circuit(A,B,C,D,F)
input A,B,C,D;
output F;
wire w,x,y,z,a,d;
and (x,B,C,d);
and (y,a,C);
and (w,z,B);
or (z,y,A);
or (F,x,w);
not (a,A);
not (d,D);
endmodule
60) Real Time Clock

61) Lift position indicator
----------------------------------------------------------------------------------------------------------------
Processes
1) Simulation
2) Synthesis
3) Placing & Routing
4) Back-annotation
5) Schematic
6) Downloading in FPGA
PART-B:
1. Briefly explain the Simulation diagram (Functional, Transport Delay, Gate Delay,
Inertial Delay).
2. Briefly explain the Synthesis diagram& various Synthesis Software Name.
3. Briefly explain the Place & Route and back annotation diagram.
4. Briefly explain the FPGA Schematic Entry with diagram.
5. Briefly explain the Physical Layout using CAD Tools.
6. Briefly explain about the transistor level circuit design with CAD example.
114

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K.L.N.

COLLEGE OF ENGINEERING, POTTAPALAYAM

(An ISO 9001:2000 certified institution)

ELECTRONICS AND COMMUNICATION ENGINEERING

Janakiram Digitally signed by Janakiraman

VLSI Design LABORATORY

VI Semester ECE Branch

Mr. N. JANAKIRAMAN M.E., M.B.A., I.T.I.L., M.I.S.T.E., (A.C.S.,)

1) Study of Simulation tools

Chapter (1) Simulation of the coding ------------------------------ (10)

EC1404 – VLSI Design Laboratory

1. Create Verilog design input file(s) using template driven editor.

Programmable Logic Device: FPGA

1. Creating a New Project

• Project Name: Write the name of your new project

Leave the top level module type as HDL.

Clicking on NEXT should bring up the following window:

Clicking on NEXT on the above window brings up the following window:

If creating a new source file, Click on the NEW SOURCE.

3. Creating a Verilog HDL input file for a combinational logic design

4. Editing the Verilog source file

• Adding Logic in the generated Verilog Source code template:

Remember that the names are case sensitive.

• Other constructs for modeling the logic function:

1. Simulation of the coding:-

EXPERIMENTAL RESULTS USING SIMULATION TOOLS CAN BE INFERRED FOR:

2. Synthesis of the coding:-

Synthesis your design, from the source window select, synthesis/implementation

1) Double click the schematic to internal view

2) Double click the schematic for internal view

3) Double click outside the schematic to move one-level back

This schematic shows a representation of the design in terms of logic elements

1) Double click the schematic to inner view

2) Double click the LUT to inner view

3) This is Gate Level view of LUT

EXPERIMENTAL RESULTS USING SYNTHESIS TOOLS CAN BE INFERRED FOR:

1) UTILIZATION OF LUTS & SLICES

2) I/O BUFFER ASSIGNMENT

3) RTL SCHEMATIC IN GATE LEVEL

4) TECHNOLOGY SCHEMATIC IN LUT LEVEL

5) TIME DELAY BETWEEN I/Os & PATH

3. Place and Route and Back Annotation for FPGA

You see the Pins in FPGA Æ save file

Save file as XST Default click ok and close the window.

You can see where your pins are placed

See!!! You changed place and route of the design

Double click Back annotated Pin Location

Once back annotation is completed, constraint file is generated.

EXPERIMENTAL RESULTS CAN BE INFERRED FOR:

3) RUN TIME MINIMIZATION

4. Development through Schematic Entry

Click Add I/O markers

Double click the I/O pin

Enter the Name and click ok

Click Add wire button

Final schematic diagram. Then synthesis or simulation process

5. Compilation and Implementation of the Design

User Constraint File:

When programming is complete, the Program Succeeded message is displayed.

6. Testing a Digital Logic Circuit in FPGA

Model of the XC3S400 VLSI development board:

• LCD Interface: - 16 Character/ Digit 2 Row LCD.

• RS : Register select signal used to select Data register or a Command/Status register.

• R/W# : Read/Write select control line.