01 Introduction to the Microprocessor and computer

The Microprocessor and its Architecture

Microprocessor (MP) is an integrated circuit that contains the entire central processing unit (CPU) of a computer
on a single chip. In 1978, Intel introduced a 16-bit microprocessor, the 8086.

Fig: 8086 External Bus

Bus Operation
Bus is group of conducting lines which carry binary information.
Internal Bus: connects two minor components within a major component (or IC), such as the connection
between the control unit and internal registers of the MPU.
External Bus: connects two major components, such as MPU and an interface (Memory or input/output).
Although some systems include more than one external bus, 8086 and 8088 processors contain only one
external bus called system-bus.
Typical system-bus includes: Address-bus (carries physical address of memory or input/output locations),
Data-bus (carries data to be read or written into MPU registers) and Control-bus(carries information to
control the read or write operation).
Address Bus
• Address bus is used by the μP to select a memory location, from where data can be read or written.
• The number of address lines varies from one processor to the other processor and are unidirectional.
• The number of memory locations that the μP can address is determined by number of address lines. A μP
with “N” address lines can address upto 2N locations. i.e. if a μP contains 16 address lines, it can address
216 memory locations.
Data Bus
• The data bus is a bidirectional bus which carries data between the μP and other units of microprocessor
based system(ie. Memory or I/O devices)
• The number of data lines varies from processor to processor.
• Many devices in a system will have their outputs connected to the data bus, but only one device at a time
will have its outputs enabled
Control bus
The μP issues proper timing and bus control signals to memory and I/O device. It is unidirectional.
8086 Architecture
The functional block diagram of 8086 is divided into
• Bus Interface Unit (BIU)
• Execution Unit (EU)
While EU decodes and executes instructions, BIU fetches instructions from memory and stores them in the
QUEUE.
BIU and EU operate in parallel independent of each other.
This type of overlapped operation of the functional units of a MP is called Pipelining.

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Bus Interface Unit: The blocks present in this BIU are,
• Adder
• Segment Registers
• Instruction Pointer(IP)
• The Queue
Adder ( ∑ ): It is the address conversion mechanism used to generate 20bit Physical address.
• 16-bit code segment(CS) register contents are loaded into a 20-bit Adder ( ∑ ) in BIU and shifted to left
by 4-bits, inserting zeros in four LSBs.
• Thus, CS contents are changed from 16 to 20 bits in BIU.
• The 16-bit offset in IP is added to the shifted CS to generate 20-bit physical address.
Segment Registers: The BIU contains four 16-bit segment registers. They are:
1. Code Segment (CS) Register
2. Data Segment (DS) Register
2. Stack Segment (SS) Register
3. Extra Segment (ES) Register
Each segment has a maximum capacity of 64k bytes.
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 • Code segment holds the base address of
memory where instructions of a program are
stored.
• Data segment holds the base address of
memory, where program data, variables and
constants are stored.
• Stack segment holds the base address of stack,
where data related to stack operations are
stored.
• Extra segment stores the base address of
memory, where data corresponding to string
operations are stored.
• Each segment is assigned a base address that
identifies its lowest addressed byte storage
location.

Instruction Pointer (IP): Holds the offset address that should be added to the shifted CS to generate 20-bit
physical address.

Instruction object code queue

• 8086 processor maintains 6-byte object code queue.
• Fetched instructions are arranged in a queue.
• Operates in FIFO (first in first out ).
• Output of this unit is sent to execution unit.

The Execution Unit (EU):

This unit performs the following tasks,
• The EU tells the BIU where to fetch instructions or data from
• It decodes the instructions
• Executes the instructions.
For doing above tasks, the EU has following sections,
• Execution and Control Unit
• Decoder
• ALU
• General purpose registers
• Pointer and Index registers
• Flag registers
Control Unit: This unit directs the internal operations
Decoder: This unit translates the instructions fetched from memory into series of actions.
ALU: This unit performs arithmetic and logical operations.
General-purpose Registers: The 8086 has four 16-bit general purpose registers. Each is further divided into two
8-bit registers-higher order and lower order. They are

• Accumulator AX—AH,AL
• Base Register BX---BH,BL
• Counter Register CX---CH,CL
• Data Register DX---DH,DL
These registers are used for temporary storage of frequently used intermediate results.
The advantage of storing data in the internal registers instead of memory is that they can be accessed much
faster.

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Pointer and Index Registers: There are four other general purpose registers.
Two pointer registers namely,
• Stack pointer(SP)
• Base pointer (BP)
Two index registers namely,
• Source index (SI)
• Destination index (DI)
These registers are used to store offset value of memory address.
• This offset value is used in computing the memory address.
Flag Register
• Flag register is a 16 bit register within the EU of 8086.
• Flag register is also called as status register.
• 9 of the 16 bits of a flag register are implemented.
• It contains 6 status flags and 3 control flags.
• Flag is a flip flop which indicate some condition produced by the execution of an instruction.
• Status flags are Carry flag, Parity flag, Auxiliary Carry flag, Zero flag, Sign flag and overflow flag.
• Control flags are Trap flag, Interrupt flag and Direction flag.
Status flags:
• Carry Flag (CF) : This flag is set if there is a Carry out of the MSB in case of addition or a
Borrow in case of subtraction.
• Parity Flag (PF): This flag is set if the lower byte of the result contains even no. of 1s.
• Auxiliary Carry Flag (AF): This flag is set when there is a carry out of the bit 3 position in an
arithmetic operation.
• Zero Flag (ZF) : This flag is set if the result of an arithmetic or logical operation is zero.
• Sign Flag (SF) : It is set if an arithmetic operation causes the MSB=1(negative).
• Over Flow Flag (OF): This flag is set if an overflow occurs i.e. If the result of a signed operation is large
enough to the capacity of the destination location.
Control Flags:
• Trap Flag (TF): If this flag is set, the processor enters into single step execution mode. i.e., the trap
interrupt is generated after execution of each instruction.
• Interrupt Flag (IF): If this flag is set, the external mask able interrupt is enabled. Otherwise they are
ignored.
• Direction Flag (DF): This is used by String manipulation instructions. If this flag is set, the contents of
index registers will be decremented after each operation.

Addressing Modes:
The processor will get data (operand) from different sources. It can get data from a register. It can access data
directly from an instruction. It can get data from input-output ports, or else from memory location. So, the
different ways in which a processor can access data are called addressing modes.

CS+IP gives physical address where the instruction is present in the code segment of memory.
SS+SP gives physical address where the instruction is present in the stack segment of memory.
An instruction is a command given to the processor so that it can perform a particular task, which is specified by
the user. An instruction contains an op-code and a number of operand fields. Op-code will specify what kind of
operation the processor has to perform on the operands.

Classification of Addressing Modes

1. Register Addressing mode

2. Immediate Addressing mode
3. Memory Addressing mode
4. Relative Addressing mode
5. Implied Addressing mode

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1. Register Addressing Mode
 Source/Destination can be one of the 8086 registers.

2. Immediate Addressing Mode

 8/16 bit data can be specified as part of the instruction.

3. Memory Addressing Mode

 One of the operand is in memory.
 8086 must use
 A Segment Register.
 A 16 bit Offset (Effective Address).
 By default DS register is used for accessing data from memory.
 16 bit offset can be specified in many ways
Different ways of specifying Offset.
A. Direct Memory Addressing
B. Register Indirect Addressing
C. Based Addressing
D. Indexed Addressing
E. Based Indexed Addressing

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A. Direct Memory Addressing
 Effective address is specified directly in the instruction
E.g. MOV BX, [5062]
 20 bit physical address of memory location is calculated using DS and Offset value 5062.

B. Register Indirect
 The effective address of memory operand is present in one of the base or index register [BX, BP, SI, DI].
E.g. MOV CX, [BX]
if DS=1000H, BX=2000H Then the contents of memory location 12000H are copied to the register CX.

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C. Based Addressing
 Effective Address can be obtained by adding 16 bit offset given in instruction along with 8 or 16 bit
displacement.
 Offset register must be base register (BX or BP).
 Segment register is DS or SS.
E.g. MOV AX, 4[BX]
Here address in BX+4 will give the effective address. The contents of segment register are shifted left and added
to this effective address to get Physical address. The data in that physical address is copied into AX.
D. Indexed Addressing
 Effective Address can be obtained by adding 16 bit offset given in instruction along with 8 or 16 bit
displacement.
 Offset register must be Index register (SI or DI).
 Segment Register is DS.
E.g. MOV AX, 4[SI]
Here address in SI+4 will give the effective address. The contents of segment register are shifted left and added
to this effective address to get Physical address. The data in that Physical address is copied into AX.
E. Based Indexed Addressing
 Effective Address can be obtained by adding 16 bit offsets given in instruction along with 8 or 16 bit
displacement.
 Offset registers must be base register (BX or BP) and Index register (SI or DI).
 Segment register is DS
E.g. MOV AX, 4[BX][SI]
Here address in BX+SI+4 will give the effective address. The contents of segment register are shifted left and
added to this effective address to get Physical address. The data in that Physical address is copied into AX.
4. Relative Addressing Mode
 Specify the operands as 8 bit signed displacement relative to PC
E.g. JNC 08H
 If carry=0 then PC is loaded with current PC content + 8 bit signed value. (JNC=Jump with no carry)
5.Implied Addressing Mode
 No operands are specified
E.g. CLC
 means Clear Carry Flag

Data movement instructions

These instructions are used to transfer data from source to destination.
 The operand can be a constant, memory location, register or I/O port address.
MOV Des, Src:
 Src operand can be register, memory location or immediate operand.
 Des can be register or memory operand.
 Both Src and Des cannot be memory location at the same time.
E.g.: MOV AL, BL
MOV BX, [0301 H]
PUSH Operand:
 It pushes the operand onto the top of stack.
E.g.: PUSH BX
POP Des:
 It pops the operand from top of stack to Des.
 Des can be a general purpose register, segment register (except CS) or memory location.
E.g.: POP AX
XCHG Des, Src:
 This instruction exchanges Src with Des.
 It cannot exchange two memory locations directly.
E.g.: XCHG DX, AX

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IN Accumulator, Port Address :
 It transfers the operand from specified port to accumulator register.
E.g.: IN AX, 0028 H
OUT Port Address, Accumulator:
 It transfers the operand from accumulator to specified port.
E.g.: OUT 0028 H, AX
LEA Register, Src: (LEA=Load Effective Address)
 It loads a 16-bit register with the offset address of the data specified by the Src.
E.g.: LEA BX, [DI]
 This instruction loads the contents of DI(offset) into the BX register.
LDS Des, Src: (LDS=Load Data Segment)
 It loads 32-bit pointer from memory source to destination register and DS.
 The offset is placed in the destination register and the segment is placed in DS.
E.g.: LDS BX, [0301 H]
LES Des, Src:(LES=Load Exgtra Segment)
 It loads 32-bit pointer from memory source to destination register and ES.
 The offset is placed in the destination register and the segment is placed in ES.
 This instruction is very similar to LDS except that it initializes ES instead of DS.
E.g.: LES BX, [0301 H]
LAHF:
 It copies(loads) the lower byte of flag register to AH.
SAHF:
 It copies (saves) the contents of AH to lower byte of flag register.
PUSHF:
 Pushes flag register to top of stack.
POPF:
 Pops the stack top to flag register.

Arithmetic Instructions
ADD Des, Src:
 It adds a byte to byte or a word to word.
E.g.:
ADD AL, 74H
ADD DX, AX
ADD AX, [BX]
ADC Des, Src:
 It adds the two operands with CF(Carry Flag).
E.g.:
ADC AL, 74H
ADC DX, AX
ADC AX, [BX]
SUB Des, Src:
 It subtracts a byte from byte or a word from word.
 For subtraction, CF acts as borrow flag.
E.g.:
SUB AL, 74H
SUB DX, AX
SUB AX, [BX]
SBB Des, Src:
 It subtracts the two operands and also the borrow from the result.
E.g.:
SBB AL, 74H
SBB DX, AX
SBB AX, [BX]
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INC Src:
 It increments the byte or word by one.
 The operand can be a register or memory location.
E.g.: INC AX
DEC Src:
 It decrements the byte or word by one.
 The operand can be a register or memory location.
E.g.: DEC AX
NEG Src:
 It creates 2‟s complement of a given number.
 That means, it changes the sign of a number.

CMP Des, Src:

 It compares two specified bytes or words.
 The Src and Des can be a constant, register or memory location.
 Both operands cannot be a memory location at the same time.
 The comparison is done simply by internally subtracting the source from destination.
 The value of source and destination does not change, but the flags are modified to indicate the result.

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Logic Instructions
The logical instructions are and, or, xor, test, and not
The 80x86 logical instructions operate on a bit-by-bit basis. Both 8, 16, and 32 bit versions of each instruction
exist. The AND, NOT, OR, and XOR instructions do the following:
AND dest, source ;dest := dest and source
OR dest, source ;dest := dest or source
XOR dest, source ;dest := dest xor source
NOT dest ;dest := not dest
The specific variations are
AND reg, reg
AND mem, reg
AND reg, mem
AND reg, immediate data
AND mem, immediate data
AND eax/ax/al, immediate data
OR uses the same formats as AND
XOR uses the same formats as AND
NOT register
NOT mem

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Examples:

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Programming the microprocessor
From the discussion of microprocessor 8086, it is clear that all the instructions are nothing but the combination
of 0s and 1s. ‘0’ indicates a low signal (may be voltage 0V) and ‘1’ indicates a high signal (may be voltage 5V).

We have to store the program (i.e. set of instructions) in computer memory. The starting address of the
program to be executed must be specified and it should be loaded into the program counter (PC). After that,
program counter keeps track of the execution of the program till the end of the program.

Every program must end with a stop or terminating instruction, otherwise the control unit will keep on fetching
information from memory. Once it encounters a halt or stop instruction, execution stops.

We use emu8086 to learn programming. The emu8086 is the emulator of 8086 (Intel and AMD compatible)
microprocessor and integrated assembler with tutorials for beginners. The emulator runs programs like the
real microprocessor in step-by-step mode. It shows registers, memory, stack, variables and flags. All memory
values can be investigated and edited by a double click. The instructions can be executed back and forward.

MOV AL, 10 ; 8-bit data 10 into AL

MOV CL, 20 ; 8-bit data 20 into CL
ADD AL, CL ; Contents of AL and CL added
HLT; Stop.

Arithmatic Coprocessor

A coprocessor is a computer processor used to supplement the functions of the primary processor (the CPU).
Operations performed by the coprocessor may be floating point arithmetic, graphics, signal processing, string
processing, encryption or I/O Interfacing with peripheral devices. By offloading processor-intensive tasks from
the main processor, coprocessors can accelerate system performance.

A coprocessor is a specially designed microprocessor, which can handle its particular function many times faster
than the ordinary microprocessor.

For example − Math Coprocessor.

Some Intel math-coprocessors are −

 8087-used with 8086

 80287-used with 80286
 80387-used with 80386

The coprocessor shares the same memory, IO system, bus, control logic and clock generator. The coprocessor
handles specialized tasks like mathematical calculations, graphical display on screen, etc.

The 8086 and 8088 can perform most of the operations but their instruction set is not able to perform complex
mathematical operations, so in these cases the microprocessor requires the math coprocessor like Intel 8087 math
coprocessor, which can easily perform these operations very quickly.

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Block Diagram of Coprocessor Configuration

8087 Numeric Data Processor

8087 numeric data processor is also known as Arithmatic co-processor, Math co-processor, Numeric
processor extension and Floating point unit. It was the first math coprocessor designed by Intel to pair with
8086/8088 resulting in easier and faster calculation.

Once the instructions are identified by the 8086/8088 processor, then it is allotted to the 8087 co-processor for
further execution.

The most prominent features of 8087 numeric data processor are as follows −

 It supports data of type integer, float, and real types ranging from 2-10 bytes.
 The processing speed is so high that it can calculate multiplication of two 64-bits real numbers in ~27 µs
and can also calculate square-root in ~35 µs.
 It follows IEEE floating point standards.

8087 Architecture

8087 Architecture is divided into two groups, i.e., Control Unit (CU) and Numeric Extension Unit (NEU).

 The control unit handles all the communication between the processor and the memory such as it
receives and decodes instructions, reads and writes memory operands, maintains parallel queue, etc. All
the coprocessor instructions are ESC instructions, i.e., they start with „F‟, the coprocessor only executes
the ESC instructions while other instructions are executed by the microprocessor.
 The numeric extension unit handles all the numeric processor instructions like arithmetic, logical, and
data transfer instructions. It has 8 register stack, which holds the operands for instructions and their
results.

Interfacing: Interface is the path for communication between two components. Interfacing is of two types,
memory interfacing and I/O interfacing.

Memory Interfacing
The primary function of memory interfacing is that the Micro-processor should be able to read from and write
into a given register of the memory chip.

A memory device can be interfaced to a processor, by using the following interfacing devices.

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Decoders
A Decoder is a logic circuit that takes "n" codes as inputs and converts it (or decodes it) to 2n output signals.
The output of Decoder is used to select one of multiple memory chips.
Latches
Because the processor multiplexes data and address lines, using the latch we can ensure that we have latched the
address lines, till the memory chip has consumed that information.
Transceivers
The Transceiver is used to buffer multiple devices from the Processor.
It ensures that all devices do not simultaneously communicate over the Data Bus.
Without the transceiver, it is possible that more than one memory device can send data on to the data-bus at a
time, so that the processor, may not know exactly, from which devices it is reading data from.

IO Interfacing

There are various communication devices like the keyboard, mouse, printer, etc. So, we need to interface the
keyboard and other devices with the microprocessor by using latches and buffers. This type of interfacing is
known as I/O interfacing.

There are two methods for interfacing I/O devices with microprocessor. They are

Memory Mapped I/O and I/O Mapped I/O.

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In this method of interfacing, there will be a separate 64KB address space for I/O devices different from 1mb
address space of memory devices. Address and data bus will be same for both memory and I/O devices. But,
control signals will be different for memory and I/O devices. For memory devices, they have memory read/write
control signals and for I/O devices, they have separate I/O read/write control signals. If processor uses in/out
instruction then it is an IO opearation. If processor uses mov instruction, then it is a memory access operation.
Automatically, the pin is either pulled Low or High depending on which instruction is used.

***

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