Department of Electrical and Electronics Engineering

Reg. No. :
MANIPAL INSTITUTE OF TECHNOLOGY, MANIPAL
(A Constituent Institute of Manipal University, Manipal)

FIFTH SEMESTER B.E. DEGREE END SEMESTER EXAMINATION

(REVISED CREDIT SYSTEM)
04 December 2008
DIGITAL SYSTEM DESIGN (ELE 311)
Time: 3 hours Max. Marks: 50
Note : Answer any FIVE full questions.
Missing data, if any, may be suitably assumed.

1A. Differentiate between semi-custom and full-custom design of integrated circuits. (02)
1B. Evaluate the following expression and determine the resulting value.
A=“1101” , B=“0010”, C=“01010101”;
(i) X= not A & not B xor C ror 2
(ii) Put the parenthesis in the above expression to obtain X=“01110111” (03)
1C. Write VHDL code for a 2 to 4 decoder with active low enable, using behavioral model.
Using this as component, develop structural model for 4 to 16 decoder. Draw the block
diagram to illustrate this. (05)
2A. Write the Entity part and draw the synthesized circuit for the code given below. If an
XOR gate is to be the synthesized circuit, what modifications are required in the code?

architecture circuit_synth of circuit is

begin
process(s)
begin
if s= “00” or s=“11” then
y<=‘1’;
else y<=‘0’;
end if ;
end process;
end; (04)
2B. Illustrate user defined data types in VHDL with any two examples. (02)
2C. Design and develop VHDL code of 4 bit prime number detector using dataflow model. (04)
3A. Write a behavioral VHDL code for the following:

Q 0
D D
F

clock 1
0

clear (03)
3B. Write a behavioral VHDL code for a negative edge triggered JK flip flop with
asynchronous preset and asynchronous reset pins. (03)
3C. Write a VHDL function that will find the 2’s complement of a 4 bit number. (04)

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 Department of Electrical and Electronics Engineering

4A. Differentiate between the following

a) Signals and variables.
b) Concurrent and sequential statements. (04)
4B. Draw the Mealy state diagram to detect the sequence 1011, in a continuous data stream.
Hence write the VHDL code for the same. (06)
5A Write VHDL Test bench code for a full adder. (03)
5B Explain the Design flow for FPGA based system design, highlighting what happens in
each step. What are the advantages with FPGA based system design. (03)
5C Implement 16 input AND gate using LUTs and dedicated resources available in Xilinx
SPARTAN-3 FPGA. Draw the circuit schematic and indicate the truth table of the
LUTs. Determine the total number of LUTs required. (04)
6A What is the advantage of scan testing? A sequential network has two inputs, three
flip-flops and two out puts. One row of the state transition table is as follows.

Present state Next state for X1X2 Output Z1Z2

Q1Q2Q3 00 01 10 11 00 01 10 11

110 111 101 100 011 10 01 11 00

Draw the timing diagram for testing this row of the transition table using scan testing (04)
6B Explain Logic Element and operating modes available in Altera MAX-II FPGA.
Explain the technology used to make it field programmable. (06)

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