Design of high speed and Area efficient full adder
with Body-biasing
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Abstract—A new 1-bit full adder cell has been introduced in
this paper. According to this approach body-biasing and semi
domino logic both are used in a single full adder. Body-biasing
technique is used to vary the threshold voltage to operate this
adder at higher speed by allowing the faster gate switching. The
important thing in this approach is that there is no requirement
of any external circuitry for body-biasing. Also, the power
consumption of the proposed full adder circuit is very low by
using the lower power supply and semi domino logic. Proposed
design circuit is 1.5 to 2 times faster than the dynamic gate-level
body biased design. The circuit design and analysis are carried
out at 45 nm technology in SILVACO-ICCAD environment. The
proposed design has lower energy consumption per operation
and robust against process and temperature variation.
Index Terms—Component, formatting, style, styling, insert.
(key words)
I. INTRODUCTION
Full adder circuit is the basic building block of arithmetic
circuits like multiplication, addition, division and exponent
circuit. By improving the performance of the full adder cell, the
performance of the arithmetic circuits will automatically
improve. Now a day many researchers is trying to improve the
performance of the full in term of improve the speed of the full
adder and small in area. A full adder cell is used to add 1-bit of
three binary numbers and gives the output in 2-bit.
In the body-biasing technique [4], body terminal of the
MOSFET (4th terminal of the MOSFET) is connected to the
potential. Body effect occurs when body or substrate of
transistor is not biased at same level as that of source. With
the help of body biasing, threshold voltage of the device can
be changed [4]. There is different technique used for changing
the threshold voltage of the device. One of them is Forward
body biasing (FBB) [1]. This technique is very useful to
reduce the delay of the circuit. In this technique MOSFET
moves from deep sub-threshold region to moderate inversion
region which makes the device robust against temperature and
process variation [1]. The FBB technique can be applied at
different level from macro-level to transistor level. When
threshold voltage is reduced to block level, it provides a
temporary speed boost, and increase leakage power for all the
gate in the block. So it increases the energy consumption.
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There are two different sub-threshold logic families that
used to body biasing the circuit so that it can reduce the
threshold voltage. First is Variable threshold voltage sub
threshold CMOS (VT-Sub-CMOS) and second is Sub
threshold dynamic threshold voltage MOS (Sub-DTMOS)
logic [1].
Variable threshold voltage sub threshold CMOS (VT-Sub-
CMOS) is define as, it is the sub CMOS logic with additional
stabilization scheme. This stabilization circuit is used to
monitor the transistor current which can change due to
temperature and process variation and provide the suitable
biasing to the substrate. In Variable threshold voltage sub
threshold CMOS (VT-Sub-CMOS), both stabilization circuit
and logic circuit works in sub-threshold region. The
stabilization module having two main components, First is
Leakage current Monitor (LCM) and second is Self-substrate
bias (SSB). The leakage current Monitor works as the current
sensor and Self-substrate bias works as the controller. The
LCM circuit senses any fluctuation in the transistor current
and activate the SSB circuit and this SSB circuit gives the
suitable body-biasing to the transistor to reduce the
fluctuation. The LCM circuit works well in the strong
inversion operation as compare to sub-threshold region. .In the
LCM circuit the leakage current is monitor separately. Due to
the change in temperature and process variation [1], it changes
the conduction of sensor transistor. The change in the
conduction gives the output voltage. An error amplifier is used
to detect and amplify the output voltage which used to activate
the SSB circuit. SSB circuit has three parts ring oscillator,
buffer and charge pump. The charges pump having the diodes
and associated charging capacitors. Charge pump is powered
by the pulses which are generated by the ring oscillator. The
change gives by the charge pump is used to body-bias the
transistor. The charge pump is activated by the output of the
sensor's output. When the required biasing has been achieved
the pump is deactivated by the sensor [1].
In Sub threshold dynamic threshold voltage MOS (Sub-
DTMOS) logic the gate and body terminal of the transistor
connected. It has not required any additional circuitry for body
biasing the transistor. When the gate voltage of the transistor
is change i.e. when voltage apply at the gate same voltage has
been applied at the body terminal of the MOSFET which
reduces the threshold voltage of the MOSFET. At VIN=0 or in
OFF state Sub-threshold dynamic threshold voltage MOS
(Sub-DTMOS) works same as the simple MOSFET. In OFF
state it has the threshold voltage, sub-threshold and off current
same as the simple MOSFET. In ON state substrate is forward
body biased and reduce the threshold voltage of Sub threshold
dynamic threshold voltage MOS (Sub-DTMOS).Due to
reduction in body charge threshold voltage has got reduced.
In this paper we have proposed the full adder cell at
nenoscale level. This proposed design is high speed and more
area efficient. By using less power supply [6], the power
dissipation in the circuit is very less. The rest of the paper is
structured as follow: Section II describes the idea about the
gate level body biasing. Section III describes the technology
used in the proposed design. Section IV describes the
proposed design and analyse power, speed and PDP (Power
delay product). Sections V shows the simulation results and
compare it with gate level body-biased design.
II. GATE LEVEL BODY-BIASED FULL ADDER
Gate level body-biased full adder design has two major
parts [2]. First is logic sub-circuit and second is body biasing
generator (BBG). The logic sub-circuit is used to generate the
logic of full adder and the body biased generator is used to
generate the body biasing voltage for the devices in the full
adder circuit. Fig. 1 shows the gate level body-biased full adder
circuit.
When the output voltage is equal to the VDD (0V).then the
Body-biasing generator transfer the voltage on VB which
prepare the pull-up (pull-down) network for fast switching.
The MOSFET which is used in the switched network has
already been body-biased before arriving inputs. In the
proposed technique the gate to output transition is favoured by
switching current. So the switching current is higher than the
CMOS technique. This circuit is faster and energy efficient
then the DTMOS configuration. In the DTMOS gates, input
signals transition become slow due body capacitive effect. But
in Gate level body biased full adder design input signal
transition is not become slow down [5].
The main advantage of this circuit is that, the body-bias
voltages always reach before input transition. The body-biased
generator sees the high load capacitance and it does not make
the speed bottleneck due to arriving the body bias voltage
before arriving the input. Energy wastage in charging or
discharging body capacitance by BBG does not take place
when input signal change its level and without change in the
output level.
In the gate level body biased full adder design, it was
expected that, due to FBB and BBG in the circuit may increase
the active leakage current more than the conventional adder
cell. But the active leakage current which is responsible for
total energy dissipation is depending only on cycle time and
activity factor. For body-bias generator, 8 additional transistors
is connected to make 4 buffer to body bias and speed up the
circuit. It has increased the area of the as compare to
conventional adder cell.
In the gate level body biased full adder design (from fig. 1),
2 buffer circuit (BBG) is connected after the carry logic circuit
and 2 buffer is connected after the sum output. It makes the
design more robust against process and temperature variation.
In gate level body biased full adder cell BBG transistor can
further be reduced in size to reduce the load capacitance at the
carry and sum node.
III. TECHNIQUE USED IN PROPOSED DESIGN
There are so many full adder cells circuits are used. Such as
Conventional static logic full adder circuit (CSL),
Conventional dynamic logic full adder circuit (CDL),
Complementary pass-transistor logic (CPL). But every full
adder has their own advantages and disadvantages. The design
technique which is used is based on semi-domino logic [3].
The circuit shown in the fig. 2.
In Conventional static logic full adder circuit (CSL), Full
adder circuit has pull-up and pull-down networks. This circuit
consists of 28 transistors in one full adder cell. It has low
power dissipation, good noise margin and robust circuit. But
the no. of transistor used in thus circuit can further be reduced
so that area of the circuit can be less, so domino logic was
used to reduce no. of transistors. It is known as
Conventional dynamic logic full adder circuit (CDL).
In Conventional dynamic logic full adder circuit (CDL), 16
transistors were used. This circuit has higher speed and small
area but reduce the performance of the circuit in terms of
robustness, power and design effort. It losses more power.
Complementary pass-transistor logic (CPL) has 32 transistors
and its operation is based on Complementary pass-transistor
logic. This circuit gives full swing operation, high speed and
good driving capabilities. But due to presence of lot of nodes,
it dissipates more power.
A. Circuit description
For understand the operation, the whole circuit can be
divided into small parts. Such as recharge transistors,
evaluation network, footer transistor, keeper transistor and
semi-domino inverters. This circuit has 2 pre charge
transistors (M1,M8), 2 keeper transistors (M2,M9), 2 evaluation
networks (evaluation carry, evaluation sum) and 6 footer
transistors(M3,M4,M5,M10,M11,M12). PMOS keeper transistors
are used to compensate the charge at dynamic node. The stack
transistor (M3,M10) is used to prevent the free discharge of the
dynamic node.
NMOS footer transistors are used to compensate the charge
at dynamic node when the noise voltage impulses occur at the
gate input. Evaluation network is used to evaluate the logic. It
connects the dynamic node to the ground when all the inputs
of the transistor which is used in the network at high as well as
clock are high. During the precharge phase, Dynamic node is
fully charge and turn ON the NMOS transistor in the buffer.
The source of NMOS transistor (M7,M14) is connected with
the NMOS clock transistor at the place of ground.
B. Operation of the circuit
When the clock is low then PMOS transistor (M1,M8)
become ON and it connects the dynamic node to the to the
power supply and precharge the dynamic node at VDD. At that
time precharge phase has been started. When the clock goes
high,its starts the evaluation phase and reduce the charge of the
dynamic node through pull down network. Evaluation phase
can only take place if the if any of transistor in pull down
network become ON and connect the ground to the dynamic
node. During the evaluation phase when all inputs of the pull
down network transistor don't connected to the logic 1,
dynamic node remains at logic 1.But in evaluation phase, pull
down network leaks the charge due to more fan-in. It is called
sub-threshold leakage. This leaked charge is compensate by the
PMOS keeper transistor and try to maintain the voltage of the
dynamic node.
There can be condition when noise voltage can come at the
inputs of the pull down transistors. In that condition keeper
transistor may not be able to maintain the voltage level at the
dynamic node. To stop this noise footer transistors (M3,
M4,M5,M10,M11,M12) are connected to the pull down networks
of sum and carry parts. Transistors M3 and M10 work as the
stack transistor. During the evaluation phase when the
dynamic node is at logic 1 then this stack transistor prevent
the discharge of charge of dynamic node simultaneously at
sum and carry. For compensate the charge from discharge of
dynamic node, M5, and M12 transistors are used to make a path
in sum and carry.
 In case of the noise analysis of the carry part of full adder
when dynamic node is at high voltage. Pull down network is
OFF and clock transistor are at low voltage then it makes the
gate of the NMOS of the buffer transistor (M7) at high voltage
(VDD) and source terminal at low voltage level due to voltage
of clock transistor. It turns ON the buffer transistor (M7) and
gives the output which is equal to the clock transistor voltage.
IV. PROPOSED DESIGN
This is a proposed design of full adder cell. In this design,
both body-biasing and semi domino logic are used. This
circuit takes very small power supply and gives the output
with low delay. There is not additional circuitry is required for
body biasing. The proposed circuit shown in the figure 3.
The main advantage of using domino logic is that, it has
very high speed application and reduces the area from the
previous circuit. Domino logic swaps the pull up network by a
single transistor so that the no. of transistors used is
automatically get reduced. So it reduces the area of the circuit
and also provides high speed performance.
In the proposed design, It has two main parts, First is logic
sub-circuit and second is body bias generator circuit. The logic
sub-circuit is used to get the required logic. This logic sub-
circuit consist of domino logic. Body-biasing generator used
to generate the body-biasing voltage without using additional
circuitry. Body biasing generator consists of buffer circuit
which is design with the two MOS. One NMOS is connected
to the pull up network of the buffer and one PMOS is
connected to the pull down network of the buffer.
A. Circuit analysis
There are the different parts in the circuit. Such as
precharge transistors, evaluation network, footer transistor,
keeper transistor and semi-domino inverters. This circuit has 2
pre charge transistors, 2 keeper transistors, 2 evaluation
networks (evaluation carry, evaluation sum) and 6 footer
transistors. PMOS keeper transistors are used to compensate
the charge at dynamic node. The stack transistor is used to
prevent the free discharge of the dynamic node.
The source of NMOS transistor is connected with the
NMOS clock transistor at the place of ground. Evaluation
network is used to evaluate the logic. It connects the dynamic
node to the ground when all the inputs of the transistor which
is used in the network at high as well as clock is high. During
the precharge phase, Dynamic node is fully charge and turn
ON the NMOS transistor in the buffer. NMOS footer
transistors are used to compensate the charge at dynamic node
when the noise voltage impulses occur at the gate input.
All the devices used in the circuit are sized to minimum
length of channel (Lmin =45nm) and channel width is chosen to
get strength between pull-down and pull-up network. Equal
width is used for series connected transistors. Table I shows
the width ratio of pull-down and pull-up networks for different
stacks configuration.
TABLE I. PULL- UP/PILL-DOWN WIDTH RATIO
Stack Configuration Proposed design
1. 1.1W/W
2. 3.2W/2.5W
3. 5.5W/4.5W
The proposed design is checked at different-different stack
configuration. The power supply for the proposed design is
varied from 0.35-0.6 volt. The width of body biased generator
can further be reduced to reduce the load capacitance at the
sum and carry node.
B. Power analysis
In the proposed design two buffer stages is used in the logic
sub-circuit. This buffer stages is used to stop the pre-charge
pulses to reach at the output stage. Generally precharge pulses
reach at the output stage but in the proposed design it has
stopped completely.
C. Delay analysis
The delay analysis is done by connecting the 4 proposed
full adders in the series. Initially calculate delay of each adder,
and then connect the 2 adder in series and it is used to fed
Device under test. Device under test is also the same full
adder.
V. RESULTS AND DISCUSSION
Figure 5 shows the comparison graph between Delay
versus VDD. As the supply increases, it reduces the delay in the
circuit. By using body-biasing generator circuit in the proposed
design it reduces the delay more make the circuit faster. At
supply VDD=0.4, the proposed design is reduce the delay
approx. 50% to the Daley in gate level body-biased design.
From the results proposed design is approximately 2 times
faster than the gate-level body-biased design.
Figure 6 shows the comparison between Power dissipated
in the circuit versus VDD. The power dissipation in the
proposed design is not more because the circuit operates by
small power supply and the BBG buffer circuit is blocking the
precharge pulses to reach to the output node. From the figure it
can see that power is increasing with the increase in the power
supply. The proposed design has reduced the power dissipation
approximately 50% than the gate level body-biased design.
Figure 7 shows the comparison between Power delay
product dissipated in the circuit versus VDD. Power delay
product or figure of merits is the parameter which is used to
find the energy consumption per operation. The lower power
delay product gives the better performance of the circuit.
Power delay product is the product of power and delay. In the
proposed design (From the fig. 7) PDP is very small as
compare to the gate level body-biased design. Proposed design
has better performance than the gate level body biased full
adder.
VI. CONCLUSION
In this paper we have designed a full adder cell with body-
biasing and semi domino logic. A channel length of 45nm is
used in the circuit, and simulation is done by SILVACO –
ICCAD with 45nm model file. From the simulation results it
can be seen that Propose design is having delay, power and
figure of merits. Domino logic is used in the circuit to improve
the speed of the circuit. It reduces the threshold voltage of the
transistors so transistor is working in sub-threshold region.
Due to operating in the sub-threshold region, circuit is
required very small voltage level for operation. This circuit
can save more power and give high speed performance.
ACKNOWLEDGMENT
Amit Kumar is very thankful to VLSI Lab and Neno-
material lab of ABV-IIITM Gwalior for providing me
computational and research infrastructure.
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