nc/i

DESIGN IDEAS BOOK

fortheCDP1802
COSMAC Microprocessor
BMP
BMP 802
 D E S I G N IDEAS B O O K

FOR THE CDP180Z

COSMAC MICROPROCESSOR

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 ACKNOWLEDGEMENT

We w o u l d l i k e to express our t h a n k s to all contributors

D. B l o c k
Boon
Johnson
Nizet
Paradise
Pintaske
Shand
Strahler
H. T w e d d l e

and e s p e c i a l l y M-C. V a n d e c a a s b e e k for her c o n s i d e r a te

t y p i n g work.

RCA A p p l i c a t i o n s Team - Europe.

 CONTENTS

PAGE

I n t r o d u c t i on
1 List of 1800 series devices
3 S p e c i a l i t i e s about 1800 series
4 Short d e s c r i p t i o n of CDP1802 CMOS m i c r o p r o c e s s o r
12 COSMAC i n s t r u c t i o n set
14 Static - What does it mean for your design
21 Oscillator design considerations
25 A m i n i m u m system
27 M i n i m u m CDP1802 key or switc h scan system
31 DMA-input - To read a paper tape
33 D M A - o u t p u t - Check the memory
34 I n t e r r u p t m e c h a n i s m in the CDP1802
38 8 l e v e l i n t e r r u p t v e c t o r i n g scheme
40 CDP1863 as a baud rate generator for the
CDP1854 UART
42 Synchronous s e r i a l o u t p u t for the CDP1802
44 I n t e r f a c i n g two C O S M A C systems u s i n g CDP1854 UART
46 Understanding the CDP1855 MDU
58 U s i n g the MDU
63 Memory m a p p i n g t h e M D U
64 Faster M D U t h r o u g h p u t u s i n g "DMA M E T H O D "
69 D i g i t a l filter u s i n g the CDP1855
73 M u l t i p l e i n t e r r u p t w i t h CDP1851
79 V I S - A c o m p l e t e v i d e o interfac e system
97 CDP1802 m i c r o p r o c e s s o r s in t e l e p h o n e s
101 Minimum i n t e l l i g e nt telephone
102 16 bit o u t p u t
103 LED interface
105 D-A c o n v e r t e r
106 A-D converter
108 CA3162 - a three d i g i t A/D interface for COSMAC
CONTENTS (cont'd) - (2) INTRODUCTION

PAGE
New and i n t e g r a t e d ci rcui ts, particularly m i c r o p r o c e s s o r s ,
are often t h o u g h t d i f f i c u l t to u n d e r s t a n d . T h i s is a
111 S i m p l e control interface for CDP1802
myth, not true, they are c o m p l e x but not d i f f i c u l t to
115 U n d e r s t a n d i n g the CDP1851 p r o g r a m m a b l e PIO
u n d e r s t a n d as they operate in a l o g i c a l way. Understan-
130 Subroutine programming techniques
d i n g m i c r o p r o c e s s o r s does r e q u i r e study, e x p l a n a t i o n s
138 Interpretive programming
and g u i d e l i n e s and the purpose of t h i s book is to p r o v i d e
140 Macro for BCD to b i n a r y c o n v e r s i o n
such i n f o r m a t i o n t o h e l p y o u become r e a l l y f a m i l i a r w i t h
141 D e t a i l e d program : a traffic light
these d e v i c e s and e s p e c i a l l y the CDP1802, a CMOS m i c r o -
148 Character search r o u t i n e
proces sor.
150 Memory move r o u t i n e
152 Data bus c o n t e n t i o n
Happy r e a d i n g a n d good l u c k .
153 W a t c h dog
154 UT4 ROM m o n i t o r program
174 O u t p u t r o u t i n e u s i n g UT4
177 I n t e r r u p t entry and e x i t
RCA A p p l i c a t i o n s T e a m - Europe.
181 Cassette i n t e r f a c e u s i n g UT4
183 Real t i m e c l o c k w i t h o u t h a r d w a r e
186 PROM p r o g r a m m e r for CDP18U42
191 CDP1802 system w i t h o u t RAM
193 D e b u g g i n g aid

199 Appendix A Data sheet CDP1802

220 Appendix B P i n - o u t 1800 s e r i e s
224 Appendix C CDP1802 c o d i n g form
225 Appendix D Selected R C A l i t e r a t u r e
226 Appendix E RCA Sale s Offices - E u r o p e
228 Appendi x F RCA a u t h o r i z e d D i s t r i b u t o r s - E u r o p e
I
LIST OF 1800 SERIES DEVICES

CDP 1802 CMOS Mi croprocessor

CDP 1804 CMOS 1 C h i p Microcomputer
CDP 1805 CMOS M i c r o p r o c e s s o r h i g h performance

CDP 1821 CMOS RAM IK x 1

CDP 1822 CMOS RAM 256 x 4
CDP 1823 CMOS RAM 128 x 8
CDP 1824 CMOS RAM 32 x 8
CDP 1825 CMOS RAM IK x 4

CDP 1831 CMOS ROM 512 x 8 (on c h i p d e c o d i n g )

CDP 1832 CMOS ROM 512 x 8
CDP 1833 CMOS ROM IK x 8 (on c h i p d e c o d i n g )
CDP 1834 CMOS ROM IK x 8
CDP 1835 CMOS ROM 2K x 8 (on c h i p d e c o d i n g )

CDP 18U42 CMOS E P R O M 256 x 8

CDP 1851 CMOS PIO with interrupt conditions

CDP 1852 CMOS I n p u t - O u t p u t port
CDP 1853 CMOS 1 of 8 decoder
CDP 1854 CMOS U A R T up to 500K bit/sec
CDP 1855 CMOS Multiply/divide unit
CDP 1856 CMOS Bus buffer for memories
CDP 1857 CMOS Bus buffer for I/O
CPD 1858 CMOS Latch-decoder for memories
CDP 1859 CMOS Latch-decoder for m e m o r i e s
 S P E C I A L I T I E S U S I N G THE 1800 S E R I E S
CDP 1861 CMOS Video display controller
CDP 1862 CMOS Colour generator controller
CDP 1863 CMOS P r o g r a m m a b l e frequency generator Small systems e v e n w i t h o u t R A M
CDP 1864 CMOS TV interface in PAL
- S u b r o u t i n e s c a l l s do not need R A M , on c h i p r e g i s t e r s
m i g h t be e n o u g h memory.
CDP 1866 CMOS 4 bit l a t c h decoder
In some cases e v e n i n t e r r u p t is p o s s i b l e w i t h o u t RAM
CDP 1867 CMOS 4 bit l a t c h decoder
CDP 1868 CMOS 4 bit l a t c h decoder Very fast i n t e r r u p t r e s p o n s e saves o n l y w h a t is n e e d e d

O p t i m i z e a d d r e s s i n g modes
CDP 1869 CMOS V i d e o interface a d d r e s s and sound
CDP 1870 CMOS Arithmetic on program counters
V i d e o interface color generator
CDP 1871 CMOS A S C I I keyboard encoder S e v e r a l stack p o i n t e r s

M u l t i p l e data p o i n t e r s
CDP 1872 CMOS I n p u t port h i g h speed
CDP 1873 CMOS Some p r o g r a m c o u n t e r s for fast s u b r o u t i n e response
1 of 8 binary decoder h i g h speed
CDP 1874 CMOS Input port h i g h speed Easy to i m p l e m e n t interpreters
CDP 1875 CMOS O u t p u t port h i g h speed
S p e c i a l "macro i n s t r u c t i o n s " p o s s i b l e

CDP 1876 CMOS CMOS i n t e l l i g e n c e w i t h o u t power c o n s u m p t i o n

V i d e o interface c o l o r generator R G B
CDP 1802 structural advantages
This l i s t shows only CDP 1800 series devices other parts are D M A transfer b u i l t i n
MWS series for memories and the whole CD4000 series.
C o m p l e t e system w i t h o u t s e l e c t i o n l o g i c for RAM and ROM

CMOS ROMs for s e q u e n t i a l CMOS systems

Software i n t e r r u p ts u s i n g SEP

16 bit I/O in one i n s t r u c t i o n

Power reductio n by use of W A I T l i n e

Power r e d u c t i o n u s i n g frequency reduction

 SHORT DESCRIPTION
of CDP1802 CMOS Microprocessor
One p o s s i b i l i t y to understand t h i s Microprocessor'could
be to set up a w i s h l i s t and transfer it into CMOS after-
wards :
1. A sixteen bit program counter is needed to address 64K.
2. The a c c u m u l ator together^ wi th the ALU (arithmetic and
logic unit) manipulates the data, 8 bit (1 byte) wide.
3. Add i n s t r u c t i o n s (e.g. FF + FF) g i v e an overflow in the
accumulator (D-register) , so a DF (data flag) is needed.
4. A stack pointer points to a free location in RAM to store
and l o a d from memory via program control (16 bit long).
5. One p o i n t e r is n o r m a l l y not e n o u g h , 16 c o u l d be the opti-
mum ( a l l 16 b i t l o n g ) .
6. To address one of these r e g i s t e r s , 4 bit are needed (N-
designator) . T h i s g i v e s the p o s s i b i l i t y for memory opera-
tions to define for e x a m p l e : load into register from RAM
and use r e g i s t e r 7 as the address p o i n t e r, then store
it, using register 9 as pointer to another address.
7. The i n s t r u c t i o n to be executed is 8 bit l o n g ; 4 bit are
N d e f i n i t i o n and the other 4 bit are the i n s t r u c t i o n , being
l o a d e d i n t o an I register.
8. The d i s a d v a n t a g e of always d e f i n i n g a register c o u l d be
overcome by d e f i n i n g and X-regi ster w i t h s p e c i a l i n s t r u c -
t i o n s u s i n g t h i s d e s i g n a t o r . T h i s X can be changed as
needed d u r i n g program flow.
9. T h i s designator usage as for the X pointer could be
used as well for something completely different. As
defined before all registers are 16 bit l o n g .
Introducing a 4 bit P register pointer adds the special
feature of m u l t i p l e program counters. One i n s t r u c t i o n
would change from one program counter to another by just
c h a n g i n g the contents of P w i t h one i n s t r u c t i o n .
10. After reset P is set to fi and program execution starts
at 2000 with register 0 as program counter.
11. To have after reset a defined X p o i n t e r , it is set to 0
as we! 1 .
12. A serial i n p u t and o u t p u t is very useful for a serial
data l i n k to a terminal without a lot of external hard-
ware. T h i s is done via a Q o u t p u t , a f l i p f l o p and a
flag input.
13. One fla g i n p u t l i n e only is very often not enough. For
a m i n i m u m system four i n p u t f l a g s a l l together s h o u l d be suf-
ficient. The Qoutput could even be used to m u l t i p l e x t h i s
to 8 i nput 1 i nes.
14. Interrupt is a needed feature, but the p r o b l e m is to define
how m u c h to put on the c h i p . The easiest way is to have one
l i n e w i t h a very fast response and to o p t i m i s e e x t e r n a l l y
with additional hardware, for example using the EF l i n e s to
d i s t i n g u i s h between 4 interrupts for a less c o m p l e x system
already.

15. The P register definition allows easily to have a fast
interrupt response. This instruction is modified and
a u t o m a t i c a l l y puts 1 in the P-register and 2 in the X-
register, then starting program execution from the loca-
tion where Rl p o i n t s to.
16. To a l l o w or not a l l o w an i n t e r r u p t a l E - f 1 i p - f 1 op is
needed (interrupt enable).
17. The very fast interrupt response changes the program
counter to 1 but it has to be remembered somehow, how X and
P were before the interrupt. This is done via the T-
register. If an interrupt occurs, the contents of X,
P is automatically transferred into the T register, before
b e i n g changed to 2, 1.
A save of the T-register on stack is n o r m a l l y the first
instruction of the interrupt program.
18. A Microprocessor has to communicate via I/O parts. If the
ports are in memory, even for a m i n i m u m system, d e c o d i n g
l o g i c is needed; as w e l l the transfer has to go through
the CPU (as it can only address one d e v i c e at the same
time (memory - CPU - I/O). W i t h some s p e c i a l I/O l i n e s
t h i s can be overcome and a direct transfer from memory to
I/O is p o s s i b l e w i t h o u t i n v o l v i n g the CPU, except for
addressing. Three lines (N0, Nl, N2) can address up to
8 devices (8 x IN, 8 x OUT). For a s m a l l system 3 I/O
devices can be selected d i r e c t l y , even w i t h o u t a d d i t i o n a l
logic.
19. T h i s structure leads to an i n c l u d e d DMA channel. As
the I/O transfer is directly to memory (or from),
register 0 is used to point to a memory location, and
the DMA channe l works both ways (input and output).
U s i n g cycle s t e a l i n g , an S2 (DMA) cycle is inserted
between normal fetch and execution. DMA-IN means that the
byte on the data bus is stored at the location where
R0 points to and the pointer is incremented to be pre-
pared for the next DMA-IN. DMA-OUT takes the byte where
R0 points to and puts it on the data bus to be stored
in an output part, incrementing i t s e l f after the trans-
fer.
(The DMA output feature is used together with the video
c o n t r o l l e r s CDP1861, CDP1864).
20. As all these l i n e s together add up to more than 40 l i n e s ,
a reduction has to be made. The 16 l i n e s of the
address bus can be reduced to 8 l i n e s by s e n d i n g out
the h i g h byte together w i t h a reference p u l s e and then
the 1ow byte.
T h i s s e q u e n t i a l addressing leads to the p o s s i b i l i t y of
internal ROM address selection. As the w h o l e address
is on the address b u s , the h i g h byte can be l a t c h ed in
the ROM and decoded. T h i s a l l o w s a 64K ROM system
without any external decoding l o g i c . The mask for the
on c h i p d e c o d i n g l o g i c defines the address area of each
ROM.
F i g u r e 1 shows the p i n o u t of the CDP1802 and figure 4 the
internal structure. One a d v a n t a g e of t h i s Microprocessor is its f l e x i b i l i t y of
c h a n g i n g pointers and program counters w i t h just one instruc -
Some of the pin f u n c t i o n s need further e x p l a n a t i o n s : tion.

CLOCK (1) and )<TAL (39) form a crystal generator gate H i g h or low o p e r a t i n g speed is only dependent on the a p p l i -
TOTT (2) and CTTO (3) d e f i n e the mode of the CPU cation. As t h i s M i c r o p r o c e s s o r is d e s i g n e d in static CMOS
RUN is the normal mode of the CPU l o g i c , the user sets the clock frequency(up to 6.4MHz for
2. PAUSE means freeze the C P U , for e x a m p l e for slow e x a m p l e ) . But the low current c o n s u m p t i o n at low frequen-
memories or lower power consumption. cies m i g h t a l s o be important. This processor can e a s i l y
3. RESET to h a v e a defined start c o n d i t i o n modify its own c l o c k frequency, for e x a m p l e u s i n g the Q
(R(3 = 0000, X = 0, P = 0, Q = 0, IE = 1) output to decide between two clock frequencie s w i t h some
4. LOAD uses the DMA c h a n n e l to load data, but external d e v i c e s .
s t o p p i n g program e x e c u t i o n .
Q (4) is the f l i p - f l op under program control Figure 5 shows a b l o c k d i a g r a m of a CDP1802 system. Figure
SCI (5), SCO (6) represent the state of the CPU (See F i g . 3) 6 g i v e s the t i m i n g r e l a t i o n s .
MRD (7) memory read output
BUS 0-7 (8-15) - the data bus A p p e n d i x A shows the instruction set of the CDP1802.
VC|- (16) I/O v o l t a g e , separated from i n t e r n a l v o l t a g e V D D
N0-N2 (17-19) I/O address l i n e s For more information about CDP1802, see data sheet of CDP1802
or MPM201 user m a n u a l .
'SS (20) g r o u n d
["-rF~4 (21-24) i n p u t flag l i n e s to be tested under program
control
MAO-7 (25-32) m u l t i p l e x e d address bus
TPB (33) reference p u l s e for I/O transfer
TPA (34) reference p u l s e for h i g h order address byte
M W R (35) memory write
INT (36) i n t e r r u p t request l i n e
DMA OUT (37) DMA output p u l s e to get a byte from memory,
pointed to by R0
DMA I'M (38) DMA i n p u t p u l s e to store a byte into memory
pointed to by R0
'DD to (40) internal processor voltage, can be h i g h e r or e q u a l
work at h i g h e r frequency.
<CC
 10
CLEAR WAIT MODE
11
L L Load
L H Reset CDP1802
H L Pause
H H Run Timing
Diagram
F i g u r e 2 : CDP1802 m o d e s

State Code Lines

State Type
SC1 SCO
SO (Fetch) L L
SI (Execute) L H
S2 (DMA) H L
S3 (Interrupt) H H

F i g u r e 1 : PIN OUT F i g u r e 3 : State Codes

I/O FLAGS I/O REQUESTS

MEMORY ADDRESS LINES

MAI MA3 MAS MAT CLEAR I XTAL CLOCK I TFT I ~ff4 W STERRuPtaJT SCO Sc

DATA FROM /////

BUS TO CPU ////'

"5MA~
REQUEST

EF I-4

Figure 4 :
Internal Structure
of the CDP1802
Mi croprocessor
NOTES'
I. THIS TIMING DIAGRAM IS USED TO SHOW SIGNAL RELATIONSHIPS
ONLY AND DOES NOT REPRESENT ANY SPECIFIC MACHINE CYCLE

3. SHADED AREAS INDICATE "DON'T CARE " OR UNDEFINED STATE;

MULTIPLE TRANSITIONS MAY OCCUR DURING THIS PERIOD

CDP1802 INSTRUCTION EXECUTION TIMES 2-Byte instructions also require 2 Machine Cycles: 1 Fetch,
1 Execute.
1-Byte instructions require 2 Machine Cycles: 1 Fetch, 3-Byte instructions require 3 Machine Cycles: 1 Fetch,
1 Execute. 2 Executes.

INSTRUCTION SIZE INSTRUCTION TIME @ f =

% OF TOTAL
Bytes of Bytes of Address Total Bytes REPERTOIRE
Op. Code or Data of Memory 6.4 MHz 3.2 MHz 2 MHz
1 0 1
93 2.5 (is 5 in SMI
j 1 2
1 2 3 7 3.75 MS 7.5 (is 12 MS
•—•
Awrage Initru "lion
. Execution Tim _
Fi gure 5 : B 2&IU 5.2 Ml 8.3 MS

Typical CDP1800
System Figure 6 : CDP1802 T i m i n g Diagram
 12 13

COSMAC INSTRUCTION SET

In order to better u n d e r s t a n d the i n s t r u c t i o n set of the 5. Branches are always w i t h i n a page , means they are a b s o l u t e ,
CDP1802, some e x p l a n a t i o n s are necessary (see APR. A) : it is not p o s s i b l e to branch over page boundaries.

1. As the CDP1802 has 16 registers, many i n s t r u c t i o n s exist 6. For jumps o u t s i d e a p a g e , l o n g b r a n c h e s are used.
16 t i m e s , for e x a m p l e the first i n s t r u c t i o n 0N means LOAD
via N, w i t h N = O...F. T h i s means that one of the 16 regis- 7. A s p e c i a l control i n s t r u c t i o n is IDL. T h i s stops the
ters (N) is used as pointe r (16 b i t ) to memory and the infor- program counter and it waits for DMA or I N T E R R U P T .
m a t i o n (data) at t h i s l o c a t i o n is loaded i n t o the D - r e g i s t e r .
T h i s "N" is v a l i d for 10 i n s t r u c t i o n s and so uses already 160 8. I/O transfer is always between memory and I/O, t h i s means :
of the 256 p o s s i b l e op-codes.
a) I n i t i a l i z e memory pointer
2. A second type of instructions is referenced to r e g i s t e r X. b) Set X to t h i s register
73 means STXD (store via X and decrement). Here the 4 bit c) O u t p u t or i n p u t
X - d e s i g n a t o r (0-F) p o i n t s to one of the 16 registers. The
contents of t h i s r e g i s t e r (16 b i t ) p o i n t s to one of the 65K 9. For further e x p l a n a t i o n s , see MPM-201 user m a n u a l .
addresses. At this location, the information of the D-
register is stored and afterwards t h i s r e g i s t e r is automa-
t i c a l l y decremented (stack o p e r a t i o n s ) to p o i n t a g a i n to a
free 1 o c a t i on.

3. All r e g i s t e r s can be i ncremented and decremented.

T h i s g i v e s e a s y - t o - u s e counters :

a) I n i t i a l i z e regi ster
b) Decrement r e g i s t e r
c) Take h a l f of it i n D
d) Is it 00 ?
e) If 00 e x i t , if not back to decrement

4. For l o g i c and a r i t h m e t i c o p e r a t i o n s , there are two classes

of i n s t r u c t i o n s :

a) D - r e g i s t e r and the i m m e d i a t e byte after the

i n s t r u c t i o n (ADI)

b) D - r e g i s t e r and the byte where the X - r e g i s t e r

points to (ADD)
 14 15

STATIC - WHAT DOES IT M E A N FOR Y O U R DESIGN

is static ?

Static operation e n a b l e s a d e v i c e to function from DC to the

Power s a v i n g is a c h a r a c t e r i s t i c w h i c h is featured in many
devices u p p e r frequency l i m i t . T h i s c h a r a c t e r i s t i c is due to
present Microprocesso r system d e s i g n s , both as a necessity
static memory c e l l s b e i n g e m p l o y ed in all registers. As a
of the s p e c i f i c a t i o n . For e x a m p l e in p o r t a b l e systems or
r e s u l t the d e v i c e requires no m i n i m u m refresh rate as in the
in c r i t i c a l power a p p l i c a t i o n s - t e l e p h o n e , etc... and as
case of d y n a m i c c e l l s and it can be stopped w i t h o u t data loss.
a useful s e l l i n g p o i n t w i t h low c o n s u m p t i o n and s m a l l e r u n i t
size b e i n g an a d v a n t a g e over competitors.
W h e n one considers that w i t h CMOS the major component of power
c o n s u m p t i o n is d y n a m i c and that t h i s is p r o p o r t i o n a l to fre-
The COSMAC CMOS M i c r o p r o c e s s o r and memory series can e a s i l y
quency then one a d v a n t a g e of static operation is o b v i o u s l y seen
offer t h i s c h a r a c t e r i s t i c by its static feature. In a d d i t i o n
that of power c o n s u m p t i o n .
to power s a v i n g s due to CMOS, m a k i n g it a p p l i c a b l e in s u c h
d i v e r s e a p p l i c a t i o n s such a s i n t e l l i g e n t t e l e p h o n e s , p o r t a b l e
" B Y R E D U C I N G F R E Q U E N C Y O N E C A N R E D U C E O P E R A T I O N A L POWER C O N S U M P -
d a t a systems, fire hazard e q u i p m e n t .
TION"

The COSMAC s e r i e s is based around the CDP1802 8-bit processor

As data is r e t a i n e d i n d e p e n d a n t of the c l o c k in a static d e v i c e ,
and the CDP1804 s i n g l e - c h i p 8-bit M i c r o c o m p u t e r . The M i c r o -
it can be s w i t c h e d off by s t o p p i n g the c l o c k and s w i t c h e d on to
processors h a v e an u n i q u e a r c h i t e c t u r a l feature of stack p o i n t e r
i n i t i a t e p r o c e s s i n g a t t h e same p o i n t . This has advantages in
and p r o g r a m counter d e s i g n a t o r s , w h i c h a l l o w the SP and PC to
easy devi ce control .
be redefine d in one i n s t r u c t i o n to any of two or one 1 6 - b i t
regi ster pai rs.
The c a p a b i l i t y of v a r y i n g the o p e r a t i o n a l speed from DC to
m a x i m u m h a s many a d v a n t a g e s , such a s i n i n t e r f a c i n g w i t h slower
Both processors feature o n - c h i p i n t e r r u p t ,DMA, and I/O select
d e v i c e s , memories and peripherals. T h e o p e r a t i o n speed i n a d d i -
e n c o d i n g l i n e s , four t e s t a b l e flag (EF) i n p u t s and one setable
t i o n to the hardware and software can be t a i l o r e d to a p a r t i c u -
and testable o u t p u t (Q). A d d i t i o n a l l y the 1804 has an o n - c h i p
1 ar a p p l i c a t i on .
8 - b i t counter t i m e r , 64 bytes RAM and 2K R O M .

In the a p p l i c a t i o n shown in F i g u r e 1 a COSMAC system d e r i v e s a

T h e COSMAC f a m i l y a l s o c o n s i s t s o f I / 0 - d e v i c e s : m u l t i p l y d i v i d e
pulse by entering the s u b r o u t i n e on testing for an active flag
u n i t 1855, p e r i p h e r a l I/O 1851, v i d e o i n t e r f a c e d e v i c e s - 1869,
i n p u t (EF1, 2, 3, 4) on occurence of a second f l a g i n p u t e.g.
1870, 1861, 1862, 1864, p r o g r a m m a b l e frequency generator 1863,
(EF2) t h e c l o c k speed i s m o d i f i e d , therefore, t h e p u l s e l e n g t h
e i g h t bit I/O port 1852, U A R T d e v i c e 1854 and memory, and I/O
Produced w i l l b e c h a n g e d . T h e d e s i g n therefore m i n i m i z e s soft-
support devices.
ware by a s i m p l e h a r d w a r e a l t e r a t i o n , a n d , therefore, can be
used in a memory/ software c r i t i c a l d e v e l o p m e n t .
The memory f a m i l y c o n s i s t s of CMOS R O M ' s , EPROM and R A M ' s .

As CMOS d e v i c e s , in a d d i t i o n to the s t a t i c feature they offer

h i g h n o i s e i m m u n i t y , lower s e l f h e a t i n g a n d therefore high
r e l i a b i 1 i ty.
 16 17

CLOCK
INPUT A EF1

EF2
COSMAC OUT
INPUT B CLOCK CLOCK SYSTEM _n
REGULATION
DMA OUT
OUT 'B1
F i g u r e 1 : C O S M A C System R e g u l a t e d by C h a n g i n g C l o c k F i g u r e 2 : A u t o m a t i c Software C o u n t e r
I n t i m i n g a p p l i c a t i o n s t h e t e c h n i q u e is u s e f u l d u e t o C O S M A C ' S
i n s t r u c t i o n set - the majority of i n s t r u c t i o n s are two m a c h i n e
cycles 1 o n g . * After reset R0 is p r o g r a m counter and DMA pointer.

Strict t i m i n g is a c h i e v e a b l e by i n s t r u c t i o n counting and by As DMA i n c r e m e n t s the p r o g r a m c o u n t er only every second,

clock adjustment. instruction is executed. This means that the i n i t i a l i z a t i o n
cycle l o o k s l i k e
U s i n g a t e c h n i q u e u n i q u e to C O S M A C and w e l l known to 1800
s e r i e s u s e r s , i t i s p o s s i b l e t o i m p l e m e n t a n a u t o m a t i c soft- ADD DATA MNEMONIC COMMENT
ware counter. W h e n a DMA r e q u e s t is a s s e r t e d in C O S M A C , a
00 XX .. DMA
D M A m a c h i n e cycle o c c u r s , after s e t t i n g t h e s t a t u s l i n e SCO
01 F8 00 LDI#00 .. get 00 in D-register
and r e s e t t i n g SCI and i n c r e m e n t i n g one of the s i x t e e n 1802
03 XX .. DMA
registers R0, as the DMA p o i n t e r . D a t a is i n p u t or o u t p u t from
04 B3 PHI R3 . . transfer to R3. 1
memory p o i n t e d to by R0 d e p e n d e n t on w h e t h e r r e q u e s t was DMA in
05 XX .. DMA
o r D M A o u t . B y u s i n g S C I , t h e status l i n e w h i c h i s a c t i v e d u r i n g
06 F8 OC LDIftOC .. get OC in D-register
the execute m a c h i n e c y c l e , to r e q u e s t DMA the r e g i s t e r R0 is
08 XX .. DMA
incremented every three m a c h i n e cycles, if two m a c h i n e cycle
09 A3 PLO R3 .. transfer to R3.0
i n s t r u c t i o n s are used e x c l u s i v e l y . By a d j u s t i n g the frequency,
OA XX .. DMA
a n d u s i n g e x t e r n a l c i r c u i t r y t o d i s a b l e D M A request, this simple
OB D3 SEP R3 . . set PC to R3
t e c h n i q u e can be used in many t i m i n g a p p l i c a t i o n s to get a soft-
OC .. now program starts
ware c l o c k , by connecting the D M A - o u t w i t h SCI.
.. r u n n i n g in R3
.. and R0 is only
* 80% of 1802 i n s t r u c t i o n s are two m a c h i n e cycle, the r e m a i n d e r
.. used for DMA
are three m a c h i n e cycle.

Static characteristic also a l l o w s the Microprocessor to share

the same clock as required in the other part of the system or
in fact be t a i l o r e d to the external system. T h i s is shown in
r igure 3.
 18 19

In COSMAC an i d l e state is i n d i c a t e d by a c o n s t a n t SCI' h i g h ,

w h i c h is used to s w i t c h the o s c i l l a t o r down to 50KHz. The
A system is shown in F i g u r e 3 i m p l e m e n t i n g a data c o m m u n i c a t i o n
a d v a n t a g e of t h i s system is that the processor is s t i l l run-
interface u s i n g the same c l o c k for the CPU and the b a ud rate
n i n g and an i n t e r r u p t or DMA request is d e t e c t a b l e , a u t o m a t i -
i n p u t . W i t h COSMAC a s i m p l e low frequency i n t e r f a c e can be
cally r e t u r n i n g SCO to a low state and the c l o c k to its normal
constructed omitting a down counter and crystal by u s i n g a
operation frequency.
s i m p l e cheap RC o s c i l l a t o r constructed from a s i n g l e CMOS
schmitt-trigger. T h i s , therefore, reduces system costs.
TELEPHONE LINE
TABLED!

| o!A | POWER C O N S U M P T I O N OF A T Y P I C A L C O S M A C SYSTEM AT A C L O C K F R E -

•'#:
M Q U E N C Y OF 1MHz AND 200KHz

TTTT i Typical power c o n s u m p t i o n at 5V

r CS1

CS3 UART AT 1MHz AT 200KHz

CPU "1 MRD CDP1S54
CDP1802 NO RSEL
1 x CPU (CDP1802) 4mW 0.2mW
1 x RAM (MWS5101) 0.75mW 0.2mW
1 x ROM (CDP1833) lOmW 2mW

All together 14.75mW 2.4mW

F i g u r e 3 : Data C o m m u n i c a t i o n Interface U s i n g CDP1854 TABLE 2

Static c o n s u m p t i o n
The m a i n a d v a n t a g e of a static Microprocessor system however
i s i n power s a v i n g , i n power c r i t i c a l a p p l i c a t i o n s . AT 5V (max.) AT 2V (data re

A COSMAC o p e r a t i n g at 1MHz at a t y p i c a l o p e r a t i n g power of 1 x CPU (CDP1802) 50uA O.SuA

lOmW can be reduced to a l m o s t q u i e s c e n t power l e v e l s by redu- 1 x RAM (MWS5101) 50uA 2uA
cing the c l o c k frequency. The i m p l e m e n t a t i o n of suc h a system 1 x ROM (CDP1833) 50uA luA
is shown in F i g u r e 4 where it must operate at a low power in an
Sum of static current 150uA 3.5uA
i d l e state, w h i l e w a i t i n g f or an interrupt. consumption
 20 21

The COSMAC range of Microprocesso r components can be incorpo- OSCILLATOR D E S I G N C O N S I D E R A T I O N S FOR THE CDP1802
rated in d e s i g n s u s i n g the t e c h n i q u e s a b o v e due to static pro-
perties of CMOS g i v i n g the Microprocessor user, in a d d i t i o n
Despite the w i d e s p r e a d use of crystal-control led o s c i l l a t o r s
to other CMOS features, an extremely powerful d e s i g n t o o l .
for Microprocessors, crystal selection may s t i l l pose pro-
b l e m s for many d e s i g n e r s . Most of these p r o b l e m s can be m i n i -
These' a d v a n t a g e s of the COSMAC f a m i l y h a v e led to its usage in
mized by an u n d e r s t a n d i n g of the v a r i o u s properties and speci -
many f i e l d s of M i c r o p r o c e s s o r a p p l i c a t i o n s - p o r t a b l e e q u i p - fications needed to define an o s c i l l a t o r c i r c u i t for the CDP1802
m e n t , fire hazard e q u i p m e n t , telecoms and a u t o m o t i v e - where
Microprocessor.
it is very s u c c e s s f u l in a p p l i c a t i o n s s u c h as i g n i t i o n c o n t r o l ,
i n f o r m a t i o n systems, t r a n s m i s s i o n control etc...
Clock frequency and accuracy

CONTROL Quartz crystal o s c i l l a t o r s w i l l p r o v i d e frequency s t a b i l i t y

better than 0.015=. However, many Microprocessor a p p l i c a t i o n s
Figure 4 :
EF do not r e q u i r e an exact clock frequency - therefore, the use
I CDP General C l o c k Control
of RC or LC type o s c i l l a t o r s may be a wise cost-effective choice
CLOCK CLOCK 1802
CLOCK If a crystal is to be u s e d , there are two b a s i c low-cost types
CONTROL
l to c o n s i d e r : p a r a l l e l resonant AT cut q u a r t z crystals t y p i c a l -
ly r a n g i n g from 0.8MHz to 6MHz, and low frequency t u n i n g fork
type crystal a v a i l a b l e in s e v e r a l clock frequencies from 10KHz
to 240KHz, i n c l u d i n g the p o p u l a r 32.768KHz d i g i t a l watch frequen-
cy. Statek Corp., for i n s t a n c e , s p e c i a l i z e s in l o w - c o s t t u n i n g
fjgure 5 : fork c r y s t a l s , and they h a v e n u m e r o u s free a p p l i c a t i o n s notes to
A u t o m a t i c IDLE aid in d e s i g n .
System

The o s c i l l a t o r circuit

CLOCK F i g u r e 1 shows the b a s i c crystal o s c i l l a t o r c i r c u i t for the

CDP1802. The 15 m e g o h m resistor is used to b i a s the gate in
L/
v nn ~l its l i n e a r r e g i o n so that it b e h a v e s l i k e an a m p l i f i e r . C a p a -

f
\ citors C<- and C T p r o v i d e the r e q u i r e d c a p a c i t i v e l o a d i n g for
Figure 6 :
ROM CDP
ClEAT I D L E System S t o p p i n g
1802 the C l o c k 'u -
fll*1
1—1
« 1
Q Q N0
S •fr/f
R -J 1 4 «
1-
STAR T
I 1 k>J
&T* CDP1802

F i g u r e l : B a s i c Crystal O s c i l l a t o r
 23
22

+ V DD
the crystal and act as high-frequency filters to avoid overtone CD4093
o s c i l l a t i o n s . The v a l u e s of C$ and CT can be calculated using Figure 3 :
the f o l l o w i n g equations found in ICAN-6086 : CD4093 as
4C, Cl ock O s c i 1 1 a t o r
and
- 5f

4C,
CS =
5f
LC type -- A p a r a l l e i - r e s o n a n t LC c i r c u i t may be used as the
R g is the e q u i v a l e n t resistance of the crystal. F i g u re 2 frequency d e t e r m i n i n g network for the CDP1802. (See F i g u r e 4)
shows the a p p r o x i m a t e r e l a t i o n of R g to frequency for AT The frequency and component v a l u e s have the f o l l o w i n g r e l a t i o n -
type crystals. ship :

C L is the load capacitance for the crystal, g e n e r a l l y a

standard v a l u e set by the crystal vendor between 10 and
32pF.
The h i g h - i m p e d a n c e secondary of a s m a l l 455 KC IF transformer
f is the frequency in Hz. s i m i l a r to those found in most p o r t a b l e transistor r a d i o s
makes an e x c e l l e n t LC o s c i l l a t o r (the C is b u i l t in). Further-
more, it is t u n a b l e (about ± 10%) u s i n g the s l u g .

„
Figure 2 :
E q u i v a l e n t Resistance
Versus Frequency
I ><
1 Y"..
CDP1802 Cl

^
CDP1802

FREQUENCY MHZ
~- T

figure 4 : Clock O s c i l l a t o r Figure 5 : C e r a m i c Resonator

U s i n g LC C i r c u i t
The actual v a l u e C<- used s h o u l d be about 4pF l e s s than the
c a l c u l a t e d v a l u e to a l l o w for the a m p l i f i e r i n p u t capacitance .
£ej"j*jTn_c_ resonators
R can u s u a l l y be 0 ohm u n l e s s low power d r a i n or s t a b i l i t y
Made of p i e z o - e l e c t r i c materia! .ceramic resonators behave
d u r i n g v a r i a b l e V D D v o l t a g e is important. ICAN-6086 and
s i m i l a r to crystals, requiring two capacitors and a bias
ICAN-6539 e x p l a i n in d e t a i l the need for and c a l c u l a t i o n of R.
resistor. Frequency tolerances of ± 1% are t y p i c a l m i n i m u m s
Val, of Cl, C2 and R d e p e n d on the d e v i c e used.
 24 25

A M I N I M U M SYSTEM
Crystal s p e c i f i c a t i o n s :

Frequency and tolera nee -- ± 0.01% from -20 to 100° C is common,

t i g h t e r tolerances down to ± 0.001% are a v a i l a b l e at a d d i t i o n a l To sh° w tne h"ig'1 d e n s i t y of C M O S i n t e g r a t i o n , see t h i s
cost (check w i t h vendor). block d i a g r a m w h i c h i n c l u d e s a l l d e v i c e s to h a v e a m i n i -
mum system, w i t h 25 I/O l i n e s .
Mode of o s c i 1 1 a t i on -- F u n d a m e n t a l , p a r a l l e l resonance.
1. The clock frequency of the CPU (1) is generated via
Load c a p a c i t a n c e (CL) -- T y p i c a l l y between lOpF and 32pF - a crystal; it c o u l d be replaced by a clock generator
choose a stock v a l u e the v e n d o r h a s . H i g h e r v a l u e s of C, (1/4 CD4093). To get a c l e a n POWER ON RESET 1/4 CD4093
w i l l i m p r o v e frequency s t a b i l i t y , b u t lower v a l u e s w i l l is used. EF1 to 4 and the Q l i n e are 5 I/0's already.
decrease o s c i l l a t i o n power c o n s u m p t i o n .
2. E P R O M S CDP18U42 or 57U58 can be u s e d , as w e l l NMOS
M a x i m u m e q u i v a l e n t res i s t a n c e R ) -- T h i s n u m b e r is related EPROMS are possible but this would need a bigger power
to the frequency. Most vendors w i l l s u p p l y crystals w i t h R s u p p l y . F o r p r o d u c t i o n CMOS ROMS w o u l d be used
v a l u e s lower then the curve shown in F i g u r e 2.
Another p o s s i b i l i t y is to use UT4 (CDPR512), a m o n i t o r
Max. d r i v e l e v e l -- The crystal s h o u l d be a b l e to d i s s i p a t e 5 program in R O M , g i v i n g the p o s s i b i l i t y to control the
m i l l i w a t t s of power. If the crystal cannot h a n d l e t h i s l e v e l , CPU (see data sheet CDP1832).
frequency d r i f t or e v e n d a m a g e to the crystal may r e s u l t . Crys-
t a l s w i t h lower d r i v e c a p a b i l i t y , such as the t u n i n g fork type, 3. The s e l e c t i o n l o g i c a l l o w s the f o l l o w i n g RAM's
can be used if R is i n c r e a s e d to reduce the d r i v e l e v e l . I C A N -
6086 g i v e s d e t a i l s on how to compute R, a l s o Statek has numerous CDP1824 (32 x 8)
free A p p l i c a t i o n Notes a b o u t t h i s . CDP1823 (128 x 8)
2 x CDP1822 (256 x 8)
Can types -- HC33 and HC18 are p o p u l a r types. 2 x CDP1825 (IK x 8)

A l t e r n a t i v e o s c i l l a t o r types : The CDP1825 (MWS5114) s h o u l d be enough memory for t h i s

m i n i m u m system.
RC type -- A s i m p l e RC o s c i l l a t o r is shown in F i g u r e 3 u s i n g
4- The PIO (CDP1851) adds up to 20 I/O l i n e s to t h i s m i n i -
a CD4093. The a p p r o x i m a t e frequency (f) is determined as fol-
lows : system, they can be used as i n p u t , output, b i d i r e c t i o n a l
or bit p r o g r a m m a b l e .
•f _ 1.25 at V DD = 5V
RC 5- A CDP1866 is used to d e m u l t i p l e x the address bus. Bit 0,
1, 6, 7 are latched and p r o v i d e address bits 8 and 9; with
U n l i k e the CDP1802, the CDP1804 Microprocessor uses a Schmitt
10 address l i n e s a IK E P R O M can be addressed.
inverter for the o s c i l l a t o r a m p l i f i e r so that it can be used
d i r e c t l y for the RC oscillator.
 27

NIMAL CDP1802 KEY OR SWITCH SCAN SYSTEM U S I N G A D D R E S S L I N E S

To s e l e c t RAM or R O M , address b i t s 6/7 are used.
puts RAM at 0000 and ROM at 8000 or v i c e v e r s a . As
CDP1866 has 4C~S o u t p u t s , two other RAMs or ROMs can be
addressed.
The power consumption of the complete system, r u n n i n g at
2MHz is less than 10mA.
This
keyboard scan can be implemente d in a m i n i m a l CDP1802 system,
u s i n g only address l i n es as key scan and flag l i n e s to m o n i -
tor key d e p r e s s i o n .
Address l i n e s are v a l i d d u r i n g the execute cycle of a " b r a n c h
on EF" i n s t r u c t i o n at the p o i n t of flag test, as RP c o n t e n t s .
A s i m p l e system can then be d e s i g n e d by u t i l i s i n g the u p p e r
four address l i n e s in a key board m a t r i x m u l t i p l e x . A system
is shown in F i g u r e 1.

1
M;
OH
i
TPA —» A0.1 CDP1866
BYTE ")( LOW BYTE MEMORY ADDRESS

TPA

CDP1802 6,7 8 9m 2 3 4 STB TPB

Q u u 1 I
RDY
EF
EF1 ADD BUS A
1 1
EF2 CDP1851 Fi gure 1 : S a m p l i n g of EF-Lines
ROM RAM
EPROM CDP STB
EF3 MWS 1823 RDY
57U58
EF4
No address o v e r l a p is ensured by placing memory below address
or or
B FFF HEX and m a k i n g the upper address l i n e s don't care states
CPU
OTHERS OTHERS
PIO in the mask of the ROM.
t~ f|
Y
DATA BUS ADD BUS 4-7
i i i
4 5 7
CONTROL
CDP1802 k EF1 C D E F
1

EF2 8 9
MINIMUM SYSTEM CIRCUIT DIAGRAM A B
Hardware for
EF3 4 5 6 7 Keyboard
Scan Matrix
EF4
0 1 2 3
 28 29
scan software - flow chart
Key

A key I n p u t r o u t i n e can then be p l a c e d in memory and accessed

with no dependence on MA7, 6, 5, 4. The key address lines
are set by l o a d i n g the program counter w h i l e continually
accessing t h e routine. T h e routine w o u l d t y p i c a l l y c o n s i s t
of key i n p u t - by bit set on v a l i d EF c o n d i t i o n , d e b o u n c e , r o l l - LOAD
over by software t e c h n i q u e s . ADDRESS
IN PC
A d d r e s s l i n e i s o l a t i o n i s a c h i e v e d b y d i o d e s o n each l i n e . FROM TABLE

I t i s p o s s i b l e b y u s i n g t h i s t e c h n i q u e , together w i t h some
16 scratch pad r e g i s t e r s as data storage of the 1802, to
construct a two c h i p s o l u t i o n for s i m p l e key or switch scan
a n d s e r i a l o u t p u t a p p l i c a t i o n , such a s remote p o r t a b l e data ,
control & m o n i t o r systems.

REPEAT
FOR ALL
KEY COLUMNS
(FLAG INPUTS)

A flow chart of key scan is shown. Entry is by a s u b r o u t i n e

call exit by "return" w i t h a map of the key scan.

T h i s r o u t i n e o n l y performs the f u n c t i o n of s c a n n i n g and s t o r i n g

a "lap of keys, d e b o u n c e and c o d i n g f u n c t i o n s m u s t be done e l s e -

where.
 30
31

Key scan software - code

DMA INPUT - TO REA D A PAPER TAPE
RESCAN: SEX ROW TBL ROW SCAN FETCH FROM
LDXA TABLE AND LOADED INTO
PHI PC P R O G R A M COUNTER The DMA function in the CDP1802 works as follows :
ANI #F0 END OF TABLE ?
BNZ TEST IF SO R E T U R N OTHERWIS E A DMA pulse i n i t i a t e s a cycle s t e a l i n g . The normal CPU
RET IF KEY D E P R E S S I O N (FLAG IS SET) operation is fetch-execute and a g a i n fetch new instruction
TEST: BN1 *+ 2 THEN SET BIT O T H E R W I S E and execute it with 8 clock cycles for the fetch and 8 or
ADI #01 SHIFT + C L E A R N E X T BIT 16 clock cycles for the execute (2 or 3 cycle instructions).
SHL R E P E A T FOR ALL KEY
BN2 *+2 COLUMNS (EF2, EF3, EF4) Nearly a l l i n s t r u c t i o n s are 2 c y c l e s long, a 3 cycle instruction
ADI #01 would be a LONG B R A N C H or a NOP. If the CPU sees a DMA i n p u t
SHL for e x a m p l e , it w i l l f i n i s h the current i n s t r u c t i o n and before
BN3 *+2 the new fetch it w i l l execute a DMA i n p u t :
ADI #01
SHL R0 (register 0) p o i n t s to a byte in memory and the data coming
BN4 *+2 from the i n p u t part is stored at the l o c a t i o n where R0 points
ADI #01 to, then t h i s register is a u t o m a t i c a l l y i n c r e m e n t e d to p o i n t
SEX KEYPTR . STORE MAP OF KEY to the next free location.
STXD . ROW STATUS IN M E M O R Y
BR RESCAN . B R A N C H TO B E G I N N I N G There are some d e s i g n s where t h i s feature can be used :

DC F I R A D R , F I N A D R - 10, F I R A D R - 30 1. The w h o l e system is in RAM and after s w i t c h on the program

F I R A D R - 70, F I R A D R - E0 is l o a d e d via the DMA c h a n n e l (CPU in LOAD mode).
. ROW SCAN TABLE
. F I R A D R = 1110Y 2. Fast data transfer from floppy d i s k .
. W H E R E Y IS ROM ADDRESS SELECT
3- T h i s feature can e a s i l y be used as w e l l to load a program
The data t a b l e consists of four v a l u e s setting the c o m p l e m e n t from a paper tape.
of each address l i n e in turn and E.O.T. marker.
Nine LED's, 9 photo sensors and 9 S c h m i t t Triggers are
Note that due to ROM a d d r e s s i n g l o a d i n g the contents of t h i s a l 1 that i s needed .
t a b l e into the program counter does not affect program flow.
 32 33

DMA OUTPUT - C H E C K THE M E M O R Y

E i g h t of the sensors l o o k at the data h o l e s and the 9th

(the s p r o c k e t h o l e ) l a t c h e s the c u r r e n t data i n t o the
CDP1852. A u t o m a t i c a l l y t h e s e r v i c e request l i n e i n i t i a t e s
a DMA cycle (see F i g u r e 1) and stores the information where
R0 p o i n t s to.
There are even h a n d - h e l d p a p e r tape readers on the market,
t h e i r o u t p u t s are s i m p l y connected to the data and c l o c k
i n p u t s of the CDP1852. (See MPM 201 page 79).
A low s i g n a l on the D M A - O U T l i n e causes the same c y c l e
s t e a l i n g as d e s c r i b e d (S2 cycle) but now to o u t p u t data.
A g a i n register 0 p o i n t s to a memory l o c a t i o n and the data
byte stored at this address is transfered to the output latch.
T h i s is used for fast data transfer, e i t h e r to a n o t h e r CPU or
p o s s i b l y to a floppy d i s k .

Another use is to step through the memory to verify data. Two

LED d i s p l a y s w i t h decoders are connected to the o u t p u t register.

The CPU is reset and then put in the L O A D mode. R0 is now

p o i n t i n g to addres s 0000 and a DMA OUT p u l s e gets the data from
this address into the output register and appears on the
LED display. F u r t h er D M A OUT's w i l l step t h r o u g h t h e w h o l e
memory.

STATES SO SI SO SI j'sz SO SI

MEMORY
\^
MRD CPU
CDP1802 /2CD1013

D ••— V DD

ADDITIONAL CIRCUITS FOR DMA INPUT R

L_
, '
v—
MIRIQ
-1 v
<£= i .
DATA B U S 0 7

STATES | SO | SI | SO 5 1 S O SI

A D D I T I O N A L CIRCUIT S FOR DMA OUTPUT

See MPM-201, Page 80

 34 35

I N T E R R U P T M E C H A N I S M IN THE CDP1802
tne i n t e r r u p t occurs, Rl is p r o g r a m counter and R2
x pointer. As t h i s r o u t i n e does not know if the stack
empty, at first it is decremented. A l l register s
The i n t e r r u p t m e c h a n i s m p e r m i t s an external s i g n a l to e e d e d , and only w h at is n e e d e d , i s saved (R7 m i g h t not be
interrupt normal program execution and transfer control necessary) and Q is set. There is a shorter v e r s i o n of
to a program d e s i g n e d to h a n d l e the i n t e r r u p t c o n d i t i o n .
t h i s program.
T h i s f u n c t i o n is e s p e c i a l l y needed at power down to save
data into the battery b a c k u p RAM or to respond very q u i c k l y
E X I T : RET
to an e x c e p t i o n a l event.
E N T R Y : DEC R2
SAV
Here the structure of the CDP1802 shows its a d v a n t a g e s . In
SEQ
its i n s t r u c t i o n set e x i s t s the SEP i n s t r u c t i o n to c h a n g e
BR E X I T
from the current program counter r e g i s t e r to any other.
T h i s i n s t r u c t i o n is just m o d i f i e d and g i v e s a very fast The reason for h a v i n g t h i s RET i n s t r u c t i o n in front of the
response. For an i n t e r r u p t , it is a SEP 1 i n s t r u c t i o n . rest of the p r o g r a m g i v e s the a d v a n t a g e that after the return
So a u t o m a t i c a l l y , register 1 becomes the new program t h i s r o u t i n e i s ready t o b e executed w i t h o u t b e i n g i n i t i a l i z e d
counter and registe r 2 stack p o i n t e r ; the next instruction again. The same k i n d of s u b r o u t i n e is used in SEP t e c h n i q u e .
is fetched from the location where Rl points to.
To t o g g l e the i n t e r r u p t e n a b l e f l i p f l o p , the RET and DIS
As the i n t e r r u p t program w o u l d not know w h i c h r e g i s t e r was
i n s t r u c t i o n are used.
the PC of the i n t e r r u p t e d p r o g r a m , the v a l u e s of X and P
are a u t o m a t i c a l l y s a v e d in a T-register and further inter- IE = 0 (means, i n t e r r u p t s are d i s a b l e d )
For e x a m p l e
rupts are i n h i b i t e d (interrupt e n a b l e is reset).
P = 1
X = 2
The first two i n s t r u c t i o n s of the i n t e r r u p t program normally
save the T-register on the stack and the D - r e g i s t e r as w e l l .
The sequence

Now the IE can be set to 1 a g a i n to a l l o w nested interrupts . SEX Rl . . G o to i m m e d i a t e mode (X = P)

RET .. Do return w i t h next byte (21)
A program resumes from the i n t e r r u p t n o r m a l l y u s i n g the RET ,#21 .. I m m e d i a t e byte
instruction, which takes X and P from the stack and puts them
in the registers, so the program counter is c h a n g e d a g a i n and W i l l put the byte 21 in X and P, not c h a n g i n g the program execu-
comes back to the i n t e r r u p t e d program.
t i o n but s e t t i ng IE = 1.

A short e x a m p l e demonstrates how to write i n t e r r u p t routines To d i s a b l e the IE f l i p - f l o p it w o u l d be

for the CDP1802. R0 is the current PC, X = 0.
R e g i s t e r 1 is i n i t i a l i z e d to p o i n t to address 0401, register SEX R l . . G o to i m m e d i a t e byte
2 is loaded with free RAM area (40FF). DIS .. D i s i n s t r u c t i o n with 21
,#21 .. I m m e d i a t e byte
 36 37

As X and P are e q u a l , the i m m e d i a t e byte is used and not

the byte on the stack.

Reference MPM-201 page 64, page 80. 0000 08B1

0002 ..EXAMPLE PROGRAM
0003 ..INTERRUPT ROUTINE
0000 0004
0000 000VJ ..RAM AT 840HE
0000 0006
CPU
1/2 CD4013
0007
MWR CDP1802 0000

D 0000 0008 ..MAIN PROGRAM

SYSTEM O VOD
MEMORY -TL_ 0000 0B0V
MRD
RCL 0000 - 0010 ORG 88000
U000 71005 0011 l)I8i»88 .DISABLE INTERRUPTS
0002 F804BH 0012 INITs LD1 804; PHI R1 .INI'I INTERRUPT
— IV-
SCO

—-L/
INTERRUPT
000b F801A15 0013 LDI 801; PLO R1 .REGISTER R1=0401
t
SC1
ACKNOWLEDGE
0008 F840B2; 0014 LDI 840; PHI R2 .AND AS UEI..L 'IHE
000B F8FFA2! 001S LDI 8EE; Pit) R2 .STACKPTR FOR IT
000E 7000; 0016 RET , 800 .ENABLE INTERRUPTS
0010 ; 0017
0010 7A; 0018 START: RED .RESET 0
0011 00; 001V IDE .UAH FUR INTERRUPT
0012 7B; 0020 Bt'tl .SEC (J
0013 00; 0021 IDE .WAIT FOP, INTERRUPT
0014 3014; 0022 STOP: BR SI OP .UA11 FOR RESET
0016 0023
0016 0024
0016 002B ..INiERRUPl ROUTINE
0016 0026
0016 0027 ORG 804H0
TYPICAL CIRCUIT FOR IMPLEMENTATION OF INTERRUPT OPERATION 0400 70; 0028 EXIT: REf .REHIRN II! MAIM
0401 22', 002V ENTRY: DEC R2 .PUINl 'ID FREE RAM
0402 78; 003('i SAV .SAVE 'I REGIS'I'ER
0403 22; 003'i DEC R2 .DECREMENT PUlN'lER
0404 73; 0032 S'l XD .SAVE D REGISTER
040b 76; 6033 SHRC • GET DE IN 1!
H406 73; 0034 SI XI) .AND SHIRE AUAY
0407 8773; BBSS GLII R7; SI XI) .SAVE REBIS'IFR R7
040V V7735 0036 GH1 K71 STXi)
040B ; 0037 H. .AND (JTHERS
040B ; 0033 .IF NEEDED
040B 7B; 803V SEW .SEI (J TO SHOU
040C ; 0040 .INTERRUPT HAPPENED
040C ; 0041 .START REST ORINO
040C 12", 0042 INC R2 .INCREMENT S'lACKPTR
040D 42B7! 0043 LDA R2; PHI R7 .(jET R7 BACK
040F 42A75 0044 LDA R2; PLO R7
0411 42FE1 004S LDA R2; SHI. .AS UELL DE
M413 42; 0046 LDA R2 .AND D
1414 3060; 0047 BR EXIT .BRANCH 10 EXIT
0416 ; 0048 END
0000
 38 39

most a p p l i c a t i o n s the i n c o m i n g i n t e r r u p t s m u s t be synchro-

8 - L E V E L I N T E R R U P T V E C T O R I N G SCHEME
^zed as shown to the TPA s i g n a l , to a v o i d the i n p u t of spu-
ious codes d u r i n g t r a n s i t i o n s in the 4532.

The more powerful I/O devices in the 1800 series, such DIS .. s w i t c h to service routine
INTGO
as the 1851 PIO and the 1854A UART, have i n t e r n a l inter- DEC 2 ; SAV .. p u s h X and P
ENTRY
rupt request latches and m a s k i n g l o g i c , w h i c h are under DEC 2 ; STXD .. p u s h D
software control. Therefore most m u l t i - l e v e l interrupt INP V E C T O R .. vector carries register number
tasks can be i m p l e m e n t e d efficiently without the need for BR INTGO .. p r e p a r e for next i n t e r r u p t
a sophisticated interrupt c o n t r o l l e r : a s i m p l e priority
encoder w i l l do the job. T h e h o u s e k e e p i n g software i s m i n i m a l . During initialization,

-J-VDO
Rl mus t be i n i t i a l i z e d to the a d d r e s s "ENTRY".
In response to the i n t e r r u p t the r o u t i n e f i r s t p u s h e s X, P
--,,- - E,
Eo
IMT
and D into the stack, then i n p u t s the vector code from the

on Am? r, CD4066
4532. After b r a n c h i n g to " I N T G O " to p r e s e r v e the Rl s t a r t i n g
address control is passed to the a p p r o p r i a t e r e g i s t e r via the
"DIS" i n s t r u c t i o n . This leaves interrupts d i s a b l e d to a l l o w
TxGATE the s e r v i c i n g r o u t i n e to c o m p l e t e any further housekeeping
SYNC. PRIORITY
C needed before r e - e n a b l i n g further r e q u e s t s w i t h a "RET".
LATCH ENCODER COP 1802
f
CLK
The software i n p u t s the word INP V E C T O R and it goes a u t o m a -
{
t i c a l l y on the stack .

W i t h the " D I S " i n s t r u c t i o n the contents of t h i s stack is put

in X and P and a new program counter is c h o s en a c c o r d i n g to
The c i r c u i t shown here c o n s i s t s of a CD4532 8-1evel p r i o r i t y the i n p u t word.
e n c o d e r w h i c h generates a 3 - b i t code r e p r e s e n t i n g the h i g h e s t -
p r i o r i t y i n t e r r u p t i n p u t present. When any interrupt is as- S i n c e the four " p u s h " i n s t r u c t i o n s are necessary even in a
serted an i n t e r r u p t request is passed on to the C P U . In res- s i n g l e - l e v e l system, t h e o v e r h e a d incurred by vectoring in
ponse to the i n t e r r u p t the CPU i n p u t s the 3 - b i t vector via the t h i s way is o n l y three i n s t r u c t i o n s , i . e . 9.6 uS w i t h a 5MHz
1857 tristat e buffer. Control is then passed to one of the CPU clock.
r e g i s t e r s 8 to F in a way a n a l o g o u s to the 'SEP 1 s u b r o u t i n e c a l l .
In t h i s way each i n t e r r u p t i n g d e v i c e is v e c t o r e d to its own ser- Reference : 1802 user m a n u a l MPM-201 B, p a g e 64 interrupt
v i c e r o u t i n e , whose s t a r t i n g address i s stored in the a p p r o p r i a t e servi ce .
C P U register d u r i n g i n i t i a l i z a t i o n .
 40 41

CDP1863 used as a b a u d - r a t e generator for the CDP1854A U A R T

U s i n g a standar d CPU c l o c k frequency of 2.4576MHz the follo-

w i n g rates are a v a i l a b l e :
The 1854 U A R T needs a c l o c k i n p u t frequency 16 times the
baud-rate required. By u s i n g the 1863 p r o g r a m m a b l e f r e q u e n - 1863 C o u n t Baud Rate
cy g e n e r a t o r to p r o d u c e t h i s c l o c k the b a u d rate may be set
by software. 2400
1 1200
Suggested circui t : 3 600
7 300
11 200
15 150
21 110
31 75
CDP1802 CDP1863 CDP1854 47 50

TPB CK1
OUT
u TC
RC
TPB SD1 DATA IN
All rates are accurate e x c e p t for the 110 v a l u e , w h i c h
is a c t u a l l y 109.091, an error of 0.83%.

MTJ MM For c a l c u l a t i n g the code r e q u i r e d for other rates or for

* / "L
( C O N T R O L \A OUT other clock f r e q u e n c i e s the f o l l o w i n g f o r m u l a a p p l i e s :
N2 STR B, N2
Nl
N0 Mflj Baud rate = F V T M x - x - x — x
XIAL 8 8 16 N+l
1 1 1 1
DATA BUS Where N is the v a l u e to be l o a d e d i n t o the 1863.

References :
I/O Port A s s i g n m e n t s
CDP1854A, d a t a s h e e t , f i l e 1193
OUT 2 Load U A R T t r a n s m i t register CDP1863 d a t a s h e e t , f i l e 1179
OUT 3 Load UART c o n t r o l registe r a p p l i c a t i o n note, ICAN 6632
INP 2 Read UART receive register
INP 3 R e a d U A R T status r e g i s t e r
OUT 4 Load 1863 count v a l u e
 42 43

S Y N C H R O N O U S S E R I A L OUTPUT FOR THE 1802

educe l o a d i n g o n t h e interface s i g n a l s , e s p e c i a l l y
° ck and TPB) a driver such as CDP1856 is n o r m a l l y needed
to buffer these l i n e s .
I n systems h a v i n g o u t p u t c i r c u i t r y w h i c h i s p h y s i c a l l y
remote from the processor itself , cost and complexity A typical a p p l i c a t i o n of t h i s interface w o u l d be the
may be reduced by t r a n s m i t t i n g o u t p u t data in s e r i a l i m p l e m e n t a t i o n of a remote 4 - d i g i t m u l t i p l e x e d LED d i s p l a y .
form i n s t e a d of via a c o m p l e t e p a r a l l e l bus s t r u c t u r e . The receiving register is a CD4094 w h i c h p r o v i d e s the e i g h t
Such an a p p r o a c h does not n e c e s s a r i l y need e x t e n s i v e outputs b i t s needed (4 for d i g i t - d r i v e , and 4 for s e g m e n t -
s e r i a l c o m m u n i c a t i o n s p r o t o c o l s , a n d m a y often be r e a l i - d r i v e via a CD4511 d e c o d e r / d r i v e r ) . A CD4013 d u a l f l i p -
zed with an i n e x p e n s i v e shift-register. flop and a CD4011 UB gate c o m p l e t e the interface by gene-
r a t i n g a gated c l o c k and a strobe s i g n a l for the CD4094.
As an e x a m p l e , c o n n e c t i n g a CD4014 to the b u s , c l o c k and
TPB l i n e s of the 1802 as shown r e s u l t s in a c o n t i n u o u s
s e r i a l r e p r e s e n t a t i o n of the d a t a b u s on the o u t p u t l i n e . DATA
T h i s makes use of the fact that each 1802 m a c h i n e cycle DIGIT
CLOCK
has e i g h t c l o c k p u l s e s and every e i g h t h one is framed by
DRIVE
the TPB p u l s e . T h u s , the CPU clock p r o v i d e s the shift-
clock and TPB e n a b l e s synchronous p a r a l l e l l o a d i n g of the
r e g i s t e r each m a c h i n e cycle.

TPB

SEGMENT
CDP1802 N0 •» N?1
DRIVE
DATA BUS TPB CLK

ji ;
*i f

P/S
i
CLK
_ TPB
_

r
n nrv

DATA
Note that the 4011 and 4013 are not c o m p l e t e l y u t i l i z e d
arid the spare h a l v e s may be used to interface a second
4094 w i t h no a d d i t i o n a l components. Note a l s o that the
CD4014B SDO
4094 r e g i s t e r has 3 - s t a t e a b l e o u t p u t s and so may be used
to interface to another d a t a - b u s if r e q u i r e d .

T h i s c o n f i g u r a t i o n can form the b a s i s of a n u m b e r of References :

different s y n c h r o n o u s s e r i a l o u t p u t a r r a n g e m e n t s . It
should be noted that worst-case dynamic characteristics CD4014B d a t a s h e e t , f i l e 1043
of the CD4014 w i l l r e s t r i ct the m a x i m u m c l o c k frequency CD4094B datasheet, f i l e 869
to a b o u t 3.6MHz (at 10 v o l t s ) .
 44 45

I N T E R F A C I N G TWO COSMAC SYSTEMS U S I N G 1854A UART's

Asynchronous f u l l d u p l e x data c o m m u n i c a t i o n between two
i n d e p e n d e n t COSMAC systems can be a c h i e v e d u s i n g two
1854A U A R T ' s wired as shown. Baud rate generators must
be the same frequency for both systems.
W h e n the U A R T r e c e i v e s a s e r i a l data character it generates
a data a v a i l a b l e (TO) and an i n t e r r u p t request s i g n a l (INT).
U n t i l the CPU responds by r e a d i n g the data the TO l i n e i n h i -
b i t s word t r a n s m i s s i o n from the other U A R T , and v i c e versa.
Internal t i m i n g of the 1854A is such that a p u l s e at its
•rTS input at the time that TO of the receiving UART is acti-
vated w i l l cause the stop b i t to be reset early. To a v o i d
errors, the 4013 f l i p - f l o p s p r o v i d e a 2 clock period delay
between TO (low) and FTS~ ( h i g h ) .
If the 1802 c l o c k is used to d r i v e the UART c l o c k s the f l i p -
f l o p s can be e l i m i n a t e d and r e p l a c e d w i t h a s i m p l e i n v e r t e r
since the CPU w i l l take many more than 2 clock p e r i o d s from
when it is f l a g g e d to when it s e r v i c e s (reads) the UART.

854 k 185' A
RS EL

-E
RSEL
NO-N2 CS 1 CSI
—
NO-N2
'•—
cs 5 CS3

1802 MRO
•f — CS
RO WR
r
SDO SDI TO/WR
C55 -£
wRG
1802

TPB TP 3 TPB TPB

-£
TOT IF- SDI SDO INT

EF 1-4
Tff
FE
PE OE
V
r* '— » CTS
THRE
FE
^1-4
PE/OE
DA cTs •*—
-j »— DA

BUS BUS
:uoc c CLO( K
i T R T
1
L_
BAUD
GENERATOR
^ _
BAUD
GENERATOR

J i
SET 5ET^
D Q -*• D Q 0 D •J

4013 t 013
—• a—
:LK CLK * Q CLK C LK

1 t t t
 46 47

U N D E R S T A N D I N G THE CDP1855

Functional description (See Figure 1)

2.
P R O G R A M M A B L E MULTIPLY AND D I V I D E UNIT
The CDP1855 consists of 3 registers to achieve the
m u l t i p l y and divide : X, Y, Z.
1. Features
A control register (See Figure 2} is loaded to reset
. Fast m u l t i p l i c a t i o n and d i v i s i o n of unsigned b i n a r y registers, start the m u l t i p l y and d i v i d e , reset internal
numbers. counters, set the number of MDU devices and select the
divided clock rate. A status byte (Figure 3} indicates
. No additional hardware needed, uses N - l i n e s . an overflow (for example, d i v i d e by 0).

. For more I / 0 , t w o l e v e l I/O or memory m a p p i n g . i s used. The X, Y, Z registers are loaded with the operands and
In memory, four memory l o c a t i o n s needed. via the control word the m u l t i p l y or d i v i d e is started.

, M u l t i p l y a l g o r i t h m : s h i f t right and add. At power on the device must be cleared to avoid data
bus problems. This also resets the interna.1 sequence
. D i v i d e a l g o r i t h m : s h i f t l e f t and subtract. counters and the shift p u l s e generator.

. Perform s 8 x 8 m u l t i p l y , 8 / 8 d i v i d e , 1 6 / 8 d i v i d e . The sequence counters are needed for addressing if

more than one device is used. The 1855 has two program
. E x p a n d a b l e , up to 4 c i r c u i t s in p a r a l l e l w i t h o u t addi- inputs to be set as a device number (CNO, CN1). If
t i o n a l l o g i c for 32 x 32 m u l t i p l y , 32 / 32 d i v i d e , registers are read or written, this number is compared
64 / 32 d i v i d e . with an i n t e r n a l counter and automatically incremented.
Only the device with the same number is selected. So
. Speed e x a m p l e 8 x 8 m u l t i p l y after a R/W the next device is addressed. W i t h t h i s
S o f t w a r e at 3MHz 917 ;jS type of selection no further address lines are needed
H a r d w a r e at 3MHz 67 jjS if more than one device is used.

. Mul t i p l y time at 5V 5 jjS The first instruction has to load the control register
10V 2 , 5 u S with the number of MDU's to set up internal control l i n e s .

The X, Y, Z registers in a cascaded system can be accessed

randomly, because i n t e r n a l counters keep track,always s t a r t i n g
a s e q u e n c e w i t h the most s i g n i f i c a n t d e v i c e .

Before reading r e s u l t s , these counters have to be reset

a n d a g a i n they w i l l p o i n t t o t h e most s i g n i f i c a n t byte
of X, Y , Z.
 43 49

3. D i v i d e operation (See Figure 4)

6. Now it is p o s s i b l e to do a further d i v i s i o n by
1. Reset counters resetting Z register, because Y and X are not
Specify number of MDU altered.
Reset register
NOP 7. Example

Y Z X Z
|0 1 1 111 1 I oTl C o n t r o l word » 7C
HEX
0 1 6 B 3 C =06 0 3
Y Z —— NOP REMAINDER
Reset registers 363 6 0 0 6 .03 DEC
One MDU
Reset sequence counters
Shift rate = clock frequency

2. Transfer d i v i d e n d 67 7C
Load MSB in Y 66 44
Load LSB in Z 65 ZZ
For d i v e

3. Transfer d i v i s o r in
Load in X 64 XX

4. Start the d i v i s i o n

[0 1 I1 1 I0 Oil Ol Control word = 72

Divide
One MDU
Reset counters
Fast

5. Read results
Read q u o t i e n t in Z 6D ZZ
Read r e m a i n d e r in Y 6E YY
Read status 6F OX
 50 51

4. M u l t i p l y operation

1. Reset counters
Specify number of MDU Using 3 MDU' s to multiply 20 IF 7C by 72 3C 0
Reset register
NOP

MEMORY OP CODE UNE NO. LEVEL 1 ASSEMBLY LANGUAGE

3 1|1 1 | 1 1 | 0 0| Control word = 7C LOCATION
nnod F830: 0001 LDI =30
Y L i NOP 0002 A2; 0002 PLO H2 .LOAD 30 INTO R2.0
0003 F800; 0003 LDI =00
Reset registers 0005 g2: 0004 PHI
OUT
R2
7, =50
. LOAD 00 INTO R2.1 (R2-0030)
. .LOAD CONTROL REGISTERS
0006 6750: 0005
One MDU SPECIFYING
0008 0006 •THREE MDU'sAND RESETTING
Reset sequence counters THE
0007 •SEQUENCE COUNTERS
0008
Shift rate = clock frequency 0008 6420: 0008 OUT 4, =20 . •LOAD MSB OF X REGISTER
WITH 20
641 F: 0009 OUT 4.=1F .LOAD NEXT MSB OF X REG
OOOA
WITH IF
2. I n p u t m u l t i p l i c a n t 1 in X register 64 XX 0010 OUT 4,=7C .LOAD LSB OF X REGISTER
OOOC' 647C;
WITH 7C;
I n p u t mul t i p l i c a n t 2 in Z register 65 ZZ 0011 .X REGISTER CONTAINS =201F7C
OOOE

OOOE 6572; 0012 OUT 5.*72 . .LOAD MSB OF Z REGISTER

WITH 72
3. I n i t i a t e m u l t i p l i c a t i o n 0013 OUT 5.=3C . • LOAD NEXT MSB OF Z REG
0010 653C;
WITH 3C
|0 1| 1 1 | 1 0 [0 Ij Control word 79 0012 6509: 0014 OUT 5.S09 .LOAD LSB OF Z REGISTER
WITH 09:
1 Multiply 0014 0015 •Z REGISTER CONTAINS =723C09
0014 6759: 0016 OUT 7, =59 •LOAD CONTROL REGISTERS
RESETTING
flnn MDI I 0016 0017 •Y REGISTERS AND SEQUENCE
COUNTERS
0016 0018 .AND STARTING MULTIPLY
OPERATION
The Y r e g i s t e r has to be reset, b e c a u s e its contents 0016 E2; 0019 SEX R2
0017 6E60: 0020 INP 6;IRX .MSB OF RESULTS ISSTOREDAT
is a u t o m a t i c a l l y added to the r e s u l t . 0019 0021 . LOCATION 0030
0019 5E60; 0022 INP 6 IRX
0018 6E60: 0023 INP 6 IRX
0010 6060; 0024 INP 5 IRX
4. Read r e s u l t s 001 F 6060; 0025 INP 5 IRX
0021 60; 0026 INP 5 .COMPLETE LOADING RESULT INTO
0027 . MEMORY LOCATIONS 0030 TO 0035
Read h i g h byte in Y 6E YY 0022
0028 .RESULTS -OE5580BA2B5C
0022
0029 STOP BR STOP
Read low byte in Z 6D ZZ 0022 3022:

The result of 201 F7 C,6x723C091e il OE558DBA2B5C - 1S760612797276ia. It will be stored

in memory as follows:
5. E x a m p l e : (Y c o n t a i n s 03) LOC BYTE
0030 OE
31 55
X Z Y Z 32 3D
8A
3 C X 0 6 = 0 1 6 B 33
2B
34
35 5C

+ 0 3 in Y

5 0 X 0 6 = 360 + 3 = 363
 52 53

Y Z 00 NOP
01 Multiply
10 Di vi de
11 I l l e g a l state
H i g h to reset the register
Number of MDU 00 four
01 three
10 two

§ 1 1 t
11 one
Reset sequence counters
0 shift rate e q u a l s clock frequency
1 one MDU shift clock H- 2 two MDU
Ul shift clock - 4
three or four MDU shift clock - 8
\
E
1U 5
IT &
r1 0 _J
(Figure 2) : Control Register Bit A s s i g n m e n t
2
c. £ <>

rp
:

5p-1-^ 1
L i
C
>
~^
j Status byte |0 0 0 O J O 0 0 X |
Z-REQIS
[ " If an overflow occurs d u r i n g d i v i d e 16 : 8 b i t , overflow = 1
ia
CO
T"

Q.
ONTROL RE Q
(Figure 3) : Status Byte
i U

CE 28 — V DD
CLEAR 27 — CN0
CTL 26 CN 1
MULTIP (TO./5T. -— 2 5 — CI
rt_ — 24 — YR
ZL 23 ZR
3MIFT-— 22 BUS 7
C L K —- 21 1 BUS 6
STB • 20 — aus s
RD/WE : 1 19 • BUS 4
RA2 1 18 — BUS 3
RA 1 ' 1 17 — BUS 2
RA0 • 1 16 • BUS 1
v ss —l 1 15 BUS 8

(Figure 4) : T e r m i n a l A s s i g n m e n t s
CE RA2 RA1 RA0 R/W STB REGISTER FUNCTION X FUNCTION -
0 X X X X X NO ACTION
X 0 X X X X BUS FLOATS
1 1 0 0 1 X X MULTIPLIKATOR DIVISOR 64 "
II
1 1 0 1 1 X Z LSB DIVIDEND 65
'TO MDU
1 1 1 0 1 X Y TO BE ADDED ! MSB D I V I D E N D 66
1 1 1 1 1 X CONTROL 67
1 1 0 0 0 1 X UNCHANGED UNCHANGED 6C "
1 1 0 1 0 1 Z LSB RESULT QUOTIENT 6D
•TO CPU
1 1 1 0 0 1 Y MSB RESULT REMAINDER 6E
1 1 1 1 0 1 STATUS 0000 OOOX 6F
t
1 1 X X 0 0 NO ACTION BUS FLOATS
Low l e v e l
Hi gh level
H i g h or Low l e v e l
(Figure 5) : Control Truth-Table
 56 57

0052 8 X 8 DIVISION
0416 0053
8088 0801 8446
0054 USES THE FOLLOWING MEMORY LOCATIONS:
0002 0446
005S 480 DIVIDENT
0088 8883 3P RCA BXL 0146
0056 481 DIVISOR
0084 0446
0057 402 RESULT
8000 8885 0446
0058 403 REMAINDER
8000 8886 DEHOPROGRAH 48SS 0446
0059 404 OVERFLOW
0000 8887 MULTIPLY-DIVIDE-UNrr 0446
0446
0860 ..
0808 0064 OKG 80208
0889 8446
0200 00; 0062 8ACK2: SEP 0
8848 IT COKES BACK TO CDS AT 8885 0204 F804; 0863 LDI 884
8000 TO START UT28 PRESS CCR] 0203 BF; 0064 PHI F
8888 8842 TO UGRK WITH UT24 CHANGE TO LBR 88029 8204 F800; 0865 LDI 880
8843 0206 AF; 0066 PLO F
8814 0207 EE; 8067 SEX E
0000 0845 ORG fl88 0208 677C; 0068 OUT 7.B7C
0888 F801; 8846 LDI »04 020A EF; 0069 SEX F
8882 BE; 0847 PHI E 020B 65; 0878 OUT 5
0883 F801; 0048 LDI 881 020C 64; 0874 OUT 4
8885 AE; 8849 PLO E 0200 EE; 8872 SEX E
8886 6148; 8828 OUT 1,848 .. SET TUO LEVEL 10 020E 6772; 8873 OUT 7,872
8888 DE; 0024 SEP E 0210 EF; 0074 SEX F
8889 C888HS; 0022 LBR 88085 0244 6068; B87S INP 5;IRX
000C 0023 0243 6E60; 0076 INP 6;IRX
080C 0824 0245 6F; 0077 INP 7
000C 0025 MULTIPLY 8 X 8 0246 3008; 8078 BR BACK2
080C 8026 8218 0879 ..
088C 0827 USES THE FOLLOWING MEMORY LOCATIONS: 0248 0880 ..
000C 0028 488 4.mJLTIPLIKANT 0218 0884 .. 16 X 8 DIVISION
000C 0029 401 H.MULTIPLIKANT 8218 0082
800C 8030 402 RESULT HIGH BYTE 8218 0083 USES THE FOLLOWING MEMORY AREA:
900C 0834 403 RESULT LOU BYTE 0248 0084 400 DIVIDENT HIGH BYTE
308C 8832 0218 0085 401 DIVIDENT LOU BYTE
000C 0033 ORG 80400 0248 0086 402 DIVISOR
9108 00; 0034 BACK 4: SEP 0 0248 0087 403 RESULT
0104 F804; 0035 LDI 884 8248 8088 404 REMAINDER
0403 BF; 0036 PHI F 0248 0089 405 OVERFLOW
0104 F800; 0037 LDI B80 8218 0090 ..
0106 AF; 0038 PLQ F 0218 0894 ORG 80380
0107 EE; 0039 SEX E 8300 D0; 0092 BACK3 SEP 0
0108 6770; 0040 OUT 7,870 8301 F884; 8093 LDI 804
010A EF; 0044 SEX 0303 BF; 0894 PHI F
8188 64; 0042 OUT 8304 F800; 0095 LDI 800
010C 65; 0043 OUT S 8306 AF; 0096 PLO
0401) EE; 0844 SEX E 0307 EE; 8097 SEX
018E 6779; 8045 UUT 7,879 8308 677C; 8098 OUT 87C
9118 EF; 0046 SEX F 830A EF; 0099 SEX
0111 6E60; 0047 INP 6;IHX 830B 66; 0103 OUT
0143 6D; 8048 INP 5 838C 65; 0481 OUT
0114 3800; 0049 BR BACK4 830D 64; 0102 OUT
0116 8050 830E EE; 0403 SEX
8116 0054 830F 67/2; 0404 OUT 872
8311 EF; 0405 SEX
8342 6D60; 0106 INP IRX
8314 6E60; 0107 INP :IRX
8316 6F; 0408 INP
8317 3000; 8109 BR BACK3
8319 5 0110
 58 59

U S I N G THE MDU
COSMAC systems u s i n g the CDP1855 MDU can perform an 8 bit
x 8 bit m u l t i p l y in 8% of the m a c h i n e t i m e r e q u i r e d by
systems u s i n g a software m u l t i p l y a l g o r i t h m .
b o t h m e t h o d s are e x p l a i n e d b e l o w :
. re i shows the pin c o n n e c t i o n s for u s i n g the 1855 w i t h
the 1802/1804. A s u b r o u t i n e for p e r f o r m i n g an 8 x 8 m u l t i -
1 y is l i s t e d in program 2. The o v e r h e a d of r e g i s t e r i n i -
t ' a l i z i n g is about the same as in the 1st p r o g r a m , h o w e v e r ,
Programs for the actual 13 i n s t r u c t i o n s u b r o u t i n e m u s t be executed o n l y
once since t h e M D U does a l l t h e s h i f t i n g a n d a d d i n g .

Software m e t h o d A g a i n a s s u m i n g a c l o c k frequency of 3MHz, the t i m e required

to load two 8 bit n u m b e r s , m u l t i p l y , and read the 16 bit
Software i m p l e m e n t a t i o n of an 8 x 8 m u l t i p l y a l g o r i t h m , result is o n l y 69 uSec.
based on a m e t h o d of add and s h i f t r i g h t , is l i s t e d in
program 1. N o r m a l o v e r h e a d of i n i t i a l i z i n g the CPU Step-by-step o p e r a t i o n of the MDU
registers is done in the m a i n program. Since 9 shifts
a r e required t o complete t h e 8 x 8 m u l t i p l y operation, 1. Load the control r e g i s t e r by e x e c u t i n g an OUT 7 i n s t r u c -
18 i n s t r u c t i o n s of the s u b r o u t i n e m u s t be repeated n i n e t i o n followed by the control byte, in t h i s case FO
t i m e s , r e s u l t i n g in a tota l of 344 m a c h i n e cycles. Assu- (11110000). L o g i c h i g h s on b i t s 4 and 5 d e f i ne the
m i n g a c l o c k frequency of 3 M H z , the t i m e r e q u i r e d to c o m p l e t e number of cascaded M D U ' s as one. Bit 6 resets the
the o p e r a t i o n is 917 uSec. i n t e r n a l sequence c o u n t e r s , and bit 7 s e l e c t s the o p t i -
onal c l o c k p r e s c a l e r , w h i c h causes t h e s h i f t frequency
H a r d w a r e method u s i n g the CDP1855 to be 1/2 of the c l o c k frequency. T h i s is r e q u i r e d when
the clock frequency is h i g h e r than 1.5MHz at 5V o p e r a t i o n
or 3MHz at 10V o p e r a t i o n .

2. Load the X r e g i s t e r by e x e c u t i n g an OUT 4 i n s t r u c t i o n

rflh followed by one of the 8 bit operands.
j-AAAr
Figure 1 :
iiTAL CL EAR
CL K 3- Load the I register by e x e c u t i n g an OUT 5 i n s t r u c t i o n
NO RA 0
1855 v Connecti ons
1802
followed by the other 8 bit operand. The order of steps
N1 CE
RA
Between
N2 RA 2 CI 2 and 3 can be i n t e r c h a n g e d if desired.
TPB ST J CNO Mi croprocessor
MRD RD / W E CNI
and
YL Load the control register as in step 1 but t h i s time
E ZR
CT L

YR
Multiply/
Divide Unit
w i t h F9 (11111001). Bit 3 resets register
and the code of 01 on b i t s 1 and 0 cause the m u l t i p l y
Y to zero

C ZL
o p e r a t i on to begi n .
1 1 _J
 60 61

5. T h e MDU w i l l a u t o m a t i c a l l y perform t h e 8 x 8 m u l t i -
ply and store the most s i g n i f i c a n t h a l f of the 16 bit
answer in register Y and the lesser significant half PROGRAMJLJ- ASSEMBLY
in the Z register. The time required to perform the M ADDRESS. BYTE PROGRAM COMMENTS
-^v

actual m u l t i p l y o p e r a t i o n is 8N + 1 shifts, where N = F800 LDI 00 RO = Prog, counter '.;

oooo 87 PHI R7 R7 = Product register \1 = 00
the number of M D U ' s , in t h i s case one. Therefore, it 0002
B8 PHI R8
0003
takes 9 s h i f t cycles, and since the prescaler is being F8FF LDI FF Vlnltial
0004
A8 PLO R8 R8 = 00 FF ization
used, t h i s translates to 18 clock p u l s e s of the CPU. 0005
F803 . LDI 03
0007
nnnQ AE PLO RE
To p r o v i d e enough time for the m u l t i p l y operation, ouuy
OOOA F802 LDI 02
software s h o u l d be arranged so that one 2-cycle instruc- OOOC BE PHI RE RE = Sub. Prog, counter
OOOD DE SEP RE Call subroutine
tion occurs between the m u l t i p l y command and the reading 000 E (data) (data) 8 bit Multiplicand
of the answer. 000 F (data) (data) 8 bit multiplier J

6. Read the most s i g n i f i c a n t h a l f of the 16 bit answer 0202 DO SEP RO Return to main prog.
0203 F809 LDI 09
from register Y by executing an INP6 instruction. 0205 A6 PLO R6 R6 = Loop counter
0206 FE SHL Presets DF = 0
0207 40 LDA RO Load M'cand
7. Read the lesser s i g n i f i c a n t h a l f of the 16 bit answer
from register Z by executing an INP5 instruction. The 0208 58 SIR R8 into OOFF
0209 40 LDA RO Load M'lier
order of steps 6 and 7 can be interchanged is desired. 020A A7 PLO R7 into R7.0
020B E8 SEX R8 _
020C
Sub-
97 GHI R7
" routine
0200 76 SHRC Shift low byte
020E B7 PHI R7
020 F 87 GLO R7
0210 76 SHRC Shift high byte
0211 A7 PLO R7
0212 Loop
3B17 BNF 17 Branch if DF = 0
0214 > 9
97 GHI R7
times
0215
H91 c F4 ADD Add M'lier to R7.1
u<:16
091 ~t B7 PHI R7 Return sum to R7.1
Uc 1 7
26 •*DEC R6 Index loop count
0218
0219 86 GLO R6
021A
3202 BZ 02 Loop count = 9?
0218 A6 PLO R6
300 C BRO OC Continue looping J
 62 63

M E M O R Y M A P P I N G THE MDU

PROGRAM # 2 The current CDP1855 data sheet does not currently show how
ASSEMBLY use the d e v i c e in a memory m a p p e d c o n f i g u r a t i o n ; however,
M ADDRESS BYTE PROGRAM COMMENTS it does mention the use of MWR for RE/WF, and address l i n e s
0000 F801 LDI 01 Load 0101 or functions of address l i n e s for RAO, 1 and 2. T h i s w i l l
0002 BE PHI E into
0003 AE PLO E RE of the CPU work p r o v i d e d certain non-memory operations, such as P H I ,
GLO, etc..., do not cause s p u r i o u s s e l e c t i o n of the MDU
when the contents of the i n t e r n a l registers appear on the
0004 DE SEP E Go to subroutine at 0101
0005 address bus .
Main program continues

To prevent the MDU from r e s p o n d i n g to s p u r i o u s addresses,

0100 DO SEP 0 Return to main program and thereby a v o i d i n g bus c o n t e n t i o n , the MWR and MRD
0101 F802 LDI 02 Load s i g n a l s must be OR'd to produce a v a l i d CE s i g n a l . The
0103 BF PHI F RF of the CPU
0104 F800 LDI 00 with IRX i n s t r u c t i o n is a s p e c i a l case; it s h o u l d not be used
0106 AF PLO F 0200 when R (X) is p o i n t i n g to any of the MDU register addresses,
0107 EE SEX E since t h i s i n s t r u c t i o n not o n l y presents the contents of
01 OG 67FO OUT 7, FO Load MDU control register R (X) on the address b u s , but a l s o forces MRD l o w , w h i c h
010A EF SEX F
01 OB 64 OUT 4 Load X register of MDU e n a b l e s the MDU and causes i n a d v e r t e n t a d v a n c i n g of the
010C 65 OUT 5 Load Z register of MDU sequence counters.
010D EE SEX E
010E 67 F9 OUT 7, F9 Load MDU control register The required " O R ' d " CE s i g n a l , as w e l l as l a t c h e d h i g h order
0110 EF SEX F
0111 6E INP 6 Read Y register of MDU address b i t s , are u s u a l l y a v a i l a b l e in most memory i n t e n s i v e
0112 60 IRX systems u s i n g an 1866 or 1867 d e c o d e r , or s i m i l a r hardware.
0113 6D INP 5 Read Z register of MDU
0114 3000 BR 00 Branch to 0100

0200
CLEAR
* CLEAR* +VDD
n
(data) 8 bit Multiplicand loaded in X Y
0201 (data) 8 bit Multiplier loaded in Z MAO
0202 (data) Storage space for result, high byte MAI
ruin _1
0203 (data) Storage sapce for result, low byte HIGH
1
MAy
LATCH
1802 1855
* Based on program examples submitted by 0. Pintaske, RCA Brussels. TO A t

MU/D ,1
MRD
CE CTL j
TD R
,1
BUS EF 4 C0 BUS ZL
1 1 1
 64 65

FASTER MDU T H R O U G H P U T U S I N G "DMA METHOD'

TABLE 1

W h e n u s i n g the MDU in the normal c o n f i g u r a t i o n shown in

the CDP1855 data sheet, a l a r g e p o r t i o n of the t h r o u g h p u t SYSTEM
time is consumed by l o a d i n g and u n l o a d i n g data and control MULTIPLY TIME THROUGHPUT
MULTIPLY METHOD
bytes. T h r o u g h p u t speed can be i n c r e a s e d by 453! by u s i n g IN M I C R O S E C O N D S FREQUENCY
a DMA in/out t e c h n i q u e to l o a d and u n l o a d the M D U . Figure 1
shows the h a r d w a re needed to : s e q u e n t i a l l y address the Software o n l y 917 1 KHz
M D U ; control the t i m i n g of read/write; and i s s u e DMA in/
out s i g n a l s to the C P U .
Hardware MDU 69 7.8 KHz
(normal o p e r a t i o n )
W i t h the normal I/O m a p p e d M D U , the CPU m u s t execute 6 I/O
i n s t r u c t i o n s to f a c i l i t a t e a m u l t i p l y / d i v i d e o p e r a t i o n .
Hardware MDU 29 11.4 KHz
The "DMA m e t h o d " r e q u i r e s onl y one I/O i n s t r u c t i o n , l e a v i n g using DMA technique
more u n u s e d I/O m a p p i n g space for l a r g e r systems.
Theoreti cal mi nimum 21.3 14.4 KHz
Speed c o m p a r i s o n

T a b l e 1 shows a c o m p a r i s o n of m u l t i p l y t i m e (not i n c l u d i n g
l o a d i n g and u n l o a d i n g the stack), and system throughput fre-
quency ( i n c l u d i n g l o a d i n g and u n l o a d i n g the stack) for 4
V a l u e s g i v e n are for system o p e r a t i o n at 5 v o l t s V DD and
different m u l t i p l y methods.
3 MHz c l o c k frequency.

1. The "software method" u s i n g only software (no MDU)

A d d e d hardware (Figure 1)
2. The " n o r m a l h a r d w a r e m e t h o d " u s i n g the MDU addressed
by the CPU
Both f l i p - f l o p s a r e n o r m a l l y i n t h e reset c o n d i t i o n , c a u s i n g
3. The "DMA m e t h o d " u s i n g the MDU as shown in F i g u r e 1
no DMA a c t i o n . A (0111) code is jammed into the CD4516,
4. The "theoretical m i n i m u m DMA method" u s i n g the MDU;
k e e p i n g the MDU d e - s e l e c t e d (CE = 0).
assuming m u l t i p l i c a t i o n by a constant number. Special
hardware would a v o i d r e l o a d i n g X and Y registers. A
p u l s e a t t h e CLEAR" p i n w o u l d r e p l a c e l o a d i n g t h e l a s t
When an output 2 i n s t r u c t i o n occurs, the N . l i n e goes h i g h ,
control byte (FC).
setting flip-flop B, which asserts a DMA-OUT signal at the
CPU. Later in the output cycle, d u r i n g TPB, f l i p - f l o p A is
s et, which removes the preset (JAM) signal from the CD4516.
 66 67
STRETCHED
(-—CYCLE 1
J READ X /
LOAD LOAD LOAD ? MDU MULT. F READ LOAD NORMAL
PROGRAM 1 lOR DIVIDE OfH Y CONT PROGRAM

The CD4516 merely counts up at each TPA pulse, sequentially = _T"L

a d d r e s s i n g the M D U . A d d i t i o n a l l o g i c decodes the CD4516
output to produce the DMA-I N s i g n a l (DMA-IN" has priority
over DM A-OUT). At the end of the address sequence, the
carry out (CT) restores the f l i p - f l o p s to t h e i r o r i g i n a l
states; e n d i n g the DMA a c t i o n , and d e - s e l e c t i n g the M D U .

The MDU SHIFT pin is connected to the CPU WATT pin c a u s i n g

a stretched CPU cycle d u r i n g the m u l t i p l y / d i v i d e o p e r a t i o n ,
so that the MDU receives at l e a s t 18 c l o c k p u l s e s before
the answer is read from the Z and Y registers.

Software program
TIMING DIAGRAM
The program starts by i n t i a l i z i n g register R3, d e s i g n a t i n g
it as the program counter, and freeing R0 for the DMA pointer.
RX is a l s o set to R0 so that the stack can be l o a d e d / u n l o a d e d
u s i n g INP/OUT i n s t r u c t i o n s .

The p r o g r a m enters the m u l t i p l y r o u t i n e , and loops conti-

n u o u s l y performing s u c c e s s i v e m u l t i p l y operations . T h e
l o o p i n g scheme was chosen to demonstrate the t h r o u g h p u t
rate of the system (Figure 2) in terms of m u l t i p l i e s / s e c .

A l t h o u g h not shown, the software can be m o d i f i e d to f a c i l i -

tate the use of b r a n c h and i n t e r r u p t t e c h n i q u e s to get in
and out of the m u l t i p l y loop. W i t h the a d d i t i o n of a SEP
i n s t r u c t i o n , the m u l t i p l y operation can become a one-shot
subrouti ne .
Figure 1

ANSWER
IGH
TE

M CPU

BUS
m^
Figure 2
 68 69

DIGITAL FILTER USING THE CDP1855

PROGRAM FOR MULTIPLY USING "DMA METHOD"

ASSEMBLY
M ADDRESS BYTE PROGRAM Figure 1 shows a simple low-pass f i l t e r c o m p o s e d of a
COMMENTS
0000 F800 LDI 00 i s t o r and a c a p a c i t o r . The o u t p u t v o l t a g e can be
RO = Prog. Counter
0002 B3 PHI R3 d e s c r i b e d by the d i f f e r e n t i a l e q u a t i o n :
0003 F807 LDI 07
0005 A3 PLO R3 R3 = 0007
0006 D3 SEP R3
0007 E3 SEX RO RO = RX
0008 F807 LDI 07 1. _VO + V0_[_t)= VI (t)
000 A AO PLO RO dt RC RC
OOOB F802 LDI 02
GOOD BO PHI RO
OOOE F8FC LDI FC
By u s i n g E u l e r ' s method of s a m p l i n g integration,
Put FC in Stack
0010 50 STR RO at 0207 equation 1 is transformed to :
0011 F803 LDI 03
0013 AO PLO RO
0014 F8F1 LDI Fl
0016
Put Fl in Stack 2. V 0(n) = k V I(n) V 0(n-l) ; w h e r e n 1s any
73 STXD at 0203
0017 F800 LDI 00 Put 00 in Stack
sample period,
0019 73 STXD at 0202

1 and m = 1
001A F801 LDI 01 k =
001C AO PLO RO 1 + RC/T 1 + T/RC
001D 69 INP 9 Port A data to Stack 0201
001E 20 DEC RO
001F 6A INP C
T is the s a m p l i n g time i n t e r v a l in seconds, R is in ohms,
Port B data to Stack 0200
0020 20 DEC RO and C i s i n farads.
0021 62 OUT 2 # Initiate DMA and multiply
0022 F805 LDI 05 action
0024 AO PLO RO
Equation 2 can be i m p l e m e n t e d w i th a recursive d i g i t a l filter
0025 61 OUT I that uses m u l t i p l y , a d d , and delay functions as shown in F i g u re
STACK 0205 to Port C
0026 64 OUT 4
0027 301A BR routine
Stack 0206 to Port D 2. Figure 3 shows two m u l t i p l y operations of the CDP1855. The
second operation adds the result of the first operation to its
01FF\0 i Product. The feedback delay is o b t a i n e d by a r e a d - i n and then
Dummy byte
Load X register read-out of a scratch pad memory c e l l .
0201 / Load Z register
0202 I STACK Load Y register
0203 /
Load control register The program l i s t i n g shows a routine used to do real time recur-
0204 \5 , Read X register sive d i g i t a l f i l t e r i n g , where t h e i n c o m i n g a n a l o g s i g n a l i s d i g v
Read Z register
0206 < Read Y register *ized by an A/D converter, processed by the d i g i t a l f i l t e r , and
0207 / Load control register re constructed by a D/A converter (Figure 4).

# Only one instruction required to activate a complete MDU operation

 70 71

The beginning of the program initializes CPU registers, ;4=c OUTPUT

INPUT
and loads constant data into the stack area. The program
then moves into a continuous loop of data i n p u t , data pro-
cessing (MDU action), and data output.
Figure 1

The sample rate (T) is the time it takes the program to

execute the routine loop of 15 instructions.

If the CPU clock is 3.2 MHz, the time required to complete vl(n)
one loop is 75 uSec, or a sampling frequency of about 13
»Vo(n)
KHz. Based on the Nyquist criterion of at least two samples
per cycle, the i n p u t s i g n a l frequency s h o u l d be l i m i t e d to
6.5 KHz.

Exampie
9ZCS-33I70

Assume that F i g u r e 1 has R = 30K Ohms, and C .1 uF, and Figure 2

that T = 75 uSec;

then 1 = .2 = .00110011 B i n a r y = 33 h e x ,
K (8 BIT)
k = Ix
1 + 300/75 (8 BIT) Z /^(MSD 8 BIT)
Vl(n)
and 1 3 = .11001100 Binary = CC h e x . (8 BIT) 1st OPERATION
1 + 75/300 Ix JY
Z./*v*sY (B BIT).
Assume now that the i n p u t s i g n a l goes from 0 to a f u l l scale
2nd OPERATION
v o l t a g e of 1 v o l t , and remains at 1 v o l t for 10 s a m p l e periods.
Vo(n-l) SCRATCH
U s i n g equation 2 the corresponding output v o l t a g e s are l i s t e d PAD
MEMORY
below, and if plotted w o u l d p r o d u c e a response curve s i m i l a r
to that of the a n a l o g RC c i r c u i t .
Figure 3
S a m p l e time n 0 1 2 3 4 5 6 7 8 9 10
Input voltage V , 0 1 1 1 1 1 1 1 1 1 1
ANALOG
Output v o l t a g e V Q 0 .20 .36 .49 .59 .67 . 74 .79 .83 .86 .90 ANALOG
OUTPUT
INPUT

Figure 4
 72 73

Assembly
M. Address Byte Program
MULTIPLE INTERRUPT WITH CDP1851
0000 F8 04 LOI 04 RP - RO
0002 AB FLO RB
0003 F8 05 LDI 05 Introduction
0005 AA PLO RA
0006 F8 01 LDI 01
0008 BA PHI RA RA = 0105 The f l e x i b i l i t y of CDP1802 register d e s i g n a t i o n a l l o w s easy
0009 BB PHI RB RB = 0104
0 0 0A EA
i m p l e m e n t a t i o n of a vectored interrupt system.
SEX A RX - RA
0 0 0B F8 FD LDI FD Load data
0 0 0D 73 STXD in Stack 0105 By u s i n g software and the u n i q u e register d e s i g n a t i o n capa-
0 0 0E F8 00 LDI 00 Initialize storage space
0010 73 STXD
b i l i t i e s of the CDP1802 i n t e r r u p t , s e r v i c e routines can be
data to zero (0104)
0011 F8 CC LDI CC Load data p o s i t i o n e d at random in memory.
0013 73 STXD in stack 0103
0014 F8 F9 LDI F9 Load data
0016 73 STXD in stack 0102 In the CDP1802 the i n t e r r u p t m e c h a n i s m c o n s i s t s of X, P
0017 73 STXD Decrement RX again designators b e i n g saved in a temporary register T,these
0018 F8 33 LDI 33 Load data
0 0 1A 5A
designators b e i n g s u b s e q u e n t l y loaded by 2, 1 respectively .
STR A in stack 0100
0 0 1 B Routine 64
Interrupts are automatically d i s a b l e d .
OUT 4 Load X register 1
0 0 1C 69 INP 9 READ Vj. from A/D
0 0 1D 66 OUT 6 Load Z register
0 0 1E In an interrupt vectored system the interrupt routine pointed
67 OUT 7 Load control register
0 0 1F 7A REQ Dummy instruction during multiply to by Rl consists of software, w h i c h stacks the T-register and
0020 64 OUT 4 Load X register other registers w h i c h have to be p r e s e r v e d , and a software
0021 66 OUT 6 Load Z register
0022
vectored system.
67 OUT 7 Load control register
0023 7A REQ Dummy instruction during multiply
0024 6A INP A READ Y register A software vectoring system is one w h i c h computes, with I/O
0025 5B STR B STORE in stack at 0104
0026
interrupt status i n f o r m a t i o n , the address of the i n t e r r u p t
61 OUT 1 Load D/A with same data
0027 F8 00 LDI 00 routi ne.
0029 AA PLO RA Set RX back to 0100
0 0 2A 30 IB BR Routine Branch to "Routine"
This status i n f o r m a t i o n in a m i n i m a l software system is obtained
from an i n p u t port such as the CDP1851.

0100 33 \) K constant value

0101
In the i n t e r r u p t system i m p l e m e n t e d by CDP1851 shown, several
i V data from A/D
0102 re STACK Control byte, reset Y and multiply unique features of the device have been used.
0 1 0 3 cc f AREA m constant value
0104 (data) \D Storage space for result V
0105 Control byte, multiply and add Y The interrupt system allows for m u l t i p l e interrupt requests
by use of the CDP1851 operating in a bit p r o g r a m m a b l e port
mode, port A, B set as inputs. An interrupt masking system
can be i m p l e m e n t e d by u s i n g the CDP1851 interrupt l o g i c a l
m a s k i n g feature. Interrupts are generated on the l o g i c a l
condition of port i n p u t l i n e s .
 74
By use of a SEP i n s t r u c t i o n to the interrupt P.C. the
service r o u t i n e is executed. D u r i n g the service routine
the interrupt on the d e v i c e can be reset and interrupts
a l l o w e d if necessary. On occurence of a second interrupt
the interrupt entry w o u l d be processed again,the p r e v i o u s
contents of R(N) stacked and T-register and the new v a l u e ,
from the interrupt status, loaded. Execution of the second
interrupt service routine terminates by setting P to Rl and
returning to the i n t e r r u p t entry e x i t routine.
In the i n t e r r u p t e x i t routine, the p r e v i o u s i n t e r r u p t is
restored and P set to t h i s v a l u e by the use of a return
i n s t r u c t i o n . A s c h e m a t i c of the process for two l e v e l s is
shown in Figure 3.
The i n t e r r u p t can be e n a b l e d and d i s a b l e d in the p r i o r i t y
system both in the CDP1802 and CDP1851, the latter by wri-
ting a control word.
Interrupts can be reset by one of two ways; firstly by c l e a -
ring the source of the i n t e r r u p t by,for e x a m p l e , a decode of
the CDP1802 state code l i n e s SC0, SCI; a l t e r n a t i v e l y , b y
c h a n g i n g the i n t e r r u pt mask of the PIO (CDP1851) and reset-
ting the interrupt source by o u t p u t t i n g a control word to
the p e r i p h e r a l .
T h i s system,by using only one port of the P I O ( l e a v e s the
other port a v a i l a b l e for I/O i n t e r f a c i n g .
System e x p a n s i o n
The numbe r of interrupt l e v e l s may be increased by u s i n g
the other port of the PIO in conjunction w i t h a C D 4 5 3 2 in
a s i m i l a r way to the 8 l e v e l priority system.
As the CDP1851 i n t e r r u p t l i n e s ATRT, BTFT are open d r a i n
NMOS, a W I R E D OR c o n f i g u r a t i o n is p o s s i b l e m a k i n g such a
system feasible.
75
The l o g i c a l c o n d i t i o n can be set for any of A N D , OR, N O R ,
NAND. W i t h the system shown the encoded output of the l i n e
encoders,together w i t h i n t e r r u pt mask setting c a p a b i l i t y of
the CDP1851,can i m p l e m e n t a l e v e l system w i t h an 'OR' c o n d i -
tion or a s e l e c t i v e system w i t h 'AND' c o n d i t i o n .
Interrupt l e v e l can be o b t a i n e d by an i n p u t read from the
port and software in the i n t e r r u p t service r o u t i n e , 1 o a d i n g
the a p p r o p r i a t e register with the address of the routine
to be serviced; d e f i n i n g the other b i t s in the oort as out-
put and setting these as zero.allows the bits to be read as
zero d u r i n g an i n p u t .
An e i g h t level p r i o r i t y system
A system with the c a p a b i l i t y of h a n d l i n g up to e i g h t l e v e l s
of interrupts is shown in F i g u r e 1. It consists of a CDP1851
and a CD4532, e i g h t bit p r i o r i t y encoder, the encoded output
of w h i c h is connected to D3 to D7 of one of the CDP1851 ports.
The system a l l o w s each interrupt s e r v i ce routine up to 32 bytes
w h i c h can be expanded by use of branch instructions.
The software required to i m p l e m e n t the system is shown in Figure
2A, 2B for 1802 and 1804 CPUs. One a d d i t i o n a l register is used
to permit nesting of interrupts.
The i n t e r r u p t response time at 6.4 MHz is 15 uSec .
The software consists of an interrup t ENTRY and EXIT routine,
to generate interrupt vectors and return from s u b r o u t i n e s , and
Interrupt servic e subroutines .
The interrupt program counter h i g h order b i t s are loaded in
i n i t i a l i s a t i o n , therefore g i v i n g the c a p a b i l i t y of p o s i t i o -
n i n g these routines anywhere in memory. Entry to a service
routine is done by i n p u t t i n g interrupt status to the inter-
rupt program counter low order after firstly stacking it.
 76 77

The r e l a t i v e p r i o r i t i e s of the i n t e r r u p t s are m a i n t a i n e d

TNT
6 A INT
A7 ~=
8 levels
by software. The source of the i n t e r r u p t i.e. AINT, BINT CD
B INT
4532 i nterrupt
b e i n g o b t a i n e d by p o l l i n g the status word of the PIO.

A » ^=
CDP1802 CDP1851 A5
T h i s system a l l o w s for 16 i n t e r r u p t s . A system w h i c h cas- DATA BUS"
P R I O RITY E N C O D E R S
CDP1804 PIO
cades CD4532's can be i m p l e m e n t e d but more c i r c u i t e l e m e n t s
are r e q u i r e d t h a n the before m e n t i o n e d 16 l e v e l system.
B7 CD 5= 8 levels
4532
Alternative systems i nterrupt

F o r s m a l l i n t e r r u p t systems by a l t e r i n g the priority i n p u t RC;

to b i t s D01 to D3 and l o a d i n g t h i s i n f o r m a t i o n into the P F i g u r e _! : M u l t i p l e I n t e r r u p t M a s k i n g System
designator a faster i n t e r r u p t response, of 15 uSecs at 2 MHz
can be obtained (Figure 1). figure_2a : I n t e r r u p t Entry (1802 and 1804 MNEMONICS)

1802 1804
BXL EXTINT .. Test if ext. - int.

DEC R2 E X T I N T : DEC R2 SAVE

SAV SAV X ,P on stack
GLO RN • RSXD Stack PC
STXD
INP INTST INP INTINST Get i n t e r r u p t states
PLO RN PLO RN Load INT PC
SEP RN SEP RN And execute p r o g r a m

fj_g.u_re__2J> : Interrupt E x i t (1802 and 1804 M N E M O N I C S )

LDXA RLXA .. D e s t a c k i n t e r r u p t
p L O RN

RET RET . . R e t u r n to
.. I n t e r r u p t r o u t i n e
MAIN PROGRAM 78 79
VIS - A COMPLETE V I D E O INTERFACE SYSTEM
X = 2
P = 1 INTRODUCTION
1.
SAVE T
STACK R(N).0 RCA's 1800 series is a f u l l y CMOS Microprocessor
LOAD R(N).0 family c o n s i s t i n g of CPUs, R A M s , ROMs, E P R O M s , P I O ,
SEP R(N) UART, MDU .interface c h i p s and low resolution v i d eo
Get old R(N) .0 controllers.
and return
As the need for d i s p l a y i n g data increases, RCA adds
to this l i n e a h i g h r e s o l u t i o n Video Interface
System (VIS). This system consists of CDP1869 and
CDP1870, two CMOS LSI d e v i c e s to generate all the
necessary s i g n a l s needed for v i s u a l i s a t i o n on the
screen; in a d d i t i o n a sound generator and white
Different interrupt noise are i n c l u d e d w i t h v o l u m e control on the c h i p .
service routines.
Each up to This set of d e v i c e s interfaces d i r e c t l y w i t h m i n i -
32 bytes l o n g mum a d d i t i o n a l hardware to the CPU CDP1802 but is
designed as a completely independent I/O. No refresh
s i g n a l s are needed that m i g h t stop the processor for
synchronisation d u r i n g d i s p l a y time. "Predisplay"
s i g n a l s the CPU this,one d i s p l a y l i n e before the
refresh starts and no further access to VIS memories
is possible until the d i s p l a y of a frame has been
f i n i s h e d . Then a g a i n i n t e r n a l m u l t i p l e x e r s allow
access to the VIS memories in order to change charac-
ter memory - dot and c o l o u r i n f o r m a t i o n or page memory -
I N T E R R U P T N E S T I N G FOR 1 L E V E L OF I N T E R R U P T character a l l o c a t i o n on the screen. D u r i n g d i s p l a y t i m e
the processor is c o m p l e t e l y free for other I/O or com-
puti ng .
4FF4 X M , HM

4FF3 R 1(N) .0
4FF2 2, 1
4FF1 R 2(N) .0

4FFO 2, 1
4FEF R3(N) .0

STACK C O N T E N T S FOR 3 L E V E L S OF INTERRUPT

( I n t e r r u p t e d i n t e r r u p t s e r v i c e routines)
 80 81
3. M E M O R Y SYSTEMS for V i d e o Interface Systems
2. C A P A B I L I T I E S

Two systems are p o s s i b l e , if a v i d e o system is d e s i g n e d :

In short the c a p a b i l i t i e s of VIS are :

o Programmable resolution a) F u l l bit map approac h

b) Character d i s p l a y
40 characters and 24 rows
In a f u l l bit map approach each memory bit represents
20 characters and 12 rows
a p i x e l or dot on the screen. T h i s type is ideal to
d i s p l a y curves and pictures but it needs a large amount
o Character size NTSC 6 dots w i d e by 8 dots h i g h
of memory. For e x a m p l e a d i s p l a y of 40 characters per
PAL 6 dots wide by 9 dots h i g h
l i n e and 24 rows w i th a character size of 6 x 8 in bit
map would be represented by
o Up to 256 different characters are p o s s i b l e

o Character d e f i n i t i o n in 6 bit per character l i n e x

8 character 1i nes x
40 x 24 = 960 x 6 x 8 = 48K bit b u i l t by a memory of 8K
RAM, ROM, or e v e n mixed
and 6 b i t wide.
o Up to 8 c h a r a c t e r c o l o u r s
A second c h o i c e is to d i v i d e the screen into a surface
of characters. For e x a m p l e a d e f i n i t i o n of 24 rows x
o Up to 8 b a c k g r o u n d colours
40 characters w o u l d g i v e the same r e s o l u t i o n . These
character p o s i t i o n s on the screen w o u l d be addressed by
o Hardware s c r o l 1 i ng
a page memory, so it w o u l d be 960 bytes long to d e f i n e
40 x 24 character p o s i t i o n s .
o Sound g e n e r a t i o n of 8 octaves

In the character d i s p l a y system it has to be d e f i n e d how

128 frequencies for each octave
many different characters on the screen s h o u l d be p o s s i b l e .
W i t h a m a x i m u m of 256 characters t h i s is represented by
o Noise g e n e r a t i o n - 8 ranges
8 bits.
o V o l u m e control for sound and noise -
The page memory was 960 l o c a t i o n s l o n g . In t h i s memory
it is d e f i n e d , w h i c h of these 256 characters is where.
16 steps each
It means that it has to be 8 bit wide.
o Chroma Luma generation on c h i p

o Clock s i g n a l for CPU provided

All features are under software control.

 82 83

Each character has a size of 6 x 8 b i t s , w h i c h m e a n s

256 characters need
4.1. F u l l CMOS
256 x 6 x 8 = 12K b i t s or 2K byte
The whole system has to be in CMOS in order to
offer the t r a d i t i o n a l CMOS advantages : in parti-
So for cage memory IK is needed, for the character memory
cular the p o s s i b i l i t y of battery operation,
a further 2K.
which offers low power and wide power supply
range.
Memory c o m p a r i s o n :

4.2. M i n i m u m component count

Bi t map Character map
8K byte 3K byte
The system has to be optimized for package count
for the complete system, not only for the video
This comparison looks even better for a system that needs
s i g n a l generation.
less than 256 characters, for 128 characters it w o u l d change
from 3K to 2K.
4.3. Minimum memory
Another reason to look at character m a p p i n g is for example As discussed before, the bit map approach needs
in terminal applications. To have a character on the screer
a large amount of memory. To m i n i m i z e t h i s , the
it is only necessary to store one byte in page memory; for
character map method has to be chosen, but if
bit m a p , we w o u l d have to write all the bits a g a i n and
possible at least parts of the bit map advantages
again for any character. Even in games there are fixed
should be i ncluded .
characters for objects, w h i c h can be represented by a set
of fixed characters and the motion capability of the charac-
4.4. Completely independant I/O
ter approach is much faster.
The CPU has only to be i n v o l v e d in changing the
4. DESIGN GOALS
memories or updating internal registers of VIS
and s h o u l d not be stopped during d i s p l a y time
RCA's system was developed after e x a m i n a t i o n of both methods.
(as is necessary with a conventional DMA approach).
The f o l l o w i n g needs lead automatically to the design approac This a l l o w s full CPU processing time for other tasks.
chosen.
 84
4.5. M a x i m u m r e s o l u t i o n via RF
Since the system has to be used for general
a p p l i c a t i o n s and s h o u l d not be restricted to
h i g h r e s o l u t i o n d i s p l a y s a m a x i m u m has to be
found for best v i d e o b a n d w i d t h usage.
4.6. Programmable resolution
A h i g h r e s o l u t i o n is needed to d i s p l a y l a r g e
amounts of data. E d u c a t i o n a l a p p l i c a t i o n s use
a lower r e s o l u t i o n because the d i s t a n c e between
screen and observer is greater.
4.7. G r a p h i c s and m o t i o n c a p a b i l i t y
Many a p p l i c a t i o n s w i l l need o n l y the d i s p l a y of
a fixed character set, but the p o s s i b i l i t y of smooth
m o t i o n on the screen has a l s o to be i n c l u d e d for
a p p l i c a t i o n s requiring an "animated" display. Even
semigraphic pictures should be a l l o w e d.
4.8. External synchronisation
A p p l i c a t i o n s in TV need the p o s s i b i l i t y of o v e r l a y i n g
the v i d e o s i g n a l of the t e l e v i s i o n and VIS in order
to d i s p l a y , for e x a m p l e , t i m e and c h a n n e l or receive d
text i n f o r m a t i o n .
4.9. Col our
The d i s p l a y of c o l o u r or at l e a s t of different s h a d e s
of grey is a m u s t in many a p p l i c a t i o n s . The system
has to be a o p l i c a b l e to both c o l o u r systems PAL and
NTSC; i n a d d i t i o n t h e d i r e c t colour i n f o r m a t i o n i n
RGB should be a v a i l a b l e .
85
4.10. Audio generation
Many applications need a programmable sound. This
is particularly true for the games area, but also
in the industrial area it is useful to have special
sounds for different alarms; even for a terminal
several tones could allow audible prompts.
DESCRIPTION OF THE CIRCUITS
In order to i n c l u d e most of the external hardware
( m u l t i p l e x e r s , colour generation...) it was necessary
to choose a 2 c h i p s o l u t i o n , w h e r e the CDP1869 s o l v e s
the address m a n i p u l a t i o n and the CDP1870 the v i d e o
s i g n a l generation (an a l t e r n a t i v e v e r s i o n of the COP
1870, the CDP1876, p r o v i d e s RGB l o g i c outputs in p l a c e
of c h r o m i n a n c e and l u m i n a n c e ) .
CDP1869 (see figure 1) address g e n e r a t i o n and a u d i o
5.1.
The CDP1802 M I C R O P R O C E S S O R has an e i g h t bit m u l t i -
p l e x e d address bus and generates two t i m i n g p u l s e s
TPA and TPB, to d e f i n e the presence of the h i g h
and low byte r e s p e c t i v e l y . Therefore an 8 bit
l a t c h (1) is needed on c h i p to keep the h i g h byte
and i m p l e m e n t an i n t e r n a l 16 bit address bus.
The control c i r c u i t (2) recognizes s p e c i a l instruc-
tions to set r e s o l u t i o n , sound and n o i s e , c h a n g e
memory a d d r e s s i n g , character scanning, provide
control s i g n a l s for m e m o r i e s and data bus buffer.
The s e l e c t i o n of these instructions is done via
the three I/O s e l e c t i o n s of the CDP1802; it a l s o
generates a decoded select s i g n a l for the CDP1870.
 87
86

I
b) Envelope generator for sound
The address m u l t i p l e x e r (3) decides which information
goes to the address lines of the page memory. During A 4 bit R - 2R - ladder network with a latch
defines the a m p l i t u d e of the sound s i g n a l .

i
d i s p l a y time it selects the character positions on
the screen (PMA 0...9) and scans the character lines
(CMA 0...2). During n o n - d i s p l ay time the CPU memory c) Noise generator
bus is directly connected to the page memory and it
appears as an extension on the CPU memory fixed at E i g h t ranges of white noise are provided. The
F800 to FFFF. As only 960 bytes of t h i s memory result is an e x p l o s i o n type sound effect useful
are used (max 40 x 24) in a IK system 64 bytes are i n TV game systems.
free for stack or other purposes.
d) E n v e l o p e generator for noise
The address counter (4), either defines the p o s i t i o n s on
A 4 bit R - 2R - ladder network w i t h a latch

m
the screen,or is used for character RAM l o a d i n g during
n o n - d i s p l a y time.
The home address register (5) defines the leftmost
character of the first l i n e on the screen. If it
5.2.
is set to 0000 the d i s p l a y shows an unshifted image
of the page memory contents. Loaded w i t h m u l t i p l e s
of 40 it a l l o w s l i n e by l i n e s c r o l l i n g . In the low
resolution (20 x 12) it w o u l d a l l o w the d i s p l a y of
4 different pages on the screen.
The sound and noise generator (6) consists of 4
different parts :
a) Sound generator
It is d e s i g n e d as a three bit prescale r and
a seven bit down counter that are loaded via
a command byte from the output s i g n a l and are
a u t o m a t i c a l l y loaded w i t h the same byte a g a i n .
The r e s o l u t i o n is 3 octaves and 128 different
frequencies w i t h i n each octave.
defines the a m p l i t u d e of the noise s i g n a l .
Sound and noise s i g n a l s can be m i x e d as needed.
CDP1870 (see figure 2) video s i g n a l generation
The control section (1) p r o v i d e s s i g n a l s for the
data bus m u l t i p l e x e r to a l l o w character memory
access from the C P U , latc h s i g n a l s for the control
i n s t r u c t i o n , and s p e c i a l s i g n a l s to synchronize
CDP1869 and CDP1870.
One i n p u t is used to switch the internal l o g i c
from PAL standard to NTSC s t a n d a r d .
The data bus m u l t i p l e x e r (2) is needed for character
memory access, if it is in R A M . It has an 8 bit w i d e
i n p u t . Six bits (CDB 0...5) are used for character
(dot) information (a character l i n e is 6 dots long).
The next two bits (CCBO, CCB1) are used for charac-
ter c o l o u r bit information.

^

W i t h these,4 colours out of 8 are defined per
character l i n e . Another i n p u t l i n e (PCS) is
the page c o l o u r bit and expands the colour
c a p a b i l i t i e s to 8 c o l o u r s and is n o r m a l l y
connected to the page memory (see figure 3).
If character memory is in R A M , it has to be
i n i t i a l i z e d after power o n. W i t h t h i s m u l t i p l e x e r
the character memory is switched to the CPU d u r i n g
non-di splay time .
6.
The dot o s c i l l a t o r (3) p r o v i d e s the clock for the
t i m i n g generator (4). Here nearly all the s i g n a l s
for synchronisation are generated. A special
s i g n a l ( P r e d i s p l a y ) t e l l s t h e C P U that o n e d i s p l a y
l i n e later the m u l t i p l e x e r s are switched and a
refresh cycle starts. Connected to the interrupt
s i g n a l it can d e c i d e between u p d a t i n g the VIS and
w o r k i n g on other parts of the program. In t h i s way
the CPU does not waste time in w a i t i n g for the end
of the d i s p l a y refresh.
Some other s i g n a l s are needed to synchronize the
two c h i p s , for e x a m p l e , increment page memory counter.
The dot frequency is about 5.6 MHz. T h i s s i g n a l is
d e v i d e d by two and may be used as c l o c k frequency for
the CPU.
V e r t i c a l and horizontal t i m i n g appears on COMPSYNC.
The p a r a l l e l to s e r i a l shift register (5) latches
one l i n e of a character and shifts it out to the
l u m i n a n c e and chrominance l o g i c (6) where the dot
information i's combined with the colour information
of the character.
89
COMPSYNC, L U M I N A N C E and C H R O M I N A N C E are combined
outside the c h i p and g i v e a complete v i d e o s i g n a l .
There are two bond options of the CDP1870. For
a t e r m i n a l or b u i l t in TV game it would be useless
to h a ve the complete colour v i d e o s i g n a l and sepa-
rate it afterwards. In t h i s case the CDP1876 should
be used, colour l u m i n a n c e and c h r o m i n a n c e are repla-
ced by RED G R E EN and BLUE.
EXAMPLE OF A CRT T E R M I N A L
A complete system w h i c h could be a game or a terminal is
shown in figure 3. It uses a CDP1804 (1) as processor, a
one c h i p d e v i c e with RAM and ROM on it,or is replaced by a
CDP1802 w i t h seperate RAM and ROM. The CDP1869 creates
sound and noise through the a m p l i f i e r (3) and addresses
the page memory (4) with PMA0...9 (character p o s i t i o n on
the screen), scans the l i n e s of the character memory with
CMA0...2, and generates some s i g n a l s for buffer or RAM
selection; also it gets s i g n a l s for synchronization from
CDP1870 (7).
The page memory (4) is l o a d e d and read t h r o u g h the buffer/
separator (5) .
The character RAM (6) feeds character data bits (CDB) and
colour bits (CCB) to the CDP1870 where the colour and sync
s i g n a l s are generated.
One crystal is needed for dot generation (DOT) and provides
the clock for the CPU. P r e d i s p l a y s i g n a l s if VIS refreshes
the screen or CPU can t a l k to VIS memories.
The second crystal is used for the colour burst.
 90
91
C h r o m i n a n c e , l u m i n a n c e and synch p u l s e s are c o m b i n e d
and t h i s s i g n a l is connected to a, m o n i t o r or a m o d u l a t o r .

OUT 5 programs
Another d e v i c e , the CDP1871,a keyboard encoder .scans the
key contacts and is used as i n p u t .
W h i t e noise range
W h i t e noise a m p l i t u d e
7. INSTRUCTIONS TO CONTROL CDP1869 AND CDP1870
R e s o l u t i o n (12 or 24 l i n e s )
Page length (960 or 1920 characters)
The CDP1802 CPU has a special feature to output i n f o r m a t i o n .
R e s o l u t i o n (6 x 8, 6 x 16 in NTSC, 6 x 9 in PAL)
An i n t e r n a l register is specified and loaded with the address NTSC or PAL system
of the byte to be sent. This feature is used to programme
the VIS devices.
OUT 6 selects

For the CDP1869, whic h is only connected to the address bus

o A fixed address for page or character memory access
the address itself is the information - it does not use the
data.
OUT 7 enables

For the CDP1870, the data at the memory location specified

by this register is the information. o Set home address register for s c r o l l i n g

8. SOFTWARE SUPPORT
One i n s t r u c t i o n (OUT 3) controls the COP1870 (8 bits) for
The most time-consuminq after-design task is n o r m a l l y to
o Resolution (20 or 40 characters)
set up a l l the necessary software m o d u l e s to m a n i p u l a t e
o Character colour control the data on the screen.
o Character format control
o D i s p l a y on or off
For this reason RCA provides a VIS I N T E R P R E T E R . It consists
o Background colour d e f i n i t i o n
of a 3K program w i t h 86 different s u b r o u t i n e s that can be
c a l l e d via a one byte instruction. It i n c l u d e s memory
Three instructions (OUT 4...7) control the CDP1869
m a n i p u l a t i o n as well as colour definition, setting of
OUT 4 sets sound and noise p l u s all other control i n s t r u c t i o n s. In
a d d i t i o n the interpreter permits interruption for the
o Octave execution of m a c h i n e code subroutines.
o Frequency w i t h i n the octave
9- H A R D W A R E SUPPORT
o Sound a m p l i t u d e
o Sound on and off
RCA produces a l i n e of "MICROBOARDS" - board - level micro-
computer products.
 CD -«. fD
o 3
fD CD fD « -a
—' "O l/i T3
—< -s
<<
_•. 0.0
rt
^-
n>
CU ft) Q.
CD O t/>
—• o
92CM-31906
FIGURE 1
 DOT_
BUS 0-BUS 7 \L XTAL
©-© \>
i <<^CDBO — CDB5)
CDB50 DOT
CCBO©) /I DATA A—
< CCBO CCBIJ) BUS
CCBI0 MUX ^l
' . »
PCS (? ) ' r>
CMSELffi r' 1 I— DBO— OB7
||
¥ CHROMINANCE NTSC CHROM(BLUE)*
CIRCUITS
\E AND . ^-*@ PAL CHROM(GREEN)*
VDO-6S
*RGB BOND-OUT OPTION
92CM-3I9IIRI
FIGURE 2
92CM-3I907RI
FIGURE 3
 97
96
CDP1802 M I C R O P R O C E S S O R IN TELEPHONES

The a b i l i t y of microprocessor based systems to a l l o w one

design with software program changes to meet d i f f e r i n g
functional requirements r a p i d l y and without need for
changes to the integrated c i r c u i t combined with the
practical f e a s i b i l i t y of system e x p a n s i o n are features
and benefits attractive to many system a p p l i c a t i o n s .

A microprocessor realized in CMOS technology combines

these benefits with those of very low power consumption
and low voltage operating c a p a b i l i t y . In a sub set
a p p l i c a t i o n a CMOS microprocessor a l l o w s operation of
the telephone l i n e current d u r i n g d i a l l i n g and "on hook"
for number storage and other functions e.g. clock. This
e l i m i n a t e s the need for a mains power supply w h i c h g i v e s
savings in space, cost and i n s t a l l a t i o n time.

Conceptually the system d e s i g n proposed is m o d u l a r so as

to a l l o w e x p a n s i o n from a m i n i m u m system offering for
example : repertory d i a l l i n g , repeat-last-number to a more
complex sub set with a d d i t i o n a l functions for e x a m p l e :
clock, timer,LCD d i s p l a y and cost of c a l l .

The d e s i g n assumes the use of a "key b l o c k " for d i a l l i n g

and offers either pulse output d i a l l i n g as a direct output
from the microprocessor or DTMF (Dual Tone) d i a l l i n g uti-
l i z i n g the RCA CMOS DTMF device CD22859. A n a l o g u e c i r c u i -
try for l i n e i n t e r f a c i n g , r i n g i n g etc. are independent of
. the microprocessor system.

In this system, the key block decoding and DTMF control

are performed u s i n g a complex input/output CMOS device, the
CDP1851.
 98
99
A l t e r n a t i v e decoding methods ,for example the one u t i l i z e d in
the m i n i m u m system ; are p o s s i b l e and have to be optimized for
a specific d e s i g n .
Performance Characteristics
The LCD d i s p l a y in the demonstration u n i t uses 4 x CD4056 • : ' '
d e v i c e s ; a l t e r n a t i v e d r i v i n g d e v i c e s for productio n designs
are p o s s i b l e e.g. the RCA CA22105.

A timer d e v i c e , the CD4536, is u t i l i z e d in the clock or cost- a) Program length 600 bytes
of-call function : it s i m p l y generates an interrupt with the
appropriate time period which activates' a programmed clock b) RAM size 128 bytes
routi ne.
c) O p e r a t i n g frequency 1MHz n o m i n a l
This system can be further extended by a d d i t i o n a l I/O and Can be reduced to 50KHz
memory d e v i c e s to perform extra functions such as intercom. in i d l e c o n d i t i o n (off
hook)

d) Power c o n s u m p t i o n 2 mA at 5V/lMHz
200 m i c r o a m p s at 5V/50KHz

e) Quiescent consumption 5 microamps at 2.4V

RCA has d e v e l o p e d several techniques for r e d u c i ng the opera-

ting and quiescent power consumptio n w h i c h are not u t i l i z e d
in the d e m o n s t r a t i on set. These i n c l u d e :

Automatic frequency reduction in i d l e state

System clock removal

Power switch-off for ROM

FUNCTIONS
. Keyboard d e c o d i n g Intelligent Telephone
Demo Unit
. P u l s e of DTMF
. Repeat last number
. Repertory d i a l l i n g
10 numbers/15 digits
. Cloc k 4 d i g i t LCD
. Timer or cost of c a l l
Gi-
rt)
3
cr
0>
CD
I-* w> O-
CTl O-
O
O- -h
cr
td 70 tD
O
in
0>
 I
102 103

LED I N T E R F A C E

16 BIT OUTPUT As one memory location or as one output

The CDP1802 transfers the address as two bytes : h i g h
byte and low byte. T h i s feature a l l o w s a 16 bit data
transfer from register to a 16 bit o u t p u t port. In
t h i s case not the data is used as i n f o r m a t i o n but the
address,or better the contents of one of the registers.
It is done via an o u t p u t i n s t r u c t i o n .
N o r m a l l y , the CDP1802 addresses the memory via the
X-register and the data stored at t h i s l o c a t i o n is
stored in one of 7 o u t p u t d e v i c e s .
But in t h i s case, the port on the data bus does not e x i s t .
O n l y the a d d r e s s bus is l a t c h e d means h i g h byte u s i n g TPA
and low byte u s i n g TPB. As ' c h i p e n a b l e ' the N l i n e s
used together w i t h MM. REF. ICAN-6562 "Register Based O u t p u t "
To have a LED interface to the Microprocessor system,
many p o s s i b i l i t i e s can be used. One e s p e c i a l l y easy
to use is h a v i n g a shift register as one output port.
As the data is transferred from memory directly to I/O
only a sequence of output instruction s are necessary to
transfer any number of data to t h i s output.
Connected to d r i v e r s any segment c o n f i g u r a t i o n can be
d i s p l a y e d . Each byte can be connected to decoder c i r -
cuits to use each byte as two d i g i t s .
With 4 CD4015, 4 LED d i s p l a y s can be addressed d i r e c t l y .
This c h a i n can be expanded to any number and h a s , compared
with m u l t i p l e x i n g , the advantage that once transferred the
are data i s stabl e.

CDP1802

TPA ADDRESS BUS JTRT TPB NX D A T A BUS

r
CL CJT CS2 CL TT5T CS2 CL CS2
MODE MODE MODE
1 2
CDP1852 CDP1852 CDP1852 L O G I C D I A G R A M OF CD4015

IT
A D D R E S S BUS
HIGH B Y T E
ADDRESS BUS DATA BUS
LOW BYTE OUTPUT
 105
104
D-A-CONVERSION
"DD

KFSTT

tt
2 Very often a s i m p l e a n a l o g o u t p u t is needed and the reso-
l u t i o n of 5 % w i l l be e n o u q h . In a lot of the cases even
speed is not the most i m p o r t a n t feature . U n d e r these
c o n d i t i o n s , a very cheap a n a l o g interface is p o s s i b l e ,

DB7 c o m p l e t e l y i n CMOS.
CD4015
One CD4508 8 bit l a t c h or 2 CD4076 4 bit l a t c h together
OB6
with some resistors are needed.

N Q7
CLOCK
CD4508 Q6
DBS TPB
or Q5
CD4015 2 x ANALOG
OB4 CD4076 Q4 OUTPUT
DATA or
CDP1852
Q3

Q2
SIMPLE D/A C O N V E R T E R
DB3 Ql WITH
CD4015
VOLTAGE FOLLOWER
OJ

This c i r c u i t can be used either as I/O as shown here or with

a different s e l e c t i on l o g i c - it is also s u i t a b l e for memory
space.
CD4015
For h i g h e r resolution and different l e v e l s a CD4054 is used
instead to p r o v i d e l e v e l s h i f t i n g (See ICAN-6289).

O U T P U T C I R C U I T S FOR A 4 D I G I T LED D I S P L A Y U S I N G ONE OUTPUT If this 8 bit converter is "expanded" to a 9 bit converter,
I N S T R U C T I O N A N D SHIFT R E G I S T E R S where the highes t bit never changes, the output v o l t a g e changes
between 0V and VQ D . 2 ,this means even s i n g l e supply is possible .
 106 107
A-D-CONVERSION

2. UP-DOWN-COUNTER

A n a l o g to d i g i t a l c o n v e r s i o n can be a c h i e v e d the same way

Here the counter l o o k s at the EF l i n e and counts up
as u s i n g the D/A converter and compare it with the a n a l o g
or down d e p e n d i n g on h i g h or low.
i n p u t . Four a n a l o g i n p u t s c a n b e b u i l t t h i s way, u s i n g t h e
EF l i n e s as i n p u t to the M i c r o p r o c e s s o r . In a m i n i m u m data
3. SUCCESSIVE A P P R O X I M A T I O N
a q u i s i t i o n system the Q l i n e w o u l d send the s e r i a l i n f o r m a-
tion (using the UT4 routines) to a central u n i t .
The D to A v a l u e works l i k e a w e i g h i n g s c a l e and puts
the o u t p u t to h a l f if b i g g e r a d d s the next (quarter)
uunn t i l done 8 t i m e s .
TPA Q

ETT 0
ADD * ~ ^^-il- a. Set output to half scale 1000 0000
ANALOG
• • "ET2 e b. If b i g g e r , store in a r e g i s t e r . otherwise substract
ROM INPUTS c. Try w i t h 0100 0000
CDP1833 Wfe FFI e
^*.^*L d. Then w i t h 0010 0000
e e. 0001 0000
3ATA EF4
^^th f. 0000 1000
CPU LATCH
CDP1802 ™j AND g-
h.
0000 0100
0000 0010
D/A
k. 0000 0001

T h i s system shows the feature of the CDP1802 to work c o m p l e -

So after e i g h t times,the whole conversion is done.
tely w i t h o u t R A M , as i n t e r n a l r e g i s t e r s can be used for
But with this system the analog input has to be stable
stori ng.
d u r i n g the conversion period, otherwise "out of range"
could happen.
Different a l g o r i t h m s are p o s s i b l e for t h i s type of A to D
converter u s i n g software :

1. COUNTER

The software counter starts at 00, and increments and

outputs t h i s to the l a t c h . As the EF l i n e s c h a n g e , the
v a l u e is reached and stored in one h a l f of a free regis-
ter.
 108 109

CA3162
Another approach would be to connect the CA3162 completely
A three d i g i t A/D interface for COSMAC to the data bus via an i n p u t port CDP1852.
T h i s c i r c u i t , together w i t h one CD4016 quad transmission
gate lets the CDP1802 understand a n a l o g i n p u t s w i t h an ROM RAM CPU INPUT A/D
accurracy of 3 d i g i t and a conversion rate up to 96Hz. PORT
ADDRESS CDP CA
The i n p u t range is +999mV to -99mV and an extra o v e r r a n ge 1852 3162 ANALOG
indication is b u i l t in. DATA INPUT
•• S E R I A L OUT
_L
TPA ^
ANALOG
ADD FFI INPUT
CPU S U B R O U T I N E TO I N P U T DATA IN M E M O R Y
ROM CDP1802
CDP1833 MTJ CD CA return to c a l l i n q program
4066 3162 set up memory pointer
for i n p u t of data
4FFO

F i g u r e 1 : M i n i m u m Interface
set X pointer to 8
get d i g i t
select MSD
wai t for 1ow
LSD comes next
so 2 x INC
i:•|j i :j i
ri i nput
select bi t
w a i t for it
-<3> point to NSD now
get word
look for b i t
w a i t for bit
p o i n t to
a free l o c a t i o n
9ICL- JMtSRI
EXIT go to E X I T

COMPLETE PANELMETER
FOR I N T E R F A C E WITH uP
 110 Ill

SIMPLE CONTROL INTERFACE for CDP1802

W i t h m i n o r program changes it can use interna l registers

as memory locations, this is possible as the input instruc- The COSMAC Microprocessor CDP1802 has an internal oscillator
tion stores data in M (R(X)) and in the D-reg-tster. that works with a crystal connected between CLOCK and XTAL
t e r m i n a l s . If desired, however, an external o s c i l l a t o r may
be used and fed into the CLOCK i n p u t . If an external o s c i l -
lator is used, no connection is required at the XTAL terminal.
(Note : care must be taken not to load the 'XTAL) . Any type
. . S u b r o u ti ne to i n p u t data in registers of s i n g l e - p h a s e clock may be used so long as the rise and
E X I T : SEP 5 .. Go back to c a l l i n g program fall times of the clock p u l s e are less than 15 microseconds.
MSD: INP 4 .. Get the 7 1 i n e s of CA3162 Each m a c h i n e cycle consists of e i g h t clock p u l s e s , and each
ANI #80 .. Look only at b i t 7 [instruction requires two or three m a c h i n e cycles. T h u s , with
BNZ MSD .. Wait for 1ow a 6.4MHz clock frequency, a machine cycle of 1.25 microseconds
PLO 9 .. Store in low h a l f of R9 could be a c h i e v e d , and instructions would be executed in 2.5
LSD: INP 4 .. Next d i g i t to 3.75 microseconds d e p e n d i n g on the i n s t r u c t i o n.
ANI #20 .. Low d i g i t comes faster
BNZ LSD .. W a i t for 1ow During normal operation, the CLEAR and W A IT l i n e s are both
PLO 7 .. Store it in low h a l f of R7 held h i g h . A low level on the CLEAR l i n e w i l l put the machine
NSD: INP 4 .. Now NSD into the reset mode with I,N,X,P,Q, Data bus = 0, and IE = 1.
ANI #40 .. Mask bit 6 A c t u a l l y , X,P, and R(0) are reset d u r i n g a s p e c i a l SI cycle
BNZ NSD .. Wai t for 1ow (not a v a i l a b l e to the programmer) i m m e d i a t e l y f o l l o w i n g tran-
PLO 8 .. Store i n low h a l f of R8 s i t i o n from the reset mode to any of the other modes (load,
BR EXIT .. Branch to exit run, or pause). The clock must be r u n n i n g to effect this
cycle.

The informatio n is stored in R7, R8, R9. If the C L E A R and WAIT l i n e s are both h e l d low, the m a c h i n e
enters the load mode. T h i s mode a l l o w s i n p u t bytes to be
This subroutin e exits with a SEP5 i n s t r u c t i o n , means it s e q u e n t i a l l y loaded i n t o memory b e g i n n i n a at M(OOOO). I n p u t
can be c a l l e d via SCRT. bytes can be s u p p l i e d from a keyboard, tape reader, etc...
by way of the DMA f a c i l i t y . T h i s feature p e r m i t s d i r e c t
The memory l o c a t i o n s used are : program l o a d i n g w i t h o u t the use of external "bootstrap "
programs in R O M ' s .
4FFO MSD
4FF1 NSD If the W A I T l i n e is b r o u g h t low (with CLEAR h i g h ) , the CPU
4FF2 LSD stops operation cleanly on the next negative-going transi-
tion of the c l o c k (Pause mode). O u t p u t s i g n a l s are h e l d at
For more i n f o r m a t i o n see data sheet CA3162. t h e i r v a l u e s i n d e f i n i t e l y . T h i s state is u s e f u l for several
Purposes .
 112 113

Another c i r c u i t that can be used for s i n g l e - s t e p o i n q the

Microprocessor (one m a c h i n e cycle per switch depression)
U s i n g the WAIT l i n e , the CPU can be e a s i l y s i n g l e - s t e o p e d
is shown in F i g u r e 2. This capability is often useful
for d e b u g g i n g purposes or, if stopped early in the m a c h i n e
cycle, the CPU can be held off the data bus to allow for as a d e b u g g i ng a i d .
m u l t i p r o c e s s o r systems, etc... A l s o , the WIT l i n e can be
Figure 3 provides a summary of the modes d i s c u s s e d , the
used as a data ready s i g n a l from a slow memory or neriphe-
control l e v e l s , and the characteristic features of these
ral , or s i g n a l s TPA and TPB can be streched. When the WAIT
modes. It is e v i d e n t that the run mode can be entered
l i n e is returned h i g h , the m a c h i n e resumes r u n n i n g on the
next negative-going transition of the clock input. The WAIT from either the reset or the pause mode.
s i g n a l does not i n h i b i t the o n - c h i p crystal o s c i l l a t o r . DMA' s
and Interrupts are not acknowledged in the Pause mode. For more information, see MPM 201 page 70.

F i g u r e 1 shows one c i r c u i t u s i n g standard d e v i c e s from the

CD4000 series for c o n t r o l l i n g the run and load modes of the
CDP1802. Note the power-on reset feature. For d e s i g n d e t a i l s ,
refer to ICAN-6581 "Power-On Reset/Run C i r c u i t s for the RCA
CDP1802 COSMAC Microprocessor". To l o a d and start a program
the sequence of operations w o u l d be as f o l l o w s : first, depress
the reset and then the load buttons. The CPU is now ready to
load by means of the DMA c h a n n e l . When l o a d i n g is c o m p l e t e d ,
d e p r e s s i n g the reset and then the run buttons w i l l start pro-
gram execution at M(OOOO) with R(0) as the program counter
(after one m a c h i n e cycle). If a DMA request is present when
the run switch is turned on , the m a c h i n e w i l l go into the
DMA state i m m e d i a t e l y with R(0) as the program counter. The
user s h o u l d therefore i n h i b i t DMA e x t e r n a l ly u n t i l the pro-
gram has changed to a program counter different from R(0).
Interrupts, however, are d i s a b l e d u n t i l the first instruc-
tion or DMA request is executed. T h i s delay a l l o w s the pro-
grammer to p l a c e i n s t r u c t i o n 71 and 00 in the first two memo-
ry bytes to i n h i b i t interrupts u n t i l he is ready for them.
The combined effect of the two bytes is to set IE = 0. Inter-
rupts must not occur, however, when the m a c h i n e is in the load
mode because they w i l l force the m a c h i n e into an anomalous
running state.
 115

UNDERSTANDING THE CDP1851 P R O G R A M M A B L E I/O

Qyervi ew

The CDP1851 is a general purpose p r o g r a m m a b l e I/O d e v i c e ,

h a v i n g 20 I/O p i n s w h i c h may be used in several different
modes of operation. (See t a b l e 2).

The I/O l i n e s are grouped into two sections, A and B, each

h a v i n g 10 l i n e s ; 8 data and 2 h a n d s h a k i n g l i n e s (ready and
strobe).

In essence, the CPU programs the PIO by asserting the oroper

Fiiqure 1 : S i m p l e Control Interface
of CDP1802 Microprocessor
address (if memory m a p p e d ) or the proper N - l i n e code (if I/O
mapped) on the PIO control l i n e s , and outputs a sequence of
control bytes on the data bus to the control register of the
PIO. The control bytes c o n t a i n information to d e f i n e port
mode, interrupt e n a b l e / d i s a b l e , I/O bit a s s i g n m e n t , bit
m a s k i n g , etc... (See codes A - P , T a b l e 1).

The CPU transfers data bytes to and from each port by asser-
ting codes S, T, U or V, g i v e n in T a b l e 1. Modes may be
combined so that their functional d e f i n i t i o n can be tailored
wv—o to almost any I/O requirement.

Figure 2 : C i r c u i t for S i n g l e - S t e p p i n g the CDP1802

Modes of Operation
MODE CLEAR WAIT OPERATION
RESET 0 1
a. Norma l Input/Output Mode
1, N, X, P - 0, R(0) - 0, Q " 0, BUS - 0,
IE - 1 ;TPA and TPB are suppressed;
CPU in SI.
RUN 1 1 CPU starts running one machine cycle after Ports A and B can be separately programmed to be 8 bit
CLEAR is released. Execution starts at
M(OOOO), or an S2 cycle follows if DMA
i nput or output parts w i t h h a n d s h a k i n g control l i n e s ,
was asserted. Internal sampling of interrupt
is inhibited during initialization cycle.
ready and strobe.
RESET 0 1 As above.
LOAD 0 0 CPU in IDLE. An I/O device can load memory
without "bootstrap" loader.
PAUSE 1 0 Clock:J t_±L stops internal operation.
CPU outputs held indefinitely. Permits
stretching of machine cycle to match slow
devices or memory cycles. DMA and
INTERRUPTS not acknowledged.
RUN 1 1 Clock :_J—*_ _ -T^_
Resume operation

Figure 3 : Thruth Table for Mode Control

 116
b. B i - D i r e c t i o n a l Mode
Port A can be programmed to be a b i - d i r e c t i o n a l port.
T h i s c o n f i g u r a t i o n provides a means for c o m m u n i c a t i n g
w i t h a p e r i p h e r a l d e v i c e or structure on a s i n g l e 8 bit
bus for both transmitting and r e c e i v i n g data. H a n d s h a k i n g
s i g n a l s are p r o v i d e d to m a i n t a i n proper bus flow d i s c i -
p l i n e . The h a n d s h a k i n g l i n e s for port A are used in the
normal m a n n e r for i n p u t control. The h a n d s h a k i n q l i n e s
for port B are used by port A for o u t p u t control ; conse-
q u e n t l y , port B I/O l i n e s must be in the bit programma-
b l e mode where h a n d s h a k i n g is not used.
c. B i t - p r o g r a m m a b l e Mode
Ports A and B can be separately bit programmed so that
each i n d i v i d u a l l i n e can be d e s i g n a t e d as an i n p u t or
o u t p u t 1i ne.
An a d d i t i o n a l feature of the bit p r o g r a m m a b l e mode is that
the four h a n d s h a k i n g l i n e s , A R D Y , A STROBE, B R D Y , and B
STROBE can be i n d i v i d u a l l y p r o g r a m m ed as i n p u t or o u t p u t
l i n e s (See code K, T a b l e 1).
In t he i n p u t , o u t p u t , an d b i - d i r e c t i o n a l m o d e s th e STROBE
l i n e s g i v e the PIO the t r i g g e r s i g n a l s needed to generate
i n t e r r u p t requests. However, i n t h e b i t p r o g r a m m a b l e mode
the h a n d s h a k e l i n e s are not used to carry strobe and ready
s i g n a l s , but carry I/O d a t a if p r o g r a m m e d to do so.
Interrupt
I n t e r r u p t requests are generated d i f f e r e n t l y d e o e n d i n g on the
port mode.
117
Input and Output Modes
The f a l l i n g edge of the strobe p u l s e from the p e r i p h e r a l
d e v i c e sets the INT l i n e , and the r i s i n g edge of TPB,
d u r i n g the requested read or write operation resets the
INT s i g n a l .
E H - D i r e c t i o n a l Mode (Port A only)
Set and reset of i n t e r r u p t requests are done as e x p l a i n e d
in t h e i n p u t a n d o u t p u t modes. However, since t h e A I N T
l i n e is used for both i n p u t and output interrupts the CPU
must read the status register to d e t e r m i n e what c o n d i t i o n
caused the i n t e r r u p t request.
c. B i t - P r o g r a m m a b l e Mode
Interrupt requests can be generated by p r o g r a m m i n g the PIO
to re-act to s p e c i f i e d l o g i c f u n c t i o n s (AND, OR, H A N D , or
NOR) on selected I/O l i n e s . The CPU m u s t i s s u e two control
bytes; the first w i l l select the l o g i c c o n d i t i o n , and the
second w i l l c o n t a i n m a s k i n g i n f o r m a t i o n i n d i c a t i n g w h i c h
bit(s) of e i g h t the PIO w i l l m o n i t o r for the l o g i c c o n d i -
tion. The INT signal w i l l exist w h i l e the logic c o n d i t i o n
is present. (See codes I & J, T a b l e 1).
Interrupt E n a b l e / D i s a b l e
To e n a b l e or d i s a b l e the INT l i n e s in all modes, the CPU
m u s t i s s u e a control byte for each port (See codes L M N &
P, TABLE 1). A and B i n t e r r u p t status can be read from
bit DQ and D, of the status register to d e t e r m i n e w h i c h TNT
l i n e is c a u s i n g the request if they are wired together (OR'd)
 118
a, Input Data Transfer
Refer to i n p u t port sequential t i m i n g d i a g r a m . Assume
an I/O mapped I/O system s i m i l a r to Figure 1. The peri-
pheral presents data to the I/O port and outputs a strobe
p u l s e to the PIO. The strobe pulse causes three t h i n g s
to happen :
1. The READY s i g n a l is reset i n h i b i t i n q further trans-
m i s s i o n from the p e r i p h e r a l .
2. The i n p u t data is latched in the buffer register.
3. The TFT l i n e is set low s i g n a l l i n g the CPU to read
the data.
The A and B TIT l i n e s of the PIO may be wired to the TWT
pin on the CPU to s i g n a l program i n t e r r u p t s, or they can
be wired to separate IT p i n s where p e r i o d i c p o l l i n g of the
FF p i n s is required to check for service requests.
In either case, the program w i l l branch to a subroutin e
and execute an i n p u t i n s t r u c t i o n (INP6 or INP7, see codes
S & T, T a b l e 1) w h i c h w i l l assert the proper code on the
RAO, R A 1 , and CS p i n s of the PIO. The PIO w i l l p l a c e data
onto the system bus so it can be used by the CPU and/or
written into memory.
The TPB p u l s e that occurs d u r i n g the WR~ p u l s e terminates
the interrupt request and sets the R E A DY l i n e , i n d i c a t i n g
to the p e r i p h e r a l that the PIO is ready to accept a new
data byte.
119
Output Data Transfer
Refer to output port sequential t i m i n g diagram. Assume
an I/O mapped I/O system s i m i l a r to example 1. A strobe
pulse from a p r e v i o u s output sequence or a dummy strobe
causes the INT to go low s i g n a l l i n g the CPU to output a
data byte to the PIO.
The PIO INT l i n e can be wired to the CPU INT pin or an
FT pin as e x p l a i n e d in i n p u t data transfer above. The
program w i l l branch to a subroutine and execute an out-
put instruction (OUT6 or OUT?) w h i c h w i l l assert the
proper code on the RAO, RA1, and CS p i n s of the PIO.
Data w i l l be read from memory and placed on the bus and
latched into the port buffers on the t r a i l i n g edge of
the TPB. The READY l i n e is also set at t h i s time. The
peripheral w i l l transmit a strobe p u l s e i n d i c a t i n g the
reading process is completed. The r i s i n g edge of the
strobe p u l s e causes the READY s i g n a l to reset, and the
f a l l i n g edge sets the interrupt request s i g n a l l i n g the
CPU to output another data byte.
Data Transfer, B i t - P r o g r a m m a b l e Mode
The CPU loads a data byte to the 8 bit port as in the
normal output mode. I/O l i n e s programmed as outouts
w i l l accept and latch data b i t s , however, I/O l i n e s
programmed as i n p u t s w i l l ignore the l o a d e d data (See
code H, U, and V of T a b l e 1).
The CPU reads the 8 bit port as in the normal i n p u t mode.
I/O l i n e s are n o n - l a t c h i n g and therefore i n p u t data must
be stabl e w h i l e the CPU reads. All 8 I/O l i n e s are read
whether they are programmed as i n p u t l i n e s or outout l i n e s .
Data read from the l i n e s programmed as outputs w i l l be
data b i t s l a t c h e d d u r i n g the l a s t outpu t cycle (See codes
H, S, & T, T a b l e 1).
 120
Examplas
Example 1 - S i m p l e I n p u t / O u t p u t Mode
Figure 1 shows an I/O space I/O system i n v o l v i n g the 1802
C P U , the 1851 PIO, and two p e r i p h e r a l d e v i c e s both with hand-
s h a k i n g . The TNT l i n e s are i n d i v i d u a l l y connected to FF l i n e s
1 and 2. Therefore, the CPU is not truly interrupted but must
p o l l t h e f l a g l i n e s p e r i o d i c a l l y d u r i n g t h e m a i n program.
Step by Step - Refer to flow chart for e x a m p l e 1
1. To begin using this system the device must be cleared
w h i c h a u t o m a t i c a l l y programs both port A and B to the
i n p u t mode.
2. Port B is set to the o u t p u t mode by l o a d i n g the control
register w i th control byte g i v e n in code D.
3. Port A i n t e r r u p t l i n e is e n a b l e d by l o a d i n g control byte
g i v e n in code L, T a b l e 1.
4. Dummy read port A to raise the ready l i n e .
5. Port B i n t e r r u p t l i n e is e n a b l e d by l o a d i n g control byte
g i v e n in code M, T a b l e I. Now the m a i n program can b e g i n
runni ng.
6. Some time d u r i n g or at the end of the main program the EF1
flag is polled. If it is true the program w i l l branch to
a subroutine to read port A. The CPU must output the pro-
per N - l i n e ' c o d e to read A. (See code S T a b l e 1, and i n p u t
port t i m i n g diagram). When this step is completed the flag
is a g a i n p o l l e d to check for more i n c o m i n g data.
121
7. If EF1 is false then EF2 is c o n s i d e r e d . If EF2 is true
then the program w i l l branch to a subroutine to load port
B w i t h data. The CPU m u s t output the proper N - l i n e code
and p l a c e the 8 bit data word on the bus. (See code V,
Table 1 and output port timing diagram). When this step
is completed the CPU returns to the m a i n program.
8. If EF2 is false the CPU returns to the m a i n program.
E_x_am_pjj: 2
F i g u r e 2 shows an I/O space I/O system i n v o l v i n q the 1802
CPU, the 1851 PIO, and two peripheral devices. Peripheral A
has a b i - d i r e c t i o n a l bus w i t h h a n d s h a k i n g c a p a b i l i t y for trans-
m i t and r e c e i v e . P e r i p h e r a l B has a 4 bit receiver and a 4 bit
>' transmi tter.
Effort A w i l l be programmed for b i - d i r e c t i o n a l mode with inter-
rupt c a p a b i 1 i ty.
Port B w i l l be p r o g r a m m ed for bit programmable mode with inter-
,'rupt c a p a b i l i t y for o u t p u t data when a l o g i c NOR ( a l l (O's) occurs
(on the 4 i n p u t l i n e s .
Pri ori ti es w i l l be as follows :
1. Port A input data, via interrupt and subroutine
2. Port A output d a t a , via i n t e r r u p t and s u b r o u t i n e
3. Port B outpu t d a t a , via i n t e r r u p t and s u b r o u t i n e
4. Port B i n p u t data, part of m a i n program.
Port A is used to interface with a b i - d i r e c t i o n a l device, there-
fore the h a n d s h a k i n g l i n e s A R E A D Y and A STROBE are used for
:ontrol of i n c o m i n g data (from p e r i p h e r a l to CPU). B R E A D Y and
STROBE handshaking lines are used for output control (from CPU
to peri pheral).
 122
Port B is used in the bit p r o g r a m m a b l e mode h a v i n g b i t s BO, B l ,
B2 and B3 as outputs (data from CPU to p e r i p h e r a l ) and b i t s B4,
B5, B6 and B7 as i n p u t s (data from p e r i p h e r a l to CPU).
The proper c o d i n g of the CPU N - l i n e s w i l l select whether the
data w i l l be read in, or written out to the P I O , or whether
the status r e g i s t e r is to be r e a d , or whether the control
register is to be loaded w i t h a control byte. (See T a b l e 1).
Step by step
1. To b e g i n u s i n g t h i s sytem the d e v i c e must be cleared w h i c h
a u t o m a t i c a l l y programs both port A and B to the i n p u t mode.
2. S i n c e port A is g o i n g to be the b i - d i r e c t i o n a l mode, port
B must be programmed in the bit p r o g r a m m a b l e mode. Port B
is set to the bit mode by l o a d i n g control byte g i v e n in
code G, T a b l e 1.
3. Code H control byte must be l o a d e d , T h i s byte determines
w h i c h b i t s are input/output.
4. Code I control byte must be loaded w h i c h determines the
l o g i c a l c o n d i t i o n of b i t s required to generate an interrupt
request from port B (in t h i s case a NOR c o n d i t i o n ) .
5. Code J control byte must be l o a d e d . T h i s byte t e l l s w h i c h
of the 8 b i t s in port B are monitored and w h i c h are masked
for interrupt generation. (In t h i s case a l l of the i n p u t
l i n e s B4, B5, B6 and B7 w i l l be monitored).
6. Now port A is set to b i - d i r e c t i o n a l mode by l o a d i n g code
E control byte.
7. Port A interrup t l i n e is enabled by l o a d i n g the control
register with code L control byte.
123
8. A RDY is raised ( i n p u t sectio n of port A h a n d s h a k i n g
l i n e ) by d o i n g a dummy read.
9. Port B i n t e r r u pt l i n e is e n a b l e d by l o a d i n g the control
register w i t h code M control byte. Now the m a i n program
can b e g i n r u n n i n g .
10. Port B w i l l be read p e r i o d i c a l l y as the m a i n program repeats
i ts 1oop .
11. W h e n an i n t e r r u p t request is receive d by the CPU it w i l l
branch to a s u b r o u t i n e , and a u t o m a t i c a l l y d e - a c t i v a t e the
i n t e r r u p t e n a b l e to i n h i b i t further i n t e r r u p t i o n s .
12. The CPU m u s t read the status register by o u t p u t t i ng the
proper N - l i n e code R. The statu s r e g i s t e r w i l l c o n t a i n
information d e s c r i b i n g w h i c h interrupt has occurred A and/
or B, and also i n d i c a t e whether 1 I NT was caused by an
i n p u t or an output demand from p e r i p h e r a l A.
NOTE that A INT and B INT l i n e s are wired (OR'd together
(See Fi gure 2) .
13. Several d e c i s i o n s w i l l be made based on the i n f o r m a t i o n
contained in the status register.
14. To read port A the CPU must output the proper N - l i n e code S.
15. To load port A w i t h data the CPU must output the proper
N - l i n e code, and p l a c e the 8 bit data word on the bus
(See T a b l e 1).
16. To load port B (bits BO, Bl, B2 and B3) w i t h data the CPU
must output the proper N - l i n e code, and p l a c e the 4 bit
data on the bus (See Table 1).
17, Once the interrupt subrouti nes are completed the CPU returns
to the m a i n program and the interrupt e n a b l e (CPU) is acti-
vated.
 124 125

*
CLEAR
NO
CLEAR
*
INPUT PORT SEQUENTIAL TIMING* RAO A RDY XMIT ENABLE
N1 RA1 A STROB XMIT STROBE
N2 CS
f 8 *T~PERIPHERAL
TPA
MRD RD/WE AO _J(^ DATA A

TPB
u
•—» WR/RE
TPB
A;y

B RDY
B STROB
8 8

DATA READY
SAMPLE AK
VDD
1802 1851
BO
1
<10K -RECVR
2
3 .,., —. ^

INT A INT 4 PERIPHERAL

CB INT 5
-XMITTER
6
BUSO-7 BUS B7

J I J I
SYSTEM DATA BUS J
TO MEMORY
[NORMAL PROG)C-* READ PORT- -)( NORMAL PROG •

•I/O SPACE I/O F i g u r e 1 : Hardware For E x a m p l e 1

OUTPUT PORT SEQUENTIAL TIMING*

STROBE

READY

I/O LINES >^^° DATA OUT/

i
INT CLEAR
* CLEAR
NO |K RAO
BUS ^/////////////////////////^NLm vtxnJW/////////////////////////////\ n \\ „
^ N1 », RA1 A RDY
N2 fe CS A STROB PERIPHERAL
TPB

TPA n1 / n n„
TPA ». CLOCK AO
8 •«
A
MRD RD/WE A7
'MRD | " TPB . . _ „ . . . j_. fc WR/RE
MRD 'MRD
VDD ^ TPB
MWR 1802
1851

RAO, RA1, CS LINES I VALID CODE | BRDY

SO FETCH V///////////4 10K< <10K B STROB PERIPHERAL
STATE
BO B
NORM. PROG](-> «"3( NORMAL PROG - •• ,1 8 •-
ITT A INT B7
•I/O SPACE I/O EF2
BUS 0 - 7

SYSTEM DATA BUS

tO MEMORY

Fi gure 2 : H a r d w a r e For E x a m p l e 2
 126 127

F L O W C H A R T FOR E X A M P L E 1
F L O W C H A R T FOR E X A M P L E 2

START

CLEAR

PROGRAM PORT B
TO BIT MODE
SET PORT B TO
OUTPUT MODE
DEFINE WHICH BITS
ARE IN/OUT

PICK LOGIC COND.

FOR INT GEN.
READ PORT A
<IGNORE DATA)

MASK BITS

PROGRAM PORT A
TO BIDIRECTIONAL

ENABLE A INT

READ PORT A
(IGNORE DATA)

ENABLE B INT

MAIN
PROGRAM

READ PORT B
 128 129

TABLE 1

CO
P R O G R A M M I N G CODES cn
CO
4-1

•H O CO ft
PH 4-1
ca cu 0) E>. 3
00 >-. .a oo rH O
G Td O G "^J T3 ^t
CM t-> •H Cd VH a> co
o
PL, cO
<U 4-1
Crf O]
QJ
OH cn
4-J ^
cd M
4-J
i 3
§ T)
O
DATA BUS 4-1^0 « -H cn
3 cc
i- o ^ ~-~ cn 3 cfl PJ H >
ft "~0 00 -H 3
CODE DESIRED ACTION u a 2i 1 07 De 05 04 03 D2 DI Do G 0 T3 ft
A SET PORT A TO INPUT MODE 1 0 1 O 1 0 O X O 1 X I 1 W o pa P-. -H •rH

B SET PORT B TO INPUT MODE 0 1 O 1 o o x i o x i i

O 1 X O 1 X I 1 I a> CO
C SET PORT A TO OUTPUT MODE O 1 O 1 4-1
D SET PORT B TO OUTPUT MODE O 1 O 1 O 1 X 1 O X 1 1
30 |
'BB CO
cO ft
3

E SET PORT A TO BIDIRECTIONAL 0 1 O 1 1 0 X 0 1 X I 1 CO 3 > -H 01 E>> 3

(PORT B MUST BE IN BIT MODE FIRST) ft QJ ,Q rH rH O
PQ •H G H ,0 T) rH
i i x o i x i i PH H CO 4-J ft O CO Q) CO J-i
F SET PORT A TO BIT - PROG MODE 1 0 1 0 1 4-» 4-1 O
G SET PORT B TO BIT - PROG MODE 1 1 X 1 O X 1 1 CO cd 4-J CO ft cO at B S T3
0 1 0 1 o 4-1 4-J 4J ,ra JJ Cfl cn
PH cd QJ 3 Cd QJ M
H I/O BIT ASSIGNMENT (A OR B) 0 1 0 1 (0 = INPUT, 1 'OUTPUT) P U OP -U to 00 00 -H 3
U 0 T.1 ft
1 SET LOGICAL CONDITION FOR O 1 O 1 0 De D5 D4 D3 1 O 1 K G C
INTERRUPT GENERATION (BIT - MODE) S rH ft PH -H •rH
t t LOGICAL CONDITION
(D3) O = PORT A, 1 - PORTS 0 0 NAND
(04) O = NO MASK, 1 = MASK BYTE O | OR
CO
FOLLOWS NEXT 1 O NOR CO 4-1

G M CO 3
1 1 AND •rt O CO ft
1 PH 4J
J SET MASK ING OF BITS I 0 1 O 1 (0 = MONITORED. 1 = MASKED) >• 3
< 00 QJ D OO i—I O
(PRECEEDED BY CODE 1) G E^,^ 4-J G < 13 rH
4-1 •H -5"0 T3 0 3 -H QJ cd
K SET RDY AND /OR STROBE LINES 1 O 1 O 1 D7 D6 D5 D4 03 D2 D! 0 CN cO In CO VH ft X -*-1 o
O cd 0) 4J Q) 4-J G CO VH
TO I/O LINES (BIT - MODE ONLY) erf cn M ,£ o cd -H CO
CO cn PH 4J
(Dl) O = PORT A, 1 = PORT B (D5) STROBE LINE OUTPUT DATA TO BE LOADED -a 00 -H 3
G o -a ft
(D2) O = NO CHANGE TO RDY LINE (De) RDY LINE USED AS cd G
FUNCTION, 0 = INPUT LINE EC M CM -H •H

1 = CHANGE PER BIT De I = OUTPUT LINE

(D3) 0 = NO CHANGE PER BIT 07 (Dy) STROBE LINE USED AS CO
4-1

1 - CHANGE PER BIT D? O = INPUT LINE CO 3

I = OUTPUT LINE CO ft
(D4) RDY LINE OUTPUT DATA TO 4-»
CO 4-J U 3
BE LOADED 3 rH O
•H ft T3 rH
L ENABLE A (NT OUTPUT I 0 I 0 I X X X O O O 1 CM 4-1 0) cd
4J H O
M ENABLE B [NT OUTPUT I O I 0 I X X X I 0 0 CO cd cfl 3 CD Q
O 4-1 4-J 4-J ft CO 4-1 --. cd (A
N DISABLE A iNT OUTPUT I O I O I 0 X X X 0 0 0 PH ft cd 4-J -P cn 4-1 4-> r-1 > 4-1

P QJ "O 00 -H 3
P DISABLE B INT OUTPUT I O I O I O X X X 1 O 0 o ft
a *-< C 1H C C
R READ STATUS REGISTER 1 O 1 1 O 07 De 05 D4 03 02 Dl DO
H -H CM •!-* •H

(Do) B~TNT STATUS (1 MEANS SET) \ L

(Dl) AlNT STATUS (1 MEANS SET) /MODES <D4) A RDY INPUT DATA -|
(D?) 1 = AlNT WAS CAUSED BY 1 (D 5>
A STROBE INPUT DATA BIT G !>, Q)
2' B STRODE " 1 BMJi^CT ^ „ my |NpuT DAJA PRMRAMMABLE O -H
0) •H G
T_1 4-J O cd
(D3) 1 = A INT WAS CAUSED BY [ A ONLY (Dy) B RDY INPUT DATA J o U
Q
A STROBE J 0) <}
y ^ cd
S READ PORT A I 1 O 1 0 (INPUT DATA BYTE) 3 ft tJ M 1 00
ft 4-» I O 4J O
T READ PORT B 1 1 1 0 (INPUT DATA BYTE) C 3 -H CM
M PQ PH
U LOAD PORT A 1 O 0 1 (OUTPUT DATA BYTE)
V LOAD PORT B 1 1 1 O 1 (OUTPUT DATA BYTE)
 130
SUBROUTINE PROGRAMMING TECHNIQUES
For p r o g r a m m i n g s u b r o u t i n e s , three m a i n t e c h n i q u e s are used
w i t h the CDP1802 in COSMAC systems :
SEP - Set program counter
MARK - Save old contents of X, P
SCRT - Standard c a l l and return t e c h n i q u e
1. SEP t e c h n i q u e uses the advantages of h a v i n g several
registers, to i n i t i a l i z e some of them, and change the
P p o i n t e r via a SEP instruction to c a l l s u b r o u t i n e s .
The e x a m p l e SEP t e c h n i q u e shows how it is used. After
reset, register 0 is automatically program counter.
Register 7 and register 8 are i n i t i a l i z e d to 0020 and
0030 and then with SEP 7 the PC 0 is changed to PC 7.
As after an instruction the PC is always incremented,
R (3 is pointing now to SEP 8.
As tne P designator is changed to 7 and register 7 has been
loaded with 0020, the code at 0020 is the next one to be
executed. This is a SEQ and sets the Q line h i g h . The
last i n s t r u c t i o n of t h i s " s u b r o u t i n e" is a branch before
the first i n s t r u c t i o n of the s u b r o u t i n e .
As t h i s i n s t r u c t i o n is SEP 0, the s u b r o u t i n e modifies
the P pointer and R 0 is PC a g a i n . The SEP 8 executes
a jump to a subroutine at 0030 u s i n g R8 as program
counter. After coming back to R 0 with SEP 0 a BR LOOP
closes the program loop. W i t h t h i s t e c h n i q u e , no RAM is
needed for subroutine calls and it is very fast (one in-
struction). T h i s t e c h n i q u e is used for example in the
monitor program UT4. It means, there is no need to h a v e
RAM at certain locations (e.g. for stack).
The d i s a d v a n t a g e of this t e c h n i q u e is that subroutines
may c a l l "deeper" s u b r o u t i n e s , there is no free
nesting p o s s i b i l i t y .
131
M A R K t e c h n i q u e overcomes t h i s p r o b l e m , but now RAM is
needed. Now nesting is a l l o w e d to any depth. The M A R K
t e c h n i q u e does the f o l l o w i n g :
MARK (X.P) •T; (X,P)
then P — X; R(2)-
T h i s means in words, that the current contents of the
X,P pointers ( 2 x 4 b i t ) are stored where R2 (stack
pointer) p o i n t s to and in the temporary register T
(for a later save if needed).
After that X is set to P and the stack pointer is de-
cremented to point a g a i n to a free location.
The use of mark t e c h n i q u e a l s o p r o v i d e s another b e n e f i t .
The c a l l i n g program may pass data (parameters) to the s u b -
routine v i a " i n - l i n e " data l i s t s . A n i n - l i n e data l i s t i s
a block of i m m e d i a t e constant data s u p p l i e d by the c a l l i n g
program to the s u b r o u t i n e .
The M A R K t e c h n i q u e works as f o l l o w s :
1. The c a l l i n g program executes a M A R K i n s t r u c t i o n . T h i s
instruction pushes the v a l u e s of X and P onto the stack
pointed to by R(2) and then copies P into X. The current
value of X is now the same as the old value of P. P
remains the same.
2. The c a l l i n g program c a l l s the s u b r o u t i n e via a SEP
instruction to a register that points to the subrou-
tine. The execution of the s u b r o u t i n e then b e g i n s .
3. If the c a l l i n g program has p r o v i d e d i n l i n e parameters
to the subroutine, then the subroutine picks up these
parameters by executing LDXA instructions. T h i s pro-
cedure w i l l load the next parameter to the D register
and a u t o m a t i c a l l y advance the c a l l e r ' s program counter
(R(X)) to the next byte. There should be as many LDXA
 132 133

instructions as there are i n l i n e data bytes. T h u s ,

The CALL is done u s i n g a s m a l l s u b r o u t i n e r u n n i n g in R4 :
the p a s s i n g of data is a c c o m p l i s h e d without the sub-
routine k n o w i n g the old program counter (X designator).
1. It saves the current contents of R6 in RAM on stack (R2).

4., After the s u b r o u t i n e performs its task, it returns to

2. Copies the current contents of R3 in R6.
the caller by setting X to 2, incrementing R(2) (pre-
p a r i n g R(X) for a return), and executing a RET instruc-
3. As two "parameters" the address of the subroutine is
tion. These i n s t r u c t i o n s w i l l load the contents of
loaded and transferred into R3.
memory byte p o i n t e d to by R(2) to the X and P registers.
Processing c o n t i n u e s w i t h t h e c a l l i n g program running
4. The last instruction executes a SEP 3 and the subroutine
w i t h its o r i g i n a l X and P.
starts in R3,
5. Upon return of control from the s u b r o u t i n e to the c a l l i n c
5. Parameter passing is oossible as the address of the c a l l i n g
p r o g r a m , the c a l l i n g program must decrement R(2) to routine is s t i l l in R6.
c o m p e n s a t e for the i n c r e m e n t in the RET i n s t r u c t i o n .
The RETURN is another short s u b r o u t i n e , r u n n i n g in R5 :
3. STANDARD CALL AND RETURN t e c h n i q u e is the most a d v a n c e d
1. Register 6 is put back in R3, as it is the address of
t e c h n i q u e d e s c r i b e d here. It has several a d v a n t a q e s over
the c a l l i n g routi ne.
the p r o c e e d i n g t e c h n i q u e s , they are :

2. X is set to 2 to c a l l back the " o l d " contents of R6 from

1. There is u n l i m i t e d s u b r o u t i n e n e s t i n g c a p a b i l i t y .
stack.
2. There is no c o n f u s i o n over PC a s s i g n m e n t s .
3. Parameter p a s s i n g to s u b r o u t i nes i s w e l l d e f i n e d .
3. An INC is necessary as R2 was p o i n t i n g to a free l o c a t i o n
"below" the two R6 bytes.
SCRT is not w i t h o u t d i s a d v a n t a g e s , however, they are :

4. SEP 3 exits to R3 and the c a l l i n g program is in function

1. A d d i t i o n a l t i m e for c a l l and return.
agai n.
2. It reserves three registers for l i n k a g e .
A l l these three programming techniques
The r e g i s t e r a s s i g n m e n t for SCRT is as f o l l o w s : SEP
MARK
R2 Stack p o i n t e r SCRT
R3 Program counter can be used together and c o m b i n e d as needed as they are
R4 C a l l r o u t i n e PC fully compati ble
R5 Return r o u t i n e PC
R6 R e g i s t e r c o n t a i n s return l o c a t i o n , is used for For further i n f o r m a t i o n , see MPM201, page 54.
parameter passing. ("LINK")
 134 135

• 0600 8001 ..EXAMPLE PROGRAM

• 0008 0062 ..MARK TECHNIUUE
• 0000 8008
• 0800 8884 ..R8 PC AT 80000
• 0000 888b ..R2 STACKPOINTER
000M 0001 • 0000 8886 ..R3 MAIN PC
0008 0002 ..EXAMPLE PROGRAM • 0008 8887 ..R7 SUBI PC
0088 0003 ..SEP TECHNIUUE • 0008 8888 ..R8 SUB2 PC
00146 0004 • 0808 8889
0B08 000S ..USES • 0800 8810 ORG 60888
mm 0086 ..R0 AS MAIN PC • 8800 F84FB2; 0011 INK: LDI 84F;PHI R2 .IN11 STACKPTR
mm 0007 ..R7 AS SUB1 PC • 8003 FBFEA2',' 8012 LDI 8FF;PLO R2
mm 0008 ..R8 AS SUB2 PC • 8606 F888B3; 0013 LDI 808'; PHI R3 .MAIN PC
mm 0009 • 0009 F830A81 0014 LDI 838;PLO R3
mm 0010 ORG 80008 • 080C F88HB7; 00 1b LDI B88;PHI R7 .SUBI PC
mm 800B71 8811 INIT: LDI 800;PHI R7 INIT PROBR • 80HF FiMfiA/1; 8016 LDI B4B',PLO H7
mm 828A7; 0012 LDI «28;PLO R7 PTR FOR SUB1 • 8812 E800B8'i 8B 17 LDI 888; PHI R8 .SUB2 PC
0006 8B0B8; 0013 LDI II001PHI R8 AND PROGRAM • 08 1S F8S8AS; 0018 LDI 8S05PLO R8
830A8 'i 0014 Ll)I U305PLO R8 P1R FOR SUB 2 • 8818 E2; 0019 SEX R2 .FOR MARK
800C 00 1b" • 8019 D31 8820 SEP R8 .GO TO MAIN
000C 8816 ..MA1NPHUGRAM • 08 1A ; 8021
0017 • 801A 1 0022 ..MAIN PROGRAM
000C 71 0018 LOOP: SEP R7 CALL SEU • 081A 1 0023
0001) 0019 SUBROUTINE • 001A ; 0024 ORG 80038
0001) 8; 0020 SEP R8 CALL REU • 0838 C41 082S MAIN: NOP .ANY CODE OF
000t. 002 'i SUBROUTINE • 0831 C4; 0026 NOP .MAINPROORAM
000E 0BC; 0022 BR LOOP BACK TO LOOP • 0832 79; 8827 MARK .SAVE X,P UN STACK
00 10 0023 • 8833 D7; 0028 SEP R7 . 1:ST LEUEL SUB
001 a 0024 • 8834 22; 0029 DEC R2 .COMPENSATE FOR
0(110 B82S5 ..SUBROUTINE 1 • 883S ; 0030 .INCR OF REi-INSIR
0018 0026 • B03S 3830; 003 'i BR MAIN .BACK TO MAIN
0810 0027 ORO 800 IE • 0037 ; 0032
001F D8; 0028 BACK1: SEP R0 BACK TO MAIN • 0837 1 0038 ..SUBROUTINE 1
0020 7B; 0029 ENTRY 1: SEU SET 0 HI • 8837 ; 0084
0(021 F880B9; 0030 LDI 880'iPHI R9 LOAD C'lR REG • 8637 ; 883b ORG B008E
8824 2V, 003 1 TIMER1: DEC P,9 DECR IT • 803E 70; 0036 EX1T1: RET .EXIT TO CALLER
002S 99; 0032 OH1 R9 BET IT IN D • 8048 7B; 8887 SUB1: SEU .SET U HI
0026 3A24; 6038 BN2. TIMER1 BRANCH IF NUT • 8041 C4; 0088 NOP .ANY 01 PIER CODE
8828 0034 YET 880 • 0042 C4; 8839 NOP .OF THIS PROGR
8028 083S BR BACK1 OTHERU13E EXIT • 8843 79; 8848 MARK .X,P SUB1 ON STACK
002A 0036 • 8044 1)8; 084 1 SEP R,T .2:ND LEMEL SUB
002A 8037 • 804S 24; 0042 ,824 .PAR FOR SUB2
002A 0838 ..SUBROUTINE 2 • 8846 22; 0043 DEC R2 .COMPENSATE FOR
002A 0039 • 0847 ; 0044 .INCR OF RET-INSTR
802A 8040 OR6 B082F • 0847 E2; 004b SEX R2 .MAKE SURE X==2
002F 1)8; 0041 BACK2: SEP R0 BACK U! MAIN • 8048 12; 8046 INC R2 .PREPARE FOR RET
0030 7A'i 0042 ENCRY2: RE(J RESET (J • 8049 383F; 8847 BP, EX I'M .BRANCH TO EXJT1
0031 F8FFB9! 0843 LDI SK:',PHI R9 LOAD (MR REG • SB4B ; 8048
0034 29; 0844 TIME.R2; DEC R9 DFCR IT • 8046 ; 8849 ..SUBROUTINE 2
003S 99; 004S GH1 R9 GET IT IN U • 004B ; 0BSB
0036 3A34; 8846 BN/ TIMER2 IF NOT 7ERO llUhiP ^1 8B4B ; BBS 4 ORG B004F
0038 0047 TO TIMER2
8(538 302F; 0048 BR BACK2 ELSE EXI1 •
• 804F 78; 60S2 EXIT2: REI . EXJ. i I U CALLER
883A 0849 END • 80b'B 7A; B0S3 SUB2: REO . RESEl (J
• 0Bbi C4; 00S4 NOP .ANY CODE
• 80b'2 72; BBbb LDXA -GET PAR FROM SUB1
• 08S:>3 E2; 00S6 SEX H2 .MAKE SURE X=2
• 80H4 12; 08b7 INC R2 .PREPARE F'OR RET
• 00b'b 384F"; 00S8 BR EXIT2 .BRANCH TO EX1T2
• 00b7 ; 00S9 END
0080
 136 137

0000 0001
0000 8002 ..EXAMPLE PROGRAM
000 'i ..STANDARD CALL AND RETURN 0000 0003 ..STANDARD CALL AND
0002 ..SUBROUTINES 0000 0004 ..RETURN RUUflNE TECHNIQUE
0000 0003 ..THEY USE SOME REGISTERS 0000 000S . .

0000 0006 ..USES R2,R8,R4, RS

0R00 000B ..R2 BTACKPUINfEK 8000 0007
0000 0006 ..R3 MAIN PC 0000 0008 ORG 80888
0000 0007 ..R4 CALL PC 0000 84EB2 0009 INITs LDI H4E5PHI R2 ..INITIALIZE
0000 0008 ..Rb RE I URN PC 0003 8EEA2 0010 LDI 8FF5PLU H2 ..STACKPOINTER
0060 0009 ..H6 LINK PC 0006 0011
0000 0010 ..ARE IN1TIAI..I7ED 0006 881B4 0012 LDI 88 15 PHI R4 ..CALL PROGRAM C'iR
0000 00 1 1 ..VIA THE MAIN PROGRAM 8009 8E4A4 0013 LDI HE45PI..O R4
0000 0012 „ „
00BC 0014 .«
0000 0018 000C 88 IBS 001S LDI 88 15 PHI RS ..RETURN PROGRAM CTR
0000 B014 008F 8F4AS 0016 LDI 8M5PI..U KB
0000 00 IB ., CALL SUBROUTINE 0012 0017 ..
0000 0016 0012 800B3 0018 LDI 8005PHI R3 ..MAIN PROGRAM COUNTER
0000 80 17 UKG 881E3 00 1S 83BA3 0019 LDI ti3fci;PI..(j R3
81E8 03! 0018 EXIIA: SEP R3 ..EXECUTE SUBROUTINE 0018 0020 ••
81E4 E2; 0019 CALL: SEX R2 ..MAKE SURE X=? 0018 2; 002-1 SEX R2 ..REGISTER 2 STfiCKPUINTER
81ES 96/35 S020 GHI R65SIXD ..STORE LINKP'OINTER 0019 35 0022 SEP R3 ..GO TO MAIN PROGRAM
81E/ 8673; 0021 BLU R65STXD ..ON SIACK 001 A 0028
81E9 98B65 0022 GHI R35PHI R6 ..FREE R3 AND 001 A 0024 .. MAIN PROGRAM
81EB 83A65 0023 GUI R35PLO R6 ..R6 AS PARAMETER PTR 001 A 002S
81 ED 46B35 0024 IDA R65PHI R3 ..GET SUBROUTINE ADDRESS 001A 0026 ORB It0030
81tF 46AS5 (302B LDA-R65PLO R3 ..THAT HAS TO BE CALLED 0030 4; 0027 MAIN! SEP R4 ..GO TO CALL ROUTINE
81F1 3HE35 0026 BR EXIT A ..BRANCH TO EXIT A 0031 040; 0028 , 80040 ..AND GIVE SUBROUTINE
81FS 0027 0038 0029 ..ADDRESS WITH IT
81F3 0028 0033 4! 0030 SEP R4 ..NOU THE SAME
81K3 0029 .. RETURN SUBROUTINE 0034 0S0; 0081 , tiB0S0 ..UITH SIJB2
81F3 0030 0036 030 ; 0032 BR MAIN ..BRANCH BACK TO MAIN
81F3 0031 ORB 88 IF 3 0038 0833
81H3 03! 0032 EXITB; SEP R3 ..RETURN FROM SUBROUTINE 0038 0034 .. SUBROUTINE 1
S1F4 96B3; 0033 RETURN: GHI R65PHI R8 ..LOAD PARAMETER POINTER 0038 003S
81E6 86A3; 0034 GLO R65PIJ1 R3 ..BACK IN MAIN PC 0088 0036 ORG 80040
81K8 E2; 003B SEX R2 ..MAKE SURE X'=2 0040 B; 003? BUB Is SEQ ..SET 0
81F9 •12; 0036 INC R2 ..GO TO STACKED DA (A 8041 55 0038 SEP RS ..AND GO TO RETURN ROUTINE
31FA 72A6; 0037 LDXA5PLC! P.6 ..AND GET R6 BACK 0042
81FC F0B6; 0038 LDX5PH1 R6 ..IN BEFORE F'REED H6 8042 0040 .. SUBROUTINE 2
81HE 38F35 0039 BR EXITB ..AND BRANCH TO EXITB 0PH2 0041
8200 0040 END 8042 0042 ORG B00S0
0000 00S0 'A; 0043 SUB 2s RES ..RESET 0
00S1 I)4; 0044 SEP R4 ..CALL SUB1 ROUTINE
00S2 ^ 10485 004S , 80040
0054 t)S'5 0046 SEP Rb ..AND 60 TO RETURN ROUTINE
80SS 0047 END
0000
 138 139

The h a n d l e r does, of course, introduce an execution-time over-

INTERPRETIVE PROGRAMMING
The manual MPM-201B describes (page 66) a s i m p l e interpretive
t e c h n i q u e w h i c h r e q u i r e s that a l l r o u t i n e s b e g i n a n d e n d i n
the same page of memory. T h i s p a g e r e s t r i c t i o n can be a l i m i -
t a t i o n in c o m p l e x p r o g r a m s , where a more g e n e r a l h a n d l e r opera-
ting over the full memory range is more c o n v e n i e n t . The hand-
ler shown here uses one of the CPU registers (called here "IPC")
as its program counter. R e g i s t e r s "PC" ( m a c h i n e - c o de p r o g r a m -
counter) and "PPC" (pseudo p r o g r a m - c o u n t e r ) are as d e f i n e d in
the a n n u a l .
h e a d , but it s h o u l d be noted that t h i s is s m a l l (19.2 uS at
5MHz) - and is l e s s than one q u a r t e r of the s t a n d a r d 1802 sub-
r o u t i n e o v e r h e a d . It g i v e s a s a v i n g of memory space as w e l l ,
since a subroutine c a l l takes three bytes (the " c a l l " instruc-
tion p l u s t h e 1 6 - b i t a d d r e s s ) w h i l e a p s e u d o - i n s t r u c t i o n needs
only two bytes (the address i t s e l f ) .
References : 1802 User M a n u a l , MPM-201B, " P r o g r a m m i n g
Techniques", page 51.

IEXEC SEP PC pass control to routine

IFETCH IDA PPC
PHI PC i n i t i a l i z e PC . 1
LDA PPC
PLO PC i n i t i a l i z e PC (3
BR IEXEC reset IPC

R e g i s t e r IPC must be i n i t i a l i z e d to the address IFETCH, then

a "SEP IPC" passes control to the h a n d l e r , w h i c h operates a n a l o -
gously to the fetch cycle at machine-code level. When the pseudo-
i n s t r u c t i o n has been fetched, contro l is p a s s e d to it for the
"execute" p o r t i o n of the i n t e r p r e t i v e cycle (execute cycle).

The las t instruction in each routine is a "SEP IPC,", w h i c h

passes control back to the handler for fetching of the next
pseudo i n s t r u c t i o n .

This s i m p l e t e c h n i q u e effectively allows the programmer to

b u i l d a " v i r t u a l m a c h i n e " w i t h an architecture tailored to his
application. Consistent use of t h i s philosophy can lead to
s i g n i f i c a n t b e n e f i t s in program d o c u m e n t a t i o n , 1n ease of m o d i f i -
c a t i o n , a n d speed of d e v e l o p m e n t .
 140 141

DETAILED PROGRAM E X A M P L E
MACRO FOR BCD TO B I N A R Y C O N V E R S I O N
Showing a Traffic L i g h t

In typical Microprocessor systems numerical i n p u t s are This program shows how to use part of the instruction set.
often presented in BCD.but m a n i p u l a t i n g such data can It uses a CDP1852 8-bit output port to switch LED's ON and
be done more efficiently if they are converted to binary and OFF. Two EF flag l i n e s g i v e priority to either m a i n
form. The following short routine for the 1802 performs or secondary road, and the Q l i n e i n d i c a t e s in w h i c h state
a 2 - d i g i t BCD i n p u t from a port and converts the data to the program is :
b i n a r y l e a v i n g the result both in D and on the stack. It
is presented as a macro d e f i n i t i o n w h i c h functions in exactly
a) Normal
the same way as the standard " I N P " i n s t r u c t i o n except that b) A d v a n t a g e (longer green) m a i n road
one of the CPU registers ("WKG") is used for temporary sto-
rage . The i n s t r u c t i o n s used in t h i s program are :
MACRO
B C D I N P %PORT macro name LDI l o a d i m m e d i a t e next byte in D register
INP %PORT i n p u t to D and M (R(X)) PHI RN transfer from D to h i g h byte of RN
A N I 0F;PLO W K G save low d i g i t PLO RN transfer from D to low byte of RN
L D X ; A N I F0;SHR hi d i g i t x 8 GHI RN get h i g h byte of RN and put it in D
STXD;SHR;SHR hi d i g i t x 2 GLO RN get low byte of RN and put it in D
IRX;ADD;STXD hi d i g i t x 10 SEX RN set X pointer to RN (for output)
GLO WKG;IRX;ADD bi nary i n D OUT N o u t p u t from X where RC p o i n t s to OUT N
STXD;IRX and on stack SEP N set P pointer to N (subroutine c a l l )
MEND DEC N decrement register N
WKG = w o r k i n g RAM SEQ set the Q o u t p u t h i g h
PORT = i n p u t port REQ set the Q output low
BR BEGIN branch i m m e d i a t e
BQ LGREEN b r a n c h if Q is set
The o v e r h e a d of t h i s c o n v e r s i o n is 18 bytes of memory p l u s BN1 TEST2 branch if EF1 is not a c t i v e
51.2 uS (at 5MHz c l o c k ) e x e c u t i o n time. If the v a l u e of X BN2 TIMER branch if EF2 is not a c t i v e
is known in a d v a n c e the o v e r h e a d can be reduced to 15 bytes BNZ LOOP b r a n c h if D register is not 00
and 41.6 uS by r e p l a c i n g the "STXD , I R X " p a i r s w i t h s i n g l e
"STR" i n s t r u c t i o n s . D e p e n d i n g on the state of the Q f l i p - f l o p (LED) the program
flow is c h a n g ed between normal green and l o n g green. T h i s
If the program c o n t a i n s many of these c o n v e r s i o n - i n p u t s , the program is not o p t i m i z e d ; its i n t e n t i o n is to show s u b r o u -
r o u t i n e s h o u l d be rewritten as a "SEP"-type s u b r o u t i n e to tine c a l l s , software timers use of f l a g l i n e s , o u t p u t to exter-
save ROM space. In t h i s case the memory overhea d w i l l be nal d e v i c e s . Here one s p e c i a l output -the output i m m e d i a t e - i s
o n l y one byte per c a l l (the SEP i n s t r u c t i o n i t s e l f ) . used. As in t h i s program X and P are the same, the byte just
T h i s is a good i l l u s t r a t i o n of the memory economy o b t a i n a b l e following the output instruction is transferred to the CDP1852.
by use of the 1802's r e g i s t e r - s w i t c h i n q feature.
 142

ItC/fl State
PC-0

Set
RA 8F.OO
RB 60.00
RC 10.00 Sat:
RD 8F.OO Normal Green Main Road
RE FF.OO Red Secondary Road
RF 00.00
Sat: Put RD-»R9
R8 - Add Subr.
Go to Subr. Delay

Sat:
Rod Main Road Branch to Amber
Main Road
Green Secondary Road

Put RA _^R9 (Timer) Sat:

Long Green Main Road
Red Secondary Road

Go to Subr. Delay
PutRE-»R9

Set:
Red Main Road Go to Subr. Delay
Amber Secondary Road

Set:
PutRB _»R9 Amber Main Road
Red Secondary Road

Go to Subr. Delay Put RB-»R9

Set: Go to Subr. Delay

Red +• Amber Main Road
Red Secondary Road
Sat:
Red Main Road Red +
Amber Secondary Road
Put RC ^.R9

Put RC-»R9
Go to Subr. Delay
_L
Go to Subr. Delay

Branch to Start
 145

nc/i?oiid
State

Traffic Lights Diagram s°|id

State

Traffic Detectors

DO

LEO

-M-
-A a
i
n
ROM EF 1 Q N Lines > I/O
< Ad. Bui
TPB
TPA C.P.U.

MWR 1852

1802

Data Bus
 146 147

B8S2 NGKEENs UUT b,H41 ..(JUIPUI FUUR1H BYTE (.Nil

U8by
mm 0001 .. EXAMPLE PROGRAM VD; 00b4 GHI KD
mm 0002 .. TRAFFIC; EIGHT B9! 00bb PHI l(9
mm 0003 DB; 00b6 SEP KH
mm 0004 ..EF1 USED AS SENSOR MAID ROAD
mm 000B ..EF2 USED AS SENSOR SECONDARY 0BS8 BR AMBER . .NUU BRAHLh! TO AHBER
mm 0006 ..(J TO STOKE THE STATE AND SHOU IT 00S9
mm 0007 0060 LGKEENs UUT b,841 . .UOTPLII F O U R l H BYTE £U
mm 0008 URG 80000 ..AFTER RESET RB IS Ft; 0061
mm F88FBA; 0009 I NIT: LDI tt8F!PH| RA ..LOAD DELAY1 IN RA 9Ei 0062 GHI RE ..LUAD MALUE 4B
0003 F80BAA; 0010 LI) I »00;PLO RA BV1 0B63 PHI R9 ..IN K9.1
0886 0011 D85 0B64 SEP R8 ..AND GOTO SUB
0006 F'8S0BB; 0H12 LDI ttb0;PHI RB ..LUAD DELAY2 IN RB 8B6S
0009 F800A85 0013 LDI B001PL.O RB 68245 0066 AMBERS OUT b,»21
0(<i0C 81314 0067
800C F810BC! 001b EDI «10-,PH1 RC ..LOAD UELAY3 IN RC 98? 0068 GHI RB ..LOAD 11HER VALUE S
000F F80BAC1; 0016 EDI KBBlPLO RC B9i 0069 PHI R9 ..IN K9.1
0012 0017 D8l 0B7H SEP R8 ..CALL SUB
0012 E88FBD; 0018 LDI D8FIPHI RD ..LOAD DELAY4 IN RD 8071
001S F800AD; 0019 LDI »BB;PLO RL) 6S0D5 0072 BY1E6: OUT b,13 ..UU'I Pill SIX1H BY IE
0018 0020 0073
0018 FSFFBE; 0021 LDI 8FF;PHI RE ..LOAD DELAY b IN RE 9C! 0074 GHI HC ..LOAD HflER VALUE 6
001B F80BAE; 0022 LDI D005PLO RE B9; 007 b PHI R9 ..IN RV.1
001E 0023 081 0076 SEP R8 . .CALL llflER SUB
00 It F800BF1; 0024 LDI «00;PHI RF ..LOAD DELAY6 IN RF 0077
0021 API 002b PLO KF 3028; 0078 BR BEGIN ..S'lAR'l AtifllN THE PROGRAM
0022 0026 8879
0022 F8B0B8; 8B27 LDI ft.1CSUBKJ;PHI R8 ..SUBROUTINE: ADDRESS IN KB 0B8B
0081
URG 8UBK-1
RETURN: SEP K0
..TIMER SUBROUTINE
..00 BACK TO CALLING PROGRAM
002S F8SSA81 0028 LDI A.01SUBK);PLO K8
0028 0029 8882
0028 0030 BEGIN: SEX R0 ..SET X TO IMMEDIATE MODE 0083 SUBR: DEC R9 ..COUN) DOWN IIMLR
0029 0031 0884
0029 0032 BYTE1: OUT S,H14 ..OUTPUT FIRST BYTE 008b TEST 1: BN1 TEST2 . .U EF1 NUT SE'I Ul.) ON
082B 0033 0886 SEU ..ELSE SEI 0 ILUNG GREEN)
002B 0034 GHI RA ..LOAD TIMER 0087
062C B03b PHI R9 ..IN KEG 9.1 3DSC; 0088 TEST2: BN2 TIMER ..IF EF2 N01 SET GO ON
002D 0B36 SEP R8 ..AND GO TO TIMER 7ft! 0089 HEQ ..ELSE RESET 0 (.NORMAL GREEN'1
802E 0037 0098
002E 6S125 0088 B'IYE2: OUT b,B12 ..OUTPUT SECOND BYTE F8BA1 0091 TIMER: LDI B0A ..LOAD 0A IN
0030 0039 AM 0892 FLO KF ..RF.0
0030 0040 GHI RB ..LOAD VALUE 2 0093 LUOP: DEC RF ..AND COUNT DOUN
0031 0041 PHI K9 ..IN KEG 9.1 8F; 8894 GLO RF ..UET IT IN D AND
0032 0042 SEP R8 ..AND EXECUTE TIMER 3A5F; 009b BN7. LOOP ..IF NUT 00 GU BACK
0033 8043 8096
0033 6S31; 0B44 BYTE3: OUT 5,831 ..OUTPUT THIRD BYTE 0897 GHI K9 ..ELSE LUOK AT R9.1
003S 004S 0098 BNZ SUBK ..AND IF NOT 00 SUBR AGAIN
003S 9C; 0046 GHI RC ..LOAD TIMER VALUE 3 0099
0036 B9; 0047 PHI K9 ..IN KEG 9.1 C000b4; 0100 LBK RETURN ..IF R9.1 IS 00
0037 D8; 0048 SEP K8 ..AND 60 TO SUB 0101 ..BACK 10 CALLING PROGRAM
0038 8049 0102 END
0038 3141; 00SB BO LGKEEN ..DECIDE IF LONGGKEEN
003A 00S 1 ..BRANCH IF tl SET
 149
148

CHARACTER SEARCH ROUTINE CHARACTER SEARCH ROUTINE

SEARCHES LIST OF SIZE 'LENGTH'

AT LOCATION TABLE' FOR CONTROL

A n o t h e r software e x a m p l e i s t h i s search r o u t i n e .
CHARACTER FOUND ON STACK

A table pointer is set up and the contents of this memory A.1 (TABLE)—»-PNTR.1
location is compared with a byte on the parameter stack A.0 (TABLE)—»-PNTR.(J INITIALIZE
SEX PARSTK USE PARAMETER STACK
u s i n g the XOR i n s t r u c t i o n . The new character is loaded @ PNTRI.XOR.O GET AND COMPARE
via PNTR in D-register and XORed with the byte on the BZ FINISH END IF MATCH
parameter stack, therefore, the SEX PARSTC is necessary. PNTR. 0. XOR. A (TABLE + LENGTH) TABLE OVER?
BNZ NWCHAR IF NOT, BRANCH
If it was the searched character, branch to F I N I S H , other- ERROR: PHIPNTR IF SO, FLAG ERROR
wise compare with the end of the t a b l e . If not yet reached, FINISH: DEC PNTR RESET PNTR
SEP RETURN GO BACK
go to N W C H A R , E R R O R means that the end of the tabl e has been END
found but not the character, so the h i g h byte of PNTR is modi-
f i e d , then the r e g i s t e r PNTR is decremented followed by a re-
turn to the c a l l i n g orogram. T h i s program is written for SCRT,as
the return is at the end of the program and the PC for t h i s
s u b r o u t i n e has to be i n i t i a l i z e d , before it can be c a l l e d .
 150 151

MEMORY MOVE ROUTINE

T h i s type o f r o u t i n e c o u l d b e , f o r e x a m p l e > u s e d a s PROM

programmer t o g e t h e r w i t h a m o n o s t a b l e generator to p r o -
gram d i f f e r e n t t y p e s o f E P R O M S , e . g . 18U42, 2 7 U 5 8 . The
monostable streches program e x e c u t i o n using the W A I T line
(see PRO M p r o g r a m m e r ) .
PI
0000 0001 ..3P RCA BXI.
Here i t is used to t r a n s f e r a p r o g r a m f r o m PRO M t o R A M , 0000 BBB2 . .

load the start address and START the program.

mm B803 ..MEMORY MOVK PHOIiRAH
0000 B664
mm sees ..
0000 B0S<S PKO(iAD=»8«00 ..SSTARTADI)
1 UP' MUMf. PROGRAM
The p r o g r a m s t a r t s w i t h PC = 0 and as the p r o g r a m to be mm 0007 BOURCf:=«V00H ,.S'S'(AR'IAI)I) OF SOURCE PROGRAM
e x e c u t e d runs in Rj3 as w e l l , another r e g i s t e r has to be mm B8B8 Dt:8i:i:N=n00H('i . .sSTARTADD
p OF DESTINATION
mm B889 PiAXAI)l>-«V7FF ..H: HIGHEST ADD OF SOURCE PROGRAM
PC f o r the t r a n s f e r program. T h i s is done b y t h e f i r s t 0080 0H1!d b-|ftK'f=80(!ifi1 ..8"S T A R (ADDRESS OF PRCKiRAM
part of the program. 0800 6011 BEB=PRU(iAiJ+7 ..Bl:
BEtilN OP MOVE PROGRAM
0800 0012 PKUUP('=fe ..PI-
PROGRAI'iOUIJhirER REGISTt-R
8008 0013 . ..

The t r a n s f e r program runs in R9. Source and destinatio n mm 00 14 OKI.) PR1.IHAI)

mm BH1S5
pointer are loaded and the t r a n s f e r is done. Then the mm F88B1 001fi 1. 1.) I A . K B t U J ..Lt
LOAD R 9 UITH S T A R T ADD OF MOVE
PROG PC is loaded w i t h the start a d d r e s s and the SEP PROG 8802 BV; 0017 PHI V
8883 F807; 0818 LL)J. A . 0 ( B b u J
PC s t a r t s the transferre d program. 880S A9'i 0019 PL. (.I 9
8806 DV; B820 8EP 9 ..i:if
SET R V AH PROGRAM COUNTER
880? 0021 . ..

8807 F8V0; 00?a BEGs LI.!). A.1(S()UR(,;K:i ,,,Ll

LOAD R A UITH SOURCE
880V Bft5 BB23 PHI A
' 880A E800; BBiM LPJ, A.0lB()URi;F:i
880C AA; 00/i!:i PLiJ A
•. 6801) FB00 ; 9826 Llil ft.1([)KSiriN:i ..L!
.LOAD R H UIlH DPS I .(NATION
'. 880F m; BBS;; PHI H
: 8816 F808 ! B0?8 LDl fl.0(l)tiJl):N.'i
881? A R 5 002V PIJJ H
I 8813 4A1 0030 KtPFA : LI.) A A . . PPICK
: UP A B Y I E AND INC R A
8814 SB; 003 1 :-riR B ..ifS'lORP
1 88 15 1B; 0032 INC H
1 8816 V A ; 0033 (iHI A
8817 FRV8; 0034 XRi A.KIIAXADD.l + l ..tf
881V 3A131 003S BNi K h P I " A I
8H1B H8B0; B0:« l...l.)i A . K b ' I A K ' C l ..Li
8811) 88; B037 PH.I. PKlKiPi:
88 It F801; 083H LDl fl,0(ti[AKi:i
8B»i ft0; 8039 PL (I PRUliPC
8R/M D8" HB4B iitr pRdliPt; . .S
S'lAK'l
1 'I HE '(RANHPP.KKKD PROGRAM
ma. 004 1 END
BH0H
 152 153

DATA BUS CONTENTION D U R I N G CDP1802

WATCH DOG
REGISTER-TO-REGISTER OPERATIONS

By noting the absence of p u l s e s , generated by status repor-

In 1802 based systems u s i n g v a r i o u s R O M ' s (CDP1832, 1834)
or E P R O M ' s (2708, 2758, 2716) bus contention problems have
been found to occur during internal data transfer operations
(GHI, P H I , G L O , PLO). As a r e s u l t , data is lost in one or
more regi sters .
The 1802 generates a v a l i d 1 6 - b i t address and a TPA s i g n a l
d u r i n g i n t e r n a l operations. If the c h i p - s e l e c t s i g n a l for
the ROM or EPROM is only controlled by h i g h e r order address
b i t s , t h e n it is very p r o b a b l e that these m e m o r i e s can be
selected a n d h a v e t h e i r o u t p u t d r i v e r s "turned on", crea-
ting a bus contention problem with the 1802 data bus drivers.
ting statements inserted in a running program, this dual
m o n o s t a b l e generator recognizes if a pulse is m i s s i n g and
r e i n i t i a l i z e s the Microprocessor based system or forces
it to an interrupt, if glitches on the busses or peri-
p h e r a l s stop the program. W i t h the CDP1802 the Q output
f l i p - f l o p can be e a s i l y used to retrigger t h i s monoflop.
A SEQ, REQ i n s t r u c t i o n in the program creates a p u l s e ,
that always retriggers the timer. If the program stops,
the second monostable generates a reset or interrupts the
processor.
r
Cl1 n1
Rl \ ro n o 1 .
V DD

The s o l u t i o n to t h i s p r o b l e m is to e i t h e r gate the c h i p - ll l l

select functions with MRD externally, or find a spare i n p u t / + TRIGGER Q
on the m e m o r i e s for WRO . D u r i n g these r e g i s t e r o p e r a t i o ns FROM TO RESET
MO is h e l d h i g h . (See T a b l e 1 on p a g e 90 of the MPM-201B CDP1802 1/2CD4098 1/2CD4098 OR
Manual). See below for specific suggestions. Q LINE INTERRUPT

A. H i r i n g MRD to a spare i n p u t
DUAL M O N O S T A B L E FOR UATCH DOG F U N C T I O N
o CDP1834 (CS1 or CS2) - only if they are " a c t i v e low"
o 2716, 2732, 1758 (Ol)
The same function c o u l d be a c h i e v e d w i t h counter t i m e r
c i r c u i t s to a v o i d any c a p a c i t o r , u s i n g clock s i g n a l
B. G a t i n g MRTJ e x t e r n a l l y w i t h the c h i p - s e l e c t function
of the processor system (e.g. CD4020).

—l
f H tO.MAI >MA2> A3 |
1
TPA
r
HR6 MET) MAI
| ROM/EPROM

-551 1
MA2.MA3-I
^ess I
-en l
1 I/O J

\7 1
ROU(COPie!!/5l2.»
EPROM <2708/IK«8)
 154
UT4 CMOS ROM M O N I T O R P R O G R A M
A CMOS ROM m o n i t o r program is necessary for a p r o t o t y p i n g
system to have an easy p o s s i b i l i t y to load programs, verify
and start e x e c u t i o n .
One external f l a g and the Q o u t p u t are used for t h i s i n t e r -
face. For a d d i t i o n a l h a r d w a r e , see F i g u r e 1 and F i g u r e 2 ,
it assumes a clock frequency of 2MHz for 100 and 300bd. T h i s
m o n i t o r program does not need any R A M .
It starts at 8000 ( h i g h e s t address bit h i g h ) means after
reset t h i s l i n e has to be set h i g h e x t e r n a l l y to start the
monitor program. (See e v a l u a t i o n kit manual MPM203 or MPM
224, as w e l l M i c r o b o a r d brochures).
After b e i n g entered it i n i t i a l i z e s i t s e l f and w a i t s for CR
or LF. C a r r i a g e return sets it to f u l l d u p l e x and l i n e feed
to h a l f d u p l e x . The answer is the UT4 prompt. T h i s u t i l i t y
program can even work t o g e t h er w i t h a p a p e r tape reader or
punch. For a d d i t i o n a l i n f o r m a t i o n , see MPM224, MPM203.
?M C o m m a n d
To interrogate memory, the user types a command such as
155
A g a i n , if more than four d i g i t s are e n t e r e d , o n l y the l a s t
four are used. T h i s feature a l l o w s the user to correct a
mistake. He s i m p l y keeps t y p i n g , p u t t i n g in the correct
4 - d i g i t v a l u e s (230024 is e f f e c t i v e l y 0024).
!M C o m m a n d
In g e n e r a l , data is entered i n t o memory by m e a n s of a
command such as
!M2F 434F534D4143
T h i s command enters six bytes (two hex d i g i t s each) i n t o
memory b e g i n n i n g at location 2F. It is normally termina-
ted by a CR. Once a g a i n , the s t a r t i n g l o c a t i o n is deter-
m i n e d by the l a s t four d i g i t s e n t e r e d . Data is entered
into memory after each two hex d i g i t s are typed. If the
user types a n od d n u m b e r o f d i g i t s , th e l a s t d i g i t i s
i g n o r e d , and the error message ('?') is typed out.
The !M command p r o v i d e s two o p t i o n s that f a c i l i t a t e memory
loading. F i r s t , a s t r i n g of d a t a can be e x t e n d e d from l i n e
to l i n e by t y p i n g in a comma just before the n o r m a l CR.
(In t h i s case the user m u s t type C R - L F (carriage return-
l i n e feed) before he can b e g i n a new l i n e ) . For e x a m p l e :

?MF5 3 !M23 56789ABC,(CR) (LF)

DEF0123456,(CR) (LF)
and t e r m i n a t e s it w i t h C R ( c a r r i a g e return). UT4 responds
3047 (CR)
by p r i n t i n g out the contents of memory b e g i n n i n g at loca-
tion OOFS: three bytes are p r i n t e d out as two hex d i g i t s
enters 11 s u c c e s s i v e bytes b e g i n n i n g at l o c a t i o n 0023.
each. Each l i n e of o u t p u t b e g i n s w i t h the a d d r e s s , and
Between s u c c e s s i v e h e x p a i r s w h i l e data i s b e i n g e n t e r e d ,
data is g r o u p e d in 2-byte (4-digit) b l o c k s . W h e n neces-
any n o n - h e x character except the comma (and s e m i c o l o n , as
sary, new l i n e s are begun every 16 bytes, with the pre-
w i l l be discussed) is ignored. T h i s a r r a n g e m e n t permits
v i o u s l i n e s e n d i n g in s e m i c o l o n s . The user may enter any
arbitrary LF's, spaces (for readability), n u l l s (generated
n u m b e r of d i g i t s to specify the b e g i n n i n g l o c a t i o n ( l e a d i n g
by the u t i l i t y program or by a time-share system to give
zeroes are i m p l i e d , if necessary). If more than four d i g i t s
the c a r r i a g e time to return), etc...
are entered, only the l a s t four are used. The n u m b e r of
bytes to be typed out s h o u l d be in hex.
 156 157

As a second o p t i o n a l form of data entry, a string of i n p u t

or
data can be terminated by a s e m i c o l o n (and a CR). The
u t i l i t y program then expects more data to follow on the
?P (address) £R
next l i n e , but preceded by a new b e g i n n i n g address. The
l i n e m u s t have the format of an !M c o m m a n d , but w i t h the
UT4 ignores i n i t i a l characters u n t i l it detects ?, !, or 2.
i n i t i a l !M omitted. (The u t i l i t y program ignores all non-
Then, inputs which are not c o m p a t i b l e with the above formats
hex characters f o l l o w i n g !M, w h i c h a l l o w s the CR, LF, and
cause an error message.
n u l l s to be i n p u t from the Teletype w i t h o u t d i s t u r b i n g the
!M command). Note a l s o that the s e m i c o l o n feature on i n p u t
Summary of UT4 operating instructions
a l l o w s n o n - c o n t i g u o u s memory to be l o a d e d .

A further d e t a i l e d summary of these b a s i c operating instruc-

£P Command
tion is g i v e n below, repeating the information just g i v e n in
a more concise form.
A t h i r d u t i l i t y command is jBP. For e x a m p l e

1. After pressing " R U N UTILITY" (start at 8000), the user

2P6C
s h o u l d press either CR or LF: LF for h a l f d u p l e x , CR
for f u l l duplex. This instruction sets up the b i t -
Starts e x e c u t i o n at l o c a t i o n 6C w i t h R0 as the program
serial t i m i n g and specifies echo or not.
counter (after the user presses CR and the u t i l i t y pro-
g r a m p r o v i d e s a LF). The 1 a s t - f o u r - d i gi ts-i n r u l e a p p l i e s
2. UT4 w i l l return * as a prompt.
to the address typed in.

3. F o l l o w i n g *; UT4 ignores all characters u n t i l one of ?,

£P a l w a y s b e g i n s w i t h RjD as p r o g r a m counter and X = 0. This
?, or ! is typed in.
a r r a n g e m e n t is c o n s i s t e n t w i t h the fact that P = 0 and X = 0
after the CPU is RESET. Refer to the CDP1802 data sheet for
4. F o l l o w i n g ?M or !M, UT4 waits for a hex character. It
other actions of RESET.
then assembles an address. If more than four hex d i g i t s
are typed, only the last four are used. Next, a space
Summary of command usage
is required. Note : A denotes a space.
In summary , after r e c e i v i n g the prompt character, '*' the
a. For ?M addr A a hex count must follow (again, only
user may type
the last four d i g i t s are kept), and the command is
terminated by CR.
?M (address) A (count) OR

For !M addr A data must follow. An even number of

!M (non-hex) (address) A (data) ( o p t i o n a l , or ;) CR
(Where the data may h a v e n o n - h e x d i g i t s between each hex p a i r )
hex d i g i t s is required. Before each hex p a i r a r b i -
trary f i l l e r , except for a CR, comma, or s e m i c o l o n ,
is a l l o w e d . CR terminates the command, u n l e s s it is
i m m e d i a t e l y preceded by a comma or, as is generally
the case, by a semicolon.
 158
i. In case of comma CR the user must insert an
LF for UT4 to continue to accept data. T h i s
procedure is a form of line continuation.
ii. In case of a semicolon all following charac-
ters are ignored u n t i l the CR is typed. Then
the user must again provide an LF, and UT4
continues as if it had received o p t i o n a l f i l l e r ,
then a starting address, then a space, and then
data.
iii. The !M command can be followed by as many conti-
nuation l i n e s as needed, m i x e d between the two
types if desired, and is f i n a l l y terminated with
a CR not preceded by a comma or s e m i c o l o n ,
5. Command ?P must be followed by s t a r t i ng address (last
four digits used if more than four are typed in). If
no address is entered, 0 is assumed. Program execution
begins at this l o c a t i o n with R0 as program counter w i t h
X set to 0.
6. W h e n a !M or ?M command is accepted and compeleted, UT4
types another prompt character.
7. When UT4 detects bad syntax, it types out a ? and returns
the carriage. If a mistake is made when data is entered
(by typing in an odd number of d i g i t s ) , all data w i l l
have been entered except the last hex d i g i t . Note that
the " o n l y - l a s t - f o u r - d i g i t s " r u l e in the address f i e l d
allows the user to correct an error without retyping
the w h o l e command. For e x a m p l e , a m i s t a k e n 234 can be
corrected by c o n t i n u i n g 2340235=0235. A bad command
can be aborted by typing in any i l l e g a l character except
after !M or ?M or between i n p u t hex data p a i r s . In
these cases, the user s h o u l d type any d i g i t and then,
for e x a m p l e , a period.
159
UT4 register storage feature
UT4 provides for storing in RAM 13 1/2 of the 16 CDP1802
scratch-pad registers. A CDP1824 32-byte RAM tias to be
provided for this function. The RAM o c c u p i e s addresses
8COO - 8C1F. By pressing RESET followed by RUN U, regis-
ters RO - RF are a u t o m a t i c a l l y stored in the CDP1824, in
numerical order, most significant byte first. RO, Rl, and
R4.1 are altered in the process.
By u s i n g the command
7M8COO 20
The register contents w h i c h existed in the Microprocessor
at the i n s t a n t that RESET was pressed preceding the depres-
sion of RUN U can be examined. It s h o u l d be remembered that
UT4 uses registers RO, Rl, R3, R4. 1, R5, and RC - RF. These
registers, therefore, w i l l be modified. S h o u l d the user wish
to continue program e x e c u t i o n , he must i n i t i a l i z e these r e g i s -
ters, by program if necessary. A sample l i s t i n g is given in
Figure 1. It s h o u l d be r e c a l l e d that RO, Rl, and R4.1 are
not correct.
The b i t serial t e r m i n al interface
The serial t e r m i n a l i n t e r f a c e is an e x a m p l e of m i n i m i z i n g
hardware c o m p l e x i t y by the use of software. F u r t h e r , it
i l l u s t r a t e s the increased f l e x i b i l i t y that can be more
readily a c h i e v e d by software. The CPU receives serial data
by s a m p l i n g ET4. It t r a n s m i t s serial data via its Q output.
Details on the electrical I/O interface are given in the
A p p l i c a t i o n Note e n t i t l e d "Data T e r m i n a l Interface C o n s i -
derations for RCA Microprocessor E v a l u a t i o n Kit CDP18S020.
 160 161

The s a m p l e character waveform in F i g u r e 4 h e l p s to show what

the interface software m u s t do. E a c h character is framed by
a START bit and one or two STOP b i t s . On i n p u t , t h i s s i g n a l
is tied to ET"4~ w h i c h is sensed by UT4 at the m i d p o i n t s of
each of the b i t s . Software a s s e m b l e s the r e s u l t a n t ASCII
character. On output, the character is transmitted one b i t
at a t i me t h r o u g h the Q output of the CDP1802. (See F i g u r e s
2 and 3) .

The f l e x i b i l i t y o b t a i n a b l e w i t h software is demonstrated by The EIA RS232 Serial Data Interface For
the a b i l i t y of the p r o g r a m UT4 to s a m p l e a character s t r i n g C o n n e c t i n g TI S i l e n t 700 Data T e r m i n a l
and adjust its t i m i n g so as to cope w i t h t e r m i n a l s of d i f -
ferent, even n o n - s t a n d a r d , character rates. However, it
s h o u l d be noted that w h i l e a p r o g r am is t i m i n g e i t h e r i n p u t
or output in this manner (i.e., by counting instruction exe-
c u t i o n s ) , it is c o m p l e t e l y d e d i c a t e d to that task and cannot
be interrupted except for an occasional DMA service.

R0 Rl R4.1
7M8COO 20/ / s/
8COO DODO 8202 2222 3333 9444 5555 6666 7777;
8C10 8888 9999 AAAA BBBB CCCC DDDD E E E E FFFF

Figure 1 : Sample L i s t i n g I l l u s t r a t i n g Register Storage

This u t i l i t y p r o g r a m can even work together with a paper

tape reader or p u n c h . For a d d i t i o n a l i n f o r m a t i o n see MPM Figure 3 : The 20mA Current Loop Interface To Connect
224, MPM203. a Teletype In F u l l D u p l e x Mode

Figure 4 :
Data Terminal Bit
Serial O u t p u t For
INTELLIGENCE BITS The Character "M"
- 7 DATA BITS »
PLUS I PARITY BIT

_ COMPLETE CHARACTER _
"M" (40|6>

*-ONE BIT TIME P- PARITY BIT

B • START BIT 0 - DATA BIT
F-STOP BIT -ASYNCHRONOUS TIME
BETWEEN CHARACTERS
 162 163

UTILITY PROGRAM UT4 LISTING

!h
0000 0001 OkG #8000 •T 6004 0048
8000 0002 .. UT4 IS A UTILITY PROGRAM TO ALTER 8004 0049 . . THE FOLLOWING WR
8000 0003 .. MEMORY, DUMP MEMORY, AND BEGIN PROGRAM 8004 0050
.. EXECUTION AT A G I V E N LOCATION. THE COMMANDS . . 8COO-8C1F IF IT
8000 0004
8000 0005 .. ACCEPTED ARE SPHHKH (BEGIN EXECUTION AT THE 8004 0051 . . TO BE RAM ( ELSE
8000 0006 .. SPECIFIED LOCATION WITH RO AS PROGRAM 8004 F88CB1 ; 0052 LDI #8C ;PHI CL . .CL IS CLOBBERED
8000 0007 .. COUNTER), 1MHHHH DATA (POT DATA AT SPECIFIED 8007 0053 . .BY THIS ROUTIINE
8007 81EA1 ; 0054 LDI *1E ;PLO CL . .SET UP WHERE RF.O
oOOO 0008 . . LOCATION), AND ?MHHHh HHHH (OUTPUT DATA 8 0.0 A 00 5 5
. . FROM SPECIFIED LOCATION FOR SPECIFIC COUNT) . . IS TO GO, MINUS 1
BOUO 0009 800A F8AOb4; 0056 LDI #AO ;PHI R4
. . AT THE B E G I N N I N G OF A C O M M A N D ALL C H A R A C T E R S ..R4.1 STORES A MODIFIED
8000 0010 600D 0057 . .INSTRUCTION
800D El ; 0058 SEX CL
8000 0011 .. ARE IGNORED U N T I L A ? , ! , O R S IS 800E F8D051; 0059 LOOP2: LDI #DO ;STR CL ..SET UP SEP INSTRUCTION
6000 0012 .. E N C O U N T E R E D . IN THE ?M AND !M C O M M A N D S WON
8000 0013 .. HEX CHARACTERS ARE IGNORED AFTER M UNTIL A 8011 ; 0060 . .FOR RETURN
8000 0014 .. HEX IS READ, THEM THE FIRST NON HEX 8011 F3; 0061 XOR
.. CHARACTER MUST BE A SPACE . NON HEX . . C H E C K THAT IT WROTE
8000 0015 8012 3A29 ; 0062 BNZ UT4
8000 0016 .. C H A R A C T E R S B E T W E E N HEX PAIRS OF THE DATA IN 8014 21 ; 0063 DEC CL
.. THE !h COMMAND ARE IGNORED EXCEPT FOR CR, ..PREPARE FOR MODIFIED
8000 0017 6015 ; 0064 . . INSTRUCTION
dOOO 0018 .. S E M I C O L O N , AND COMMA. 8015 94FC70j 0065 GHI R4 ;ADI#70 . . S E E IF IT IS IN THE 90°S
sooo 0019 .. THE BAUD RATE OF UT4 IS DEPENDENT UPON THE
sooo 0020 .. T E R M I N A L BEING USED. A CR OR LF IS E N T E R E D 8018 331C; 0066 BDF *+#04
8000 0021 .. AT THE B E G I N N I N G TO SPECIFY THE A P P R O P R I A T E 601A FC21 ; 0067 ADI#21
.. DELAY B E T W E E N BITS. UT4 W I L L ECHO . . IF N 0 . 8 N BECOME S 9N
oOOO 0022 6 0 1C FC 7 F; 0068 AD 1*7 f
.. CnARACI'ERS IF A CK IS CHOOSEN AS THE . . I F Y E S , 9N BECOMES 8 ( N - 1)
8000 0023
8000 0024 .. TIMING C H A R A C T E R . ECHOING WILL NOT TAKE 601E B451; 0069 PHI R4 ;STR CL
.. PLACE IF A LF IS INPUT AS THE TIMING . . SET M O D I F I E D INSTR
SOOO 0023 6020 ; 0070
.. CHARACTER. . . INTO RAM
8000 0026 8020 F3; 0071 X(jR
.. UI4, AT INITIATION, STORES, ALL REGISTERS . CK THAT IT WROTE
8000 0027 8021 3A29 ; 0072 BNZ UT4
8000 0028 .. B E T W E E N 8COO AND 8C1F IF IT F I N D S RAM T H E R E 8023 01; 0073 SEP CL . .GO TO E X E C U T E INSTR
8000 0029 .. (BUT RO, R l , AND R4.1 ARE CLOBBERED). 6024 ; 0074 . . (80-9F)
8000 0030 PTER=*00 . . A U X I L I A R Y FOR MAIN R O U T I N E 6024 51 ; 0075 3TR CL ..STORE R E S U L T IN RAM
8000 0031 CL=*01 ..CLOBBERED 6 0 2 5 2 1 2 1 ; .. 0076 DEC CL ;DEC CL . .BACK UP FOR NEXT BYTE
8000 0032 ST-*02 ..STACK POINTER-ONLY 8027 300E; 0077 BR LOOP2
8000 0033 . . R E F E R E N C E TO RAM 8029 ; 0078
8000 OJ34 SUB=#03 . . S U B R O U T I N E PC 6029 90B5B3; 0079 UI4:GHI RO ;PHI PC ;PHI SUB ..#SO-tPC.1
8000 0035 PC=*U5 ..MAIN PROGRAM C O U N T E R 602C ; 0080 ..AND SUB.1
8000 OOJ6 SwITCt! = CL . . D I S T I N G U S H E S B E T W E E N ?M AND !h 602C F830A5; 0081 LDI A.O(UT4A) JPLO PC
8000 0037 D6LAY = ffOC . .DELA* ROUTINE PROGRAM COUNTER 802F D5; 0082 SEP PC
8000 0038 ASL=lfOD ..HEX A S S Y M B L ^ REG ON INPUT , 6030 E5; 0083 UT4A:3EX PC
6000 0039 ..AUx FOR HEX OUTPUT • 6031 7 1 5 5 ; 0084 D1S, #5 5 NOTE PC-5 ASSUMED
8000 0040 CENTER=ASL ..USED TO C O U N T OUTPUT BYTES • 6033 ; 0085 HERE!
8000 0041 AUX=*OE ..AUX. l HOLDS BIT-TIME CONSTANT • 8033 6101 ; 0086 OUT 1 ,#01 . .SELECT
S RCA GROUP
oOOO 0042 CHAR=*OF ..CKAR.l HOLDS I/O BYTE • 8035 F8FEA3; 0087 LDI A.O(TIMALC) ;PLO SUB ..READ ONE
8000 0043 • 8038 ; 0088 ..TO SET TIMER
8000 0044 .. ENTER IN RO • 8038 D3; 0089 SEP SUB
8000 0045 NOP • 8039 ; 0090
8001 F880BO; 0046 LDI A.KUT4) ;PHI RO ..SET PC WHILE • 8039 ; . 0091 . . . INITIATION NOW D
8004 0047 . . FINGER IS ON • 6039 ; 0092
• 8039 F89CA3; 0093 STAKT:LDI A.O(TYPESD) ;P
 164 165

803C 0094 SEP SUB; ,#OD . . CR-CARRIAGE RETURN 8077 F89CA3; 0141 LUI A.O(TYPE5D) ;PLO SUB . .TYPE
D30D;
803E D30A; 0095 ST2:SEP SUB; ,#OA .LF-L1NE FEED 807A 8 DAI; 0142 GLO ASL ;PLO SWITCH
8040 D32A; 0096 SEP SUB; ,#2A ..* AS PROMPT CHARACTER 807C 9DB1; 0143 GHI ASL ;PHI SWITCH
8042 F800ADBD; 0097 ICNORE:LDI #00;PLO ASL;PHI ASL ..PREPARE TO 807E D30A; 0144 LINE:SEP SUB; ,#OA . .LF
8046 0098 . . INPUT HEX I 8080 90BF; 0145 LINE1:GHI PTER ;PHI CHAR ..PREPARE LINE
8046 ! 0099 . . DIGITS, CLEAR ASL 1 8082 ; 0146 . .HEADING
8046 F83BA3; 0100 LDI A.O(READAH) ;PLO SUB 5 8082 F8AEA3; 0147 LDI A.O(TYPE2) ;PLO SUB
8049 D3; 0101 SEP SUB . . INPUT COMMAND 8085 03; 0148 SEP SUB . .TYPE 2 HEX DIGIT
804A FB24 ; 0102 XRI #24 . . IS IT $ ? .S
804C 32D6; 0103 BZ DOLLAR I 8086 80BF; 0149 GLO PTER ;PHI CHAR
804E FB05 ; 0104 XRI #05 . . IS IT ! ? (TEST WITH S.XOR. ! ) 1 8088 F8AEA3; 0150 LDI A.O(TYPE2) ;PLO SUB
I 8081) D3; 0151 SEP SUB . .TYPE
8050 Al ; 0105 PLO SWITCH . .AND SAVE RESULT 1 808C D320; 0152 SEP SUB; ,#20 . .SPACE
8051 CE; 0106 LSZ . .EQIV. TO BR RDARGS 1 808E ; 0153
8052 FB1E; 0107 XRI #1E . . IS IT ? 808E 40BF ; 0154 TLOOP:LDA PTER ;PHI CHAR . .FETCH 1 BYTE FOR
8054 0108 ..?(TEST WITH $.XOR. ! .XOR.?)
8090 ; 0155 . .TYPING
8054 3A42; 0109 BNZ IGNORE . .IGNORE ALL UNTIL A COMMAND IS 8090 F8AEA3 ; 0156 LDI A.O(TYPE2) ;PLO SUB
8056 0110 READ 8093 D3; 0157 SEP SUB TYPE 2 HEX
8056 0111 8094 21 • 0158 DEC SWITCH
8056 0112 . . THE FOLLOWING IS COMMON FOR ?M AND IM 8095 81 ; 0159 GLO SWITCH
8056 Oil 3 . .(SWITCH. 0 -0 FOR THE LATTER) 8096 3A9B ; 0160 BNZ TL3 B R A N C H IF NOT DONE YET
8056 0114 8098 91 ; 0161 GHI S W I T C H
8056 D3; 0115 RDAKGS:SEP SUB ..NOTE SUB AT READAH. NOW 6099 3239 ; 0162 BZ START B R A N C H IF DONE
8057 0116 . . READ HEX ARCS 809ii 80FAOF ; 0163 TL3 :GLO PTER ;ANI#OF . .IS PTER DIV BY 16
8057 FB4U; 0117 XRI #4D . . SHOULD BE M 809E 3AA6; 0164 BNZ TL2
8059 3ACA; 0118 BNZ S Y N E R R 80AO D33B; 0165 SEP SUB; ,#3B . .IF YES TYPE ; THEN
805B D3; 0119 RD1:SEP SUb 80A2 D30D; 0166 SEP SUB; , # 0 D ..CR AND
805C 3B5B ; 0120 BNF * -#01 ..IGNORE NON HEX CHARS. 80A4 307E ; 0167 BR LINE
805E 0121 . .AFTER M. 80A6 F6; 0168 IL2 :SHR DIV BY 2?
805E D3; 0122 SEP SUb BOA7 338E; 0169 BUF TLOOP IF NO LOOP B A C K , ELSE
805F 335E; 0123 BDF *-#01 . . READ IN FIRST ARC 80A9 30BC ; 0170 BK TLOOP -#02 . . AND THEN LOOP BACK
8061 U124 ..(LOCATIONN IN MEMORY) 80AB 0171
3061 FB20; 0125 XRI #20 ..NEXT CHAR SHOULD BE A SPACE • 80AB 0172 ..THE FOLLOWING DOES(!h LOC DATA) COMMAND
80AB 0173 . .ENTER AT EX1
S063 3ACA; 0126 BNZ SYNERR 80AB 0174
8065 9DBO; 0127 Gril ASL ;PHI PTER 80AB 0175 .'.EFFECT OF THE FOLLOWING IS TO READ IN HEX
8067 8UAO; 0128 GLO ASL ;PLO PTER ..PTER NOW POINTS INTO 8 CAB 0176 . . T E R M I N A T I N G WITH A CR, IGNORING NON-HEX CHARS.
8069 0129 . .USER MEMORY
8069 81 ; 0130 GLO SWITCH . . LOOK AT SWITCH 80AB 0177 . . PAIRS ; EXCEPTIONS: A COMMA BEFORE A CR ALLOWS
806A 32B4; 0131 BZ EX1 . . IF 0 IT WAS !
806C ; 0132 . .OTHERWISE IT WAS ? SOAIi 0178 ..THE INPUT TO CONTINUE ON THE NEXT LINE AND A
806C ; 0133 . .THE FOLLOWING DOES (?M LOC COUNT) COMMAND 80AB 0179 . . SEMICOLON ALLOWS AN !M COMMAN D TO
806C ; 0134 80AB 0180 . .BE ASSUMED.
806C F800ADBD; 0135 LDI #00 ;PLO ASL ;PHI ASL ..CLEAR ASL 80AB 0181
8070 03; 0136 RD2:SEP SUB 80AB D3 ; 0182 EX3:SEP SUB . . INPUT UNTIL A HEX IS READ
8071 3370; 0137 BDF RD2 . . READ IN SECOND ARC
8073 0138 . . (NUMBER OF BYTES) 80AC 3BAB; 0183 BNF EX3
8073 FBOD; 0139 XRI #OD . .NEXT CK FOR CR 80AE ; 0184
8075 3ACA; 0140 BNZ S Y N E R R 80AE D3; 0185 EX2:SEP SUB . .LOOKING FOR SECOND HEX
 166 167

80AF ; 0186 . .DIGIT 80EE 0232 . . E X I T TO UT4

80AF 3BCA; 0187 BNF SYNERR . . BR IF NOT HEX 80EE 0233
80B1 8D50; 0188 GLO ASL ;STR PIER . .**SET BYTE** 80EE 0234
80B3 10; 0189 INC PTEk 80EE 0235
80B4 D3; 0190 EXllSEP SUB . .NOTE SUB AT 80EE 0236
80B5 ; 0191 . . READAH 80EE 0237 ..SUBROUTINES
80B5 33AE 0192 BDF EX2 . . BR IF HEX 80EE 0238
6067 FBOD 0193 XRI #OD . .CHECK IF CR 80EE 0239 . .DELAY ROUTINE
80B9 3239 0194 BZ START 80EE 0240 ..DELAY IS 2(1+AUX.1(3+@SUB) )
80BB FB21 0195 EX4:XKI #21 . . ELSE CK IF C O M M A 80EE 0241 ..USED BY TYPE, READ, AND TIMALC.
80EE 0242 ..AUX.l IS ASSUMED TO HOLD A DELAY CONSTANT
80BD ; 0196 . . (TEST WITH CR.XOR. , ) 80EE 0243 ..-((BIT TIME OF TERMINAL)/
80BD 32AB 0197 BZ EX3 . . IFELSE BRANCH 80EE 0244 ..(20*INSTR TIME OF COSMAC))-!.
80BF FB17 0198 XRI #17 . . CK FOR SEMICOLON(TESI tfiTh 80EE 0245 ..THIS CONSTANT CAN BE GENERATED
80EE 0246 ..AUTOMATICALLY BY THE TIMALC ROUTINE.
80C1 ; 0199 . . C R . X O R . , .XOR. ; ) 80EE 0247
80C1 3AB4 0200 BiiZ EX1 . . IGNORE ALL ELSE 80EE 3; 0248 DEXITrSEP SUB
80C3 D3; 0201 SEP SUB ..ON SEMI IGNORE AL UNTIL CR 80EF EF6AE; 0249 DELAY1:GHI AUX ;SHR ;PLO AUX ..SHIFT OUT
80F2 0250 ..ECHO FLAG
80C4 0202 . . THEN LOOP BACK 4>OF2 E; 0251 0ELAY2:DEC AUX ..AUX.O HOLDS BASIC
80C4 IBOD; 0203 XRI #OD ! 80F3 0252 ..BIT DELAY
80C6 AC3; 0204 BNZ *-#03 80F3 43FF01; 0253 LOA SUB #01 ..PICK UP A CONSTANT
80C8 05B; 0205 BR RD1 . . THEN BRANCH BACK ; 80F6 AF4; 0254 BNZ *-#02 ..LOOP AS SPECIFIED
80CA 0206 . . FOR !M C O M M A N D ' 80F8 0255 ..BY CALL
80CA 0207 80F8 8E; 0256 GLO AUX ..DONE YET ?
80CA F89CA3; 0208 SYNERR:LDI A.O(TYPE5D) ;PLO SUB . . GENERAL 80F9 32EE; 0257 BZ DEXIT
80CD 0209 . . RESULT OF 80FB 23; 0258 DEC SUB ..POINTS SUB
80CD 0210 . . S Y N T A C T I C ERROR 80FC 0259 ..AT DELAY POINTER
60CD D30D; 0211 SEP SUB; ,vOD . .CR ':, 80FC OF2; 0260 BR DELAY2
80CF C081F8; 0212 LBR fSYJEit . .F I N I S H E R R O R M S G ' 80FE 0261
1 80FE 0262 ..ROUTINE TO CALUCULATE BYTE TIME AND ECHO
80D2 ; 0213. 80FE 0263 ..FLAG. tfAITS FOR LF (NO ECHO) OR CR(ECHO)
80D2 ; 0214* ..THE FOLLOWING DOES SP HHHri , 80FE 0264 ..BE TYPED IN. ALSO SETS UP POINTER TO
601)2 ; 0215 ORG #t)OL>6 1 80FE 0265 ..DELAY ROUTINE.
80U6 D3; 0216 DOLLAR:SE£> BUB . . NOTi SUB.O-READAH 80F£ 0266 ..AUX.l ENDS UP HOLDING, IN THE MOST
8UD7 FB50; 0217 XRI #50 . . SHOULD BE P [ 80FE 0267 ..SIGNIFICANT 7 BITS,THE DELAY CONSTANT.
80D9 3ACA; 0218 BNZ SYdEllR 80FE 0268 ..LEAST SIGNIFICANT BIT IS 0 FOR ECHO, 1 FOR
80DB D3; C 219 D1:SEP SUB 80FE 0269 ..NO ECHO
80DC 33DB; 0220 BDF or . . A S S E M B L E HEX 80FE 0270
80DE ; 0221 ..STING INTO ASL 80FE 93BC; 0271 TIMALC:GHI SUB ;PHI DELAY
BODE FBOD; 0222 XRI #OD . .FIRST HONHEX 8100 F800AEAF 0272 LDI #00 ;PLO AUX ;PLO CHAR
80EO ; 0223 ..MUST BE CR 8104 F8EFAC; 0273 LDI A.O(DELAYl) ;PLO DELAY
80)50 3ACA; 0224 BNZ SYNERR , 8107 ; 0274 ..DELAY ROUTINE READY
80E2 9UBO; 0225 GHI ASL ;PHI RO 1.8107 3707; 0275 B4 * ..WAIT FOR START BIT
80E4 8UAO; 0226 GLO ASL ;PLO RO . . SET UP N E X T PC 8109 3F09; 0276 BN4 * ..WAIT FOR FIRST
80E6 F89CA3; 0227 LDI A.O(TYPE5b) ;PLO SUB \B ; 0277 . -NON ZERO DATA BIT
80tl9 D30A; 0228 SEP SUB; ,#OA . . LF 1 810B F803; 0278 LDI #03 . . S E T UP FOR
80EB E5 ; 0229 SEX PC 1 810D ; 0279 ..10 EXECUTIONS
80EC 7000; 0230 RET, #00 . . AND U S E R PROGRA M 810U ; 0280 . . S O ROUND-OFF IS MINIMAL
80EE ; 0231 . . bEGINS (IN RO) | 810D FF01; 0281 TC2:SMI #01
 168 169

810F 3AOD; 0282 BNZ *-#02

GLO CHAR ..LOOK TO SEE 8131 3337; 0329 BDF NFND
8111 8F; 0283
. . IF DATA 8133 FCOA; 0330 ADI #OA
8112 ; 0284
0285 . . C H A N G E D PREVIOUSLY 8135 3387; 0331 BDF FND . . SUB NET 30
8112 ; 8137 FCOO; 0332 NFND:ADI #00 ..SETS DF=0
0286 BNZ Z R O N E . .BR IF IT HAD 8139 9F; 0333 REXIT:GHI CHAR ..CHARACTER INTO D
81 12 3A17 ; 813A D5;
0287 B4 INCR • • ELSE LOO FOR 0334 SEP R5
8114 3719;
0288 . . CHANG E TO 0 NOW 813B F800; 0335 R E A D A H r L D I #00
8116 ; 813D 38;
0289 . . B R A N C H IF NO 0336 SKP ..SKIP OVER TO R E A D 1
8116 ; 813E 83;
0290 INC CHAR - . IF YES SET S W I T C H 0337 READ:GLO SUB ..CONSTANT WITH A VALUE tO
8116 IF;
I 813F C8; 0338 LSKP
0291 ZRONE:B4 DAUX ..LOOK FOR C H A N G E 8140 F801 ; 0339 TTYRED:LDI #01
8117 371E;
0292 . . TO 1 , liR IF YES f 8142 AF; 0340 R E A D 1 : P L O CHAR ..SET ENTRY FLAG
8119 8143 F880BF;
0293 INCR : INC AUX 0341 R E A D 2 : L D I #80 ;PHI CHAR ..INITIALIZE
8119 IE; 8146 ; 0342 . . INPUT BYTE
811A F807 ; 0294 LDI #07 • • SET UP FOR
0295 . . 20 1NSTR. LOOP 8146 ; 0343 . .WHEN SHIFTED 80
811C 8146 ;
0296 BR TC2 0344 . . IS 1 , WILL BE DONE
811C 300D;
811E 0297 ..AUX.O NOW HOLDS #LOOPS IN 2 BIT TIMES
0298 DAUX:DEC AUX ;DEC AUX ..REDUCE C O U N T 8146 E3; 0345 SEX SUB
81 IE 2E2E;
. . TO B A L A N C E 8147 8FF6; 0346 GLO CHAR ;SHR ..DF=1 - t E N T R Y VIA TTYRED
8120 0299
0300 . . FIXED O V E R L O A D
8120 8149 3B4D;
0301 . . IN C A L L I N G D E L A Y 0347 BNF TTY1-#02
8120 8148 6780 ;
0302 GLO AUX ;ORI #01 ;PHI AUX ..LSB A U X . 1 = 0348 OUT 7 ,#80 . .READER ON
8121; 8EF901BE;
814D 3F4D; 0349 BN4 * ..WAIT FOR END OF LAST DATA BIT
.1 I 814F 374F;
0303 SEP RC; ,#OC ..1-5 BIT 0350 TTY1:B4 * ..WAIT FOR PRESENT START BIT
8124 DCOC ; t 8151 DC02 ;
0304 . .TIME DEAY 0351 SEP RC ; ,#02 ..DELAY HALF BIT TIME
81 26 8153 3 7 4 F ; 0352
8126 3F2C; 0305 BN4 WAIT . . BR IF L F = t N O ECHO, LSB A U X . 1 = 1 B4 TTY1 ..BR IF NO START BIT
I 8155 8FF6; 0353 GLO CHAR ;SHR ..ENTRY VIA TTYRED?
8128 0306
GHI AUX ;'ANI#FE f 8157 3 B 5 B ; 0354 BNF NOBIT . . BR IF NO
8128 9EFAFE; 0307
PHI AUX . . C R - t E C H O , LBB A U X . 1=0 8159 6740 ; 0355 OUT 7 ,#40
812B BE; 0308
k 8156 ; 0356
812C DC26 ; 0309 WAIT:SEP RC ; ,#26
SEP R5 i 815B E2C4; 0357 NOBIT:SEX R2 ;NOP ..RESET X, AND DELAY
812E D5 ; 0310
1 81 5D 9EF6; 0358 BIT:GHI AUX ;SHR ..ECHO ?
812F 0311 1 815F 3368 ;
0312 0359 BDF NOECHO . . BR IF NO
812F I 8161 3766 ;
0313 0360 B4 OUTBIT ..IS THE BIT A 1 ?
812F 1 8163 7B ;
0314 ..READ ROUTINE — READS 1 BYTE INTO C h A K . l . 0361 SEO . . SET 0
812F I 8164 3068;
0315 ..WHEN E N T E R E D -VIA R E A D A H , THEN 0362 BR NOECHO
812F • 8166 7A ;
0316 ..IF INPUT IS A HEX DIGIT ITS HEX V A L U E 0363 OUTBIT:REO .. R E S E T Q
81 2F • 8167 C4 ; 0364
B12F 0317 ..IS SHIFTED INTO ASL FROM THE RIGHT HOP . .DELAY
..AND DF=1,ELSE DF = 0; C L O B B E R S C H A R , A U X . O , (ASL I 8168 DC07 ; 0365 NOECHO:SEP RC ; ,#07 ..WAIT ONE BIT TIME
812F 0318
..OS READAH) . L E A V E S BYTE IN D (BUT C L O B B E R E D IF • 816A C4C4; 0366 NOP ;NOP . .MORE DELAY
812F 0319
..SUBR LINKAGE IS USED). L E A V E S PC AT R E A D A H 1 816C 9FF6BF ; 0367 GHI CHAR ;SHR ;PHI CHAR ..SHIFT
812F 0320 1 8 1 6F ;
..ENTRY POINT; EXITS TO R5 . 0368 . .THE INPUT CHAR
812F 0321 1 816F 3378 ;
0322 0369 BDF NEXT . . BR IF INPUT FINISHED
812F 1 8171 ; 0370
0323 . .WARNING:READ PROCESS HAS NOT FINISHED. DO . .D=ChAR. 1
812F I 8171 F98C ; 0371
0324 ..NOT TYPE I M M E D I A T E L Y , OR ELSE ENTER TYPE VIA ORI#80
812F I 8173 3 F 5 B; 0372
0325 . .TYPE5D BN4 NOBIT . . BR IF INPUT WAS A ZERO
812F 1 8175 B F ; 0373
0326 PHI CHAR
812F 1 8176 305D; 0374
0327 ORG #812F BR BIT . .CONTINUE LOOP
812F •8178 ; 0375
81 2 F FC07 ; 0328 CKDEC:ADI #07 . . CK FOR ASCII DECIMAL INPUT
18178 ; 0376
 170 171

NEXT:REQ ..OUTPUT THE STOP BIT 81 A6 FBOA; 0427 XR1#OA . . I S IT LINE FEE D ?
8178 7A; 0377 81A8 3ABF; 0428 BNZ TY2
8179 3243 0378 BZ READ2 ..BR IF D=0, =tCHAR.l
. . I S A NULL 81AA F88B; 0429 LDI#8B . . ( # OF B I T S ) + ( # O F NULLS
817B 0379 81AC
GLO CHAR . .CK ENTRY FLAG 0430 . . T O FOLLOW LF+1)
817B 8F ; 0380 81AC 30C1; 0431
BNZ REXIT . . BR IF ENTRY WAS VIA READ BR TY3
817C 3A39 0381 8 1 AE Qy r
IT ;
• 0432 TYPE2.-GHI CHAR
0382 GHI CHAR ..014 ENTRY
SUE 9F ; 81AF F6F6F6F6 0433 TY4.-SHR ;SHR
817F FF41 0383 SMI#41 ..CK FOR ASCII HEX ;SHR ;SHR ..SHIFT FIRST
BNF CKDEC ..(AT TOP OF ROUTINE) 81B3 i 0434 ..HEX TO RIGHT
8181 3B2F 0384 81B3 FCF6;
SMI#06 . . CK FOR A THRU F 0435 ADI*F6 ..CONVERT TO HEX
8183 FF06 0385 81B5 3BB9;
0386 BDF NFND 0436 BNF *+#04 ..IF A OR MORE
8185 3337 81B7 FC07 ; 0437
0387 ADI#07 ..ADD NET 37
8187 81B9 FFC6AE; 0438 SMI*C6 ; PLO AUX
ft O o O ..ELSE ADD NET 30
8187 U J OO
81BC F81B; 0439 LDIflB
FEFEFEFE; 0389 FNDrSHL ;SHL ;SHL ;SHL ..10+(* OF BITS)
8187 81BE C8 ; 0440 LSKP .EQUIV. TO BR TY3
818B FC08FE; 0390 ADI#08 ;SHL
FND1:PLO AUX ..READY TO SHIFT INTO RD 81BF 0441
818E AE ; 0391 81BF F80B; 0442 TY2.-LDHFOB
818F 8D7EAD; 0392 GLO ASL ;SHLC ;PLO ASL ..SHIFT ..(* OF BITS TO OUTPUT)
. .LOW HALF 81C1 AF; 0443 TY3:PLO CHAR ..SAVE MAIN TALLY VALUE
8192 0393
8192 9D7EBD; 0394 GHI ASL ;SHLC ;PHI ASL ..SHIFT 81C2 ; 0444
0395 . .HIGH HALF ; 81 C 2 ; 0445
8195 81C2 7B; 0446 BEGIN:SEQ . . S
8195 8EFE; 0396 GLO AUX ;SHL
BNZ FND1 ..BR IF NOT FINISHED 81C3 8E; 0447 GLO AOX ..GET CHAR TO BE TYPED
8197 3A8E ; 0397
0398 BR REXIT 81C4 AD; 0448 PLO RD ..SAVE THE CHAR.
8199 3039; 81C5 ; 0449
819B 0399 ..TYPE ROUTINE — TYPES 1 BYTE FROM @R5!,(3R6!, ..(AOX.O CLOBBERED)
..OR C H A R . 1, OR TYPES A BYTE AS TWO HEX DIGITS 81C5 DC07 ; 0450 PREBIT:SEP RC ; ,t 17 . .WAIT ONE BIT TIME
819B 0400
..FROM CHAR.l FOLLOWS A LINE FEED BY SIX NULLS. 81C7 ; 0451 . .RETUR I FROM DELAY WITH D«0
819B 0401
0402 ..USES 2 A U X I L I A R Y REGS-AUX AND CHAR-PLUS 1 81C7 2F ; 0452 DEC CHAR ..DEC THE BIT COUNTER
819B ' 81C8 F 5; 0453
0403 ..RAM LOCATION @ST. EXITS READY TO TYPE 1 BYTE SD . . SIT DF-1
819B f 81C9 8 D 76 AD ;
0404 . .FROM @R5! . EXITS TO R5 0454 . GLO RD ;SHRC ; ;PLO RD ..SHIFT
819B f 81CC ;
0405 ..WHEN ENTERED AT TYPES D , PAUSE S TO ALLOW AN 0455 ..OUTPUT CHAR
819B 81CC 33D1 ;
0406 ..EARLIER READ TO COMPLETE. 0456 BDF OUT1B .. BR IF THE BIT IS A 1
819B
0407 81CE 7B ; 0457 SEO .ELSE SET Q TO ZERO
819B | 81CF 30D3;
0408 ..AUX.O HOLDS OUTPUT CHAR (AT FIRST), THEN 0458 BR OUT1B-H? 2
819B \ 1 D 1 7A;
0409 ..THE DELAY CONSTANT BETWEEN BITS. CHAR.O HOLDS 0459 OUTIB:REQ . . S T 0 TO 1
819B | 81D2C4;
0410 ..THE N U M B E R OF BITS (11) IN ITS LOWER DIGIT, 0460 NOP EL AY
819B
041 1 ..AND IN ITS UPPER DIGIT HOLDS A CODE-- 81D3 8FFAOF; 0461 GLO CHAR ;ANI*OF ..FINISHED TYPING ?
819B
04 1 2 0 FOR BYTE OUTPUT 81D6 C4C4; 0462 NOP ;NOP ..DEIAYU4 INSTR.LOOP)
819B
0413 1 FOR FIRST HEX OUTPUT 81D8 3 A C 5 ; 0463 BNZ PREBIT ..BR IF NOT FINISHED
819B 8 IDA 8 F F C F B ;
04 14 2 FOR LST NULL OUTPUT 0464 NXCHAR:GLO CHAR ;ADIfFB
819B
0415 8 FOR LF OUTPUT 81DD AF ; 0465 PLO CHAR ..SET UP FOR NEXT CHAR
819B
041 6 SIDE 3B9F; 0466 BNF TEXIT ..BUT EXIT IF NO MORE
819B
0417 ORG *819C 81EO F F 1 B ; 0467 SMI*1B ..TEST FOR ALTERNATIVES
819B
819C DC17 ; 0418 TYPE5D:SEP RC ; ,#17 ..3 BIT TIME DELAY ' 81E2 329F; 0468 BZ TEXIT ..IF JUST TYPED LSI NULL
819E 38 ; 0419 SKP , . SKP TO TYPE5D 81E4 3BEA; 0469 BNF HEX2 ..IF JUST TYPED FIRST HEX
819F D5; 0420 T E X I T r S E P R5 81E6 ; 0470 ..JUST TYPED LF OR NULL—
81AO 4538 ; 0421 TYPE5:LDA R5 ;SKP ..ENTRY FOR UT4 81E6 F800; 0471 LDIfOO ..PREPARE TO TYPE NULL
81A2 0422 . . SKIP TO TYPE ' 81E8 30F5; 0472 BR HX22
81A2 4638 ; 0423 TYPE6:LDA R6 ;SKP ..ENTRY FOR G.P. 81EA ; 0473
0424 . . IMMED TH 81EA 9FFAOF; 0474 HEX2:GHI CHAR ;.
;ANI#OF ..GET 2ND HEX DIGIT
81A4 I 81ED
81A4 0425 TYPE:GHI CHAR FCF6; 0475 ADI*F6 ..CONVERT TO HEX
0426 TY1:PLO AUX ..SAVE BYTE FOR LATER 81EF 3BF3; 0476 BNF *+#04 . . IF A MORE
81A5
 172 173

TABLE 2

ENTRY POINTS FOR UT4 SUBROUTINES

ABSOLUTE
81F1 FC07 ; 0477 ADI#07 ..ADD NET 37 ADDRESS FUNCTION and COMMENTS
81F3 FFC6 ; 0478 SMI#C6 . .ELSE ALL NET 30
81F5 AE; 0479 HX22 :PLO AUX ..STORE
.S' CHAR A W A Y
READ 813E Input ASCII •* CHAR.l, D (if non-
81F6 30C2 ; 0480 BR B E G I N
. standard linkage).
81F8 0481
81F8 B30A; 0482 F S Y N E R T S E P SUB; ,ffOA
81FA D33F ; 0483 SEP S U B ; ,#3F READAH 813B Same as READ. If hex character, DIGIT ->-
81FC C08039 ; 0484 LBR S T A R T ASL (see text).
81FF J 0485 END
0000 TTYRED 8140 Same as READ. Controls paper tape reader
(see text).

TYPE5D 819C 1.5-bit delay. Then TYPES function.

TYPES 81AO Output ASCII character at M(R5). Then

increment R5.
TABLE 1
TYPE6 81A2 Output ASCII character at M(R6). Then
increment R6.
UT4 REGISTER UTILIZATION TYPE 81A4 Output ASCII character at CHAR.l,

TYPE2 81AE Output hex digit pair in CHAR.l,

REGISTER REGISTER
NAME NUMBER FUNCTION and COMMENTS TIMALC 80FE Read input character and set up control
byte in AUX.l. Initialize RC to point to
PTER RO Altered by UT4 while storing registers. DELAY1.

CL Rl DELAY1 80EF Delay, as function of M(R3) (see text).

Then R3+1 •* R3.
SUB R3 Program counter for all READ, all TYPE,
and TIMALC routines.
NOTES:
PC R5 Program counter for UT4, which calls the
routines above. 1. All routines except DELAY use R3 as program counter, exit
with SEP5, and alter registers X, D, DF, AUX, and CHAR.
DELAY RC Program counter for the DELAY routine.
Points to DELAY1 in memory. 2. DELAY routine uses RC as program counter, exits with SEP3
after incrementing R3, and alters register X, D, DF, and
ASL RD Assembled into by READAH (input hex digits). AUX.

AUX RE AUX.l holds time constant and echo bit. 3. READ and READAH exit with R3 pointing back at READAH.
AUX.O is used by all READ and TYPE routines
and by TIMALC. 4. All five TYPE routines exit with R3 pointing at TYPES.

CHAR RF CHAR.l holds input/output ASCII character. 5. As indicated in Table 3-1, ASL = RD, AUX = RE, and CHAR = RF.
CHAR.0 is used by all READ and TYPE routines
and by TIMALC.
 174 175

OUTPUT R O U T I N E U S I N G UT4 9. B r a n ch now if t h i s byte in D is #00, w h i c h means end

of string (29,43).

The monitor program UT4 i n c l u d e s all the software to use 10. If it is not#00, do a SEP 3 and c a l l the TYPE r o u t i n e
the "software" U A R T w i t h EF4 and Q l i n e , n o t only for the (30).
monitor program, but as w e l l these subroutines can be
c a l l e d by user programs. T h i s is very u s e f u l , f o r e x a m p l e , 11. TYPE exits w i t h a SEP 5 w h i c h m e a n s the program c o n t i -
to send messages to the terminal d u r i n g program execution. nues at location #0028 and branches back to OUTPUT
(31).
Description of the program :
12. If the s t r i n g has been sent a d e l a y r o u t i n e is i n i t i a -
1. At the first instruction,interrupts have to be d i s a b l e d l i z e d and when it has f i n i s h e d , the same string is sent
as the w h o l e t i m i n g is via counters that cannot be again.
i nterrupted (line 9).

2. The TYPE s u b r o u t i n e comes back w i t h a SEP 5 i n s t r u c t i o n ,

w h i c h m e a n s it has to be c a l l e d from a program r u n n i n g
in R5 as PC (10-12) .

3. A D E L A Y counter has to be i n i t i a l i z e d (14-15).

4. T i m i n g constant and echo bit h a v e to be l o a d e d (17-18).

5. The text p o i n t e r has to be p r e p a r e d , pointing to the text

bytes at add #0036 (20-21).

6. A c a l l of s u b r o u t i n e at $819C gets the t i m i n g right

(23-25).

7. Now the o u t p u t r o u t i n e starts w i t h p r e p a r i n g R3 to

81A4 (27).

i. Now the first ASCII c h a r a c t e r is l o a d e d via R6 in D and

t h e n to R F . l , where the s u b r o u t i n e TYPE gets the byte
from (28).
 176 177

INTERRUPT ENTRY AND EXIT

• :

C o m p a t i b l e w i t h SCRT
8000 5 (400 1 .. EXAMPLE PROGRAM • I n t e r r u p t Entry
000B 5 0802 ,.
,„
OUTPUT A STRING
UB.CNG LIT 4 ROUTINES
Ht ' :
•
0('!0H 5 00(53
8000 5 0004 • :
^Bi'
W h e n the 1802 re'ponds to an i n t e r r u p t , X and P are set
0000 5 B00S CONST 1--880EF
0000 5 00B6 CONST 2~B2B06 to 2 and 1 r e s p e c t i v e l y . T h u s , the interrupt h a n d l e r
00BB 5
8000 "
00B7
0008 ORG ti0tiB8
K
•
• always starts at the l o c a t i o n l o a d e d into Rl d u r i n g
0000 X1005 0009 INl'f! DIS.KBB ..DISABLE INTERRUPTS initialization. It is c o n v e n i e n t for most purposes
0002
8('i0b
FH00BS
FBB9A5
0010
0011
LDI A.liURITEiiPHI Rb
LLH A . K C U R I T E J l P L U RS
..LOAD MAIN PC Rb
..U1TH START ADDRESS
• to use Rl to execute a short housekeeping routine
0008
80(19
Db;
•
0012
0013
SEP Rb ..CHANGE PC FROM (>> TO S • w h i c h is a n a l o g o u s to the " C A L L " r o u t i n e of SCRT.
Such a r o u t i n e is shown in F i g . 1.
8809
0fi0C
FBB0BC
FBEFAC
8814 WRITE:
00 Ib
LDI A.1(CONSTi:i5PHI RC
LDI rt. HI CONST 1;);PL(J RC
. .1NI.T DELAY POINTER
I
1
080F
860H
5
F828BE
8016
0017 LDI A.1(C(iNST2:i;PHl RF .,.(N1T T1HE CONSTANT •
1
U s i n g R2 as stack p o i n t e r , the h a n d l e r first p u s h e s
0012 FB0(-iAl:. 00 IB LDI A.K(ClJNST2T;PUJ RE ...AND ECHO BIT X, P, D, DF and R3 onto the stack. It is a l s o neces-
00 1b
00 ib
5
FB00BA
00i 9
0020 LDI A. 1! TEXT J5PHI R6 ..PREPARE TEXT POINTER
• sary to save R4 and R5, since an i n t e r r u p t may occur
0018 F836A6 0021 LDI A. 01 TEXT] 5 PL .0 R6 1
• d u r i n g s u b r o u t i n e c a l l s or returns, when one of these
001B
0018
5
F881B3
0022
0023 1.1)1 IftM'iPHl KG ..LOAD R3 UITH 819C TO
I
I
r e g i s t e r s is a c t i v e . To reduce i n t e r r u p t respons e
00 1E FS9CA8 0024 LDI ti9C5PI.O R3 ..DO A TYPE'S!) FIRST time o n l y the low bytes of R4 and R5 are s a v e d , t h u s
0021 1)300; 002b SEP R3,80H ..EXECUTE ("YPFbD •
I a s s u m i n g t h a t the C A L L and E X I T r o u t i n e s do not cross
0023
0023
5
F8A4A3';
0026
B827 OUTPUT: LDI fJA4',PLU R3 ..PREPARE R8 FUR TYPE I t
page b o u n d a r i e s . (This r e q u i r e m e n t i s a l r e a d y s a t i s -
0026 46BF! 0828 LDA K65PHI RF ..GET BYTE IN RF.1 AND D :S fied by SCRT, because of the use of short branches in
802B
002A
322D5
D35
0029
0030
67 DELAY
SEP R3
..IF IT IS 00 GO TO DELAY
..OTHERWISE SEND IT
f
} the CALL and EXIT routines - a g a i n to reduce execution
802B 30235 0031 BR OUTPUT ..BACK AGAIN time).
002D 5 0032
8B2D E8PF5 0033 DELAY: LDI BEE ..LOAD DELAY CONSTANT
002F B75 0034 PHI R7 : ..IN R7 It is not necessary to save R6, s i n c e t h i s r e g i s t e r
0030 275 003b LOOP: DEC R7 ..DEC (HIS REGISTER
0031 975 0036 GHI RX '• • ' ..GET R7.1 IN D-REGISTER ( " l i n k " ) w i l l b e saved a u t o m a t i c a l l y b y a n y SCRT s u b -
0032 3A3H5 0037 BNZ LOOP ..IE NOT 00 DEC AGAIN t r o u t i n e c a l l used i n t h e i n t e r r u p t s e r v i c e r o u t i n e .
0034 30095 0038 BR URITF ..GO TO NEXT CHARACTER
0036 5 0039 In fact, the information in R6 is very u s e f u l in debug -
8036 0D0AS2434 12042 50040 TEXT: ,X'0D0A' ,T'RCA BRUSSELS' g i n g s i n c e by r e a d i ng R6 the p r o g r a m m e r can e a s i l y
003D
0044
b2bbS3b34b4Cb3 50040
0l)0Ab3b4b2494E 5004-f ,X'0D0A' /('STRING OUTPUT '
\ idetify not o n l y w h i c h s u b r o u t i n e was a c t i v e at the
004B 47204FSbb4b"0SS 50041 I time of the interrupt but also the l o c a t i o n of the
00S2
00S3
b45 0041
0D0Abbb'3494E4X 50042 ,X'0D0A' ,'T'USING UT4 ROUTINES'
I
1 c a l l to that s u b r o u t i n e .
,00bA 20bbb43420b24F 50042
0061 5bb4494E4b"S35 0042
..END OF STRING
•
[
•
0067 005 8843 ,X'HB'
0068 5 8844 END •M
0080 • I
1'
1 r.
I
1•
 178 179

B. Interrupt E x i t
To a l l o w use of SCRT s u b r o u t i n e s d u r i n g i n t e r r u p t s , R4
and R5 are r e - i n i t i a l i z e d and f i n a l l y the s t a r t i n g ad-
At the end of any interrupt s e r v i c e , the m a c h i n e status
dressof the s e r v i c e r o u t i n e i t s e l f is l o a d e d into R 3 ,
m u s t be restored for return to the interrupte d oroqram.
w h i c h becomes p r o g r a m counter after e x e c u t i o n of the
T h i s is done by a r o u t i n e a n a l o g o u s to the "EXIT" of
SEP 3 i n s t r u c t i o n .
SCRT. T h i s r o u t i n e needs a d e d i c a t e d p o i n t e r , and it
is often c o n v e n i e n t to use R0 for t h i s task in a p p l i -
After p a s s i n g control to R3, Rl is l e f t reset to the
c a t i o n s not u s i n g DMA. H o w e v e r , for g e n e r a l i t y it is
i n t e r r u p t entry p o i n t (by the " b r a n c h - t o - s t o p " i n s t r u c -
suggested that the next " a v a i l a b l e " register , R7,
tion). S i n c e i n t e r r u p t s are a u t o m a t i c a l l y d i s a b l e d on
s h o u l d be used for the r e t u r n - f r o m - i n t e r r u p t f u n c t i o n
i n t e r r u p t r e s p o n s e, t h e i n t e r r u p t h a n d l e r c a n n e v e r
in F i g u r e 1.
b e i n t e r r u p t e d , a n d interrupts r e m a i n d i s a b l e d u n t i l
t h e s e r v i c e r o u t i n e i t s e l f r e - e n a b l e s them.
The r o u t i n e shown assumes that X = 2 on entry and t h a t
i n t e r r u p t s are d i s a b l e d d u r i n g its o p e r a t i o n . It res-
Total e x e c u t i o n t i m e of the entry r o u t i n e is 78.4 uS
tores R5, R4, R3, DF and D and then branches to the
w i t h a 5MHz clock.
RET i n s t r u c t i o n , w h i c h restores X and P and r e - e n a b l e s
i nterrupts.

To pass control to the i n t e r r u p t e x i t r o u t i n e , it is

necessary to d i s a b l e i n t e r r u p t s , set X to 2 and set
P to 7. A t w o - i n s t r u c t i o n sequence is needed to do
this : -

SEX 3 ; D I S , # 27

T h i s s e q u e n c e is a n a l o g o u s to the SEP 5 used for s u b -

r o u t i n e e x i t s u n d e r SCRT, and may be c o n v e n i e n t l y defined
as a macro if s e v e r a l i n t e r r u p t r o u t i n e s are used in the
application.

I n c l u d i n g the e x i t i n s t r u c t i o n s , total time overhead is

54.4 uS w i t h a 5MHz c l o c k .
 180 181

CASSETTE I N T E R F A C E U S I N G UT4

A s i m p l e cassette interface can be connected to UT4 u s i n g

mm 8001 .. EXAMPLE: PROGRAM its r o u t i n e s to load and store data on a normal cassette.
mm 0002 .. INTERRUPT HANDLER
mm 0003 .. RUNS IN R1 CEN'fRYJ The terminal and the cassette interface are in p a r a l l e l .
mm 0004 .. AND IN R7 CEXI'I !l
mm 000S
mm 0006 CALL=H81E4 .ADDRESS CALL KOU'l .
The command
mm 0007 RH=88<F4 .ADDRESS RET RttUl.
mm 8008 INTSRV=«0180 .ADD OF SERVICE ROD I.
mm 0009 7M0000 1000 (CR)
mm 0010 ORB 80200
mm D3", 0011 TUP1: SEP R3 .UU TO SERVICE RUU'lINE
0201 22; 0012 ENTRY: DEC R2 .GO ill FREE S'lALK w i l l write 4000 bytes from memory to the t e r m i n a l , s t a r t i n g
78; 0013 SAV .SAVE X,P
0283 22; 0014 DEC R2 .DEC PU1NIER at address 0000. The Q output switches an oscillator, con-
73; 001S STXl) .SAVE D REGISTER
s i s t i n g of a 1/2 CD4001, on and off. T h i s s i g n a l is fed
020S 76; 0016 SHRC .GET UK IN D
0206 73; 8817 STXD .STORE ON STACK through a v o l t a g e d i v i d e r and then recorded on the tape.
0207 83; 0018 GLU R3 .SAVE '(HE
0208 73; 0019 S1XD .PROGRAM CHUNK R (Switch tape to R E C O R D just before the (CR')).
020? 93; 0020 6H1 R3 .REGISTER R3
020A 73; 0821 S'l XD
To get t h i s i n f o r m a t i o n back from tape i n t o memory, type via
020B 0822 GL.O K4 . SAVE LOU PftR'l
020C 0023 STXL) . OF R4 termi nal .
020D 0024 GLO RS . AND AS UEEL
0Z0t: 73; 002b STXl) . RS.0
028F E8E4; 0026 L!)I ft.0CCAL.IJ .INiT
1M
0211 A41 0027 PLU R4 .R4.8 and then switch tape recorder to p l a y.
0212 F8F4; 0028 LDI A.01REI] .AND
0214 AS; 8029 PLU RS .Rb.li The s i g n a l is a m p l i f i e d , rectified and two other gates of the
02 IS F8B1; 0830 LDI A.K INISRV!) .LOAD NOU ADDRESS CD4001, s h a p e it and feed it to EF4 where it is ored w i t h
ay 17 b3; 0031 PHI R3 .OF IMiERRUPT
0218 F808; 8032 LI) I A.8(.IN'(SRV:i .SERVICE ROUHNE the termi nal si gnal .
02 1A A3; 0033 PL.il R3 .IN R3
021B 3000 ; 0034 BR TOP1 .AND BRANCH '(0 '(UN
0211) 003b After h a v i n g stored the f i l e , UT4 comes back w i t h * and the
02 ID 0836 cassette recorder has to be switched off.
02 10 S037
0211) 0038 TGP2: KE'I .GFI X,P BACK
02 it E2; 0039 1NEXFI : SEX H2 .SF'( X=2 FIRS'I
02 IF 60; 8048 IRX .PREPARt S'lACKP'lR
0220 72AS; B041 LDXAiPLll RS .RES'IORE REGISTERS
0222 72A4; 8042 LDXA5PLU R4
0224 72B3; 8843 LIMA; PHI R3
0226 72A8; 8844 LDXA'JPLtl R3
0228 72F6; 884S LDXA'iSHR .Cit'l DH BACK
022A 72; 0046 LDXA .AND I) AS DELL
022B 30 if); 0047 BR HIH2 .BRANCH U! 1UP2
0221) 8048 END
0000
182 183

REAL TIME CLOCK WITHOUT H A R D W A R E

" A real t i m e c l o c k function can be i n c l u d e d in C O S M A C pro-

grams w i t h o u t a d d i t i o n a l hardware. C o n n e c t i n g SCI (STATE
CODE 1) and DMA OUT (see F i g . 1) r e s u l t s in an a u t o m a t i c
i n c r e m e n t of R0 after every i n s t r u c t i o n . The fetch-execute
is m o d i f i e d to fetch-execute-DMA. The c l o c k frequency is
chosen to g i v e a c o m p l e t e wrap-around of R0 in w h a t e v e r time
period is r e q u i r e d for the a p p l i c a t i o n . For e x a m p l e , a
crystal of 1,572864MHz g i v e s 1 second. If a less c o n v e n i e n t
frequency is used, software t e c h n i q u e s can be used to adjust
the t i m i n g by add and substract.

How does it work :

N o r m a l l y the SCI l i n e is low. At the moment w h e n the DMA

l i n e is s a m p l e d i n t e r n a l l y , it is therefore sensed as low.
So after an execute, a DMA cycle is i n s e r t e d . Now the SCI
goes h i g h (DMA cycle) and the DMA OUT is h i g h as w e l l . As
the DMA request is t h u s removed , a n o r m a l fetch starts, but
the DMA pointer has i n c r e m e n t e d i t s e l f . There is no o u t p u t
port for the DMA d a t a as the o u t p u t function i t s e l f is not
used : only the i n c r e m e n t of R0 is i m p o r t a n t.

Software i m p l i c a t i o n s :

1. I n s t r u c t i o n e x e c u t i o n time is d e g r a d e d by a factor of
1,5 because i n s t r u c t i o n s effectivel y take 3 cycles
(fetch - execute - DMA).

2. 3 cycle i n s t r u c t i o n s and i n t e r r u p t s c a n n o t be used in

s u c h a n a p p l i c a t i o n b e c a u s e they d i s t r o y t h e r e l a t i o n -
s h i p of the DMA coun t to r e a l - t i m e .

3. I n i t i a l i z a t i o n m u s t be intersperse d with NOP's or any

other i n s t r u c t i o n w h i l e R 0 r e m a i n s p r o g r a m counter .
As R0 is PC and DMA p o i n t e r , the s e q u e n c e of the pro-
g ram i s :
 ; I
!r
1 , in
f- lu
s
184 189 (START)

1 — OD— 7^
NOP (DMA) f;
f'
!
GHI R0 Load register i ; XTAL CLOCK SECONDS

NOP (DMA)
i JL
PHI R3 R3 w i t h
*
1
• *
<^'
W*-I

NO ^XMir^orE^X.
^%E L A, p 5 E O^X^
NOP (DMA)
LDI #0B The start l o c a t i o n
NOP (DMA) | 6P\A"|
UPDATE
MIMUTES
PLO R3 Of the m a i n program !' COP 1802 •-'
I
NOP (DMA)
? ' '

SEP 3 And SEP R3 w/™"^

^XuoiJlZSjX^^
I

As DMA has p r i o r i t y after the reset first a DMA is I f

OPD^TE.
executed, i n c r e m e n t i n g R0 p o i n t i n g now to the GHI R0. i
'':'

MOUCS
After execution of this instruction another DMA is done. *

JL
;
T h i s means that o n l y odd i n s t r u c t i o n s are executed as F i g u r e 1 : H a r d w a r e For '"
l o n g as R0 is DMA p o i n t e r and PC. Here NOP was chosen
as f i l l e r , but any other i n s t r u c t i o n works as w e l l .
Real Time Clock \T )
|

4. The m a i n program is r e p o n s i b l e for k e e p i n g track of Figure 2 : Flowchart

the v a l u e in R0 and u p d a t i n g a c l o ck register - w h i c h •>
To U p d a t e
m i g h t be s i m p l y a seconds c o u n t e r , or c o u l d be a p a c k e d i BCD Real-Time Clock The C l o c k
BCD storage of real t i m e in s e c o n d s , m i n u t e s and hours, I: . . . . . . . ••
even i n c l u d i n g date, month a n d year. 'I
SECOND " R9 . . SECONDS COUNTER
', CLOCK - m .. ro N—TS TO STORAGE LOCATION
: DISP - -* <20 . . STORAGE LOCATION
This i d e a i s e s p e c i a l l y useful i n data l o g g i n g a p p l i c a - MAIN - R3 . . MAIN PROGRAM COUNTER
STACK - R2 . . STACK POINTER *
tions w i t h very s i g n i f i c a n t s a v i n g i n hardware a n d there- i ' EXTCLK: STR CLOCK .. STORE HOURS
fore reduced system cost. '.
:' GOBACK:
A.*(DISPI-»CLOCK.(I
SEP MAIN
.. RESET 'CLOCK'
EXIT POINT
| . ENTCLK: DEC SECOND ENTRY POINT
' .' GLO SECOND
'' BNZ GOBACK MINUTE ELAPSED?
For more i n f o r m a t i o n , see A p p l i c a t i o n Note ICAN-6677 ! I 60-«SECOND. 0 RELOAD 'SECOND'
1 ! SEX STACK
"Software C o n t r o l of M i c r o p r o c e s s o r - B a s e d Real Tim e C l o c k " . i.: MINUTE: 9 CLOCK. AND.#*F .. GET LSD MINUTES
I ; ADI 247

i
< '

MIN10:
BDFMIN10
SMI 246
STR STACK
CHECK FOR CARRY
IF NO CARRY ADD 1
AND STORE
' r 9 CLOCK. ANDJ>F^ .. GET MSD MINUTES
BNFMINFIN IF NO DF DONE
ADI 176
BDFMINFIN CHECK FOR CARRY
SMI 160 - CARRY
IF NO - ADD 1
MINFIN: S OR. 9—*f CLOCK .. COMBINE AND STORE
, ' BNF EXTCLK IF NO DF DONE
HOURS: INC CLOCK POINT TO HOURS
' P CLOCK + 221
BDF EXTCLK IF MIDNIGHT EXIT
: BR MINUTE USE SAME CODE
END
 186 187
PROM P R O G R A M M E R FOR CDP18U42
To program a l o c a t i o n , i n p u t

!MXX YY (CR)
The CMOS EPROM CDP18U42 is the first of a series of UV
erasable CMOS PROMS for the COSMAC microprocessor. and to verify, type
The content is 2K b i t s o r g a n i z ed as 256 x 8 b i t . N o r -
m a l l y these E P R O M S are programmed u s i n g the f a c i l i t i e s ?MXX YY (CR)
of the d e v e l o p m e n t system. Its programmer package per-
forms sophisticated program and verify functions in In this circuit, the location of the EPROM is programmed
a d d i t i o n to s a v i n g data f i l e s and p r i n t i n g program l i s t s . di rectly.

However, since the CDP18U42 is r e l a t i v e l y easy to pro- A d d i n g a R A M , and u s i n g a s m a l l M E M O R Y M O V E routine, programs

gram, the user may d e s i g n and b u i l d a low cost PROM can be typed in the RAM and after v e r i f i c a t i o n the program is
programmer c i r c u i t to perform the basic programming func- transferred from the RAM into the EPROM using a MEMORY MOVE
tions. Two c i r c u i t s are suggested in F i g u r e s 1 and 2. routine and coming back to the monitor via LBR 8000.

The d e s i g n of F i g u r e 1 uses LED's to d i s p l a y data and

addresses. Two modes of operation are a v a i l a b l e :
P R O G R A M and V E R I F Y . In the program mode, data is entered
in b i n a r y u s i n g e i g h t t o g g l e switches at the address i n d i -
cated by the address LED's. After releasing the ADVANCE
s w i t c h , a t i m i n g cycle is i n i t i a t e d in w h i c h the CDP18U42
is put in the program mode and the program v o l t a g e (20V)
is a p p l i e d to the V Q D > V S A T p i n s . At the end of t h i s
t i m i n g cycle the address counter is incremented by one
and the CDP18U42 is ready to accept the next data byte.

After p r o g r a m m i n g is completed, the CDP18U42 may be checked

by p l a c i n g the P G M / V E R I F Y switch in the V E R I F Y p o s i t i o n . In
this, mode the CDP18U42 is selected in the read mode and the
program voltage c i r c u i t is d i s a b l e d . After depressing the
RESET switch, each data byte may be read on the DATA OUTPUT
LED's, starting at address #00, using the ADVANCE switch.

The d e s i g n Figure 2 uses a monitor program together with a

terminal and UT4 to program the CDP18U42.
 189
188

Til

o
o:

s s 1 F i g u r e 2 : PROM Programmer U s i n g S e r i a l I n t e r f a c e and UT4

 190 191

USING THE 1802 S C R A T C H P A D TO STORE RAM V A R I A B L E S

CDP1802-Based PROM Programmer Circuit Timing

S m a l l systems w i t h modest RAM r e q u i r e m e n t s can sometimes
be i m p l e m e n t e d w i t h o u t external RAM by u s i n g a p o r t i o n of
the 1802 s c r a t c h p a d r e g i s t e r array to store v a r i a b l e data.
CLOCK 00 01 10 II | 20 | 21 | 30 | 51 | 40 | 41 | 50| 51 | 60| 61 | 7 0 - 7 1 | 00 Since the scratchpad can be configured for 16-iit addresses
or 8-bit data, a t y p i c a l s m a l l system c o u l d a l l o c a t e 8 r e g i s -
ters for p o i n t e r a d d r e s s i n g , and s t i l l l e a v e 8 registers for
up to 16 bytes of " R A M " storage.

A d i f f i c u l t y a r i s e s when attempting to perform an arithmetic

or ALU o p e r a t i o n on r e g i s t e r data - or an o u t p u t i n s t r u c t i o n
these operations require M(R(X)) and the D register as o p e -
rands . R e g i s t e r to D m a n i p u l a t i o n s can be performed w i t h
V A L I D DATA
PHI, G H I , P L O , a n d G L O i n s t r u c t i o n s , b u t R(X) c a n n ot p o i n t
to an i n t e r n a l r e g i s t e r to c o m p l e t e the o p e r a t i o n .

Verify Cycle
The problem can be solved if one page of ROM is a v a i l a b l e
for use as a l o o k u p t a b l e . W i t h t h i s m e t h o d , one r e g i s t e r
-*J 9OOn« !•*-
o p e r a n d becomes t h e lower order t a b l e p o i n t e r a d d r e s s , w h i l e
the other operand is transferred to D. The l o o k u p t a b l e
c o n t a i n s s e q u e n t i a l bytes from 00 to F F , and w h e n the a r i t h -
m e t i c or ALU operation is performed, the t a b l e contents and
D are operated u p o n , w i t h the r e s u l t in the D register.

[-»- 500 n* —*

CD4098 g. -— Smt-^T
COP18OZ WITT, CDPI8U42P5H

-f VALID DATA

PROGRAM CYCLE
93CM- 32?9I

Program Cycle
 192 193

DEBUGGING AID
EXAMPLE

One of the most usefu l t o o l s for d e b u g g i n g is a short

o R e g i s t e r data is stored in R(9).l and R(B).0
program that a l l o w s to h a v e an i n t e r a c t i v e look at the
o An XOR i n s t r u c t i o n is to be performed M(R(X)) + D
state of the C P U . As the CDP1802 has 16 i n t e r n a l 16
o Lookup t a b l e is located in l o c a t i o n s 0300 - 03FF
bit r e g i s t e r s p l u s D, DF, X, P, T it is rather d i f f i -
o R(7) is d e d i c a t e d as l o o k u p t a b l e p o i n t e r
c u l t to see why s o m e t h i n g is wrong in a p r o g r a m if you
o R(7).l has a l r e a d y been i n i t i a l i z e d to 03
cannot h a v e a l o o k at them.

The most u s e f u l tool for t h i s p u r p o s e in the RCA M I C R O -

MACRO:
Get first operand i n t o D MONITOR. It c o n s i s t s of a CDP1802 m i c r o p r o c e s s o r system,
GHI R9
Use first operand to l o o k u p t a b l e v a l u e c o n t r o l l i n g the target system.
PLO R7
GLO RB Get second operand into D
E x c l u s i v e - O R D with contents of table For a m i n i m u m system and to u n d ers t a nd how a debug program
XOR
works, t h i s s m a l l aid e x p l a i n s how to do it completely in
address
software .

As t h i s is a p r o g r a m as w e l l , it needs a p r o g r a m counter
if R(9).l = AA and R(B).0 = FF
and a data p o i n t e r .
then R(7) w o u l d p o i n t to a d d r e s s 03AA
C o n t e n t s of 03AA = AA
M(R(X)) + D = AA + FF = AA It has to h a v e a "har d b r e a k " . T h i s means that it has
D w i l l contain AA when operation is complete to be p o s s i b l e to get out of a l o o p . The e a s i e s t way is
to R E S E T the microprocessor .

In t h i s state, R0 starts to be program counter and starts

at 0000, so t h i s m i n i d e b u g is l o c a t e d at 0000.

As data p o i n t e r R8 is c h o s e n .

The "soft break" is done by u s i n g the D0 i n s t r u c t i o n .

U s i n g t h i s debug program does not a l l o w the usage of R0 ,

R8, and o n l y p r o g r a m s in RAM can be d e b u g g e d . If R0 is m o d i -
fied, the "soft b r e a k " does not work, only RESET.
 194 195

If R8 is modified, the D register is lost but the

registers Rl to R7 are still saved together w i t h DF. 08001 000-i .DP RCA BXL
0000 B002 -SHALL DEBUG PROGRAM
mm B003 .SAVES SOME REGISTERS, L>, W
At l o c a t i o n s , where a break is wanted, a SEP 0 is placed 00H0 0004 .USING SOFT BREAKPOINT "1)0"
0000 000S .[.IR RESET AS HARD BRAKE
overwriting the program byte at this location, so the pro- 0000 0006 .R0 IS USED (& PC
gram has to be in RAM. 0000 00K7 .HS IS DATA POINTER
00001 6I08H -FUR UT4 BUT NUT RESTRICTED
0000 0069 -RUNS IN RAM OR RUM
As many "soft breaks" as needed can be used d u r i n g a debug 0006 0010 .TO TEST PROGRAMS IN RAM
0C100 0011
session. 0000 0012
0600 0613
0600 8014
This debug can e a s i l y be changed to s a v e more registers 0008 001b
or use others for the DEBUG itself. 0000 0016 [BRANCHHi SAVE: REiiEl OR HARD BRAKE
0000 0017
0000 0018
0000 001V
0000 0026 - ENTRY PRtlGKAM FKUI'I U'(4
0000 0021 RESTORE REGISTERS
0000
mm
B022
0023
I
S'lART EXECUTION
till 'IO USER PRUliRAM
0000 0024
mm 0(d2b
mm 0026
mm 002/ 1FOUND L>8 IN USER PROG
0000 0028 JSAVE SOME REGISTERS
0000 0029 D AND DF
mm 0030
mm 0031
0000 6032 GO TO MONITOR PROGRAM
0000 0033 AT 88000 P=«l X=8
0000 0034
0000 003S
0000 0036
0000 0037
0008 0038
0000 0039 MEMORY USAGE EOR 18S601 BOARD
0000 0040 4EE0 WANTED X,P
0000 0041 4FE1 I) REGISTER
8000 0042 4FE2 R1
0008 0043 4FE4 R2
0000 0044 4EE6 R3
0000 004S 4FE8 R4
0000 0046 4EEA RS
0000 0047 4EEC R6
0000 0043 4FEE R/
0000 0049 4FF0 DF SHOWS IF D IS OK
0008 0050
0000 00S1
 196 197

i.
0880 08H2 ..THIS SHORT DEBOG PROGRAM i 003S 8183
0000 0853 ..SAVES AND RESTORES PART OF THE 0035 0104 ..AS R8 AND KB HAVE NOT BEEN
8000 8854 ..CDF 1802 STATE USING ! 0835 010S ..CHANGED HOPEFULLY, A SEP 0
0008 0055 ..D0 AS SOFTWARE BREAKPOINT 1 0835 8106 ..IN THE USER PROGRAM WILL
8000 0056 ! 8835 0107 ..START THE SAVE ROUTINE
8088 0057 ORB 80000 BBSS 0108 ..WITH R8 POINTING TCI 84FF 1 :
0000 C0003S; 00S8 LBR SAVE ..THIS IS AN ENTRY AFTER RESET I 0835 0109
0083 0059 ..OR HARD BRAKE | 0035 E0; 0110 SAW.! SEX R0 ..X TO IMMEDIATE
0803 0068 ..RESTORE REGISTERS AND START EXECUTION | 0036 7180; 0111 DIS, 880 ..HI DIS INTERRUPTS
0083 0061 ..OF USER PROGRAM WITH $P3tCR) W 8838 585 0112 STR R8 ..SAVE D
0083 0062 ..UITH X,P FROM LOCATION B4FE0 •1 0039 88; 0113 GLO R8 ..CHECK DATA POINTER
0003 0063 IB 803A FBE1; • ' 0114 XRI 8E1
0003 K8085 0064 LDI 808 ..A SHORT DELAY H 003C 3A43; 0115 BN7. REPAIR ..IF CHANGED GO TO REPAIR
0085 B8! 0065 PHI R3 n 003E 98; 0116 GHI R8
0006 28; 0066 LOOP « DEC R8 •t 888K FB4F; 0117 XRi H4K
0007 98'i 0067 GHI R8 : W 0041 324C; 0118 B7. DOK
0088 3A06; 0068 BNZ LOOP BE 8843 ; 0119
088A 0069 H 0043 F84FB85 0120 REPAIR; LDI 84FSPH1 R8 ..SET' DATA POINTER
000A F84FB8! 0070 LDI K4F5PHI R8 ..LOAD DATA POINTER •f 0046 F8HBA85 '", 0121 I...DI BF85PLG H8 "
008D F8E2A8J 0071 LDI «E2;PLO R8 ..R8 WITH 84HE2 K 0B49 58; 0122 SIR R8 ..STORE l:0 AT DF
0010 0072 : SEX R8 ' ..SET X TO 8 •f 004A 3052; 0123 BR SDF
0811 0073 Kg' 884C 5 0124 >•
MB 11 72B -i; LDXA5PHI R1 .. RESTORE REGISTERS BE 804C F8F0A8; 0125 DDK: LDI 8F05PLU R8 ..SET R8 TO DF LOCATION
0013 72A1; 0075 LDXA;PLi! R1 ..R1 10 R7 • 004F F880S8; 8126 LDI 800 5 SIR R8 ..STORE D IS UK
0815 72B25 0076 LDXA5PH1 R2 •I 8852 ; 0127
0017 72A25 0077 LDXA5PLO R2 H 8052 E85 0128 SDF; SEX R8
0019 72B35 8878 LDXA;PHI R3 •ft 8053 7EF 1 5 0129 SHLC50R ..SAVE DF
00 IB 72A3; 0879 LDXA5PLO R3 ' . ' , • 0055' 73; 0130 8TXD
001D 72B41 8080 LDXA5FHI R4 •K 8056 ; 0131
0011- 72A45 8081 LDXA5PLO R4 mm 0066 8773; 8132 GLO R7",STXD ..SAVE R1 TO K?
0B21 72B5; 0082 LDXAIPHJ R5 •1 0058 9773; B133 GHI R75STXD
0023 72A5! 0083 LDXA'PLO RS HI 805A 8673'i 8134 GLU R6",STXD
0025 72B6; 0084 Ll)XA;PHI R6 ','•,: H: 005C 9673; B135 GHI R65STXD
0027 72AA; 0085 LDXA;PL(J H6 '''... . H; 005E 85735 0136 GLO R55STXD ,
72R7; 0086 LDXA',PHI R7 ;. •E 0060 95735 0137 GHI R55S1XD
002B 72 A 7; 0087 LDXA5PLO H7 :' ' - ', H 0062 84735 0138 GLO R4;STXIJ
082D 0088 mf 8864 94735 0139 GUI R45SIXD
0B2D F076; 0889 LDXlSHRt: ..GET DF BACK • 0066 8373; 8140 GLO R35STXD
002F 0898 B 0068 9373; 0141 GHI R35STXD
002F F8E.1A8; 089 1 LD) 6K15PLO R8 ..SET ADD OF D K 006A 8273; 0142 GLO H25STXD
0032 Fti1, 8892 L.DX ..A HI.) LOAD •I 006C 92735 0143 GHI R25S1XD
0033 0093 •[ 006E 8173; 0144 GLO R1",SIXD
8033 28; 8894 DtC HB ..POINT TO X,P K 0078 91735 0145 GHI R15STXD
0034 70; 8095 REI' ..DIS TO DISABLE INTERRUPTS •1 8072 0146
00'JS 8096 W 0072 080H0; 0147 fiONI'l: LBR 88080 ..BRANCH TO M808H
0085 8897 ..NOW THE USER PROGRAM IS RUNNING 8875 0148 ..U14 WAITS FOR CK OR LF
0036 889i:i ..WITH THE SUGGESTED X,P FROM 4FEH 0R75 8149
0035 8899 ..II COMES HACK TO DEBUG VIA A SEP 0 007S 0150 ..NOW ?I1 AND !M CAN BE USED TO MODIFY
0085 8188 ..IT STORES PAR! OH THE 1802 REGISTERS 0B7S 8151 ..MEMORY AND WHEN USER PROGRAM IS S T A R T E D ,
0036 8181 ..AND BRANCHES 10 88806 8075 8152 ..THESE VALUES WILL Bt TRANSFERRED
0035 0102 ..1114 WAITS NOW FOR CR OR LF 0875 0153 ..INTO THE CDP1802
 198 199
APPENDIX A

Microprocessor Products 8
Solid State CDP1802D *
007S 0154 Division
0155 ..IF THE EXIT 10 UI4 CDP1802CD I
06175 01S6 ..IS CHANUtD A LFITLE BIT
007S ..THE STATE IS DISPLAYED
007S 0158 ..IHMtUIATELY AFTER A D0 IN USER PROGRAM
007S 0159 COSMAC Microprocessor
007S 0160
007b "880BC 0161 LDI 880',PHI RC .SET DELAY POINTER Features:
0078 8LFAC 0162 LI)I 8EF5PI.O RC • Instruction fetch-execute time of 2.5 or 3.75 jus
at VDD = 10 V; 5.0 or 7.5 /^s at VDD = 5 V
8B7B 0163
• Static silicon-gate CMOS circuitry - no minimum
0BXB 0164 LDI HiiSlPHI RE .TIME CONSTANT clock frequency
H07E 800AF. 0165 LU1 B005PLU RE .AND ECHO BIT • Full military temperature range (-55 to +125°C)
HH81 0166 » High noise immunity, wide operating-voltage range
0081 F H167 LDI K815HHI R3 .PREPARE FOR TYPESD • Single voltage supply • Low power
LDI 8005PH) Rl) .TO TYPE • Single-phase clock; optional on-chip « TTL compatible
0B84 f "800BD 0168
40-Lud Dual In- crystal-controlled oscillator • On-chip DMA
0087 h 8 11 AD 0169 LDI HI-ilPLi) Rl! .17 BYTES Lina Ceramic • Simple control of reset, run, and pause
008A 017(4 Packaje ID) • 8-bit parallel organization with bidirectional data bus
KH00B1 LDI fiMkilPHI Rl .TELL n IS A CDP1002D • Any combination of standard RAM and ROM
008D 0172 LDI «11',PLU R1 .?M SEUUENCF CDP1802CD • Memory addressing up to 65,536 bytes
• Flexible programmed I/O mode
00V0 0173
0090 F80HB5; 0174 LUI fietnPHl Rb .PREPARE R5 The RCA-CDP1802 is an LSI COS/MOS • Program interrupt mode
8-bit register-oriented central-processing unit • Four I/O flag inputs directly tested by
0093 K896A5; 01/b LDI A . t l l B A L K J i P L O Rb branch instructions
(CPU) designed for use as a general-purpose
0896 0176 • Programmable output port
SEP Rb .USE R5 AS PC computing or control element in a wide • 91 easy-to-use instructions
0096 0177 BACK:
range of stored-program systems or products. • 16 x 16 matrix of registers for use as
069? U1/8 multiple program counters, data
0179 LDI. B4MPHI Mi .LOAD DISPLAY POINTER The CDP1802 includes alt of the circuits re- pointers, or data registers
0180 LDI fiE0;PLi) RB quired for fetching, interpreting, and exe-
cuting instructions which have been stored controllers. Further, the I/O interface is
009I.) 0181
in standard types of memories. Extensive
0091) 018i' LBR «8H8E .ENi'ER UT4 capable of supporting devices operating in
input/output (I/O) control features are also polled, interrupt-driven, or direct memory-
00A9 0183
provided to facilitate system design.
END access modes.
8184
The COSMAC architecture is designed with The CDP1802D and CDP1802CD are func-
0000
emphasis on the total microcomputer sys- tionally identical. They differ in that the
tem as an integral entity so that systems CDP18020 has a recommended operating
having maximum flexibility and minimum voltage range of 4-12 volts, and the CDP
cost can be realized. The COSMAC CPU 1802CD, a recommended operating voltage
also provides a synchronous interface to range of 4-6 volts. These types are supplied
memories and external controllers for I/O in 40-lead dual-in-line ceramic packages
devices, and minimizes the cost of interface (D suffix).

Fig. 1 — Typical CDP1802 microprocessor system.

The Preliminary Data are intended for
guidance purposes m evaluating the de-
vice for equipment design. The device
is now being designed for inclusion m
our standard line of commercially avail-
able products. For current information
on the status of this program, please
contact your RCA Sales Office.
Information lurmshed by RCA is believed Printed in USA/2-78
to be accurate and reliable. However, no
responsibility is assumed by RCA for its
use; nor for any infringements of patents Trademarks! Registered®
or other rights of third parties which may Marcals) Registrada(s)
result from its use. No license is granted
by implication or otherwise under Supersedes preliminary
patent or patent rights of RCA. data issued 8/77
 200 201

File No. 1023. .CDP1802D,CDP1302CD

CDP1802D, CDP1802CD. . File No. 1023

MAXIMUM RATINGS, Absolute-Maximum Values:

RECOMMENDED OPERATING CONDITIONS at TA = 25° C Unless Otherwise Specified
DC SUPPLY-VOLTAGE RANGE, (Vcc, VDDI For maximum reliability, nominal operating conditions should be selected
(AH voltage values referenced to Vgg terminal)
so that operation is always within the following ranges:
V CC < V DO :
CDP1802D -0.5 to+15 V CONDITIONS LIMITS AT 25"C
CDP1802CD -0.510+7 V
INPUT VOLTAGE RANGE, ALL INPUTS -0.5 to V DD +0.5 V
CHARACTERISTIC Vcc1 VDD CDP1802D CDP1802CD UNITS
DC INPUT CURRENT, A N Y O N E INPUT ±10 mA (V) (V)
POWER DISSIPATION PER PACKAGE (Poh
- - "C
For T A - - 5 5 to+100 • 500 mW
Supply-Voltage Range - - 4 to 12 4 to 6 V
ForT A -+100to+125°C . Derate Linearly at 12 mW/°C to 200 mW Input Voltage Range - - VSS to VCC
VSS to VCC V
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR T A = FULL PACKAGE-TEMPERATURE RANGE 100 mW
Maximum Clock Input Rise or
OPERATING-TEMPERATURE RANGE (TA) -55to+125°C Fall Time, tr or tf 4-12 4-12 1 1 MS
STORAGE TEMPERATURE RANGE (Tstg| -65to+150°C
5 5 5 5
LEAD TEMPERATURE (DURING SOLDERING):
Instruction Time^
Atdistance1/16± 1/32inch (1.59*0.79mm) from case for 1 0 s m a x . +265°C 5 10 4 - MS
(See Fig. 8)
10 10 2.5 -

5 5 400 400
CONDITIONS LIMITS AT INDICATED TEMPERATURES (°C)
CHARACTER- Maximum DMA Transfer Rate 5 10 500 - KBvtes/sec
VCC. UNITS
ISTIC
vo VIN VDD VALUES +25 10 10 800 -
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Max.
5 5 DC - 3 . 2 DC -3. 2
Quiescent Device - - 5 - - - - - 1 100 Maximum Clock Input Frequency,
5 10 DC - 4 - MHz
Current, I L Max. - - 10 - - - - - 10 500
<CL3
MA 10 10 DC - 6.4 -
CDP1802D - - 15 - - - - - - 1000
CDP1802CD - - 5 - - - - - - 500 NOTES:
1: VCC ^V DD ; for CDP1802CD, V DD = VQQ = 5 volts.
Output Low Drive 2. Equals 2 machine cycles — one Fetch and one Execute operation for all instructions except Long Branch and
(Sink) Current, 0.4 0,5 5 1.98 1.89 1.14 0.90 1.5 2.2 -
'OL Min. 3. Lo
mA
(Except XTAL) 0.5 0,10 10 3.70 3.53 2.13 1.68 2.8 5.2 -
XTAL Output
0.4 5 5 132 126 76 60 100 - - fiA
IOL Min.

Output High Drive

(Source Current) 4.6 0,5 5 -0.46 -0.44 ^0.27 -0.21 -0.35 -0.51 • -
mA
IQH Min.
9.5 0,10 10 -1.12 -1.07 -0.65 -0.51 -0.85 -1.3
(Except XTAL)

XTAL Output
lOH Min. 4.6 0 5 -66 -63 -38 -30 -50 _ — MA
Output Voltage - 0,5 5 0.05 - 0 0.05
Low-Level 0,10 10 0.05 0.05
- - 0
VQL Max.
_ V
Output Voltage 0,5 5 4.95 4.95 _
5
High Level,
- 0,10 10 9.95 9.95 10 - Fig. 2 — Typical output high (source) current
VQH Min.
characteristics. Fig. 3 - Typical output low (sink) current
characteristics.
Input Low 0.5,4.5 - 5 1.5 - - 1.5
Voltage 0.5,4.5 - 5,10 1 - - 1
V|LMax. 10
1.9 - 3 - - 3
V
Input High 0.5,4.5 - 5 3.5 3.5 _ _
Voltage 0.5,4.5 - 5,10 4 4 - -
V| L Min.
1,9 - 10 7 7 - -
Input Leakage
Any
Current 0,15 15 +1 - +1 MA
Input -
I IN Max
3-State Output
Leakage Current 0,15 0,15 15 ±1 ±1 ±12 ±12 - ±10-* +1 MA
'OUT Max. flLOAD CAPACITANCE (4CL)-
LOAD CAPACITANCE (Ci_l — EXCEPT
Fig. 4 — Typical translation time vs. load Fig. 5 — Typical change in propagation delay as a
capacitance. function of a change in load capacitance.
 202 203
File No. 1023. .CDP1802D, CDP1802CD CDP1802D, CDP1802CD. .File No. 1023

t t

VDD

NOTE:

MD- MEASURE INPUTS

SEQUENTIALLY
TO BOTH VDD tMD^S
NOTE:
CONNECT ALL UNUSED
MEASURE OUTPUTS
INPUTS TO EITHER

[ FORCE DEVICE 1 SEQUENTIALLY.

VDD SS
INTO DMA OUT CONNECT ALL UNUSED
STATE J INPUTS TO VDO OR ^S

Fig. 11 - Input leakage current test circuit. Fig. 12 - Three-state output leakage (data bus)
IDLE-"00**T M(OOOO) test circuit.
BRANCH • " 370? AT M 18107)
Fig. 6 — Typical maximum clock frequency as a
function of temperature. Fig. 7 — Typical power dissipation as a function of
clock frequency for BRANCH instruction
and IDLE instruction for CDP1802D.

«ooo c
-OCK * /(CL" T
S

'AC MEMORY
UP)

.? .
300C
x « ?'*^ 2
t^&s
^*.'t*
/

«:£§ i
•4 ^ 4 " CC'1 v v D ' v

o ^ *L £ ' S -
~*&£.ll_ x? iS 5V
1 ^j3
S
s t ^ ^
52 ?
t ^
f 't
a
s ^^
IOCC
f 1
^
,/» '^
J
2
4.

C L O C K INPUT T R E O U E N C Y (fCL)-MHl

F/g. 8 — Required memory system address time as a function of instruction time.

NOTES:
1 THIS TIMING DIAGRAM IS USED TO SHOW SIGNAL RELATIONSHIPS
ONLY AND DOES NOT REPRESENT ANY SPECIFIC MACHINE CYCLE
2 ALL MEASUREMENTS ARE REFERENCED TO 5O% POINT OF THE
WAVEFORMS
NOTE 1 S SHADED AREAS INDICATE "DON'T CARE" OR UNDEFINED STATE ;
TEST ANY ONE INPUT WITH ALL OTHER MULTIPLE TRANSITIONS MAY OCCUR DURING THIS PERIOD
INPUTS AT "NOISE" VOLTAGE LEVELS.

Fig. 9 — Noise immunity test circuit. Fig. 10— Quiescent-device leakage current test circuit. Fig. 13 - Timing waveforms.
 204 205
File No. 1023. -CDP1802D,CDP1802CD CDP1802D, CDP1802CD. .File No. 1023

DYNAMIC ELECTRICAL CHARACTERISTICS at TA - 26°C, CL - 50 pF DYNAMIC ELECTRICAL CHARACTERISTICS (confd)

LIMITS UNITS
CHARACTERISTIC VCC vnn CHARACTERISTIC Vrr vnn L IMIT i
(V) (VI Mil). Typ. Max.
(V) (V) Typ Max
Min.
Propagation Delay Time, tp[_^j, tpni_: 5 5 - 300 450 5
Set-Up and Hold Times, tgjj, t^ 5 0 -50 ~
Clock to TPA, TPB 5 10 - 2bO 400 ns t
Data Set Up 10 25 0
10 10 - 150 250
10 10 50 0 ns
5 5 - 800 1200
£ 5 300 150
Clock-to-Memory High-Address Byte 5 10 - 600 900 ns Data Hold 5 10 200 100 -
10 10 - 400 600
10 10 150 75
5 5 - 300 550 E
5 100 0
Ctock-to-Memory Low-Address Byte 5 10 - 250 500 ns DM A Set Up 5 10 125 25 -
10 10 - 150 350
10 10 150 50 ns
5 5 - 300 450 5 5 250 150
Clock to MRD, tp|_H 5 10 - 250 400 ns DMA Hold 5 10 200 100 -
10 10 - 150 300
10 10 150 75
5 5 - 300 450
5 5 100 0
Clock to MRD, tpH|_ 5
10
10
10
-
-
250
150
400
300
ns Interrupt Set Up 5
10
10
10
125
150
25
50
: ns
5 5 - 300 450 5 5 150
Clock to MWR, tpLH. tpHL 5
10
10
10
-
-
200
1bU
300
250
ns Interrupt Hold 5
10
10
10
250
200
150
100
75
-
5 5
_
350 600 5 5 100 0 -
Clock to CPU DATA to BUS 5
10
10
10
-
-
300
200
500
400
ns WAIT Set Up 5
to
10
10
125
150
25
50 _ ns

5 5 _ 400 600 5 0
Clock to State Code 5
10
10
10
-
-
200
150
400
300
ns EF 1-4 Set Up 5
10
5
10
10
100
125
150
25
50
-
ns
5 5 _ 300 700 5 5 250 150
Clock to Q 5
10
10
10
-
-
150
100
400
300
ns EF1-4Hold 5
10
10
10
200
150
100
75
-
Clock to NIO-2), tPLH
5
5
5
10
_
-
450
300
800
600 ns
Pulse Width, t WL 5 5 600 300 -
10 10 - 200 400 CLEAR Pulse Width
10 10 300 50 -
High-Order Memory Address Byte 5 10 0 „ _ 5 5 160 - _
_
f= 4 MHz
CLOCK Pulse Width, t WL 5 10 125 - ns
SetUp,t s u f = 6.4 MHz 10 10 -bO - -
b bC 10 10 80
(See Note) f=
f=
2 MHz
5 MHz
5
10 10 30
-
-
-
-
-
-
Typical Total Power Dissipation
Idle "00" at M(OOOO), C L = 50 pF
f =
f=
2 MHz
4 MHz
5
10
5
10
- 4
60
- mW
High-Order Memory-Address Byte Hold f = 4 MHz 5 10 120
tH f = 6.4 MHz
f = 2 MHz
10
5
10
5
75
200
-
-
-
-
ns Effective Input Capacitance, CIN
Any Input - 5 - pF

Low-Order Memory-Address Hold

f= 5 MHz
f = 4 MHz
10
5
10
10
100
100
-
-
-
- ns
Effective 3-State Terminal Capacitance
DATA BUS - 7.5 - PF
f = 6.4 MHz 10 10 50 - - NOJE: Negative set-up indicates the addresses can change after the falling edge of TPA, as shown below:
 206
File No. 1023.
ARCHITECTURE
The COSMAC block diagram is shown in
Fig. 14. The principal feature of this system is
a register array (R) consisting of sixteen 16-
bit scratchpad registers. Individual registers
in the array (R) are designated (selected) by a
4-bit binary code from one of the 4-bit
registers labeled N, P, and X. The contents of
any register can be directed to any one of the
following three paths:
1. the external memory (multiplexed,
higher-order byte first, on to 8 memory
address lines);
2. the D register (either of the two bytes
can be gated to D);
3. the increment/decrement circuit where
it is increased or decreased by one and
stored back in the selected 16-bit
register.
The three paths, depending on the nature of
the instruction, may operate independently
or in various combinations in the same
machine cycle.
With two exceptions, COSMAC instructions
consist of two 8-clock-pulse machine cycles.
The first cycle is the fetch cycle, and the
second-and third, if necessary—are execute
cycles. During the fetch cycle the four bits
in the P designator select one of the 16 regis-
ters R(P) as the current program counter. The
selected register R(P) contains the address of
the memory location from which the instruc-
MEMORV ADDRESS
Fig. 14 - CDP1802 block diagram.
_CDP1802D, CDP1802CD
tion is to be fetched. When the instruction is
read out from the memory, the higher-order
4 bits of the instruction byte are loaded into
the I register and the lower-order 4 bits into
the N register. The content of the program
counter is automatically incremented by one
so that R(P) is now "pointing" to the next
byte in the memory.
The X designator selects one of the 16 regis-
ters R(X) to "point" to the memory for an
operand (or data) in certain ALU or I/O
operations.
The N designator can perform the following
five functions depending on the type of
instruction fetched:
1. designate one of the 16 registers in R
to be acted upon during register opera-
tions;
2. indicate to the I/O devices a command
code or device-selection code for peri-
pherals;
3. indicate the specific operation to be
executed during the ALU instructions,
types of tests to be performed during
the Branch instructions, or the specific
operation required in a class of mis-
cellaneous instructions (70-73 and 78-
7B);
4. indicate the value to be loaded into P
to designate a new register to be used
as the program counter R(P);
CDP1802D, CDP1802CD.
5. indicate the value to be loaded into X
to designate a new register to be used
as data pointer R(X).
The registers in R can be assigned by a pro-
grammer in three different ways: as program
counters, as data pointers, or as scratchpad
locations (data registers) to hold two bytes
of data.
Program Counters
Any register can be the main program
counter; the address of the selected register
is held in the P designator. Other registers in
R can be used as subroutine program counters.
By a single instruction the contents of the P
register can be changed to effect a "call" to a
subroutine. When interrupts are being ser-
viced, register R(1) is used as the program
counter for the user's interrupt servicing rou-
tine. After reset, and during a DMA oper-
ation, R (0) is used as the program counter.
At all other times the register designated as
program counter is at the discretion of the
user.
Data Pointers
The registers in R may be used as data
pointers to indicate a location in memory.
The register designated by X (i.e., R { X ) )
points to memory for the following instruc-
tions (see Table I):
1. ALU operations F1-F5,F7, 74, 75, 77;
2. output instructions 61 through 67;
3. input instructions 69 through 6F;
4. certain miscellaneous instructions—70-
73, 78.60, FO.
The register designated by N (i.e., R(N))
points to memory for the "load D from
memory" instructions ON and 4N and the
"Store D" instruction 5N. The register
designated by P (i.e., the program counter) is
used as the data pointer for ALU instructions
F8-FD, FF, 7C, 7D, 7F. During these instruc-
tion executions, the operation is referred to
as "data immediate".
Another important use of R as a data pointer
supports the built-in Direct-Memory-Access
(DMA) function. When a DMA-ln or DMA-
Out request is received, one machine cycle is
"stolen". This operation occurs at the end of
the execute machine cycle in the current
instruction. Register R{0) is always used as
the data pointer during the DMA operation,
The data is read from (DMA-Out) or written
into (DMA-ln) the memory location pointed
to by the R(Q) register. At the end of the trans-
COSMAC Register Summary
D 8 Bits Data Register (Accumulator)
OF 1 Bit Data Flag (ALU Carry)
R 16 Bits 1 of 16 Scratchpad Registers
P 4 Bits Designates which register is
Program Counter
X 4 Bits Designates which register is
Data Pointer
207
.File No. 1023
fer, R(0) is incremented by one so that the
processor is ready to act upon the next DMA
byte transfer request. This feature in the
COSMAC architecture saves a substantial
amount of logic when fast exchanges of
blocks of data are required, such as with
magnetic discs or during CRT-display-refresh
cycles.
A program load facility, using the DMA-ln
channel, is provided to enable users to load
programs into the memory. This facility pro-
vides a simple, one-step means for initially
entering programs into the microprocessor
system and eliminates the requirement for
specialized "bootstrap" ROM's.
Data Registers
When registers in R are used to store bytes of
data, four instructions are provided which
allow D to receive from or write into either
the higher-order- or lower-order-byte portions
of the register designated by N. By this
mechanism (together with loading by data
immediate) program pointer and data pointer
designations are initialized. Also, this tech-
nique allows scratchpad registers in R to be
used to hold general data. By employing
increment or decrement instructions, such
registers may be used as loop counters.
The Q Flip Flop
An internal flip flop, Q, can beset or reset by
instruction and can be sensed by conditional
branch instructions. The output of Q is also
available as a microprocessor output.
Interrupt Servicing
Register R(1) is always used as the program
counter whenever interrupt servicing is ini-
tiated. When an interrupt request comes in
and the interrupt is allowed by the program
(again, nothing takes place until the comple-
tion of the current instruction) the contents
of the X and P registers are stored in the
temporary register T, and X and Pare set to
new values; hex digit 2 in X and hex digit 1
in P. Interrupt enable is automatically de-
activated to inhibit further interruptions. The
user's interrupt routine is now in control; the
contents of T may be saved by means of a
single instruction (78) in the memory location
pointed to by R (X). At the conclusion of the
interrupt, the user's routine may restore the
pre-interrupted value of X and P with a single
instruction (70 or 71). The interrupt-enable
flip-ftop can be activated to permit further
interrupts or can be disabled to prevent them.
N 4 Bits Holds Low-Order Instr. Digit
I 4 Bits Holds High-Order Instr. Digit
T 8 Bits Holds old X, P after Interrupt
(X is high byte)
IE 1 Bit Interrupt Enable
Q 1 Bit Output Flip Flop
 208 209
File No. 1023. .CDP1802D, CDP1802CD
CDP1802D.CDP1802CD. .File No. 1023

INSTRUCTION SET TABLE I - INSTRUCTION SUMMARY (CONT'D)

The COSMAC instruction summary is given R(WI.O: Lower-order byte of R(W) OP
in Table I. Hexadecimal notation is used to R(W).1: Higher-order byte of R(W) INSTRUCTION MNEMONIC CODE OPERATION
refer to the 4-bit binary codes. NO - Least significant Bit of N Register
ARITHMETIC OPERATIONS**
In all registers bits are numbered from the Operation Notation
ADD ADD F4 M(R(X|) +O*DF, D
least significant bit (LSB) to the most signi- M|R(N)|»D; R(N) + 1
ADD IMMEDIATE ADI FC M(R(P)| +D*DF, D; RIP) +1
ficant bit (MSB) starting with 0. This notation means: The memory byte ADD WITH CARRY ADC 74 M ( R ( X ) | +D +DF»DF, D
R{W): Register designated by W, where pointed to by R(N) is loaded into D, and ADD WITH CARRY, ADCI 7C M(R(P)) +D +DF*DF, D
W=Nor X. or P R(N) is incremented by 1. IMMEDIATE RIP) +1
SUBTRACT D SO F5 M(R(X))-D*DF, D
SUBTRACT D IMMEDIATE SDI FD M(R(P))-D»DF, D; R(P) +1
SUBTRACT D WITH SDB 75 M(R(X))-D-(NOT DFhDF. D
TABLE I - INSTRUCTION SUMMARY BORROW
(For Notes, see page 13) SUBTRACT D WITH SDBI 7D M(R(P))-D-(NOT DFhDF, D;
OP BORROW, IMMEDIATE RIP) +1
INSTRUCTION MNEMONIC CODE OPERATION SUBTRACT MEMORY SM F7 D-M(R(X)|->DF, D
SUBTRACT MEMORY SMI FF D-M(R(P))*DF, D;
MEMORY REFERENCE IMMEDIATE RIP) +1
LOAD VIA N LDN ON M(R(N))+D; FOR N N O T O SUBTRACT MEMORY WITH SMB 77 D-M(R(X))-(NOT DF)*DF, D
LOAD ADVANCE LDA 4N M(R(N)hD; R(N)+1 BORROW
LOAD V I A X LDX M(R(X))»D SUBTRACT MEMORY WITH SMBI 7F D-M(R(P))-(NOT DFhDF, D
FO
LOAD VIA X AND ADVANCE LDXA 72 M(R(X)hD; R ( X ) + 1 BORROW, IMMEDIATE RIP) +1
LOAD IMMEDIATE LDI F8 M(R(P))»D; RIP) +1 BRANCH INSTRUCTIONS-SHORT BRANCH
STORE V I A N STR 5N D*M(R(N1)
STORE VIA X AND STXD 73 D*M(R(X)I; R ( X ) -1 SHORT BRANCH BR 30. M(R(P))*R(P).0
DECREMENT NO SHORT BRANCH NBR 38* RIP) +1
REGISTER OPERATIONS (SEE SKP)
INCREMENT REG N INC 1N RINI+1 SHORT BRANCH IF D=0 BZ 32 IF D=0, M(R(P))^R(P).0
DECREMENT REG N DEC 2N R(N)-1 ELSE RIP) +1
INCREMENT REG X IRX 60 R ( X ) +1 SHORT BRANCH IF BNZ 3A IF D NOT 0, M(R(P))*R(PI.O
GET LOW REG N GLO 8N R(N).0»D D NOT 0 ELSE RIP) +1
PUT LOW REG N AN D»R(N).0 SHORT BRANCH IF DF=1 BDF 33* IF DF=1, M(R(P)hR(P).0
PLO
GET HIGH REG N GHI 9N R(N).1*D SHORT BRANCH IF POS BPZ ELSE RIP) +1
PUT HIGH REG N PHI BN D»R(N).1 OR ZERO (
SHORT BRANCH IF EQUAL BGE \F
LOGIC OPERATIONS** OR GREATER
OR OR F1 M(RIX)l OR D^D
SHORT BRANCH IF DF=0 3B* IF DF=0, MIRIPIhRIPl.O
OR IMMEDIATE OR I F9 MIRIP)) OR D*D; R(P) +1
SHORT BRANCH IF MINUS BM ELSE RIP) +1
EXCLUSIVE OR XOR F3 MIRIX)) XOR D»D
SHORT BRANCH IF LESS BL
EXCLUSIVE OR IMMEDIATE XRI FB M(RIP)) XOR D»D; RIP) +1 IF 0=1, M(R(P))»R(P).0
SHORT BRANCH IF Q=1 BQ 31
AND 'AND F2 MIR(X)) AND D+D ELSE RIP) +1
AND IMMEDIATE ANI FA MIR(Pl) AND OD; R(P) +1 IF Q=0, M(R(P))-R(P|.0
SHORT BRANCH IF Q=0 BNQ 39
SHIFT RIGHT SHR F6 SHIFT D RIGHT, LSBIDhDF, ELSE R(P) -H
0*MSBID) 34 IF EF1 = 1, M(R(P)hR(P).0
SHORT BRANCH IF EF1 = 1 B1
SHIFT RIGHT WITH SHRC 1 76* SHIFT D RIGHT, LSBIDhDF, ELSE R(P) +1
(1 =V S S)
CARRY DF^MSBID) SHORT BRANCH IF EF1=0 BN1 3C IF EF1=0, M(R(P))-»R(P).0
RING SHIFT RIGHT RSHR ) ELSE RIP) +1
SHIFT D LEFT, MSB(D)*DF, (0= V C C)
SHIFT LEFT SHL FE SHORT BRANCH IF EF2=1 82 35 IF EF2=1, M(R(P))*R(P).0
7E»
OLSB(D)
SHIFT D LEFT, MSBIDKDF.
0=vss) ELSE RIP) +1
SHIFT LEFT WITH SHLC i SHORT BRANCH IF EF2=0 BN2 3D IF EF2=0, M(R(P))»R(P).0
CARRY DF»LSB(D) ELSE RIP) +1
(0-Vcc)
RING SHIFT LEFT RSHL } SHORT BRANCH IF EF3=1 B3 36 IF EF3=1, M(R(P))>R(P).0
(1-Vss) ELSE R(P) +1
THIS INSTRUCTION IS ASSOCIATED WITH MORE THAN ONE SHORT BRANCH IF EF3=0 BN3 3E IF EF3=0, M(R(P)hR(P).0
MNEMONIC EACH MNEMONIC IS INDIVIDUALLY LISTED
(0 = V C C) ELSE RIP) -H
T H E - A R I T H M E T I C OPE RATIONS AND THE SHIFT INSTRUCTIONS
A R E THE ONLY INSTRUCTIONS THAT CAN A L T E R THE OF SHORT BRANCH H= EF4=1 B4 37 IF EF4=1, M(R(P))*R(P).0
AFTER AN ADD INSTRUCTION (1 = VSS) ELSE RIP) +1
DF - 1 DENOTES A C A R R Y HAS OCCUR RED
QF O D E N O T E S A C A R R Y HAS NOT OCCURRED SHORT BRANCH IF EF4=0 BN4 3F IF EF4=0, M(R(P))*R(P).0
AFTER A SUBTRAC T INSTRUCTION
(0= Vcc) ELSE RIP) +1
DF 1 D E N O T E S NO BORROW D IS A TRUE POSITIVE NUMBER
DF 0 DENOTES A BORROW. D IS TWO'S COMPLEMENT
THE S Y N T AX "-INOT DF|" DENOTES THE SUBTRACTION OF THE BORROW »NOTE. THIS INSTRUCTION IS ASSOCIATED WITH MORE THAN ONE
MNEMONIC. EACH MNEMONIC IS INDIVIDUALLY LISTED.
**NOTE THE ARITHMETIC OPERATIONS AND THE SHIFT INSTRUCTIONS
ARE THE ONLY INSTRUCTIONS THAT CAN ALTER THE DF.
AFTER AN ADD INSTRUCTION:
DF = \S A CARRY HAS OCCURRED
DF ••= Q DENOTES A CARRY HAS NOT OCCURRED
AFTER A SUBTRACT INSTRUCTION:
DF • 1 DENOTES NO BORROW. D IS A TRUE POSITIVE NUMBER
DF = 0 DENOTES A BOR ROW. D IS TWO'S COMPLEMENT
THE SYNTAX "- INOT DF) ' DENOTES 1 rtE SUBTRACTION OF THE BORROW
 210 211
File No. 1023. .CDP1802D, CDP1802CD CDP1802D, CDP1802CD. .File No. 1023

TABLE I - INSTRUCTION SUMMARY (CONT'D) TABLE I - INSTRUCTION SUMMARY (CONT'D)

OP OP
INSTRUCTION MNEMONIC CODE OPERATION
INSTRUCTION MNEMONIC CODE OPERATION
BRANCH INSTRUCTIONS-LO MG BRANCH INPUT-OUTPUT BYTE TRANSFER
LONG BRANCH LBR CO M(R(P))*R(P).1 OUTPUT 1 OUT 1 61 MIRIXIV-BUS; RIX) +1; N LINES = 1
MIRIP) +1|+R(P).0 OUTPUT 2 OUT 2 62 M(R(X))»BUS; RIX) +1; N LINES = 2
NO LONG BRANCH NLBR C8* R(P) +2 OUTPUT 3 OUT 3 63 MIRIXD+BUS; RIX) +1; N LINES = 3
(SEE LSKPI OUTPUT 4 OUT 4 64 M(R(X))>BUS; R(X) +1; N LINES = 4
LONG BRANCH IF D=0 LBZ C2 IF D=0, M(R(P))»R(P).1 OUTPUT 5 OUT 5 65 M(R(X)I»BUS; R(XJ +1; N LINES = 5
M(R(P) -H)+R(P).0 OUTPUT 6 OUT 6 66 M(R(X)I»BUS; R(X) +1; N LINES = 6
ELSE RIP) +2 OUTPUT 7 OUT 7 67 M(R(X))*BUS; R(X) +1; N LINES = 7
LONG BRANCH IF D NOT 0 LBNZ CA IF D NOTO, M(R(P))*R|P).1 INPUT 1 INP 1 69 BUS»M(R(X)); BUS+D; N LINES = 1
M(R(P) +1)+R(P).0 INPUT 2 INP 2 6A BUS»M(R(X»; BUS»D; N LINES = 2
ELSE RIP) +2 INPUT 3 INP 3 6B BUS>M(R(XI); BUS>D; N LINES = 3
LONG BRANCH IF DF=1 LBDF C3 IF DF=1. M(R(P)hR(P).1 INPUT 4 INP 4 6C BUS»M(R(X)I; BUS»D; N LINES = 4
M(R(P) +1)->-R(P).0 INPUT 5 INP 5 6D BUS»M(R(X)|; BUS>D; N LINES = 5
ELSE RIP) +2 INPUT 6 INP 6 6E BUS«M(R(X)I; BUS*D; N LINES = 6
LONG BRANCH IF DF=0 LBNF CB IF DF=0. M(R(P))*R|P).1 INPUT 7 INP 7 6F BUS*M(R(X)I; BUS->D; N LINES = 7
M(R(P) +1)->R(P).0
ELSE R(P) +2 Long-Branch, Long-Skip and No Op instructions are the only instructions that require
LONG BRANCH IF Q=1 LBQ C1 IF Q=1, M(R(P))>R(P).1 three cycles to complete (1 fetch + 2 execute).
M(R(P) +1)-R(P).0 Long-Branch instructions are three bytes long. The first byte specifies the condition to
ELSE RIP) +2 be tested; and the second and third byte, the branching address.
LONG BRANCH IF Q=0 LBNQ C9 IF Q=0, M|R|P)hfl|P).1 The long-branch instructions can:
MIRIP) +1V»R(P).0
a} Branch unconditionally
ELSE RIP) +2
b) Test for 0=0 or D=£0
SKIP INSTRUCTIONS c) Test for DF=Oor DF^1
SHORT SKIP SKP 38* R(P) +1 d) Test for Q=0 or Q=l
(SEE NBR) e) effect an unconditional no branch
LONG SKIP LSKP C8* RIP) +2 If the tested condition is met, then branching takes place; the branching address bytes
(SEE NLBR) are loaded in the high-and-low-order bytes of the current program counter, respectively.
LONG SKIP IF D=0 LSZ CE IF D=0, R(P) +2 This operation effects a branch to any memory location.
ELSE CONTINUE
LONG SKIP IF D NOT 0 LSNZ C6 IF D NOT 0, RIP) +2 If the tested condition is not met, the branching address bytes are skipped over, and
ELSE CONTINUE the next instruction in sequence is fetched and executed. This operation is taken for
LONG SKIP IF DF=1 LSDF CF IF DF = 1, RIP) +2 the case of unconditional no branch (NLBR).
ELSE CONTINUE The short-branch instructions are two bytes long. The first byte specifies the
LONG SKIP IF DF=0 LSNF C7 IF DF=0, RIP) +2 condition to be tested, and the second specifies the branching address.
ELSE CONTINUE The short-branch instructions can:
LONG SKIP IF Q=1 LSQ CD IF Q=1, RIP) +2 a) Branch unconditionally
ELSE CONTINUE b) Test for D=0 or D^O
LONG SKIP IF Q=0 LSNQ C5 IF 0=0, RIP) +2 c) Test for DF=0 or DF=1
ELSE CONTINUE d) Test for Q=0 or Q=1
LONG SKIP IF IE=1 LSIE CC IF IE=1, R(P) +2 e) Test the status (1 or 0) of the four EF flags
ELSE CONTINUE f) Effect an unconditional no branch
CONTROL INSTRUCTIONS If the tested condition is met, then branching takes place; the branching address byte
IDLE IDL 00* WAIT FOR DMA OR is loaded into the low-order byte position of the current program counter. This effects
INTERRUPT; M(R(0))»BUS a branch with the current 256-byte page of the memory, i.e., the page which holds the
NO OPERATION NOP C4 CONTINUE branching address. If the tested condition is not met, the branching address byte is
SET P SEP DN N*P skipped over, and the next instruction in sequence is fetched and executed. This same
SET X SEX EN N»X action is taken in the case of unconditional no branch {NBR)
SET Q SEQ 7B 1*0.
RESET Q REQ 7A 0*O The skip instructions are one byte long. There is one Unconditional Short-Skip (SKP)
SAVE SAV 78 T»M(R(X)I and eight Long-Skip instructions.
PUSH X,P TO STACK MARK 79 (X.PhT; (X,PhM(R(2|) The Unconditiona! Short-Skip instruction takes 2 cycles to complete (1 fetch + 1 execute).
THEN P*X; RI2I-1 Its action is to skip over the byte following it. Then the next instruction in sequence is
RETURN RET 70 M(RIX)MX.P); R(X) +1 fetched and executed. This SKP instruction is identical to the unconditional no-branch
•WE instruction (NBR) except that the skipped-over byte is not considered part of the program.
DISABLE DIS 71 M(R(X))>IX,P); RIX) +1 The Long-Skip instructions take three cycles to complete (1 fetch + 2 execute).
0»IE
They can:
#An idle instruction initiates a repeating S1 cycle. The processor will continue to idle a) Skip unconditionally
b) Test for D=Q or D^O d) Test for Q=0 or Q=1
until an I/O request (INTERRUPT, DMA-IN, or DM/V-OUT) is activated. When the
c) Test for DF=Oor DF=1 e) Test for 1E=1
request is acknowledged, the IDLE cycle is terminated and the I/O request is serviced,
If the tested condition is met, then Long Skip takes place; the current program counter
and then normal operation is resumed. is incremented twice. Thus two bytes are skipped over and the next instruction in sequence
*NOTE: THIS INSTRUCTION IS ASSOCIATED WITH MORE THAN ONE is fetched and executed. If the tested condition is not met, then no action is taken.
MNEMONIC. EACH MNEMONIC IS INDIVIDUALLY LISTED.
Execution is continued by fetching the next instruction in sequence.
 212
File No. 1023- _CDP1802D, CDP1802CD
SIGNAL DESCRIPTIONS
BUS 0 to BUS 7 8-bit directional DATA BUS lines. These lines are used for
(Data Bus) transferring data between the memory, the microprocessor,
and I/O devices.
NO to N2 (I/O Lines) Activated by an I/O instruction to signal the t/O control logic
of a data transfer between memory and I/O interface. These
lines can be used to issue command codes or device selection
codes to the I/O devices (independently or combined with
the memory byte on the data bus when an I/O instruction
is being executed). The N bits are low at all times except
when an I/O instruction is being executed. During this time
their state is the same as the corresponding bits in the N
register.
The direction of data flow is defined in the I/O instruction
by bit N3 (internally) and is indicated by the level of the
MRD signal.
MRD = V c c : Data from I/O to CPU and Memory
MRD = V ss : Data from Memory to I/O
EF1 to EF4 These inputs enable the I/O controllers to transfer status
(4 Flags) information to the processor. The levels can be tested by
the conditional branch instructions. They can be used in
conjunction with the INTERRUPT request line to establish
interrupt priorities. These flags can also be used by I/O
devices to "call the attention" of the processor, in which
case the program must routinely test the status of these
flag(s). The flag(s) are sampled at the beginning of every S1
cycle.
INTERRUPT, DMA-IN, These inputs are sampled by the CDP1802 during the
DMA-OUT interval between the leading edge of TPB and the leading
(3 I/O Requests)
edge of TPA.
Interrupt Action: X and P are stored in T after executing
current instruction; designator X is set to 2; designator.P is
set to 1; interrupt enable is reset to 0 (inhibit); and instruc-
tion execution is resumed. The interrupt action requires one
machine cycle (S3).
DMA Action: Finish executing current instruction; R(0)
points to memory area for data transfer; data is loaded into
or read out of memory; and increment R{0).
Note: In the event of concurrent DMA and INTERRUPT
requests, DMA-IN has priority followed by DMA-OUT and
then INTERRUPT.
SCO, SCI,
(2 State Code Lines) These outputs indicate that the CPU is: 1 fetching an instruc-
tion, or 2) executing an instruction, or 3) processing a DMA
request, or 4) acknowledging an interrupt request. The levels
of state code are tabulated below. All states are valid at TPA.
H = V CO L = V S S .
State Code Lines
State Type
SC1 SCO
SO (Fetch) L L
S1 (Execute) L H
S2 (DMA) H L
S3 (Interrupt) H H
TPA, TPB Positive pulses that occur once in each machine cycle (TPB
(2 Timing Pulses) follows TPA). They are used by I/O controllers to interpret
codes and to -time interaction with the data bus. The
trailing edge of TPA is used by the memory system to latch
the higher-order byte of the 16-bit memory address. TPA is
suppressed in IDLE when the CPU is in the load mode.
MAO to MA7
The higher-order byte of a 16-bit COSMAC memory address
(8 Memory Address Lines)
appears on the memory address lines MAO-7 first. Those
bits required by the memory system can be strobed into ex-
ternal address latches by timing pulse TPA. The low-order
byte of the 16-bit address appears on the address lines
after the termination of TPA. Latching of all 8 higher-order
address bits would permit a memory system of 64K bytes.
213
CDP1802D, CDP1802CD. .File No. 1023
MWR (Write Pulse) A negative pulse appearing .in a memory-write cycle, after
the address lines have stabilized.
MRD (Read Level) A low level on MRD indicates a memory read cycle. It can
be used to control three-state outputs from the addressed
memory which may have a common data input and output
bus. If a memory does not have a three-state high-impedance
output, MRD is useful for driving memory/bus separator
gates. It is also used to indicate the direction of data trans-
fer during an I/O instruction. For additional information see
Table I.
Q Single bit output from the CPU which can be set or reset
under program control. During SEQ or REO instruction
execution, Q is set or reset between the trailing edge of
TPA and the leading edge of TPB.
CLOCK Input for externally generated single-phase clock. A typical
clock frequency is 6.4 MHz at V cc = V D D = 10 volts.
The clock is counted down internally to 8 clock pulses per
machine cycle.
Connection to be used with clock input terminal, for an
XTAL
external crystal, if the on-chip oscillator is utilized. The
crystal is connected between terminals 1 and 39 (CLOCK
and XTAL) in parallel with a resistance (10 megohms typ.).
Frequency trimming capacitors may be required at terminals
1 and 39. For additional information see ICAN-6565.
WAIT, CLEAR Provide four control modes as listed in the following truth
(2 Control Lines) table:
CLEAR WAIT MODE
L L Load
L H Reset
H L Pause
H H Run
The function of the modes are defined as follows:
Load
Holds the CPU in the IDLE execution state and allows an
I/O device to load the memory without the need for a
"bootstrap" loader. It modifies the IDLE condition so that
DMA-IN operation does not force execution of the next
instruction.
Reset
Registers I, N, Q are reset, IE is set and O's (Vgg) are placed
on the data bus. TPA and TPB are suppressed while reset is
held and the CPU is placed in S1. The first machine cycle
after termination of reset is an initialization cycle which
requires 9 clock pulses. During this cycle the CPU remains
in S1 and registers X, P, and R(0) are reset. Interrupt and
DMA servicingare suppressed during the initialization cycle.
The next cycle is an SO, S1, or an S2 but never an S3. With
the use of a 71 instruction followed by 00 at memory
locations 0000 and 0001, this feature may be used to reset
IE, so as to preclude interrupts until ready for them. Power-
up reset can be realized by connecting a buffered RC net:
work to CLEAR. For additional information see ICAN-
6581.
Pause
Stops the internal CPU timing generator on the first negative
high-to-low transition of the input clock. The oscillator
continues to operate, but subsequent clock transitions are
ignored.
Run
May be initiated from the Pause or Reset mode functions.
If initiated from Pause, the CPU resumes operation on the
first negative high-to-low transition of the input clock.
When initiated from the Reset operation, the first machine
cycle following Reset is always the initialization cycle. The
initialization cycle is then followed by a DMA (S2) cycle or
fetch (SO) from location 0000 in memory.
 214 215
CDP1802D, CDP1802CD. .File No. 1023
File No. 1023 CDP1802D, CDP1802CD

Vrjrj, Vgg, VQC The internal voltage supply VQQ is isolated from the Input/ 0 1 2 3 5 6 7 0 2 3 4 5 6
(Power Levels) Output voltage supply Vcc so that the processor may
operate at maximum speed while interfacing with various
external circuit technologies, including T^L at 5 volts. VQQ
must be less than or equal to VQQ, All outputs swing from TPB | | | |
Vgs to VCQ. The recommended input voltage swing is
MACHINE CYCLE j CYCLE n | CYCLE In * 11 |
V S S t o V CC-
RUN-MODE STATE TRANSITIONS
INSTRUCTION [ FETCH (SO) | EXECUTE (S1I |
The CDP1802 and CDP1802C CPU state
transitions when in the RUN, RESET, and
MRD | I
LOAD modes are shown in Fig. 15, Each
machine cycle requires the same period of NO-N2 / N - 9- F \R
time, Sclockpulses, except the initialization
cycle, which requires 9 clock pulses. The
execution of an instruction requires either
two or three machine cycles, SO followed by
» 4 ^^^ ' '
a single S1 cycle or two 51 cycles. S2 is the ALLOWABLE MEMORY ACCESS
response to a DMA request and S3 is the
interrupt response. Table II shows the con-
Fig. 15— CDP1802 microprocessor state
ditions on Data Bus and Memory-Address transitions (Run Mode).
lines during all machine states. WRITE CYCLE

n^«-{jTjTjTjirijTjTJTjTjajiruTjTjlr^ "U«r generated sign*I

Fig. 17 — Timing diagram for machine cycle type No. 5.

1 «d<" 1 ™> ' 1 CTCLi,...,

HIGH ADD ] LOW ADDRESS ^»IGH ADDj LOW AODHfSS ^IGH*OOJ LOW ADO CSS ^IGHADO) LOWAODHESS ^ICHADOJ

fEICH <») [ EXECUIt (ill | HtCM ISO! | ExtCUlE 1511 1 FtTCH <K1I

^MEMOHV R f A D C Y C L E —-*^^_ NO- ME-OBV C VCU —K-«"">BV "*" CVCL ( 4. NONMeWORVCVCLt—4- f^"V

] | C CL
1 1 1

CLOCK

TPA

nir, EXECUTE (S1I

N 1- 7

ALLOWABLE MEMORY ACCESS

DATA STROBE'

IMRD • TPB- N|

92CS-29602

Fig. 18 — Timing diagram for machine cycle type No. 6.

 216 217
File No. 1023. .CDP1802D, CDP1802CD CDP1802D.CDP1802CD. .File No. 1023

TABLE II. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES
DATA MEMORV
STATE 1 N MNEMONIC INSTRUCTION OPERATION BUS ADDRESS MRD NOTES0

R(0|
SI RESET JAM:I,N,Q,X,P-0 IE = 1 0 1 A
UNDEFINED
F RST CYCLE AFTER RESET RiO) t
INITIALIZE 0 B
NOT PROGRAMMER ACCESSIBLE UNDEFINED
MSJI iFETCmSOl SO FETCH M(R(P))-»I.N RIPH-1 M(R(P)1 R(P) 0 C

0 IDL IDLE
[Load = 0 (Program Idle)] M(R(0» R (0) 0 D,3
0 M(R(0)) PREVIOUS
[Load- 1 (Load Mode)]
0 E,3
ADDRESS
MWR " N*0 LDN LOADD V I A N M(R(N))--D M(R(N)) R(N) 0 3
MEMORY , 1 N INC INCREMENT R(N)+1 FLOAT R(N) 1 1
2 N DEC DECREMENT jjKNPj FLOAT R(N) 1 1
L VALID OUT! SHORT (BRANCH NOT TAKEN] M(R(P)) RIP} 0
N - 3
3
BRANCH (BRANCH TAKEN] M(R(P)) R(P) 0
4 N LDA LOAD ADVANCE M(R(N))->D RINI+1 M(R(N)} R(NI 0 3
5 N STR STORE VIA N D-"M(R(N|t D R(N) 1 3
0 IRX INC REG X R(X)+1 M(R(XI) RIX) 0 3
NON ME N4ORY CYCLE
6 N-1-7 OUTN OUTPUT M(RIX)HBUS R(X|+1 M|R(XH R(XI 0 6
I/O
92CS-29603 N=9-F INP N INPUT BUS-MIR(XI), D RIX) 1 5
DEVICE

Fig. 19 - Timing diagram (or machine cyle type No. 7. M(R(XI)-(X,P>

0 RET RETURN M(R(X)1 R(X) 0 3
R(X)+I, 1-+IE
M(R(X)MX,P)
1 DIS DISABLE M(R(X)I R(X| 0 3
RIXI + 1; 0-IE
A^-nj~LT\r\j~Lnj~u\ru~u~\j~\^^ 2 LDXA
LOAD VIA X M(R(X))-D
M(R(X)} R(XI 0 3
AND ADVANCE P(X}-1
STORE VIA X D--M<R(X))
3 STXD D R(X) 1 2
AND DECREMENT R(Xt-1
7 4.5,7 - ALU OPERATION MIRIXII R(X) 0 3
JCTION!_
6 - ALU OPERATION FLOAT R|XI 1 1
8 SAV SAVE T-M(R(X)) T RIXI 1 2
(X,P|-T, M(R(2)1
9 MARK MARK T R(2) ! 2
P- X; R(2)-1

S1
A REQ RESET Q Q =0 FLOAT R(PI 1 1

(Exj- 6 SEQ SET Q Q- 1 FLOAT R(P| 1 1

C,D,F ALUOPERATION IMMEDIATE MIRIP1I R(P| 0 3
E ALU OPERATION FLOAT R(XI 1 1
8 N GLO GET LOW R(N| .0-0 R(N) .0 RINI 1 1
9 N GHI GET HIGH R(N1 .1-0 RINI .1 RIN) 1 1
A N PLO PUT LOW D-»R(N).0 D RIN) 1 1
a N PHI PUT HIGH D-R(N) .1 D RIN) 1 1
0,1.2
LONG
3,8,9 ^BRANCH NOT TAKEN] M(R(P)I RIP) 0 4
92CM-29604 A,B
BRANCH
[BRANCH TAKEN] M<R(P|) R(P] 0 4
c 5,6,7
LONG (SKIP NOT T A K E N ] M(RIP)] R(P] 0 4
Fig. 20 - Timing diagram for machine cyle type No, 8. C.D.E
SKIP M(RIP)) RIP) 0
F [SKIP TAKEN] 4

0 7 0 1 3 3 4 5 0 4 NOP NO O P E R A T I O N NO OPERATION M(R(PI) RIP) 0 4

0 N SEP SET P N-P N N RtNl 1 1
e N SEX SETX N-X N N RINI 1 1
0 LDX LOAD VIA X M(R(XI)-*D M(R(Xt) R(X) 0 3
1,2,3
ALU OPERATION MIR(Xl) R(X) 0 3
4,5,7
SHIFT D RIGHT
6 SHR SHIFT RIGHT FLOAT R(X| 1 5
LSBIDI-DF 0-* MSB(D)
LOAD
F 8 LDI M(R(P))-*D R(P)+1 M|R(P)I RIPI 0 3
IMMEDIATE
9,A,B ALU OPERATION
M(R(P|I R(P) 0 3
C.D.F MMEDIATE
E SHL SHIFT LEFT ALUOPERATION FLOAT R(P) 1 1
I/O 1 F,7
N REQUEST DMA IN BUS-M(R(0» R (0)
S2 DEVICE
OUT REQUEST DMA OUT M(R(0))-*BUS M{R(0|) R(O) 0 F.8

X.P-T. 0-IE 1
S3 INTERRUPT FLOAT RIN) 9
2-X, 1-P

NOTES:
92CM-29603 A. IE = 1;TPA,TPB suppressed, stale -* SI E. Suppress TPA, wait for DMA
B. 8US = 0 for entire cycle F. IN REQUEST hai priority over OUT REQUEST
Fig. 21 — Timing diagram for machine cycle type No. 9. C. Next state always SI G. Numbers rsfar to machine cycles types -
D. Wait for DMAor INTERRUPT to timing diagrams, Figs. 16 through 20.
 218 219
File No. 1023. . CDP1802D, CDP1802CD CDP1802D, CDP1802CD. .File No. 1023

OPERATING AND HANDLING these conditions must not cause VDD~

0 K3 20 30 40 50 60 70 80 90 100 110 120 130 I4O 150 160 I TO Vss lo exceed the absolute maximum
CONSIDERATIONS
rating.
Input Signals
1. Handling To prevent damage to the input protec
AM inputs and outputs of RCA COS/MOS tion circuit, input signals should never be
devices have a network for electrostatic greater than VQQ nor less than Vgg.
protection during handling. Recom- Input currents must not exceed 10 mA
mended handling practices for COS/MOS even when the power supply is off.
devices are described in I CAN-6525, Unused Inputs
"Guide to Better Handling and Operation A connection must be provided at every
of CMOS Integrated Circuits." input terminal. All unused input termi-
2. Operating nals must be connected to either VQQ or
Operating Voltage Vss< whichever is appropriate.
During operation near the maximum Output Short Circuits
supply voltage limit, care should be
Shorting of outputs to Vrjrj, VQQ, or
taken to avoid or suppress power supply
turn-on and turn-off transients, power Vss maV damage COS/MOS devices by
supply ripple, or ground noise; any of exceeding the maximum device dissipation.

DIMENSIONAL OUTLINE
SIQNAL NAME JdGMkNA-ME.

> CLOCK i v"•' 4O VQO

CDP1802D, CDP1802CD
CONTROL/ W A I T 2 39
—•* .1 CLEAR 3 38 DMA N "1 I/O
40-Lead Dual-ln-Line Ceramic
«STATE
— f;. gc
0 ^|4^ 37 — bMA our KREOUESTS
36 — INTERRUPT
•*- ~l SCO j 6 35 .— SVR
* M R O —j 7 34
BUS ' 8 33
BUS . 9 32 MA 'I
BUS -—-> (0 31 MA
DATA BUS II 3O
BUS - BUS - — 1 2 29 MA MEMORY
«—» BUS 13 28 i MA ADDRLSS
BUS 14 2 7 — MA
^BUS —15 26 1 MA
25 MAO/ 1
24 • ETT '
1/0
OMMAN DS 1
-f HM N
!!
' '° US .— en _ *'°
, ET3 FLAGS

vss —UQ ai i EF4 j *

INCHES
MILLIMETERS
DIM
MIN MAX MIN. MAX.
A 5030 51 30 1 980 2.020
C 242 393 0.095 0 155
D 043 056 0017 0023
F 1 27 REF. 0.050 REF
G 2 54 BSC 0 100 BSC
H 076 1 78 0030 0070

The photographs and dimensions of each COS/MOS

J 020 030 0008 0012
Dimensions in parentheses are in millimeters and
are derived from ttie basic inch dimensions as in- chip represent n chip when it is part of the wafer. K 318 445 0 125 0 175
dicated. Grid graduations are in mils (JO~^ inch). When the wafer is cut into chips, the cleavage L 14.74 15 74 0580 0620
angles are 57 instead of 90 with respect to the
face of the chip. Therefore, the isolated chip is Whan incorporating RCA Solid State Device* in M - 7° - 7°
equipment, it is recommended that the deiigner
actually 7 mils 10. 17 mm) larger in both dimensions. refer to "Operating Consideration* for RCA Solid P 064 1 27 0025 0050
State Devices", Form No. 1CE-402, available on
request from RCA Solid State Division, Box 3200, N 40 40
Somerville, N. J. 08876.
NOTES
t Ludi with.n 0 13 mm (0 0051 tadiui of iru* pOMlnn

Dimensions and pad layout fofCDP1802 2 Oiimmran ' L" roctflMiof ItMlimlwn locm*dpw*tW
3 Wh«<i ih.i dcvic* 11 tupplwd iota* dipped, ih« rrwuimum
l**d Ihiukrwii (nwrow portion) mill not **cwd 0.013 in.
(0 33 mm)
 220 221
APPENDIX B
CDP1834 CDP1852 CDP1855
1024 x 8 ROM Byte I/O 8-Bit Programmable
Terminal Assignment Diagrams Multiply/Divide Unit

CDP1802 CDP1822 CDP1831

COSMAC ,.;-,•••.;• 256 x 4 RAM 512 x 8 ROM MA7 —I
MA6 — 2
^ 5*1— VDD
23 CSi/CsT— I w 24 — VDO CE
CLEAR
1 28 —v
DD
27 — CN0
MODE — 2 — 5R/SR
Microprocessor '.'../' MAS — 3
MA4 — 4
22 — MA9
2 — NC DIO — 3
23
22 — DI7 CTL
cTi/oT —
26 — CN 1
25 — CI
MA3 — 5 20 — cst DOO — 4 2 — D07
DII — 5 YL 24 — YR
MA2 — € 9 — NC 20 — DI6
DOI — 6 19 — 006
ZL 23 — ZR
CLOCK 1 i ° 4Ol VDD MAI — — C52
fAIT 39 „ XT*[ MA7 — i ^ ^
-_vDD MAO — 8 7 — BUS7 DI2 — 7 I — DI5 5HTFT 22 BUS 7
£~TAR — 38 , UHA~TH MA3 1 ~ 22 — VDD MA6 — 2 23 — CLOCK BUSO — 9 16 — BUS6 002 — 8 1 — DOS
CLK 21 — BUS 6

Q 37 15MTTjuT MA2 2 21 — MA4 MAS — 3 22 — NC BUSI — 10 15 — BUSS DI3 —' 9 — DI4

STB 2O — aus 5
SCI 36 INTI RRUPT MAI — 3 20 — R/W MA4 — 4 2 — CSI BUS2 — 1 14 — BUS4 D03 —' to — DO4
RO/WE" — 1 19 — BUS 4
SCO 35 M*wn MAO 4 1 — csl MA3 — 5 , 20 — CS2 vss — 12 13 — BUS3 CLOCK —' I 1 — cTESR RA 2 1 It — BUS 3
MAS 3 1
MR~rj — 34 TPA
MA6 6
— OD
— CS2
MA2 — 6 ,. 19 — HKD
TOP VIEW VSS-H 12 1 — CS2
RA0 — BUS !
B JS 7 33 , TPB MAI — 7 , IB — CEO TOP VIEW
B US 6 32 , MA7 MA7 7 — DO4 MAO — 8 ' 17 — BUS 7 Vss — 1 S — eus 9
NC = NO CONNECTION tzci-zartT
B US 5 31 , MA6 vss — B — DI4 BUSO — 9 ' •' 16 — BUS6 92CS-2T572 TOP VIEW
B US 4 3O MAS on — 9 — DO3 BUSI — 10 15 — BUSS
B US 3 29 . MA4 DOI 0 — DI3 BUS2 — II 14 — BUS4
DI2 1 — D02 9ZCS-29965R2
B US 2 28 MA3 V<i<; — 12 13 BUS 3
BUS I 27 MA2 TOP VIEW TOP VIEW
BUS 0 26 • MAI
92C5 -27392RI
Vcc — 25 MAO NC«NO CONNECTION SJCG-ZTSB*
N2 24 err
Nl 8 23 ETZ

vss
NO 9 22 EF3
EF4 CDP1835 CDP1853 CDP1856
TAP WIFW
2048 X 8 ROM N-Bit Decoder Bus Buffer (Memory)
92CS-29S 4 CDP1823 CDP1832 Separator
128 x 8 RAM 512 x 8 ROM (
1
v. /
24
1
VDD
:f.
CDP1804 MA6
MAS
2
3
23 — TPA
22 CEI -j ^ ft
i— VDD
COSMAC MA3 5 20 — CS2
CLOCK A
NO 2 5 — CLOCK B
DIG
ort —
~i
2
w i?" — VDD
IS — cs
Microcomputer BUS 0 — ^ ZA —VDD A7 — ~i ^ 24 — VDD MA2 6 i9 MRO
Nl
OUT 0
3
4 3
4 — N2 DOO
DOI
3
4
14
13
— DBO
— DBI
5,QN_AL_NAME ftQHH . NAME, BUS I — 21 — MAO A6 — 23 A8 1 OUT I 5 2 — OUT 4 DO2 5 12 — OB 2
_i ^ si BUS — 22 — MAI A5 — 22 NC BUSQ OUT 2 6 1 — OUT 5 DOS — 6 11 — DB3
BUS — 2 — MA2 NC 9 16 BUS6
CONTROL/ WAIT — 39 — XTSL —* A4 — 21 OUT 3 — 7 10 — OUT 6
Bgs 1 • 10 15 DI2 — 7 10 — KRTJ
* 1 ctTAft — 36 — DUA H 1 i/o BUS — 2C — MA3 A3 20 — C5 BUSS
WflnJOT r REQUESTS BUS — 19 — MA4 BUS2 1 14 BUS4 vss — 8 9 — OUT 7
vss — 8 9 — DI3

r
~\ —
- 19
37 A2 TOP VIEW
CODK - sc 56 — TTTTuJpr) BUS — 18 — MAS 18 • NC 2 13 BUSi TOP VIEW
4. >s SCO — 35 — kIWR > BUS — 17 — MA6 17 i BUS 8 92CS-287Z6
BUSO — TOP VIEW
WKfi — 34 TPA - PULSES CSI — 16 — MWR 92CS-28097
BUS I — 16 — BUS 7 CDPI83S 92CS-383T6
'BUS — 33 — TP CsT — 1 IS — Tlffrj
BUS — 32 MA 7155
BUS 3 — II 14 • BUSS
DATA eus — 30 MA vss — 1 1 3 — CS4
12 13 i BUS 4
BUS OP VIEW «CJ-Z«TQJ

*-*
BUS
BUS
—
—
29 — MA
2B ~
. MEMORY
ADDRESS
TOP V I E W
NO NO CONNECTION
CDP1851 CDP1854A CDP1857
eus —
4
eus —
Z"r MA
26 — MA
»ICS^7S7*RI
Programmable UART I/O Bus Buffer
— tBT — ZS MAO
24 ETT I/O Interface , , Mode 0
i ~~
I/O ETZ J/0
COMMANDS
N —
rpj* FLAGS
^ __
v ss — 20 21 — 4
—^_/~-—i VDD —j T CLOCK
TOP VIEW CLOCK » 40 VDD MODE(VSS) — 39 EPE
9 CDP1824 CDP1833 CS » 39 RD/WE vss — 38 WLSI

•JO A
\j£.v \J
H RAM
lir^lvl 1024 x 8 ROM
1 v/t*t A U 1 ivy IVI
RAO
RAI
»
»
38
37 « TPB
RRD
BUS 7 —
37 WLS 2
36 — SBS
BUSO 4—* 36 4—»A ROY BUS 6 — 35 — PI

CDP1821 BUSI 4—*

8US24—»
35 4—» A STROBE
34 «—»AO
BUS 3
BUS 4 —
— 34
33
RL
BUS
DIG 'r~~vy~~lfL. v

1024 x 1 RAM MA7 — i ^ 241— VDD

BUS34-*
BUS44—»
33 4—* A I
32 4—> A2
BUS 3
BUS 2 —
32
31 —
BUS
BUS
DOQ
2
3
5
4
—
—
CS
DBO
DOI — 4 3 — OBI
MA6 — 2 23 — MUX BUSS 4—1 BUS I — 30 BUS
^ _ 31 4—>A3 Q02 —— 5 2 — 082
v MA5 — 3 22 — CEI BUS* 4—¥ BUS 0 29 — BUS
MA4 — 30 4—»A4 DO 3 6 1 — DB3
MA4 — 4 < 21 — CSI BUS74—» PE — 2B BUS
MA 3 — 2 7 29 4—»A5 DI 2 7 0 -— MRD
MA 2 3 6
-ffOQ
^M^ MA3 — 5 20 — CS2
STEW > 28 4— *A6 FE — 27 — eus i 8 9 -— DI3
c~3 — 1 ^ iT i V DD
MA 1 — 4 5 — c"s~ MA2 — 6 19 — MRD
13 — D I TOP V I E W
MAO — 2 MAO 5 4 — DO
MAI-— 7 18 — CEO BTHT*^ 26 4^87 5FO — 25 00
MAI 3 14 — RWff D7 MAO — 8 17 — BUS7
6 3 — DI BHOY*— ft 25 4 ^B6 R CLOCK — 24 —- SRE
MA2 4 13 — M A9 '•• ' • 06 BUSO — 9 16 — BUS6 BTR 23 — THRU
7 2 — 02 B STROBE 4—* 24 4—»B5
MA3 — 5 12 — M AS D3 B | — 03 8USI — to is — BUSS BO 4—» 23 4— frB4 DA 22 THRE 92CS-2B097
MA4 — 6 M 1 MA7
9 OJ — 04 BUS2 — 1 14 — BUS4 BI4—» 22 4— frB3 20 21 — MR
SOI
MA6 Rlim

VSS — 8 9 '— MAS

TOP VIEW vss 20 21 4—*-B2 TOP VIEW
TOP V I E W
TOP VIEW TOP VIEW
NC = NO CONNECTION iics-2M»<i 92CS-26433RI
92CS-3l9ie
 222 223
CDP1869 CDP1872 CDP18U43
CDP1858 CDP1862 CDP1866 Hi-Speed
Address and Sound 1 K x 8 U V EPROM
4-Bit Latch Color Generator 4-Bit Latch and Decoder Generator 8-Bit Address Latch
Controller Memory Interface

RD- »DO
I 24 -VOD MAO — 1 18 -v DD 01, - 018
RESET — 2 23 - R LUM
MAI — Z 17 —CLOCK DO,—
C0~fi - 3 2 2 -G LUM
CLOCK I 1 MA2 — 3 16 — CEI
B CHR- 4 2 I -GD
MAO —
ENABLE
|, MA2 B LUM — 5 20 -8LG LUM MA3 — 4 15 — CE2
MAI 006
cso — i; MA3 8KG- 6 19 -G CHR MRD- 5 14 -CE3 01,
CSI I — CTD
LD CLK- 7 ! 8 -R CHR MWR — 6 13 -CSO 005
CS2 — CTT
CS3 1 — CTZ STP — 8 I 7 -BKGCHR
A8 — 7 12 -csi
vss — CE3 CLK OUT - 9 16 - BO
A9 8 M Cli2
TOP VIEW 57SC - 0 15 - B U R S T
LUM IN - I 14 -7TAL V SS~
9 tO — CS3 *ADDftSTB

vss- 12 13 - X T A L TOP VIEW

92 C S - 3 I 9 S 3 TOP V I E W 92CS-30747RI
92CS-3I665

CDP1870 CDP1873 CDP27C58

Color Video Generator Hi-Speed 1Kx8UVEROM
CDP1859 CDP1863 CDP1867
4-Bit Latch Programmable 1 of 8 Decoder
4-Bit Latch and Decoder
> ' Frequency Generator Memory Interface
MAO — 1 18 -V
RESET — 16 — VDD
CLOCK — ~i—^—ig" — VDD CLK 2 — IS — OE
MAI — 2 17 — CLOCK
MAO 2 IS EllATO MA2 — 3 16 — CEI
MAI — 3 14 MA2 0£
STR — 13 — DI7 MA3 — 4 15 -CE2 VSAT
4 13 MA3
A6 — 5 12 — CEO 010 — 12 — DI6 BtRTj — 5 14 — CT3 PGM/CE
6 1 _ 7JE1
DI — — 015 MWR — 6 13 — CE4 PAL CMROM - D05
7 10 — CC2
10 — DI4 NTSC CHROM D06
vss — e 9— CT3 DI2 —
A8 — 7 12 -CS
X T A L (CHROMI
TOP VIEW v ss — 8 9 — 013
All
TOP VIEW
92CS-3I696 V SS ~~ 9 10 — AIO

TOP VIEW

.;,':•: .
CONNECTIONS

CDP1861 CDP1864 CDP1868

Video Display 4-Bit Latch and Decoder CDP1871 CDP18U42CD MWS5114
PAL-Compatible Keyboard Encoder 256 x 8 UV EPROM
Controller TV Interface '; Memory Interface 1024 x 4 RAM
INLACE 40 VDO
CLK IN 39 AUD . VDO
CLR OUT 38 CLR IN =1 SHIFT
37 DMAO ]CONTROL
AO
1 ALPHA
_. u __ SC 36 , \fff

CLOCK — ]DEBOUNCE
sc 35
DMA REQ — 2. 23 — CLEAft 1 EFXB
MR 34 TPB MAO —I ^ iel— Vnn
INT REQ — 3 22 — CONTROL A BUS 33 i EVS MAI — 7 — CLOCK 3 Tpg_
] EFXA
SYNC REF 4 21 — CONTROL S BUS V SYNC MA 2 6 — CFT
CDPI864C ] 6US7
LOAD — 5 20 — DI7 BUS 3 MA 3 — 5
COMP SYNC 6 19 — DI6 • BUS 30 CSYNC BUT? — 4 — CT7 ] BUS 6
] BUSS
VIDEO — 7 18 — 015 BUS 29 RED HWR — 3 — CTO
RESET IN — 6 7 — DI4 A8 — ) BUS 4
BUS 28 BLUE 12 — CTT
DISP-STATUS — 9 16 — DI3 BUS 27 GREEN A9 1BUS3
— 012 BUS 26 BCK GW) — CS3 1 BUS 2
OISP ON — 10 5 Vss — 10
DISPOFF — 11 14 — DIf CO 25 BURST
TOP VIEW
isusi
— DIO N2 24 . ALT IBUSffl
vss — Z 13
EF 23 i R DATA JMRO
TOP VIEW
NO 19 22 i B DATA 1NXC
20 2t i 0 DATA ] NXB
vss
]NXA
TOP VIEW
92CS-3I699
 RCA CDP1802 CODIN G F O R M
NAME : . . . . PROGRAM : DATE PAGE
ADDRESS Dl D2 LN LABEL : MNEMONIC OPERAND COMMENTS
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
l/l (/> C/> (/>
ro ro ro ro ix> r o r o r o r o r o r o r o r o r o r o r o r o r o ro no ro ro co
cr> m -&> ro no c o o j r o r o r o t — » i — ' » — * * — * o o o o
O O O O O ro >—* -^ co ro Oo *--i CT\o "-^j cr^ ro »—*
O O -•• O -•- C) —• O =J O O O -•-
C/> o
O 2 *-« —i. —i ro —•- i _-.._..
fD lO fD i—i 3 "S
- • - o n
— 3
CD CD
fD 13 -<• CO Q)
O CXI —•
LO O O
o.
(0
 226 227
APPENDIX E

LIST OF RCA SALES OFFICES - E U R O P E

BELGIUM UJ<
RCA Ltd
RCA S.A. TEL : 02/720.89.80
L i n c o l n Way, TEL : 093.27.85511
M e r c u r e Center TWX : 61566
W i n d m i l l Road, TWX : 24246
rue de 1 a Fusee 100
SUNBURY-ON-THAMES

1130 BRUXELLES
M I D D L E S E X TW16 7HW,
UK
FRANCE

WEST G E R M A N Y
RCA S.A. TEL : 01/603.87.87
rue Fessart 32 TWX : 200144 RCA GmbH
P f i n s t r o s e n s t r a s s e 29 TEL : 08971/43047-049
92100 BOULOGNE TWX : 05-29051
8000 M U N C H E N 70
France W. Germany

ITALY RCA G m b H
J u s t u s - v o n - L i e b i g - R i n g 10 TEL : 04106/2001
RCA SpA TEL : 02/65.97.048-051 TWX : 02-11582
2085 QUICKBORN
Pi azza San M a r c o 1 TWX : 310637
W. Germany

20 122 MILANO
RCA G m b H
Italy
Z e p p e l i n s t r a s s e 35 TEL : 071145/4001-04
TWX : 07-23838
SWEDEN 7302 OSTFILDERN 4
(KENMAT)
RCA I n t e r n a t i o n a l Ltd TEL : 08/83.42.25 W. Germany
Box 3047 TWX : 11485
Hagalundsgatan 8

17103 SOLNA 3
Sweden
 228 229
APPENDIX F

TEKELEC A I R T R O N I C S.A. TEL : 01/534.75.35

A P P O I N T E D RCA D I S T R I B U T O R S - E U R O P E C i t s des Bruyeres TWX : 204552
rue C a r l e Vernet

F - 92310 SEVRES
AUSTRIA
B A C H E R E L E K T R O N I S C H E GER'ATE GmbH WEST G E R M A N Y
TEL : 0222/83.56.460
Rotenmllhlgasse 26 TWX : 131532 A L F R E D N E Y E E N A T E C H N I K GmbH TEL : 04106/6121
Schi 11 erstrasse 14 TWX : 02-13590
A - 1120 VIENNA
2085 QUICKBORN
BELGIUM
G U S T A V B E C K KG TEL : 0911/34961-66
INELCO ( B E L G I U M ) S.A, TEL : 02/216.01.60
E l t e r s d o r f e r Strasse 7 TWX : 06-22334
Avenue des Croix de Guerre 94 TWX : 25441
1120 8500 N U R N B E R G 15
BRUXELLES

ELKOSE GmbH TEL : 07141/4871

DENMARK
B a h n h o f s t r a s s e 44 TWX : 07-264472
TAGE O L S E N A/S TEL : 02/65.81.11
B a l l e r u p Byvej 222 7141 MOGLINGEN
TWX : 35293
P.O. Box 225
RTG E. S p r i n g o r u m G m b H & C o , TEL : 0231/54951
DK - 2750 BALLERUP TWX : 08-22534
Bronnerstrasse 7

FINLAND 4600 DORTMUND 1

T E L E R C A S OY TEL : 90/821.655
SASCO GmbH TEL : 089/46111
P.O. Box 2 TWX : 12-1111 TWX : 05-29829
H e r m a n n - O b e r t h - S t r a s s e 16
SF - 01511 V A N T A A 51
8011 P U T Z B R U N N bei M U N C H E N

FRANCE TEL : 06103/3041

SPOERLE E L E C T R O N I C KG
A L M E X S.A. TEL : 01/666.21.12 O t t o - H a h n - S t r a s s e 13 TWX : 04-17972
rue de 1 ' A u b e p i ne 48 TWX : 250067
6072 D R E I E I C H bei F R A N K F U R T
F - 92160 ANTONY
GREECE
R A D I O E Q U I P E M E N T S A N T A R E S S.A. TEL : 01/758.11.11
S E M I C O N Co TEL 734.353
rue E r n e s t C o g n a c q 9 TWX : 620630
31, V a s s i l e o s Georgiou B' Street TWX 219492
F - 92301 LEVALLOIS-PERRET
A T H E N S 516

J
m
 230 231

HOLLANj)
INELCO Nederland BV TEL : 02977/2.88.55
T u r f s t e k e r s t r a a t 63 T W X : 14693

N - 1431 GD A A L S M E E R
N A T I O N A L ELEKTR O A/S TEL : 02/22.19.00
VEKANO BV TEL : 40/81.09.75 U l v e n v e i e n 75 TWX : 11265
P o s t b u s 6115 TWX : 51804
O K E R N - OSLO 5
N - 5600 HC E I N D H O V E N
PORTUGAL
ICELAND
T E L E C T R A SARL TEL : 68.60.72-75
GEOR6 A M U N D A S O N TEL : 81180 R u a R o d r i g o do F o n s e c a , 103 TWX : 12598
P.O.Box 698 TWX 2108
LISBON 1 -
REYKJAVIK - Iceland
SOUTH AFRICA
ITALY
A L L I E D E L E C T R I C (PTY) L t d TEL : 011/892.1001
E L E D R A 35 SpA TEL : 02/349751 Components Division TWX : 87823
Vi ale E l v e z i a 18 TWX : 332.332 P . O . B o x 6090, D U N S W A R T
I - 20154 MILANO 1508

IDAC E l e t t r o n i c a SpA TEL : 049/66.02.22

Via Turazza 32 TWX : 430353 SPAIN

I - 35100 PADOVA E L E C T R I C A C O M E R C I A L COLOMINAS S.A.TEL 03/243.20.07

Division Novolectric TWX 51433
LASI Elettronica SpA TEL : 02/61.20.441-5 V a l e n c i a 109-111
Viale Lombardia 6 TWX : 331612 B A R C E L O N A 11
I - 20092 C I N I S E L L O BALSAMO
(MI) SISTECO S.A. TEL : 03/321.73.47/92
C o r c e g a 167 03/322.42.05/52
SILVERSTAR Ltd TEL : 02/49.96
B A R C E L O N A 36 TWX : 51990
Via d e i G r a c c h i 20 TWX : 332.189

I - 20146 MILANO
 232 233

SWEDEN
I.T.T. E L E C T R O N I C S E R V I C E S TEL : H a r l o w 0279/26777
FERNER Electronics AB TEL 08/80.25.40 E d i n b u r g h Way TWX : 81525
Snb'rmakarvagen 35 TWX 10312 Harlow
P.O.Box 125 E s s e x , CM20 2DE
161 26 BROMMA
STOCKHOLM JERMYN DISTRIBUTION TEL : Sevenoaks 0732/50144
Vestry Industrial Estate TWX : 95142
LAGERCRANTZ ELEKTRONIK AB TEL 0760-861.20 Sevenoaks
Kanalvagen 5 TWX 11275 Kent
P.O.Box 48
MACRO M A R K E T I N G Ltd TEL : B u r n h a m 06286/4422
19401 UPPLANDS VASBY
396 Bath Road TWX : 847945
SIough
SWITZERLAND
Berks
BAERLOCHER AG TEL 01/42.99.00
P.O.Box 485 TWX 53118 SEMICOMPS NORTHER N Ltd TEL : K e l s o 05732/2366
CH - 8021 ZURICH E a s t B o w m o n t Street TWX : 72692
Kelso
TURKEY R o x b u r g h s h i re
Sco 11 and
TEKNIM COMPANY Ltd TEL 27.58.00
Riza Sah P e h l e v i C a d d e s i 7 TWX 42155
YUGOSLAVIA
KAVAKLIDERE ANKARA
AVTOTEHNA TEL : 317.044
P.O.Box 593 TWX : 31223
UK
Titova 36-X1
C R E L L O N E L E C T R O N I C SL t d . TEL Burnham 06286/4434
L J U B L J A N A 61000
380 B a t h Road TWX 84571
SIough
EGYPT
B e r k s , SL1 6JE
SAKRCO ENTERPRISES TEL : 744440
VSI E L E C T R O N I C S Ltd. P.O.Box 1133 TWX : 93146 SKRCO UN
TEL : H a r l o w 0279/29666
R o y d o n b u r y I n d u s t r i a l Park TWX : 81387 37 Kasr el N i l Street
Horsecroft R o a d Apt. 5
Harlow CAIRO - Egypt
Essex, CM19 5BY