White Paper

POWER INTEGRITY IN SYSTEMS DESIGN: PART 1

March 2010

ABSTRACT

This paper discusses the fundamental requirements of power integrity (PI), and the most important concept used in PI, the network impedance. It answers the questions
commonly asked by digital designers on how a power delivery network (PDN) is represented, how PDN impedance is generally defined, what the target impedance is and
its effective range, and the factors affecting impedance analysis. The paper also addresses the contributions of IC current, package inductance, and on-die capacitance to
PDN impedance analysis.

Author:
Zhen Mu
Mentor Graphics Corporation
8005 SW Boeckman Road
Wilsonville, OR 97070 USA
Phone: +1 800-592-2210 or +1 503-685-7000

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POWER INTEGRITY AND THE POWER DELIVERY NETWORK
Power Integrity, or PI, as a term was first introduced in the early 2000’s. However, the practice of power delivery
in digital system designs has been playing an important role from the beginning: without power properly
delivered, there would be no signals. In a system design, engineers need not only to ensure logic signals be
transferred correctly and timely, but also to guarantee that the system can generate logic signals in the first place.
Figure 1 gives a design flow employed by IBM [7] in the early 80’s, which shows the inter-dependency of signal
and the power delivery designs. It clearly demonstrates that design procedures to control static IR-drop and
power noise are parallel to signal designs.
In 2005, the power delivery panel at the IEEE EMC symposium presented a complete definition of power
integrity for a power delivery network (see Figure 2):
a. A power delivery network (PDN) has Physical
to deliver sufficiently clean power Parameters
l, w, h, a, r, d
supply to ICs;
b. The PDN has to provide low noise Electrical
reference path to signals; and Parameters
c. The PDN should not radiate R, L, C, T

excessively.
This definition is actually the industry Signal Power
Distribution Distribuition
requirements on power delivery designs.
The first requirement, “sufficiently clean DC Drops AC Noise

supply to ICs”, states that an ideal PDN Voltage

should not consume any power itself Tolerance
and a PDN should provide sufficient
Characteristic Circuits
power supply efficiently only to “active Impedance ZC
devices” (ICs). These are the Noise
Tolerance
characteristics of PDN: sufficiency and
efficiency. The requirement on “low
noise reference path for signals” means Performance Net Design Noise Limits
that PDN should not introduce
Loadings Signal Coupled Switching
additional signal integrity (SI) problems Discontinuity Noise Noise
and radiation to the system. In reality, a
Delay Wiring Noise Physical
PDN is the path, or interconnects, from Equation Rules Rules Image
VRM (source of power supply) to ICs
(active devices), which consists of Logical
Computer Aided Design System
boards and packages with planes, routed Connections

traces, and decoupling capacitors. Since

a totally lossless network cannot be Performance
Design Test Build
realized, the task of PDN design is to Verification Patterns Data Analysis
minimize such loss and to provide
Figure 1: A design flow employed by IBM in the early 80’s

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desired voltage levels at ICs, which means for PDN to
have low resistance (at static stage) or impedance (at
AC stage).
Figure 2: PDN as defined by industry representatives
IMPEDANCE OF A POWER DELIVERY
SYSTEM AND ITS TARGET
As stated earlier, a well designed PDN is required to
have low impedance on the delivery path. The
question is: how “low” is enough so that a PDN can
deliver sufficient power supply for ICs to work
properly? To answer this question, we first need to
define the impedance so that a PDN can be
mathematically represented.
Suppose a power delivery system (PDS) comprises the
PDN as a linear network with named nodes and
branches, and current flowing from a VRM through
the PDN to ICs; then the impedance at any location of
that PDN can be defined as following:
(1)
The impedance here is the ratio of actual node voltage
change to the total dynamic current drawn by ICs at
any frequency point. If the total current is normalized
as 1, the node voltage at any location gives the impe-
dance at that node. At a given frequency, when x and y
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are the coordinates of IC power supply pins, the
impedance would be the one seen by an IC component
looking into the PDN, which is what board or system
designers are interested in, and needs to be minimized.
It is important to
emphasize that the PDN
impedance is defined in
frequency domain. Then,
how do we use it in a
digital design which
works with transient
signals in time domain?
Considering that the
power supply for an IC
needs to be steady at a
required DC level and the IC can tolerant certain
variation of DC voltage, the DC voltage level and the
tolerance give the variation range of power supply.
Since the voltage changes in the time domain consist
of frequency components at all frequencies, the goal of
a PDN design can be described by the minimum range
of voltage changes and maximum current drawn by
ICs. This is what we call the target impedance ZT [2]:
(2)
Here, the supply voltage and allowed ripple (in
percent) gives the power supply budget and the current
is the worst-case transient current drawn by ICs
connecting to PDN. Because voltage ripple and the
worst-case transient current can happen over any
frequency range, this makes the target impedance
independent of frequency. In practice, a target
impedance that is effective at all frequencies is not
achievable nor necessary, due to the limited switching
speed of a physical IC. A maximum frequency, fMAX,
must be defined for each particular design, as Figure 3
shows. Obviously, a good PDS design is obtained
when equation (1) is less than, or equal to ZT at all
(x,y) points and, f ≤ fMAX as shown in Figure 4.
 IC POWER PINS, CURRENT PROFILES, AND
THEIR IMPACTS ON PDN IMPEDANCE
When a VRM module is simplified to be the
combination of ideal voltage source plus passive
circuit elements, the PDN circuit, from the voltage
source to IC power pins, becomes a linear network.
ZT Such a linear network becomes multi-port network, as

f
fMAX

Figure 3: The target impedance in equation (2) is

frequency independent ZT

ZACTUAL f
fMAX

ZT Figure 5: The target impedance requirement

changes beyond fmax

shown in Figure 6, when considering the multiple

power pins on a chip. In the frequency domain, an
ideal DC voltage source is equivalent to ground,
f
fMAX which makes all ports of the network formed by IC
power pins. In reality, these ports (Test points 1 and 2
Figure 4 A good PDN design: meeting target impedance

In the region of f > fMAX , the target impedance can

get higher, as Figure 5 shows, to avoid over-design.
P1 Pn+1
Because the voltage ripple is caused by the
combination of the switching currents of all ICs, to P2
N-port Pn+2
Network
which a PDS provides power, the term “current” in
equation (2) represents actually the total allowable PN
Pn
current to switch at the same time. It does not identify
when and where individual switching current occurs.
From this point, the target impedance in (2) is rather
Figure 6 A multi-port linear network
pessimistic. In other words, a design meeting the
target impedance of (2) may not be an efficient one.

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as illustrated in Figure 2) represent the end points of a
power delivery path and the locations where proper
voltage levels need to be maintained. As in the typical
case of equation (1), when node coordinates are at the
IC power pins, it is the self impedance and transfer
impedance of the multi-port network that have to meet
the target impedance requirement.
It is worth of pointing out that the PDN impedance
based on the assumptions above is determined only by
the physical structure and port locations of the power
delivery path. This is the same way the impedance
matrix of a multi-port linear network is derived. This
is the characteristics of a PDN and is not dependent on
supply voltage or IC current draw. It is also the reason
that all PI simulation tools do not use actual IC current
to obtain PDN impedance.
Then, what is the role of IC current in PI analysis? IC
current consists of two parts, DC current and dynamic
current (or switching current). DC current provides the
chips with proper working bias voltage, while dynamic
current occurs only when elements in the chip change
states. In this paper, we will be concentrating on the
discussion of the dynamic current.
The answer is “Yes”, under the condition that the
spectrum of the switching current in frequency domain
becomes insignificant (or dies down) for all
frequencies greater than fmax. Figure 7 gives an
example of switching current as a pulse function in
time domain and its resulting spectrum in the
frequency domain.
Suppose the impedance and current spectrum at one
port (one IC power pin) is Zp(f) and Ip(f), then the
voltage in frequency domain at the corresponding port
can be calculated as: Vp(f) = Zp(f) x Ip(f) at any
frequency point.
The time domain voltage Vp(t) can be derived by
applying an inverse Fourier Transform to Vp(f).
If Zp(f) and Ip(f) satisfy Zp(f) < ZT and Ip(f) < Imin for
f < fMAX, Vp(t) is guaranteed to be within the voltage
ripple limit.
The example above in fact presents a way to estimate
maximum frequency for target impedance. It is easy to
understand why: if there is no current beyond fMAX,
there would be no reason to keep low impedance at
those frequency points.

In high speed digital designs, chips switch their states In summary, the actual IC current does not affect PDN
in sequence. Therefore, all switching current has its impedance. It, however, can help determine the upper
profile in time domain. When switching current with a limit of target impedance of a PDN.
certain profile happens, it means a time
variation current source is applied to a PDN at
one or several ports (IC power pins). This
current induces voltage drops across PDN,
which reveals the actual voltage delivered to a
particular chip during its state changes.
The question now is: with a PDN designed to
meet the pre-defined target impedance in the
frequency domain and known switching
current profiles at all IC power pins in time
domain, would the voltage change caused by
switching current at IC power pins be
guaranteed within the allowed voltage ripple Figure 7 A pulse function in the time domain and its
spectrum in frequency domain
budget?

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The last question on IC current would be where can a include on-die capacitance in PDN impedance
PDN designer obtain switching current profiles? As analysis, a capacitor parallel to the IC current source
discussed earlier, the switching current represents the can be connected. Accounting for such capacitance has
dynamic power consumption of each chip, which the same disadvantage as for package inductance.
consists of a core and I/Os. Considering that the Similar options should be considered in PI tool
simulation tools for boards or packages have no access designs.
to the IC database, and the chip structure is generally
SUMMARY
beyond the scale of board/package tools’ solving
Although Power Integrity is relatively a new term in
capacity, the best approach of getting accurate
high-speed digital design and analysis, its concept has
switching current profile is to contact IC
been used in designs for many years. The goal of
manufacturers who own power analysis tools and
power integrity is to have a PDN provide sufficient
measurement equipment for chips. Fortunately, IC
power to ICs efficiently, without introduce additional
manufacturers are willing to provide such information
SI or EMI problems. The important means to
to satisfy their customers, the system designers.
designing a good PDN is to make PDN impedance
IC AND PACKAGE PARASITICS EFFECTS ON below a pre-defined target impedance. Designers need
PDN IMPEDANCE to understand the following:
The above discussion about PDN impedance assumes a. A PDN design is actually performed in frequency
that a power delivery path ends at the BGA of a domain;
component mounted on a printed circuit board, and IC b. The PDN impedance and target impedance are both
current is drawn directly at BGAs. In reality, the actual defined in frequency domain;
component on the board includes chip and package, c. Target impedance definition is relatively
and BGAs only connect to package. Therefore, pessimistic;
d. IC current profiles do not affect PDN impedance,
interconnects on the package for power distribution is
but can help determine the upper limit of its target;
also on the power delivery path and becomes part of e. The PDN should include the effects of package
the PDN. Generally, interconnects on a package are inductance and on-die capacitance, but be aware of
inductive, and introduce additional impedance to the the associated disadvantages.
PDN on the board. If the total inductance on package
power nets is available, it can be included into PDN
impedance by connecting the inductance in series at
the BGAs for IC power supplies. The disadvantage of
including the package inductance is that the PDN
impedance becomes “chip-dependent”. If one
component is replaced by another, the impedance of
the entire PDN needs to be re-analyzed. The best way
to cover both cases is to equip PI tools with user
preferred options regarding package effects.
Besides package inductance, ICs have on-die
capacitance which can present at IC power pins and
can be resonant with rest of the PDN impedance. To

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REFERENCES
[1] Mu, Z., Discussing impedance distribution with
multiple stimulating sources in power distribution
system design and simulation, EPEP2008, Oct. 2008.
[2] Smith, L. D., Anderson, R. E., Forehand, D. W.,
Pelc, T. J., and Roy, T., Power distribution system
design methodology and capacitor selection for
modern CMOS technology, IEEE TRANS. Advanced
Packaging, Vol. 22, No. 3, August 1999.
[3] Mu, Z., Power delivery system: sufficiency,
efficiency, and stability, IEEE International Symp.
ISQED, March 2008.
[4] Chua, L. and Lin, P., Computer aided analysis of
electronic circuits: algorithms and computational
techniques, Prentice-Hall, 1971.
[5] Mu, Z., Simulation and modeling of power and
ground planes in high speed PCB designs, IEEE
International Symp. Circuits and Systems, May 2001.
[6] Wetmore, P., Wang, B., and Chua, F., Simulation of
ground bounce in multilayer packages and PCBs,
EPEP1998, Oct. 1998.
[7] Davidson, E. E., Electrical design of a high speed
computer package, IBM J. RES. Develop. Vol. 26 No.
3, May 1982.

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