Вы находитесь на странице: 1из 8

DAC.COM KNOWLEDGE CENTER ARTICLE www.dac.com

A Comprehensive ESD Protection Design Flow Utilizing A Suite of ESD Verification Tools in Advanced
A Comprehensive ESD Protection Design
Flow Utilizing A Suite of ESD Verification
Tools in Advanced Technologies
Mujahid Muhammad, Robert Gauthier, Junjun Li, Ahmed Ginawi, James
Montstream, Souvick Mitra, Amol Joshi, Karen Henderson, Nicholas
Palmer, Brian Hulse
IBM Corp., Essex Junction, VT USA
Notice of Copyright
This material is protected under the copyright laws of the U.S.
and other countries and any uses not in conformity with the
copyright laws are prohibited. Copyright for this document is
held by the creator — authors and sponsoring organizations —
of the material, all rights reserved.

This document has been submitted to, and reviewed and posted by, the editors of DAC.com. Please recycle if printed.

DAC.COM KNOWLEDGE CENTER ARTICLE www.dac.com

Page 2 of 8

ARTICLE: ESD Protection

A Comprehensive ESD Protection Design Flow Utilizing A Suite of ESD Verification Tools in Advanced Technologies

Mujahid Muhammad, Robert Gauthier, Junjun Li, Ahmed Ginawi, James Montstream, Souvick Mitra, Amol Joshi, Karen Henderson, Nicholas Palmer, Brian Hulse

IBM Corp., Essex Junction, VT USA

Abstract— We review an ESD protection design flow and supporting design/verification tools. ESD tested hardware results show the excellent predictive capability of this design flow and supporting tools.

Index Terms— Electrostatic discharge, ESD design flow, ESD design tools, ESD simulation, ESD hardware testing.

DAC.COM KNOWLEDGE CENTER ARTICLE www.dac.com

Page 3 of 8

I. INTRODUCTION

As technology scaling continues, meeting product electrostatic discharge (ESD) targets has become even more challenging. This is partly due to the fact that even as on-chip dimensions are shrinking, the current handling capability of the ESD protection device needs to remain constant to meet typically fixed ESD qualification target levels. Process and design parameters that have made meeting ESD targets very difficult include channel length scaling, gate oxide scaling, and increasing metal sheet resistances. Hence, the design of ESD protection devices must be continuously verified as a chip is being designed. A successful first-time right ESD protection strategy for any integrated circuit is only possible when ESD protection evaluation and verification has been done at every stage of the overall integrated-circuit design flow. This evaluation must ensure that a robust current handling, low resistance, desired discharge path exists for conduction of ESD current between any two pads. It must also be ensured that during an ESD event, the voltage drops across any internal circuit device should not lead to failure of that device due to conduction of ESD current through this undesired discharge path. Figure 1 shows a typical ESD protection strategy implemented in an integrated circuit. The figure shows an I/O signal pad connected with ESD diodes to the power and ground buses. An ESD protection device (ESD power clamp) is also connected between the power pads and the ground pads. Figure 1 also shows the desired and undesired paths for ESD current flow for a positive ESD zap on the I/O signal pad with reference to the ground pad. As can be seen, the desired ESD discharge path is through the ESD diode and ESD power clamp devices in the circuit. Such a robust ESD protection should be enabled for possible ESD events on all pads with reference to all other pads in the integrated circuit.

Vdd ESD Internal Power Circuit Clamp I/O Pad ESD Diode Gnd Desired Path
Vdd
ESD
Internal
Power
Circuit
Clamp
I/O Pad
ESD Diode
Gnd
Desired Path

Undes ir ed P at h desired Path

I/O Pad ESD Diode Gnd Desired Path Un des ir ed P at h Figure 1:

Figure 1: Typical diode-based ESD protection strategy showing desired and undesired path for an ESD event on an I/O signal pad with the ground pad referenced.

Figure 2 shows further details of this ESD discharge path. It should be noted that in addition to determining appropriately sized ESD protection devices, the effective power bus resistances between the ESD devices connected to the I/O signal pad and the ESD power clamp connected to the power pad are also a crucial aspect of the discharge path. A large power bus resistance R VDDeff would result in a large voltage drop across the power bus, directly leading to increased I/O signal pad voltage. If this voltage drop is greater than the snapback voltage of the driver NFET connected to the same pad, the driver NFET will snapback and provide a path for ESD current flow. I/O damage therefore results because the driver NFET is unable to handle this ESD current [1].

DAC.COM KNOWLEDGE CENTER ARTICLE www.dac.com

Page 4 of 8

R VDDeff Pre-drive circuits I/O Pad R VSSeff Power Clamp
R
VDDeff
Pre-drive
circuits
I/O Pad
R
VSSeff
Power Clamp

Figure 2: Details of an ESD discharge path during a positive human body model (HBM) ESD event on the I/O signal pad with the ground pad being referenced.

II. ESD Protection Design Flow

As described in the previous section, detailed analysis is required on all pads to ensure a robust ESD protection design on the complete integrated circuit part. This calls for a very comprehensive ESD protection design methodology from the initial cell schematic level to the final chip layout level. While use of an ESD design rule checking (DRC) capability has been the typical practice in industry [2], this is not the appropriate tool to verify all the requirements, and cannot be used until layout level. Appropriate ESD design and verification tools must be available at each level of the design process. Figure 3 shows a comprehensive ESD protection design flow starting from the cell/macro schematic level and ending at the full-chip layout level. At the cell schematic design stage, the discrete ESD devices for the signal pads and power pads are selected from the ESD physical design kit (PDK) based on I/O pad requirements for leakage, capacitance, area and other parameters. This ESD PDK has discrete and flexible parameterized cell (pcell) ESD devices along with their schematics and their model libraries. Once these ESD devices are added to the overall I/O cell schematic, a cell schematic level ESD topology checking (schematic echeck) tool is used to check the basic presence and design parameters of these ESD devices. Next, ESD schematic optimization is performed by running schematic-level ESD simulations on these schematics to verify the robustness of the ESD devices and to ensure that there is no breakdown of internal circuit devices during an ESD event. Once these checks are completed at the cell schematic level, we move to the cell/macro layout stage.

ESD Cell Schematic ESD Download Device Schematic Schematic Topology ESD PDK Selection Check Optimization
ESD
Cell
Schematic
ESD
Download
Device
Schematic
Schematic
Topology
ESD PDK
Selection
Check
Optimization
Level
Cell
Layout
Extracted
ESD Current
Level
ESD
Density
ESD DRC
Simulation
Checking
Full Chip
Cross Domain
Schematic
ESD checking
Level
Full Chip
Power/Gnd
ESD Current
Layout
Resistance
Density
ESD DRC
Level
Extraction
Checking

Figure 3: Details of the ESD design flow highlighting the tools used at various levels of the design process.

DAC.COM KNOWLEDGE CENTER ARTICLE www.dac.com

Page 5 of 8

At the cell/macro layout level stage, a DRC tool is used to check certain ESD design rules that cannot be checked in the initial cell schematic level stage. This check is followed by a back-end-of- line (BEOL) check that ensures robust wiring between the pads and the ESD protection devices, using a current density-based checking tool. In addition, a layout extraction-based simulation can also be completed at this stage in order to obtain more accurate ESD simulation results. Moving to the full-chip schematic level, we check for potential ESD failure regions that can occur due to creation of a vulnerable undesired discharge path when individual cells are brought together for the complete chip. One important example would be the mitigation of potential cross-domain issues when a particular device is connected between two different power domains. Finally, at the full-chip layout stage, the DRC and the current-density tools are run again to ensure ESD robustness at the chip level too. In addition, we also extract and analyze the power and ground bus resistances between the I/O cells and the power cells to ensure that these resistances are within the design limits that were specified during ESD simulation.

III. ESD Design/Verification Tools Used and Examples

In this section, several key ESD tools used in the design flow are described in some detail. A schematic level checking tool is used to check the basic topology of the ESD protection circuit. Such a tool is appropriate for checking the presence of the ESD devices, the minimum design parameters of these ESD devices, and any other ESD-specific requirement that can be checked at the schematic level. It is also not necessary for designers to wait until the later layout level stage to check these requirements. Figure 4 shows a snapshot of schematic level checking tool run and the associated error report. It shows an I/O pad connected to the primary (or HBM) ESD protection devices and single NFET and PFET driver devices. Figure 4 also highlights the single NFET driver that fails a specific check requiring any NFET driver connected to an I/O pad to be a stacked (or cascaded) NFET.

connected to an I/O pad to be a stacked (or cascaded) NFET. Figure 4: Snapshot of
connected to an I/O pad to be a stacked (or cascaded) NFET. Figure 4: Snapshot of

Figure 4: Snapshot of a single NFET driver highlighted as an error and the error message when the schematic checking tool is run (rule requires a stacked NFET driver to be connected to the I/O pad).

Once the basic ESD topology is verified, a schematic-level simulation tool is used for comprehensive design and verification of ESD robustness on any given pad [3]. The ESD devices used in the schematic are represented by extended high-current ESD models which capture their behaviors during an ESD event. In addition, the internal devices are represented by ESD shell models that capture the devices’ behaviors during an ESD event. By running simulations to the desired ESD

DAC.COM KNOWLEDGE CENTER ARTICLE www.dac.com

Page 6 of 8

targets, this tool can highlight any failures either in the ESD devices themselves or in the internal devices connected to the same pad. Figure 5 shows a flowchart of all the automated steps performed by the ESD simulation tool. The tool provides great flexibility to designers, allowing them to vary various ESD design parameters as they run simulations, and to come up with an ESD protection strategy that is best for ESD and normal operation.

I/O, analog core, or macro schematic design

operation. I/O, analog core, or macro schematic design Design update and optimization ESTEEM Pre-simulation
Design update and optimization
Design update
and optimization

ESTEEM

Pre-simulation setup

Generate ESD-enabled full compact model library (ESD shell models attached to base MOSFET models)

Chip level bus resistances and power clamps added to schematic/netlist if not already included

Setup standard ESD stimulus sources to resemble HBM, MM and CDM events

Post-simulation Report

Output log file parser; generate ESD report on simulated ESD events

Schematic back annotation (highlight failure device; failure path; failure type)

(highlight failure device; failure path; failure type) Industry Standard Circuit Simulator (exit on ESD failure)

Industry Standard Circuit Simulator (exit on ESD failure)(highlight failure device; failure path; failure type) Simulator output log Figure 5: Flow chart of the

Simulator output logIndustry Standard Circuit Simulator (exit on ESD failure) Figure 5: Flow chart of the automated st

Circuit Simulator (exit on ESD failure) Simulator output log Figure 5: Flow chart of the automated

Figure 5: Flow chart of the automated steps done by the ESD simulation tool.

Once these schematic-level checks are completed, designers proceed with the layout work on their cells. At this layout level, an ESD DRC tool coded is used to check various ESD DRC rules such as the presence of parasitic bipolar paths in the layout, the presence of latchup guardrings, the design dimensions of these guardrings, etc. Since the presence of these parasitics are not detected in the schematics, they must be checked at the layout level. Figure 6 shows an example of such a parasitic formed on a diffusion connected to the pad. Since this parasitic forms an undesired weak ESD discharge path, it is necessary to catch such layout violations.

Negative Discharge TO DRIVER TO PAD GND OTHER CIRCUIT N+ N+ P+ N+ STI N-WELL
Negative
Discharge
TO DRIVER
TO PAD
GND
OTHER
CIRCUIT
N+
N+
P+
N+
STI
N-WELL RESISTOR
N-WELL of PFET
P- WAFER
ESD rule

Figure 6: Cross-section illustration of the parasitic bipolar that can occur when an N-well connected to an I/O pad is too close to another N-well connected to a different pad.

DAC.COM KNOWLEDGE CENTER ARTICLE www.dac.com

Page 7 of 8

A current density checking tool is used next to verify the robustness of the BEOL connection between pads and ESD devices, or between ESD devices. This tool performs static current density analysis on each pad using the maximum allowed current density values for each BEOL level, relevant to a given ESD event. Figure 7 shows an example reported failure. A BEOL region is highlighted where the current density is higher than the allowed maximum. Figure 8 shows a physical failure analysis (PFA) image of the same region after an ESD test. As can be seen, the failure report from the current density checking tool correlates very well with the PFA image.

checking tool co rrelates very well with the PFA image. Metal >200% >150% >125% >100% Figure

Metalchecking tool co rrelates very well with the PFA image. >200% >150% >125% >100% Figure 7:

>200%tool co rrelates very well with the PFA image. Metal >150% >125% >100% Figure 7: Screen

>150%co rrelates very well with the PFA image. Metal >200% >125% >100% Figure 7: Screen shot

>125%very well with the PFA image. Metal >200% >150% >100% Figure 7: Screen shot of the

>100%well with the PFA image. Metal >200% >150% >125% Figure 7: Screen shot of the result

Figure 7: Screen shot of the results of the current density-based tool run, showing regions with greater than allowed maximum current densities in a metal bus.

than allowed maximum current densities in a metal bus. Figure 8: Optical image of a part

Figure 8: Optical image of a part after failure analysis, showing regions of BEOL failure matching the failure regions predicted by the current density-based tool.

Once cell layouts are complete without any errors from the cell-level checking tools, designers can put together various different cells to form a complete integrated circuit. At this stage, we apply tools that are crucial to be run at the full-chip schematic level. Figure 9 shows results of a cross- domain schematic checking tool run. Here, the devices are connected across two power domains. The devices whose source and drain are connected to one domain but whose gates are connected to another domain are vulnerable during ESD events. PFA imaging of an ESD failure has demonstrated that such cross-domain devices fail if additional protection is not designed. A full-chip schematic-level tool can detect such a device. Another example use of this tool would be to detect the absence of ESD devices between two different domain (in two different cells) ground pads.

DAC.COM KNOWLEDGE CENTER ARTICLE www.dac.com

Page 8 of 8

DAC.COM KNOWLEDGE CENTER ARTICLE www.dac.com Page 8 of 8 Figure 9: Screen shot of the result
DAC.COM KNOWLEDGE CENTER ARTICLE www.dac.com Page 8 of 8 Figure 9: Screen shot of the result

Figure 9: Screen shot of the results of the cross-domain schematic checking tool and the error report, highlighting an NFET device whose terminals are connected to two different power domains.

In the final full chip layout level of design, ESD DRC and current density checks are run on the layout to ensure the absence of ESD DRC errors, and that the BEOL wiring is robust in the final layout. A Power/Ground bus resistance extraction tool is also run at this stage to ensure that the power bus resistances are within the limits specified and assumed in previous ESD simulations [4].

IV.CONCLUSION

We have described an ESD protection design flow and a suite of ESD tools to check and verify ESD robustness at four stages of a standard design flow. Usage of these tools is described. The tool and flow functionality have been verified using ESD testing and physical failure analysis on various product chips.

REFERENCES

[1] M. Muhammad, R. Gauthier, K. Chatty, J. Li and C. Seguin, “Failure Analysis of I/O With ESD Protection Devices in Advanced CMOS Technologies”, Proc. IPFA Symposium, 2007, pp. 276-279.

[2] T. Smedes, N. Trivedi, J. Fleurimont, A. J. Huitsing, P. C. de Jong, W. Scheucher and J. van Zwol, “A DRC- based check Tool for ESD Layout Verification”, Proc. EOS/ESD Symposium, 2009, pp. 4A.2-1 – 4A.2-9.

[3] J. Li, S. Joshi, R. Barnes and E. Rosenbaum, ”Compact Modeling of On-Chip ESD Protection Devices Using Verilog-A”, IEEE Trans. on CAD 25(6) (2006), pp. 1047 – 1063

[4] C. J. Brennan, J. Kozhaya, R. Proctor, J. Sloan, S. Chang, J. Sundquist and T. Lowe, ”ESD Design Automation for a 90nm ASIC Design System”, Proc. EOS/ESD Symposium, 2004, pp. 166-173.