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Профессиональный Документы
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1. Design for Moore’s Law 2. Use Abstraction to Simplify Design 3. Make the Common Case Fast
4. Performance via Parallelism 5. Performance via Pipelining 6. Performance via Prediction 7. Hierarchy of
Memories 8. Dependability via Redundancy
Exponent: 11 bits
5. What is a guard bit and what are the ways to truncate the guard bit?
Guard bits are extra bits which are produced during the intermediate steps to yield
maximum accuracy in the final results.
1.Chopping
.Rounding procedure
6. What are R-type instructions?
Add r1, r2,r3 is the R – type instruction – the source operands and destination operand is registers.
11 (a) What is an addressing mode? Explain the various addressing modes with suitable examples (13)
Addressing mode is the way of representing the location of the operand.
Various addressing modes:
1. Direct add mode
2. Indirect add mode
3. Immediate add mode
4. Register add mode
5. Register add mode
6. Register indirect add mode
7. Displacement add mode - 3 marks
Explanation of above addressing modes - 10 marks
(OR)
(b) Discuss about the various techniques to represent instructions in a computer system (13)
Representing the instruction :
Representing instruction in 32 bit format
Representing instruction in 64 bit format
One addressing
Two addressing
Three addressing
Zero addressing
Stack addressing - 3 marks
Explanation with example - 10 marks
12 (a) Multiply following pair of signed numbers using Booth’s bit pair recoding of multiplier. A = +13
(Multiplicand) And B = -6(Multiplier)
(13)
Using above algorithm the problem will be solved . - 13 marks
(OR)
(b) (i) Design non restoring division with example. (7)
Algorithm for Non-restoring division is given in below image :
Flow chart with example problem - 13 marks
(ii)Explain how floating point addition is carry out in a computer system. Give an example for a binary
Floating point addition. (6)
- 13 marks
13 (a) What is pipelining? Discuss about pipelined data path and control. (13)
A single-cycle datapath, which can be partitioned (subdivided) into functional units as shown in Figure 5.2. Because the single-
cycle datapath contains separate Instruction Memory and Data Memory units, this allows us to directly implement in hardware
the IF-ID-EX-MEM-WB representation of the MIPS instruction sequence. Observe that several control lines have been added,
for example, to route data from the ALU output (or memory output) to the register file for writing. Also, there are again three
ALUs, one for ALUop, another for JTA computation, and a third for adding PC+4 to compute the address of the next instruction.
13 Marks
(OR)
(b) Briefly explain about various categories of hazards with examples (13)
There are situations, called hazards, that prevent the next instruction in the instruction stream from being executing during its
designated clock cycle. Hazards reduce the performance from the ideal speedup gained by pipelining.
Structural Hazards. They arise from resource conflicts when the hardware cannot support all possible combinations
of instructions in simultaneous overlapped execution.
Data Hazards. They arise when an instruction depends on the result of a previous instruction in a way that is
exposed by the overlapping of instructions in the pipeline.
Control Hazards.They arise from the pipelining of branches and other instructions that change the PC.
4 marks
Explanation on above 9 marks
14. (a) Explain the basic MIPS implementation with necessary multiplexers and control line. (13)
Explanation and diagram - 13 marks
(OR)
(b)Describe operand formatting in a pipeline processor with a diagram. (13)
MIPS pipelined processor diagram - 5 marks
Explanation with operands - 8 marks
15. (a) Explain in detail how exceptions are handled in MIPS architecture? (13)
Introduction
In this unit, you will learn how to add interrupt and exception support to your multicycle CPU design. For additional
information, please refer section 5.6 and appendix A in the Hennessy and Patterson textbook. Note: you will only be
implementing a subset of the exception and interrupt functionality of the MIPS architecture. Therefore, use this page as your
definitive source of information regarding this unit.
Exceptions and interrupts are unexpected events that disrupt the normal flow of instruction execution. An exception is an
unexpected event from within the processor. An interrupt is an unexpected event from outside the processor. You are to
implement exception and interrupt handling in your multicycle CPU design.
When an exception or interrupt occurs, the hardware begins executing code that performs an action in response to the exception.
This action may involve killing a process, outputting a error message, communicating with an external device, or horribly
crashing the entire computer system by initiating a "Blue Screen of Death" and halting the CPU. The instructions responsible for
this action reside in the operating system kernel, and the code that performs this action is called the interrupt handler code. You
can think of handler code as an operating system subroutine. After the handler code is executed, it may be possible to continue
execution after the instruction where the execution or interrupt occurred.
Exceptions: Types
For your project, there are three events that will trigger an exception: arithmetic overflow, undefined instruction, and system call.
Arithmetic overflow occurs during the execution of an add, addi, or sub instruction. If the result of the computation is too large
or too small to hold in the result register, the Overflow output of the ALU will become high during the execute state. This event
triggers an exception.
Undefined instruction occurs when an unknown instruction is fetched. This exception is caused by an instruction in the IR that
has an unknown opcode or an R-type instruction that has an unknown function code.
System call occurs when the processor executes a syscall instruction. Syscall instructions are used to implement operating
system services (functions). - 6 marks
(OR)
(b)Explain data path and its control in detail. (13)
Data path in MIPS architecture diagram - 6 marks
Explanations about data path - 7 marks
16). a) Perform addition and subtraction of single precision floating point numbers A and B , Where A=44900000H and
B=42A00000H. (15)
23 = mantissa (m).
The Decimal value of a normalized floating point numbers in IEEE 754 standard is represented as
- 4 marks
b). Explain in detail about the multiplication algorithm with suitable example and diagram. (15)
binary multiplication algorithm with flow chart - 9 marks
Example problem - 6 marks