ESE-2018 Mains Test Series: Electrical Engineering Test No: 2

Detailed Solutions
ESE-2018 Electrical Engineering

Mains Test Series Test No : 2
Section A : Electrical Circuits + Microprocessors
Q.1 (a) Solution:

1Ω
There are two reference nodes in the given circuit,
R4
Let us name them as A and B. A
10 V 2Ω B
+–
By applying the KCL at node A, we get, R2
4A R1 2Ω 2Ω R3 2A
VA VA − VB − 10 V VA − VB
+ + = 4A
2Ω 2Ω 1Ω
VA + VA – VB – 10 V + 2 VA – 2VB = 8 V
4VA – 3VB = 18 V ...(i)
By applying KCL at node B, we get,
VA − VB VA − VB − 10 V VB
+ +2A =
1Ω 2Ω 2 Ω
2VA – 2VB + VA – VB – 10 V + 4 V – VB = 0
3VA – 4VB = 6 V ...(ii)
By solving equations (i) and (ii), we get,
54 30
VA = V and VB = V
7 7
VA2 (54 /7)2

The power dissipated by R1, P1 = = W = 29.755 W
R1 2
Test No : 2 ELECTRICAL ENGINEERING | 9
2
⎛ 24 ⎞
⎜2 − 10 ⎟
(VA − VB − 10 V) 7
The power dissipated by R2, P2 = =⎝ ⎠ W = 21.6 W
R2 2
VB2 (30 / 7)2

R3 2
(VA − VB )2 (24 /7)2

R4 1
Q.1 (b) Solution:

• It is given that, the load is delivering the magnetizing reactive power. So, the load can be
effectively modelled as the combination of a resistor and a capacitor.
• The two possible models of the load are as follows:
I1
+
R1 +
250 V 250 V R2 –jX2

–jX1
–
–
Model-1 Model-2
To determine the values of R1 and X1 (also C1) of model-1 :

S = 40 kW – j30 kVAR
2 2
⎥ S⎥ = 250 I 1 = (40) + (30) kVA = 50 kVA
50 × 1000
So, I1 = = 200 A
250
I 12 R1 = 40 kW
40 × 1000
R1 = Ω=1Ω
200 × 200
I 12 X1 = 30 kVAR
30 × 1000 3
X1 = Ω= Ω
200 × 200 4
1 3
= Ω
ωC 1 4
Given that, ω = 100 rad/sec
4 4 40
So, C1 = = F= mF = 13.33 mF
3 ω 300 3
Model-1 : A resistance of 1 Ω in series with a capacitance of 13.33 mF.
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10 | ESE 2018 : MAINS TEST SERIES
To determine the value of R2 and X2 (also C2) of model-2 :
VL2
= 40 kW
R2
250 × 250
R2 = Ω = 1.5625 Ω
40 × 1000
VL2
= 30 kVAR
X2
250 × 250 25
X2 = Ω= Ω
30 × 1000 12
1 25
= Ω
ωC 2 12
12
C2 = F = 4.8 mF
25 × 100
Model-2 : A resistance of 1.5625 Ω in parallel with a capacitance of 4.8 mF.
Q.1 (c) Solution:

As the switch is initially opened for a long time, the voltage across the capacitor at t = 0– is zero and
the current flowing through the inductor at t = 0– is also zero.
dv1 (t ) dv2 (t )
(i) To determine and at t = 0+ :
dt dt
di1 (t )
v1(t) = L
dt
5Ω
v2(t) = (10 Ω) i1(t)
+ +
i2(0 ) i1(0 )
vC (t) = v1(t) + v2(t) 2A
+ +
d vC (t ) + 2H v1(0 )
+
i2(t) = C 10 V –+ 4 F vC(0 ) –
dt + +
– 10 Ω v2(0 )
At t = 0+: i1(0+) = 0 A –
i2(0+) = 2 A
v1(0+) = v2(0+) = vC(0+) = 0 V
dvC (t )
C = i 2(t)
dt
dvC (0 + ) 1 2
So, = i2 (0 + ) = V/sec = 0.50 V/sec
dt C 4
dv2 (t ) di1 (t ) 10 Ω
= (10 Ω) = v1 (t )
dt dt 2H
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dv2 (0+ )
So, = 5v 1(0+) = 0 V/sec
dt
v1(t) + v2(t) = vc(t)

dv1 (t ) dvC (t ) dv2 (t )
= −
dt dt dt
dv1 (0+ ) dvC (0 + ) dv2 (0 + )

So, = − = 0.50 − 0 = 0.50 V/sec
dt dt dt
d 2 v2 ( t )
(ii) To determine at t = 0+:
dt 2
v2(t) = (10 Ω) i1(t)
d 2 v2 (t ) d ⎡ di1 (t ) ⎤ 10 Ω d
= (10 Ω) dt ⎢ dt ⎥ = 2 H dt [ v1 (t )]
dt 2 ⎣ ⎦
d 2 v2 (0+ ) dv1 (0 + )
So, = 5 = 5 (0.50) = 2.50 V 2 /sec 2
dt 2 dt
(iii) To determine v1(t) and v2(t) at t = ∞ :
• At t = ∞, the circuit will be in steady state. In this state, a capacitor acts as an open circuit and
an inductor acts as a short circuit, for DC excitation.
• So, the equivalent of the circuit given in the question at t = ∞ can be drawn as,
2
5Ω A
3
2
0A i1(∞) = A
3
+
+ v1(∞)
vC(∞) –
10 V –+
– +
At t = ∞ 10 Ω v2(∞)
–
v1(∞) = 0 V
2 20
v2(∞) = (10 Ω) i1(∞) = 10 × V= V = 6.67 V
3 3
Q.1 (d) Solution:

(i) Memory mapped I/O:
In this scheme, there is only one address space. This address space is allocated to both memory
and I/O devices. Some addresses are assigned to memories and some to I/O devices. The address
for I/O devices is different from the addresses which have been assigned to memories. An I/O
device is also treated as a memory location. In this scheme one address is assigned to each
memory location and one address is assigned to each I/O device.
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In this scheme, all data transfer instructions of the microprocessor can be used for transferring
data from and to either memory or I/O devices. For example, MOV D, M instruction would
transfer one byte of data from a memory location or an input device to the register D, depending
on whether the address in the H-L register pair is assigned to a memory location or to an input
device. If H-L contains address of a memory location, data will be transferred from that memory
location to register D, while if H-L pair contains the address of an input device, data will be
transferred from that input device to register D.
This scheme is suitable for systems using microprocessor with less number of instructions and
which require less number of I/O devices. We can see this type of scheme in dedicated systems.
Advantages:
• No special instructions are required for communicating with I/O devices.
• Direct data transfer is possible between any register of the microprocessor and I/O devices.
• All the arithmetic and logical operations can be directly performed with I/O data.
• Special status/control signal, like IO/ M in 8085 microprocessor, to distinguish between
memory and I/O transfer is not required.
Disadvantages:
• Decoding 16-bit address for I/O device requires more hardware circuitry.
• By assigning some address space for I/O devices, we cannot use the system memory
efficiently.
(ii) I/O mapped I/O:
Some CPUs provide one or more control lines (for example, IO/ M line for 8085), the status of
which indicates either memory or I/O operation. When the status of IO/ M line is high, it
points to I/O operation and when low, it points to memory operation. Thus, in this case, the
same address may be assigned to both memory and an I/O device-depending on the status of
IO/ M line. This scheme is referred to as I/O mapped I/O scheme.
Here two separate address spaces exist-one space is meant exclusively for memory operations
and the other for I/O operations. Usually, the space assigned for I/O is much smaller than
memory space.
Advantages:
• As the address space assigned to I/O devices is less compared to memory space, circuitry
required to decode the address of I/O devices is less complex.
• As separate address spaces are assigned to both I/O devices and memory, we can use the
system memory efficiently.
Disadvantages:
• Separate instructions are required for I/O communication.
• Direct data transfer is possible between I/O devices and accumulator only but not with
other registers of microprocessor.
• Arithmetic and logical instructions cannot be performed directly with I/O data.
• Special status/control signal is required by the microprocessor to distinguish between I/O
and memory transfer.
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Q.1 (e) Solution
Addressing modes of 8086 for sequential control flow instructions:
(i) Immediate addressing mode: In this addressing mode, immediate data is a part of instruction,
and appears in the form of successive byte or bytes.
Example: MOV AX, 0020H; Here, the 16-bit data to be moved to the register AX is 0020H.
(ii) Direct addressing mode: In this addressing mode, a 16-bit memory address (offset) is directly
specified in the instruction as a part of it.
Example: MOV AX, [0020H]; Here, the 16-bit data to be moved to the register AX is present
in a memory location in the data segment. The offset address of the memory location in the
data segment is 0020H. The effective address of the memory location is “10H × [DS] +
0020H”.
(iii) Register addressing mode: In this addressing mode, the data is stored in a register and it is
referred using the particular register. All the registers, except IP, may be used in this mode.
Example: MOV AX, BX; Here, the 16-bit data to be moved to the register AX is present in
the register BX.
(iv) Register indirect addressing mode: In this addressing mode, the offset address of the memory
location is specified indirectly, using the offset registers. In this addressing mode, the offset
address is in either BX or SI or DI register and the default segment register is either DS or
ES.
Example: MOV AX, [BX]; Here, the 16-bit data to be moved to the register AX is present in
a memory location in the data segment. The offset address of the memory location in the
data segment is in the register BX. The effective address of the memory location is “10H ×
[DS] + [BX]”.
(v) Indexed addressing mode: In this addressing mode, the offset address of the memory
location is specified indirectly, using one of the index registers. DS is the default segment
register for index registers SI and DI. In case of string instructions, DS and ES are default
segment registers for SI and DI respectively. This addressing mode is a special case of the
“register indirect addressing mode”.
Example: MOV AX, [SI]; Here, the 16-bit data to be moved to the register AX is present in
a memory location in the data segment. The offset address of the memory location in the
data segment is in the register SI. The effective address of the memory location is “10H ×
[DS] + [SI]”.
(vi) Register relative addressing mode: In this addressing mode, the offset address of the memory
location is obtained by adding an 8-bit or 16-bit displacement to the content of any one of
the registers BX, BP, SI and DI. The default segment register for this addressing mode is
either DS or ES.
Example: MOV AX, 50H [BX]; Here, the 16-bit data to be moved to the register AX is
present in a memory location in the data segment. The offset address of the memory location
in the data segment is obtained by adding 50H to the content of the register BX. The effective
address of the memory location is “10H × [DS] + 50H + [BX]”.
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(vii) Based indexed addressing mode: In this addressing mode, the offset address of the memory
location is obtained by adding the content of a base register (BX or BP) to the content of an
indexed register (SI and DI). The default segment register for this addressing mode is
either DS or ES.
Example: MOV AX, [BX] [SI]; Here, the 16-bit data to be moved to the register AX is present
in a memory location in the data segment. The offset address of the memory location in the
data segment is obtained by adding the content of the register BX to the content of the
register SI. The effective address of the memory location is “10H × [DS] + [BX] + [SI]”.
(viii) Relative based indexed addressing mode: In this addressing mode, the offset address of
the memory location is obtained by adding an 8-bit or 16-bit displacement to the sum of the
content of a base register (BX or BP) and the content of an indexed register (SI and DI). The
default segment register for this addressing mode is either DS or ES.
Example: MOV AX, 50H [BX] [SI]; Here, the 16-bit data to be moved to the register AX is
present in a memory location in the data segment. The offset address of the memory location
in the data segment is obtained by adding 50H to the sum of the content of the register BX
and the content of the register SI. The effective address of the memory location is “10H ×
[DS] + 50H + [BX] + [SI]”.
Q.2 (a) Solution:

• The given two-port network can be viewed as a combination of two individual two-port
networks with parallel connection at port-1 side and series connection at port-2 side as shown
below.
I1′ I2′ I2
+ ′ Two-port + +
V Network-1 V′
– 1 – 2
I1
+
V1 V2
–
I1′′ I2′′
+ ′′ Two-port + ′′
V V
– 1 Network-2 – 2 –
I1′ 8Ω 6Ω I2′ I1′′ 4Ω Ip I2′′

1:2
+ + + +
+
V1′ 1 10 Ω 2 V2′ V1′′ 1 5Ω 2 Vp V2′′
–
Ip 2Ω –
– – –
Network - 1 Network - 2
• As the input side has parallel connection and output side has series connection, it is convenient
to calculate the overall g-parameters (inverse hybrid parameters) from the g-parameters of
individual two-port networks.
So, [g] = [g1] + [g2]
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To determine the g-parameters of network-1 :
• By applying KVL in loop (1) of network-1, we get,
V1′ = 8 I 1′ + 10( I 1′ + I 2′ ) = 18 I 1′ + 10 I 2′
⎛ 1 ⎞ ⎛ 10 ⎞
I 1′ = ⎜ ⎟V1′ − ⎜ ⎟ I 2′ ...(i)
⎝ 18 ⎠ ⎝ 18 ⎠
• By applying KVL in loop (2) of network-1, we get,
V2′ = 6 I 2′ + 10( I 1′ + I 2′ ) = 16 I 2′ + 10 I 1′
⎛ 1 10 ′ ⎞
= 16 I 2′ + 10 ⎜ V1′ − I2 ⎟
⎝ 18 18 ⎠
⎛ 10 ⎞ ′ ⎛ 188 ⎞ ′
V2′ = ⎜ ⎟ V1 + ⎜ ⎟ I2 ...(ii)
⎝ 18 ⎠ ⎝ 18 ⎠
• From equations (i) and (ii), we get,
⎡1 10 ⎤
⎢ 18 − 18 ⎥
[g1] = ⎢ ⎥
⎢ 10 188 ⎥
Ω
⎣⎢ 18 18 ⎥⎦
To determine the g-parameters of network-2:
• From the basic properties of the transformer,
V2′′
Vp = and Ip = 2I 2′′
2
• By applying KVL in loop (1) of network - 2, we get,

′′ ′′ ′′ ′′
V1′′ = 4I1 + 5( I1 + I p ) = 9I1 + 10I 2
⎛ 1 ⎞ ′′ ⎛ 10 ⎞ ′′
I 1′′ = ⎜ ⎟V1 − ⎜ ⎟ I 2 ...(iii)
⎝9⎠ ⎝ 9 ⎠
• By applying KVL in loop (2) of network - 2, we get,
5( I p + I1′′ ) + 2( I p ) − Vp = 0
⎛1 10 ⎞ V ′′
5 ⎜ V1′′ − I 2′′ + 2 I 2′′ ⎟ + 4 I 2′′ − 2 = 0
⎝9 9 ⎠ 2
10 ′′ ⎛ 100 ⎞
V2′′ = V1 + ⎜ 8 − + 20 ⎟ I 2′′
9 ⎝ 9 ⎠
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⎛ 10 ⎞ ′′ ⎛ 152 ⎞ ′′
V2′′ = ⎜ ⎟V1 + ⎜ ⎟ I2 ...(iv)
⎝ 9 ⎠ ⎝ 9 ⎠
• From equations (iii) and (iv), we get,
⎡1 10 ⎤
⎢9 − 9 ⎥
[g2] = ⎢ ⎥
⎢ 10 152 Ω ⎥
⎣⎢ 9 9 ⎥⎦
To determine the z-parameters of the overall network:
• The g-parameters of the overall network can be given by,
[g] = [g1] + [g2]
⎡1 10 ⎤ ⎡ 2 20 ⎤
⎢ 18 − 18 ⎥ ⎢ 18 − 18 ⎥
= ⎢ 10 ⎥+⎢ ⎥
⎢ 188 ⎥ ⎢ 20 304 ⎥
Ω Ω
⎢⎣ 18 18 ⎥⎦ ⎢⎣ 18 18 ⎥⎦
⎡3 30 ⎤
⎢ 18 − 18 ⎥ 1 ⎡1 −10 ⎤
= ⎢ 30 ⎥=
⎢ 492 ⎥ 6 ⎢⎣ 10 164 Ω ⎥⎦
⎣⎢ 18 18 ⎥⎦
• Which can be expressed as,
V1 10 I 2
I1 = − ...(v)
6 6
10 V1 164 I 2
V2 = + ...(vi)
6 6
• From equation (v), we get,
V1 = 6I1 + 10I2 ...(vii)
• From equations (vi) and (vii), we get,
10 164 I 2
V2 = (6 I1 + 10 I 2 ) +
6 6
V2 = 10I1 + 44I2 ...(viii)

• From equations (vii) and (viii), the z-parameters of the overall network can be expressed as,
⎡ 6 Ω 10 Ω ⎤
[z] = ⎢ ⎥
⎣10 Ω 44 Ω ⎦
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Alternative Method:
• The standard equations of z-parameters can be given as,
V1 = z11 I1 + z12I2
V2 = z21 I1 + z22I2
V1 ⎫
z11 = ⎪
I1 I2 = 0 ⎪
⎪
⎬ When port-2 is open circuited
V2 ⎪
z21 =
I 1 I = 0 ⎪⎪
2 ⎭
V1 ⎫
z12 = ⎪
I2 I1 = 0 ⎪
⎪
⎬ When port-1 is open circuited
V2 ⎪
z22 =
I 2 I = 0 ⎪⎪
1 ⎭
When port-2 is open circuited:
8 Ω Ia 0A 6Ω I2 = 0
Ia Ia +
I1 10 Ω
Ib Ia 0A
+
V1 0A V2
1:2
– 4Ω Ib + +
I1 5Ω Vp Vs
Ib – – –
2Ω 0A 0A
V1 = 8Ia + 10Ia = 18Ia

Also, V1 = 4Ib + 5Ib = 9Ib
So, 18Ia = 9I b
I b = 2Ia
I 1 = Ia + Ib = 3Ia
Vp = 5Ib = 10Ia
Vs = 2Vp = 20Ia
V2 = 10Ia + Vs = 30Ia
V1 18 I a
z11 = = =6Ω
I1 I2 = 0
3 Ia
V2 30 I a
z21 = = = 10 Ω
I1 I2 = 0
3 Ia
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When port-1 is open circuited:

8Ω Ia 6Ω I2
(I2 – Ia) +
I1 = 0 A
Ia Ia 10 Ω
I2
+ +
V1 2I2 I2 V2 V2
1:2 –
– Ia 4 Ω (Ia + 2I2) + +
Vp Vs
Ia 5Ω
–
– –
Ia 2I2 2 Ω I2
By applying KVL in input side loop, we get,

8Ia + 4Ia + 5(Ia + 2I2) – 10(I2 – Ia) = 0
27Ia + 10I2 – 10I2 = 0
Ia = 0
So, V1 = –8Ia + 10(I2 – Ia) = 10I2
V2 = 6I2 + 10(I2 – Ia ) + Vs = 16I2 + 2Vp
= 16I2 + 2(5Ia + 10I2 + 4I2)
= 16I2 + 28I2 = 44I2
V1
z12 = = 10 Ω
I2 I1 = 0
V2
z22 = = 44 Ω
I2 I1 = 0
• By summarizing the results, we can express the z-parameters of the overall network as,
⎡6Ω 10 Ω ⎤
[z] = ⎢
⎣10 Ω 44 Ω ⎥⎦
Q.2 (b) Solution:

(i) To determine Vx using superposition theorem :
• When 3 A current source is acting alone,
9Ω
3A 4Ω 5Ω
′
+ Vx –
Ix′ 2Ω
Using current division rule,
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4 4 3
I x′ = 3 A × = 3× A= A
9+ 4+ 5+2 20 5
6
Vx′ = I x′ × 2 Ω = V = 1.2 V
5
2A
9Ω
4Ω 5Ω
′′
+ Vx –
Ix′′ 2Ω

9 18
I x′′ = −2 A × =− A
9+4+2+5 20
Vx′′ = I x′′ × 2 Ω = − 1.8 V

9Ω Ix′′′
4Ω 5Ω 6A
′′′
+ Vx –
Ix′′′ 2Ω

5 3
I x′′′ = − 6 A × =− A
9+4+2+5 2
Vx′′′ = I x′′′ × 2 Ω = − 3 V
• When 30 V voltage source is acting alone,
9Ω
4Ω 5Ω
′′′′
+ Vx –
–+
Ix′′′′ 2 Ω 30 V
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30 3
I x′′′′ = A= A
9+ 5+ 4+ 2 2
Vx′′′′ = I x′′′′ × 2 Ω = 3 V
• When all the 4 sources are acting simultaneously,
Vx = Vx′ + Vx′′ + Vx′′′ + Vx′′′′ = 1.2 – 1.8 – 3 + 3 = –0.6 V

(ii) To determine Vx using source transformation technique:
A practical current source can be transformed into a practical voltage source as shown below.
a a
Rs
Is Rs
+ Vs = IsRs
–
b b
Using the above property, the given circuit can be simplified as,
18 V
9Ω
30 V
4Ω
12 V 5Ω
+ Vx –
Ix 2Ω 30 V
12 + 30 − 30 − 18 6
Ix = A=− A
9+5+ 4+2 20
6
Vx = Ix × 2 Ω = − V = − 0.6 V
10
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Q.2 (c) Solution:
Flow Chart:
Start
Load register D with 0AH
HL register pair is pointed to

memory location 3000H
Move content of memory

location, pointed by HL pair, to ACC
Decrement register D
Is Yes
D=0?
Store ACC
No
at memory
Increment the content of location 4000H
HL register pair
Stop
Compare content of memory
location, pointed by HL pair,
with content of ACC
Is Yes
CY = 1 ?
No
8085 assembly language program:

MOV D, 0AH
LXI H, 3000H
SAVE: MOV A, M
NEXT: DCR D
JZ STOP
INX H
CMP M
JC SAVE
JNC NEXT
STOP: STA 4000H
HLT
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Q.3 (a) Solution:

The sum of all the elements of any column of a complete incidence matrix results in zero. Using this
property, the complete incidence matrix Aa of the given reduced incidence matrix A can be developed
as,
Nodes Branches
1 2 3 4 5 6 7
a 1 1 0 0 0 0 1
b –1 –1 1 0 0 0 0
Aa =
c 0 0 –1 1 0 0 0
d 0 0 0 –1 –1 –1 0
e 0 0 0 0 1 1 –1
(i) To prove that the set of branches {1, 3, 4, 5} constitutes a tree of the graph:
By rearranging the columns of the matrix Aa , such that the columns corresponding to the
branches {1, 3, 4, 5} will be together as shown below.
Nodes Branches
1 3 4 5 2 6 7
a 1 0 0 0 1 0 1
b –1 1 0 0 –1 0 0
Aa = c 0 –1 1 0 0 0 0 = [Aat : Aal ]
d 0 0 –1 –1 0 –1 0
e 0 0 0 1 0 1 –1
Nodes Branches
1 3 4 5
a 1 0 0 0
b –1 1 0 0
Aat = c 0 –1 1 0
d 0 0 –1 –1
e 0 0 0 1
From the matrix Aa t , we can notice that,

• Branch 1 connects nodes a and b, branch 3 connects nodes b and c, branch 4 connects nodes c
and d, branch 5 connects nodes d and e. It indicates that the set of branches {1, 3, 4, 5} connects
all the nodes present in the graph.
• No two columns are identical in the matrix Aat , which implies that there are no parallel branches
between any two nodes. Thus the subgraph does not contain any loop.
The above two criteria satisfy the requirement of a tree. Therefore the set of branches {1, 3, 4, 5}
constitute a tree of the graph.
Alternatively,
The columns of the reduced incidence matrix can be rearranged such that,
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Nodes Branches
1 3 4 5 2 6 7
a 1 0 0 0 1 0 1
b –1 1 0 0 –1 0 0
A =
c 0 –1 1 0 0 0 0 = [A t : A l ]
d 0 0 –1 –1 0 –1 0
1 3 4 5
1 0 0 0
–1 1 0 0
At = 0 –1 1 0
0 0 –1 –1
When the set {1, 3, 4, 5} forms a tree, the determinant of the matrix At is non zero, i.e., the matrix At
should be a non-singular matrix.
1 0 0
1 0
⎥ At⎥ = (1 ) −1 1 0 = (1) (1) = (1) (1) ( −1) = −1 ≠ 0
−1 −1
0 −1 −1
So, the set of branches {1, 3, 4, 5} constitute a tree of the graph.

(ii) To develop the tie-set matrix corresponding to the tree formed by the set of branches {1, 3, 4, 5}:
• By applying KCL at all the nodes of the graph, form the matrix Aa, we can write,
I1 + I2 + I7 = 0 (from KCL at node a)
–I1 – I2 + I3 = 0 (from KCL at node b)
–I3 + I4 = 0 (from KCL at node c)
– I4 – I5 – I6 = 0 (from KCL at node d)
I5 + I6 – I7 = 0 (from KCL at node e)
• Now from the above relations, the twig currents (I1, I3, I4, I5) can be expressed in terms of link
currents (I2, I6, I7) as follows.
I 1 = –I2 – I7
I 3 = I1 + I2 = –I2 – I7 + I2 = –I7
I 4 = I3 = –I7
I 5 = –I4 – I6 = –I6 + I7
• The branch currents can be expressed in terms of link currents in matrix form as follows.
⎡ I1 ⎤ ⎡ −1 0 −1 ⎤
⎢I ⎥ ⎢ 0 0 −1⎥
⎢ 3⎥ ⎢ ⎥
⎢I4 ⎥ ⎢ 0 0 −1⎥ ⎡ I 2 ⎤
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
⎢ I5 ⎥ = ⎢ 0 −1 1 ⎥ ⎢ I6 ⎥
⎢I2 ⎥ ⎢ 1 0 0 ⎥ ⎢ I7 ⎥
⎢ ⎥ ⎢ ⎥ ⎣ ⎦
⎢ I6 ⎥ ⎢ 0 1 0 ⎥
⎢I ⎥ ⎢0 0 1⎥
⎣ 7⎦ ⎣ ⎦
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• Now, the tie-set matrix corresponding to the tree {1, 3, 4, 5} of the graph can be given by,
Loops Twigs Links
1 3 4 5 2 6 7
l2 –1 0 0 0 1 0 0
Bf = l6 0 0 0 –1 0 1 0
l7 –1 –1 –1 1 0 0 1
Alternatively,
• The tie-set matrix can be composed as,
B f = [ Bt Bl ] = [ Bt U 3 × 3 ]
Where, Bl = U3 × 3 = identity or unit matrix of order 3 × 3

T
Bt = − ⎡ At−1 Al ⎤
⎣ ⎦
⎡1 0 0 0⎤
⎢ −1 1 0 0 ⎥
At = ⎢ ⎥
⎢ 0 −1 1 0 ⎥
⎢ ⎥
⎣ 0 0 −1 −1⎦
⎡1 0 0 0⎤
⎢1 1 0 0⎥
At−1 = ⎢ ⎥
⎢1 1 1 0⎥
⎢ ⎥
⎣ −1 −1 −1 −1⎦
⎡1 0 0 0⎤ ⎡1 0 1⎤ ⎡1 0 1⎤
⎢1 1 0 0⎥ ⎢ −1 0 0 ⎥⎥ ⎢⎢0 0 1 ⎥⎥
⎡ At−1 Al ⎤ = ⎢ ⎥ ⎢ =
⎣ ⎦ ⎢1 1 1 0⎥ ⎢0 0 0 ⎥ ⎢0 0 1⎥
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
⎣ −1 −1 −1 −1⎦ ⎣ 0 −1 0 ⎦ ⎣0 1 −1⎦
⎡ −1 0 0 0 ⎤
T
Bt = − ⎡ At−1 Al ⎤ = ⎢⎢ 0 0 0 −1⎥⎥
⎣ ⎦
⎢⎣ −1 −1 −1 1 ⎥⎦
1 3 4 5 2 6 7
–1 0 0 0 1 0 0
So, Bf = 0 0 0 –1 0 1 0
–1 –1 –1 1 0 0 1
(iii) To prove the results obtained in part (i) and (ii) using the graph:
• By using the complete incidence matrix Aa , the graph can be constructed as shown below.
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2
l2 c d
3 4
a
1 b
l7
5
7 l6
6
e
• From the above graph, it is clear that, the branches 1, 3, 4 and 5 are the twigs and the branches
2, 6 and 7 are links of the given graph. Hence the set of branches {1, 3, 4, 5} constitutes a tree.
• From the above graph, the tie-set matrix for the selected tree can be constructed as,
Loops Twigs Links
1 3 4 5 2 6 7
l2 –1 0 0 0 1 0 0
Bf = l6 0 0 0 –1 0 1 0
l7 –1 –1 –1 1 0 0 1
(iv) The total number of trees possible for the given graph can be calculated as,
Total number of trees = ⎥ AAT⎥
Where, A = reduced incidence matrix
⎡ 1 −1 0 0 ⎤
⎢ 1 −1 0 0 ⎥
⎡1 1 0 0 0 0 1⎤ ⎢ ⎥
⎢ −1 −1 1 0 0 0 ⎢0 1 −1 0 ⎥
0 ⎥⎥ ⎢ ⎥
AAT = ⎢⎢ ⎢ 0 0 1 −1 ⎥
0 0 −1 1 0 0 0⎥
⎢ ⎥ ⎢ 0 0 0 −1 ⎥
⎣ 0 0 0 −1 −1 −1 0⎦ ⎢ ⎥
⎢ 0 0 0 −1 ⎥
⎢1 0 0 0 ⎥
⎣ ⎦
⎡ 3 −2 0 0 ⎤
⎢ −2 3 −1 0 ⎥
= ⎢⎢ ⎥
0 −1 2 −1⎥
⎢ ⎥
⎣ 0 0 −1 3 ⎦
3 −2 0 0
3 −1 0 −2 −1 0
−2 3 −1 0
⎥ AAT⎥ = = (3) −1 2 −1 + (2) 0 2 −1
0 −1 2 −1
0 −1 3 0 −1 3
0 0 −1 3
= 3(15 – 3) + 2(–10) = 16
So, total 16 trees are possible for the given graph.
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Q.3 (b) Solution:

“The total energy absorbed by the resistor in the given circuit, for t > 0, does not depend on the
value of R”.
Proof :
• The total energy absorbed by the resistor for t > 0 can be given by,
∞
2
WR = ∫i (t )R dt
0
i (t ) R
+ +
vC1(t ) C1 C2 vC2(t )
– –
• The equivalent of the given circuit for t > 0 in Laplace domain can be drawn as shown below.
I (s ) R
1 1
sC1 sC2
V1 V2
+ +
s – – s
V1 V2
−
s s (V − V2 )/s
I(s) = = 1
1 1 1
R+ + R+
sC 1 sC 2 sC e
C1C 2
Where, Ce =
C1 + C 2
(V1 − V2 )
So, I(s) =
⎛ 1 ⎞
R⎜s + ⎟
⎝ RC e ⎠
By taking the inverse Laplace transform of I(s), we get,

⎛ V1 − V2 ⎞ −t /RC e
i(t) = ⎜ ⎟e u(t )
⎝ R ⎠
• Now, the total energy absorbed by the resistor for t > 0 is,
∞ 2
⎛ V1 − V2 ⎞ −2 t /RC e
WR = ∫ ⎜ R ⎟ Re dt
0 ⎝ ⎠
∞
(V1 − V2 )2 −2 t /RC e
=
R ∫e dt
0
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∞
(V1 − V2 )2 ⎡ e −2t /RC e ⎤
= ⎢− ⎥
R ⎢⎣ 2/RC e ⎥⎦ 0
(V1 − V2 )2 RC e ⎡ −∞ 0 ⎤
= × −e + e
R 2 ⎣ ⎦
1
WR = C e (V1 − V2 )2
2
The above relation of WR is independent of the value of “R”. Hence, the total energy absorbed
by the resistor in the given circuit, for t > 0, is independent of the value of R.
Q.3 (c) Solution
Step-by-step procedure for converting an 8-bit (2-digit) BCD number into its equivalent binary
number:
Suppose we have a decimal number 49, it can be represented in BCD format as (0100 1001) and
in binary format as (0011 0001)2 = 31H. To convert the number represented in BCD format into
binary format, the steps involved are,
Step-I: Unpack the number into MSD and LSD form and store the MSD and LSD in separate
registers. For the decimal number 49, the MSD is 04 and LSD is 09. Let us assume, MSD is
stored in register B and LSD is stored in register C. So the content of registers B and C are,
(B) = (0000 0100)2 = 04H and (C) = (0000 1001)2 = 09H
Step-II: Multiply MSD by decimal number 10 or MSD is added 10 times accumulatively with
0000H as initial sum. For the example taken, after multiplying the content of register D by a
decimal number 10, the contents of both the registers will be,
4 × 10 = (40)10 = (0010 1000)2 = 28H
(B) = (0010 1000)2 = 28H and (C) = (0000 1001)2 = 09H
Step-III: Add LSD to the result obtained in step-II. For the example taken, by adding the
contents of registers obtained at the end of step-II, we get,
(0010 1000)2 + (0000 1001)2 = (0011 0001)2 = 31H
So, the final result of addition will be the equivalent binary number of the given BCD number.
8085 assembly language program to convert the BCD number into its equivalent binary number:
Main Program:
Label Mnemonics Comments
LXI H, 2500H ; Load HL pair with 2500H
LXI D, 2600H ; Load DE pair with 2600H
MOV A, M ; Load the 2-digit BCD number to accumulator
ANI 0FH ; Separate the LSD of the 2-digit BCD number
MOV C, A ; Store the LSD in register C
MOV A, M ; Load the 2-digit BCD number to accumulator again
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ANI F0H ; Separate the MSD of the 2-digit BCD number

RRC ; Rotate right the content of accumulator four times, to shift
the MSD to the least significant nibble of accumulator
RRC ;
RRC ;
RRC ;
MOV B, A ; Store MSD in register B
XRA A ; Clear accumulator
MVI L, 0A H ; Load the register L with 0AH (decimal number 10)
SUM: ADD B ; Add MSD ten times to the content of accumulator
DCR L ; Decrement the content of register L
JNZ SUM ; Jump to SUM, if the addition for 10 times is not completed
ADD C ; Add LSD to (MSD×10 )
STAX D ; Store the result in 2600H
HLT
Q.4 (a) Solution:

(i)
• To determine the Norton’s equivalent current IN,
By applying KVL in loop (1) of the circuit shown below, we get,
2Vx
–4 V – Vx + 2Vx = 0 2Ω I1 A IN a
+–
Vx = 4 V –
Vx +
Vx 4 V –+ 3A IN
and I1 = =2A 1
2Ω
By applying KCL at node A, we get, b
I1 + IN = 3 A
I N = 3 A – I1 = 3 A – 2 A = 1 A
• To determine the Norton’s equivalent resistance RN,
By applying KVL in loop (1) of the circuit shown below, we get, 2Vx
2Ω a I0
–2Vx + Vx = V0 +–
–
Vx +
Vx = –V0
1 + V0
–
Vx V
and I0 = =− 0
2Ω 2Ω
b V0
V0 RN =
I0
So, RN = = −2 Ω
I0
• To determine the average power absorbed by the 1 Ω resistor using the Norton’s equivalent
circuit,
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a
I
IN 1A RN –2 Ω 1Ω
RN −2 Ω
I = × IN = ×1A = 2 A
RN + 1 Ω −2 Ω + 1 Ω
The average power absorbed by 1 Ω resistor is,
P1 Ω = I 2(1 Ω) = (2)2 (1) W = 4 W
(ii) To determine the average power absorbed by the 1 Ω resistor using the nodal analysis,
By applying KCL at node A of the circuit shown below, we get,
2Ω A a
VA − 4 V VA − 2 Vx +–
+ = 3A – V +
2Ω 1Ω x I
2Vx
4V + 3A
From KVL in loop (1), we get, – 1 1Ω
VA = Vx + 4 V
So, Vx = VA – 4 V b
So, VA – 4 V + 2[VA – 2VA + 8 V] = 6 V

–VA + 12 V = 6 V
VA = 6 V
Vx = VA – 4 V = 2 V
VA − 2Vx
The current through 1 Ω, I = =2A
1Ω
The average power absorbed by 1 Ω resistor is,
P1 Ω = I 2(1 Ω) = 4 W
Q.4 (b) Solution:

To determine the coupling coefficient of the coupled coils:
Given that, L1 = 2 H, L2 = 1 H and M = 1 H
Coefficient of coupling can be given by,
M 1 1
k = = = = 0.707
L1 L2 (2)(1) 2
To determine the energy stored in the coupled coils:
• The coupled coil in the given circuit can be equivalently modified as shown below.
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M=1H (L1 – M) = 1 H (L2 – M) = 0 H

1 2 1 2
L1 = 2 H L2 = 1 H M=1H
1′ 2′ 1′ 2′
• So, the given circuit can be equivalently drawn as,

4 Ω –j4 Ω j2 Ω j0 Ω
1 1H i3
F 0H
+ 8
100cos(2t ) V 100∠0° 1H j2 Ω i2 2Ω
– i1
• By using mesh analysis, we can write,
⎡4 j 2 ⎤ ⎡i1 ⎤ ⎡100 ∠ 0° ⎤
⎢ j 2 2 + j 2 ⎥ ⎢i ⎥ = ⎢ 0 ⎥
⎣ ⎦ ⎣ 2⎦ ⎣ ⎦
100 ∠ 0° j2
0 2 + j2 100(2 + j 2) 100(2 + j 2)
i1 = = =
4 j2 4(2 + j 2) + 4 4(3 + j 2)
j2 2 + j2
2
= 50 ∠0.1974 (rad) A
13
2
= 50 cos(2t + 0.1974) A
13
4 100 ∠ 0°
j2 0 − j 200
i2 = = A
4 j2 4(3 + j 2)
j2 2 + j2
200 + j 200 j 200

i3 = i1 + i2 = − A
4(3 + j 2) 4(3 + j 2)
50 50
= = ∠ − 0.588 (rad) A
(3 + j 2) 13
50
= cos(2 t − 0.588) A
13
• The energy stored in the coupled coils can be given as,
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1 1 1
w(t) = ( L1 − M ) i 12 + ( L2 − M )i 22 + Mi32
2 2 2
1 1 1 1
= (1) i 12 + (0) i 22 + (1) i 32 = ⎡i 12 + i 32 ⎤
2 2 2 2⎣ ⎦
1 ⎡ 50 × 50 × 2 50 × 50 ⎤
• At t = 1.5 sec, w(t = 1.5 sec) = ⎢ cos 2 (3 + 0.1974) + cos 2 (3 − 0.588)⎥ J
2⎣ 13 13 ⎦
2500 ⎡
= 2 cos 2 (3.1974) + cos 2 (2.412)⎤ J = 245.14 J
26 ⎣ ⎦
Q.4 (c) Solution:

• The overall dealy produced by the given subroutine program can be calculated by determining
the total number of T-states required to execute the program.
• The total number of T-states required to execute the program can be determined by analysing
the given program as shown in the following table:
Number of times Number of T-states
Instruction
executed for one time execution
MVI B, Data_8 bit 1 7
LOOP: DCR B N 4
(N – 1) ⇒ true 10 ⇒ true
JNZ LOOP 1 ⇒ false 7 ⇒ false
RET 1 10
• The total delay produced by the subroutine in terms of T-states can be given by,
Delay = (1 × 7T) + (N × 4T) + [(N– 1) × 10T + 1 × 7T] + (1 × 10T)
= (14 N + 14) T = 14 (N + 1) T
• The time delay corresponds to one T-state is,
1 1
T = = = 0.5 μs ∵ Give that, fCLK = 2 MHz
f CLK 2 MHz
• So, the total delay produced by the program is,
1
Delay = 14( N + 1) μs = 7(N + 1) μs ...(i)
2
• To determine the required value of N, to produce a delay of 70 μs:
From the result concluded in equation (i),
Delay = 7 (N + 1) μs
7 (N + 1) μs = 70 μs
N + 1 = 10
N = 9
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Q.4 (d) Solution:

The program to transfer a string of data in 8085 microprocessor can be written as follows:
LXI H, 4000H
LXI D, 5000H
MVI C, 10H
AGAIN : MOV A, M
STAX D
INX H
INX D
DCR C
JNZ AGAIN
HLT
The program to transfer a string of data in 8086 microprocessor can be written as follows:
MOV SI, 4000H
MOV DI, 5000H
MOV CX, 10H
AGAIN : MOV AX, [SI]
MOV [DI], AX
INC SI
INC DI
DEC CX
JNZ AGAIN
HLT
Section B : Digital Electronics-1 + Control Systems-1
5. (a) Solution
(i) BD + B(D + E) + D(D + F ) = BD + BD + BE + DD + DF
= BD + BE + DF
(ii) ABC + ( A + B + C ) + ABCD = ABC + ABC + ABCD
( )
= AB C + CD = AB(C + D)
= ABC + ABD
(iii) ( B + BC )( B + BC )( B + D) = B(1 + C) (B + C) (B + D)
= B(B + BC + BD + CD)
= B + BC + BD + BCD
= B(1 + C + D + CD) = B
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(iv) ABCD + AB(CD) + ( AB)CD = ABCD + AB(C + D) + ( A + B)CD

= ABCD + ABC + ABD + ACD + BCD
= CD( AB + A + B) + AB(CD + C + D)
= CD( A + B + B) + AB (C + D + D) = AB(1 + C ) + CD( A + 1)
= AB + CD
(v) ABC ⎡⎣ AB + C (BC + AC )⎤⎦ = ABC ⎡⎣ AB + BCC + ACC ⎤⎦

= ABC (AB) = ABC
(vi) AB + ABD + ABD + ACD + ABC = AB + AB(D + D) + ACD + ABC
= AB + AB + ACD + ABC
= A( B + B) + ACD + ABC
= A + ACD + ABC
= A + CD + BC
Q.5 (b) Solution:
A multiplexer is a circuit that accepts inputs from several different channel and feeds all of them
into a single output channel in a sequential order. The input is selected by the value of select input
or control inputs.The demultiplexer performs the reverse of operation of a multiplexer. It accept a
single input and distributes it over several outputs. The select input or control input code determines
the output line in which data input will be transmitted.
I0
I1 Y (output)
MUX
n:1
In – 1
Sm – 1 S1 S0
Select input
Where (2m = n)
Y0
Y1
Data
Demultiplexer
input
Yn – 2
Yn – 1
Sm – 1 Sm – 2 S1 S0
4 : 1 Multiplexer with low input at ‘G’ (enable)
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I0
I1 Y S1 S0 Y
I2
4:1 0 0 I0
I3
MUX 0 1 I1
1 0 I2
1 1 I3
G
S1 S0
Y = S1 S0 I0 + S1 S0 I1 + S1 S0 I 2 + S1 S0 I 3
Q.5 (c) Solution:

According to Mason’s gain formula,
N
C Pi Δ i
R
= ∑ Δ
i=1
P i = Gain of ith forward path

Δ = 1 – Σ (Individual loop gains) + Σ (Multiplication of gains of two non touching loops)
– Σ (Multiplication of gains of three non touching loops) + .....
Δi = Δ calculated by considering the loops non touching to the ith forward path
N = total number of forward paths
Forward path gains of the given SFG:
P 1 = G1G2G3G4G5
P 2 = G1G4G5G6
P 3 = G1G2G7
Individual loop gains of the given SFG:
L1 = –G4H1
L2 = –G2G3G4G5H2
L3 = –G4G5G6H2
L4 = –G2G7H2
Two non-touching loop gains of the given SFG:
L1L4 = G2G4G7H1H2
There are no three non-touching loops in the given SFG.
So, Δ = 1 + G4H1 + (G2G3 + G6) G4G5H2 + G2G7H2(1 + G4H1)
= (1 + G4H1)(1 + G2G7H2) + (G2G3 + G6) G4G5H2
Only forward path-3 has non touching loop to it.
So, Δ 3 = 1 – L1 = 1 + G4H1
Δ 1 = Δ2 = 1
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The overall transfer function,
C G1G4G5 (G6 + G2 G3 ) + G1G2 G7 (1 + G4 H 1 )
=
R (1 + G4 H1 )(1 + G2 G7 H 2 ) + (G2 G3 + G6 )(G4G5 H 2 )
Q.5 (d) Solution:

• The closed-loop transfer function of the given system will be,
G(s ) K / s(s + 10) K
T(s) = = = 2
1 + G(s ) 1 + K s + 10s + K
s(s + 10)
• The transfer function of a standard second order system can be given as,
ωn2
T(s) =
s 2 + 2 ζωn s + ωn2
• By comparing the transfer function of the given system with the transfer function of the standard
second order system, we get,
ωn2 = K ⇒ ωn = K
5 5
2ζωn = 10 ⇒ ζ = =
ωn K
2 2
⎛5⎞ ⎛ 5 ⎞
• When ζ = 0.50, K = ⎜ ⎟ =⎜ ⎟ = 100
ζ
⎝ ⎠ ⎝ 0.5 ⎠
• So, for the given transfer function, at K = 100,
ωn = K = 100 = 10
ζ = 0.50
• Settling time for ± 2% tolerance band,
4 4 4
ts = = = = 0.80 sec
ζωn (0.50 × 10) 5
• The peak overshoot is,
−πζ / 1−ζ 2
Mp = e = e −π/2 0.75
= 0.163
• The percentage peak overshoot is,
%Mp = Mp × 100 = 0.163 × 100 = 16.3%
• The time at peak overshoot is,
π π π
tp = = = = 0.363 sec
ωd ω 1 − ζ 2 10 1 − 0.25
n
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Q.5 (e) Solution:

• The Routh table for the given characteristic equation can be formed as follows:
s4 1 2 10
s3 K K+1 0
2 K − ( K + 1) ⎛ 1⎞
s2 = ⎜1− ⎟ 10 0
K ⎝ K⎠
10K 2
s1 ( K + 1) − 0 0
( K − 1)
s0 10 0 0
• For the system to be stable, all the elements in the first column of the Routh table should have
same sign. For this, the following conditions should be satisfied.
From s3 row, K > 0 ...(i)
1
From s2 row, 1− > 0
K
K > 1 ...(ii)
10K 2
From s1 row, ( K + 1) − > 0
(K − 1)
K 2 – 1 – 10K 2 > 0
–9K 2 – 1 > 0 ...(iii)
• No real value of “K” satisfies all the equations (i), (ii) and (iii) simultaneously. So, the given
system is unstable for any real value of “K”.
Q. 6 (a) Solution
Circuit description:
The required combinational circuit has 4 input terminals and 1 output terminal as shown below.
A1
A
A0
Combinational
F
B1 circuit
B
B0
A (A1A0) and B (B1B0)are two 2-bit binary numbers. F = 1, if sum = (A)10 + (B)10 is an odd number;
otherwise F = 0.
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Truth table:
A B SUM
(A)10 + (B)10 F
A1 A0 B1 B0
0 0 0 0 0 0
0 0 0 1 1 1
0 0 1 0 2 0
0 0 1 1 3 1
0 1 0 0 1 1
0 1 0 1 2 0
0 1 1 0 3 1
0 1 1 1 4 0
1 0 0 0 2 0
1 0 0 1 3 1
1 0 1 0 4 0
1 0 1 1 5 1
1 1 0 0 3 1
1 1 0 1 4 0
1 1 1 0 5 1
1 1 1 1 6 0
Minimization:
B 1B 0
00 01 11 10
A1 A0
0 1 3 2
00 1 1
4 5 7 6
01 1 1
12 13 15 14
11 1 1
8 9 11 10
10 A0 B0
1 1
A0 B0
F = A0 B0 + A0 B0 = A0 ⊕ B0
Logic circuit:
A0
F
B0
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Q. 6 (b) Solution
B
B B
A
EF EF
EF EF EF EF EF EF EF EF
CD CD
0 1 3 2 16 17 19 18
CD CD 1 1 ABCDE
4 5 7 6 20 21 23 22
CD 1 ABCDEF CD
A 12 13 15 14 28 29 31 30
CD CD
1 1
8 9 11 10 24 25 27 26
CD 1 CD 1 1 1
ABCDF
EF EF
EF EF EF EF EF EF EF EF
CD CD
32 33 35 34 48 49 51 50
CD CD
36 37 39 38 52 53 55 54
CD CD
A 44 45 47 46 60 61 63 62
CD CD
1 1
40 41 43 42 56 57 59 58
CD CEF CD
1 1
So, the minimized expression of the given logic expression is,

F(A,B,C,D,E, F) = CEF + ABCDF + ABCDE + ABCDEF
Q.6 (c) Solution:
The poles locations of a 2nd order system can be given by,
jω
jωd
φ
–ξωn 0 σ
Damping ratio (ξ) is equal to, ξ = cos φ

4
Settling time (ts) is equal to, ts = (for 2% tolerance)
ξω n
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1 −1 ⎛ 1 ⎞
For ξ = , φ = cos–1 (ξ) = cos ⎜ ⎟ = 45°
2 ⎝ 2⎠
1 −1 ⎛ 1⎞
For ξ = , φ = cos–1 (ξ) = cos ⎜ ⎟ = 60°
2 ⎝ 2⎠
4 4
For ts = 0.50 sec, ξωn = = =8
ts 0.50
4 4
For ts = 0.25 sec, ξωn = = = 16
ts 0.25
So, the allowed region for poles in s-plane can be given as,
jω
ξ = 1 line
2
j ωd (max)
ξ = 1 line
2
j ωd (min)
60°
45°
–16 –8
45° 0 σ
60°
s-plane
Shaded portion indicates

–j ωd(min)
the allowed region of the
closed-loop poles
–j ωd(max)
ts = 0.50 sec line
ts = 0.25 sec line
Finding ω d(max) :
ω d (max)
tan (60°) =
16 ωd (max)
ωd(max) = 16tan(60°)
= 16 3 rad/sec 60°
= 27.713 rad/sec 16
fd(max) = 4.41 Hz
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Finding ω d(min) :
ω d (min)
tan (45°) =
8
ωd (min)
ωd(min) = 8tan(45°) = 8 rad/sec
45°
fd(min) = 1.27 Hz
8
So, the allowed range of the frequency of damped oscillations is,
(8 to 27.713) rad/sec (or) (1.27 to 4.41) Hz.
Q.6 (d) Solution:

• For the purpose of frequency domain analysis, the open-loop transfer function can be modified
by replacing “s” with “jω” as follows:
1
G( jω) =
jω(1 + jω)(1 + j 4ω)
1
M = G( jω) =
ω (1 + ω2 )(1 + 16 ω2 )
−1 −1
φ = ∠ G( jω) = −90° − tan ( ω) − tan (4ω)
At ω = 0, G( jω) = ∞∠–90°
At ω = ∞, G( jω) = 0∠–270°
At ω = 0.1, G( jω) = 9.24∠–117.5°
At ω = 1, G( jω) = 0.17∠149°
• The intersection points of the polar plot with ±180° line can be investigated as follows:
φω=ω = ±180°
pc
−90° − tan −1 (ωpc ) − tan −1 (4ωpc ) = –180°
⎛ 5 ωpc ⎞
tan −1 ⎜ ⎟ = 90°
⎜ 1 − 4 ω2pc ⎟
⎝ ⎠
1 − 4 ω2pc = 0
1
ωpc = rad/sec = 0.50 rad/sec
4
1
Mpc = M ω = ω =
ωpc (1 + ω2pc )(1 + 16ω2pc )
pc
2 2×4 8
= = = = 0.80
⎛ 1⎞⎛ 16 ⎞ 10 10
⎜1 + ⎟ ⎜1 + ⎟
⎝ 4⎠⎝ 4 ⎠
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• The polar plot of the open-loop transfer function of the given system can be drawn as shown
below:
Im[G( jω)]
0.80
ω=∞
Re[G( jω)]
ω = 0.50
ω=0
• The gain margin of the given system is,

1 10
GM = = = 1.25
M pc 8
Gain margin in dB, GMdB = 20log10 (GM) = 20log10 (1.25) = 1.94 dB
Q.7 (a) Solution :

Flow chart for the design of a 4-bit parallel binary substractor (using 2’s complement method)
to perform A – B can be given as follows:
Start
Take two 4-bit binary

numbers A and B
Apply
2's complement to B
Add A to the
2's complement of B
Is MSB NO Apply 2's complement

of the result
to the intermediate result
is 0 ?
YES
Display the result
End
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Implementation of the 4-bit parallel subtracter:

A4 A3 A2 A1 B4 B3 B2 B1
Logic 1
A4′ A3′ A′2 A1′ B′4 B ′3 B′2 B′1

C5 C5′ 4 bit parallel Adder (1) C1′
S′4 S′3 S′2 S′1
Logic 0
A4′ A3′ A′2 A′1 B ′4 B ′3 B′2 B′1

C5 C5′ 4 bit parallel Adder (2) C1′
S′4 S′3 S′2 S′1
S4 S3 S2 S1
sign bit (S)
0 ⇒ result is +ve magnitude of
1 ⇒ result is –ve the result
Q.7 (b) Solution:

• The standard form of a second order system and its transfer function can be given by,
ω2n
R(s) + C(s )
– s(s + 2 ζωn )
C ( s) ωn2
T(s) = = 2
R(s ) s + 2ζωn s + ωn2
• For the purpose of frequency domain analysis, with sinusoidal excitation, the transfer function
can be modified by replacing “s” with “jω” as follows:
ωn2
T( jω) =
( jω)2 + 2ζωn ( jω) + ωn2
ωn2
=
(ωn2 − ω2 ) + j 2ζωωn
ω
• For the purpose of simplifying the calculations, let us consider the ratio u = as the normalized
ωn
operating frequency and the transfer function can be written in terms of normalized frequency
as follows:
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1
T( jω) = 2
(1 − u ) + j 2ζu
• The magnitude and phase of the above transfer function can be given as,
1
⎥ T( jω)⎥ = M =
(1 − u ) + (2 ζu)2
2 2
⎛ 2 ζu ⎞
∠T( jω) = φ = − tan −1 ⎜ ⎟
⎝ 1 − u2 ⎠
• The resonant frequency (ωr ) of a system is the frequency at which the magnitude of T( jω)
attains its maximum and the maximum value of the magnitude is called as resonant peak (Mr ).
So, M ω=ω = Mr
r
ωr
• Let us take the normalized resonant frequency as ur = .
ωn
• At ω = ωr or u = ur , the slope of the magnitude curve will be zero.
∂M
i.e., = 0
∂u u=u
r
∂M 4(1 − u2 )u − 8ζ 2 u
∂u u=u = =0
r 2[(1 − u 2 )2 + (2 ζu )2 ] 3/2 u = ur
(1 − ur2 )ur − 2 ζ 2 ur = 0
1 − ur2 = 2ζ 2
ur = 1 − 2ζ 2
2
ωr = ωn 1 − 2ζ
• The resonant peak (Mr) can be calculated as,
Mr = M ω = ωr (or) M u = ur
1
=
(1 − u 2 )2 + 4ζ 2 u 2
u = ur = 1− 2 ζ 2
1 1
= =
2 2 2 2
(1 − 1 + 2ζ ) + 4ζ (1 − 2ζ ) 2ζ 1 − ζ 2
• The phase of the system at ω = ωr can be given by,
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−1 ⎛ 2 ζu ⎞
φ r = − tan ⎜ ⎟
⎝ 1 − u2 ⎠ u = ur = 1− 2 ζ 2
⎛ 1 − 2ζ2 ⎞
−1
= − tan ⎜ ⎟
⎜ ζ ⎟
⎝ ⎠
• A typical magnitude versus frequency characteristic of a feedback control system can be given
as shown below.
M
Mr
1.0
1
= 0.707
2
0 ωr ωc ω
• A standard second order control system has unity gain at ω = 0 and the frequency at which the
1
magnitude drops to is called as cut-off frequency “ωc”. Generally for a control system the
2
bandwidth is nothing but the cut-off frequency.
1
So, M ω=ω =
c = ωb 2
ωb
• Let us take the normalized bandwidth as, ub = and it can be calculated as follows:
ωn
1 1
=
(1 − ub2 )2 + 4ζ 2 ub2 2
1 − 2 ub2 + ub4 + 4ζ 2 ub2 = 2
ub4 − 2(1 − 2ζ 2 )ub2 − 1 = 0
2(1 − 2 ζ 2 ) ± 4(1 − 2ζ 2 )2 + 4
ub2 =
2
2 2 4
= (1 − 2 ζ ) ± 2 − 4ζ + 4ζ
ub can be only a positive value.
So, ub = (1 − 2ζ 2 ) + 2 − 4ζ 2 + 4ζ 4
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• So, the bandwidth of a standard second order system is,
1/2
⎡ 2 2 4⎤
ωb = ωn ⎢(1 − 2ζ ) + 2 − 4ζ + 4ζ ⎥
⎣ ⎦
• The resonant frequency of a standard second order system is,
2
ωr = ωn 1 − 2ζ
• The resonant peak of a standard second order system is,
1
Mr =
2ζ 1 − 2ζ 2
Q.7 (c) Solution:

(i) To develop the root locus diagram of the given system:
K(s + 2)
G(s) =
(s + 1)2
• Open loop poles : s = –1, –1
Open loop zero : s = –2
Number of open loop poles, P = 2
Number of open loop zeros, Z = 1
Number of root locus branches terminate at infinity = P – Z = 1
• For K = 0, the branches of root locus diagram will originate at s = –1. For K = ∞, one root locus
branch terminate at s = –2 and another branch terminate at s = infinity.
• One root locus branch will terminate at infinity along a straight line asymptote, whose angle
with respect to real axis can be given by,
(2 q + 1)π
θ = ; q = 0, 1, 2, . . . . . (P – Z – 1)
P−Z
Here, P – Z = 1
π
So, θ = =π or 180°
1
• The point of intersection of asymptote with real axis is called as centroid and it is given by,
Σ(real parts of OL poles) − Σ(real parts of OL zeros)
σ =
P−Z
( −1 − 1) − ( −2)
= =0
1
• The root locus exists on the real axis to the left of s = –2.
jω
K = –∞ K=0
–2 –1 0 σ
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• These exists a breakaway point at s = –1 and a breakin point at a point on real axis left to s = –2
and this point can be determined as follows:
K( s + 2)
CE : 1 + =0
(s + 1)2
( s + 1)2
K = −
( s + 2)
dK
Solving, = 0
ds
−2( s + 2)( s + 1) + ( s + 1)2 (1)

= 0
(s + 2)2
(s + 1)[2(s + 2) – (s + 1)] = 0
(s + 1) (s + 3) = 0
s = –1, –3 ⇒ Both are valid break points
So, a breakaway point exists at s = –1 and a breakin point exists at s = –3.
( −1 + 1)2
At s = –1, K = − =0
( −1 + 2)
( −3 + 1)2
At s = –3, K = − =4
( −3 + 2)
• There are no complex open-loop poles or complex open-loop zeros. So, there is no need to
calculate any angle of departure or angle of arrival.
• The root locus plot completely lies on the left side to the jω-axis. So, there is no need to
calculate the intersection of root locus branches with jω-axis.
• With the help of all the above rules, the root locus plot (for 0 < K < ∞) of the given system can
be plotted as shown below.
jω
Asymtote K=∞
∞ ←K σ
s = –2
Centroid
Breakin point Breakaway point

s = –3 s = –1
K=4 K=0
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(ii) To determine ζ min using the root locus plot:
• In the above root locus plot, at a particular value of K, the damping ratio of the system will be
minimum and at this value of K, the ζ-line will be the tangent to the circle in root locus diagram
as shown below.
jω
jω0
ra
ζ-li
di
ne
us
=
1
φ0
s = –3 –2 σ0 s = –1 σ
(Centre)
ζmin = cos φ0
• From the above diagram, it is clear that, when ζ = ζmin, σ = σ0 and ω = ω0.
σ0
So, ζmin = cos φ0 =
σ02 + ω02
• The equation for circle in the root locus diagram can be given by,
(σ + 2)2 + ω2 = 1 ...(i)
• The equation for straight line tangent to the circle, which is passing through origin can be
given by,
ω = mσ ...(ii)
dω
m =
dσ
⎛ dω ⎞
ω = ⎜ ⎟σ ...(iii)
⎝ dσ ⎠
• From equation (i),
σ 2 + 4σ + 4 + ω2 = 1
σ 2 + 4σ + ω2 = –3 ...(iv)
dω
2σ + 4 + 2ω = 0
dσ
dω ( σ + 2)
= − ...(v)
dσ ω
dω
• By substituting of equation (v) in that of in equation (iii), we get,
dσ
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ω2 = –(σ + 2)σ = –σ2 – 2σ

σ2 + ω2 = –2σ ...(vi)
• From equations (iv) and (vi),
–2σ0 + 4σ0 = –3
3
σ0 = − = −1.5
2
σ02 + ω02 = –2σ0 = 3
• The minimum value of the damping ratio of the system is,
σ0 1.5 3
ζmin = cos φ0 = = =
σ02 + ω02 3 2
3
ζmin = = 0.866
2
Q. 8 (a) Solution
(i) F1(A, B, C, D) = Σm(0, 2, 3, 5, 7, 8, 9, 10, 11, 13, 15)
CD
00 01 11 10 BC
AB
0 1 3 2
00 1 1 1
4 5 7 6
01 CD
1 1
BD
12 13 15 14
11 1 1
AD
8 9 11 10
10 1 1 1 1
AB
BD
Possible prime implicants: BD , BD , AB , AD , BC ,CD

Essential prime implicants: BD, BD
To determine the possible minimal expressions:
The minterms of the given expression which are not covered by the essential prime implicants
are m3, m9, m11.
m3 is covered by ⇒ prime implicants BC , CD
m9 is covered by ⇒ prime implicants AB , AD
m11 is covered by ⇒ prime implicants AB , AD , BC , CD
So, the possible minimal expressions are,
F1(A, B, C, D) = BD + BD + BC + AB
= BD + BD + BC + AD
= BD + BD + CD + AB
= BD + BD + CD + AD
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(ii) F2(A, B, C, D) = Σm(0, 2, 4, 5, 6, 7, 8, 10, 13, 15)
CD
00 01 11 10
AB
0 1 3 2
00 1 1 AD
4 5 7 6
01 1 1 1 1 AB
12 13 15 14
11 1 1 BD
8 9 11 10
10 1 1
BD
Possible prime implicants: BD, BD, AB, AD
Essential prime implicants: BD, BD

To determine the possible minimal expressions:
The minterms of the given expression which are not covered by the essential prime implicant
are m4, m6.
m4 is covered by ⇒ prime implicants AB, AD
m6 is covered by ⇒ prime implicants AB, AD
So, the possible minimal expressions are,
F2(A, B, C, D) = BD + BD + AB
= BD + BD + AD
Q.8 (b) (i) Solution:

• It is given that, the input variables A, B and C are to be connected to the select lines of the MUX.
• So, the input signals to MUX can be determined by using the following table:
Q0
Q1 ABC ABC ABC ABC ABC ABC ABC ABC
D 0 2 4 6 8 10 12 14
D 1 3 5 7 9 11 13 15
I0 = D I1 = D I2 = D I 3 = 0 I4 = 0 I5 = D I6 = 1 I7 = 1
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Implementation:
I0
I1
I2
I3
8×1
Y F
I4 MUX
I5
I6
I7 S2 S1 S0
Logic-0 Logic-1 D A B C
Q.8 (b) (ii) Solution:

Largest 3 bit number is = (111)2 = (7)10
So square of (7)2 = (49)10 = (110001)2, that is, it requires 6 bit to represent output.
Let these outputs are Y5, Y4, Y3, Y2, Y1, Y0
Input Output
A B C Y5 Y4 Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 0 0 0
1 0 0 1 0 0 0 0 0 1
2 0 1 0 0 0 0 1 0 0
3 0 1 1 0 0 1 0 0 1
4 1 0 0 0 1 0 0 0 0
5 1 0 1 0 1 1 0 0 1
6 1 1 0 1 0 0 1 0 0
7 1 1 1 1 1 0 0 0 1
∴ Y5 = Σ(6, 7)
Y4 = Σ(4, 5, 7)
Y3 = Σ(3, 5)
Y2 = Σ(2, 6)
Y1 = 0
Y0 = Σ(1, 3, 5, 7)
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Solving for above outputs
BC BC BC BC BC BC BC BC
Y5 ⇒ A Y4 ⇒ A
A 1 1 A 1 1 1
Y5 = AB Y4 = AB + AC
BC BC BC BC BC BC BC BC
Y3 ⇒ A 1 Y2 ⇒ A 1
A 1 A 1
Y3 = ABC + ABC Y2 = BC
Y1 = 0
BC BC BC BC
Y0 ⇒ A 1 1
1 1
A
Y0 = C
Now the circuit will be

A A
Y5
B B
Y4
A
A C
B
C
Y3
A B
B Y2
C C
Y1 = 0
Y0 = C
Assuming inverted inputs are available, also 3-input AND gates are available.
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Q.8. (c) Solution:

• The open-loop transfer function of the given system is,
K (s + 3)(s + 5)
L(s) = G( s) H ( s) = ...(i)
(s − 2)(s − 4)
(i) Analysis using Nyquist stability criterion:
• The number of open-loop poles in the right-half of s-plane is, P = 2.
• The Nyquist plot of the given system can be obtained by mapping the contour which encloses
the entire right-half of s-plane on to the L(s) = G(s)H(s) plane. This contour which encloses the
right-half of s-plane is called as the Nyquist contour, which is shown below.
jω θ
C2 : s = lim Re j
+j∞ R→∞
C2 π π
θ : + to −
C1 2 2
+
j0
–5 –3 j0
–
2 4 σ
C3 s-plane
–j∞
Segment C1 of the Nyquist contour can be mapped on to the L(s) plane as follows:
• For this segment, s = jω and ω is varying from 0+ to ∞.
• For the purpose of mapping C1, the open-loop transfer function of the given system can be
modified by replacing “s” with “jω”.
K (3 + jω)(5 + jω)
L( jω) =
( −2 + jω) ( −4 + jω)
15 K
At ω = 0+, L( jω) = ∠0°
8
At ω = ∞, L( jω) = K∠0°
At ω = 1, L( jω) = 1.75K∠70.35°
• The intersection points of Nyquist plot with 180° line can be investigated as follows:
⎛ ω⎞ ⎛ ω⎞ ⎛ ω⎞ ⎛ ω⎞
tan −1 ⎜ ⎟ + tan −1 ⎜ ⎟ − 180° + tan −1 ⎜ ⎟ − 180° + tan −1 ⎜ ⎟ = –180°
⎝3⎠ ⎝5⎠ ⎝2⎠ ⎝4⎠
⎛ 8ω ⎞ ⎛ 6ω ⎞
tan −1 ⎜ 2⎟
+ tan −1 ⎜ ⎟ = 180°
⎝ 15 − ω ⎠ ⎝ 8 − ω2 ⎠
8ω(8 – ω2) + 6ω(15 – ω2) = 0

ω(64 – 8ω2 + 90 – 6ω2) = 0
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14 ω2pc − 154 = 0
ω2pc = 11
ωpc = 11 rad/sec = 3.316 rad/sec
L( jω ) 4K
ω = ω pc = 11 = = 1.33K
3
• The intersection points of Nyquist plot with 90° line can be investigated as follows:
⎛ 8ω ⎞ −1 ⎛ 6 ω ⎞
tan −1 ⎜ ⎟ + tan ⎜ ⎟ = 90°
⎝ 15 − ω2 ⎠ ⎝ 8 − ω2 ⎠
⎡ 8ω(8 − ω2 ) + 6ω(15 − ω2 ) ⎤
tan −1 ⎢ 2 2 2⎥
= 90°
⎢⎣ (15 − ω )(8 − ω ) − 48ω ⎥⎦
2 4 = 0
120 − 71 ω90 + ω90
2 71 ± (71)2 − 480
ω90 = = 1.73, 69.3
2
Valid value ω90 will be less than ωpc.
So, ω90 = 1.73 = 1.316 rad/sec
• The intersection points of the Nyquist plot with 270° line can be investigated as follows:
⎛ 8ω ⎞ −1 ⎛ 6 ω ⎞
tan −1 ⎜ ⎟ + tan ⎜ ⎟ = 270°
⎝ 15 − ω2 ⎠ ⎝ 8 − ω2 ⎠
120 − 71 ω2270 + ω270

4 = 0
ω270 = 69.3 = 8.32 rad/sec (∵ ω270 > ωpc )
• Nyquist plot corresponding to the segment C1 of the Nyquist contour is as follows:
Im[L (s)]
L(s) - Plane
ω90 = 1.316
ωpc = 11 ω= ∞ ω = 0+
–4K 0 K 15K Re[L(s)]
3 8
ω270 = 8.32
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Segment C3 of the Nyquist contour can be mapped by taking the mirror image (about real axis) of
the Nyquist plot corresponding to segment C1 as shown below:
Im[L(s)]
L(s) - Plane
ωpc = 11 ω = ±∞ ω = 0+, 0–
–4K 0 K 15K Re[L(s)]
3 8
Segment C2 of the Nyquist contour can be mapped on to the L(s)-plane as follows:

π π
• Along the segment C2, “s” can be written as lim Re j θ where θ varies from + to − .
R →∞ 2 2
K (3 + Re jθ ) (5 + Re jθ )
L(s) = lim = K ∠ 0°
R → ∞ ( −2 + Re j θ )( −4 + Re j θ )
• So, the segment C2 of the Nyquist contour can be mapped on to the L(s)-plane as a point K∠0°.
• The overall Nyquist plot of the given system can be drawn as follows:
Im[L(s)]
ω90 = 1.316
ω90 = –8.32
ωpc = 11 ω = ±∞ ω = 0+ , 0–
II –4K 0 K 15K Re[L(s)]

I
3 8
ω270 = 8.32
ω270 = –1.316
Nyquist stability criterion:

• To determine the stability of the closed-loop system, the number of encirclements of the
point (–1 + j0) by the Nyquist plot should be determined, which will be equal to,
N(–1 + j0) = P – Z
where, P = Number of open-loop poles in the right-half of s-plane
Z = Number of closed-loop poles in the right-half of s-plane
• The closed-loop system will be stable, when Z = 0.
• When Z = 0, N(–1 + j0) = P – 0 = P = 2
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• When the point (–1 + j0) lies in the region-I of the Nyquist plot,
N(–1 + j0) = 2 ⇒ system will be stable
When the point (–1 + j0) lies in the region-II of the Nyquist plot,
N(–1 + j0) = 0 ⇒ system will be stable
• So, to make the closed-loop system stable, the Nyquist plot should encircle the point (–1 + j0),
4K
which is possible when > 1.
3
• Hence, the system will be stable for,

4K
> 1
3
3
K > = 0.75
4
(ii) To verify the result using Routh stability criterion:
• The characteristic equation of the given system is,
(s2 – 6s + 8) + K(s2 + 8s + 15) = 0
(1 + K)s2 + (8K – 6)s + (15K + 8) = 0
• Using the Routh table, the system will be stable, when the following conditions are satisfied.
s2 (1 + K ) (15K + 8)
(1 + K) > 0 ⇒ K > –1 ...(i) 1
s (8K − 6) 0
(8K – 6) > 0 ⇒ K > 0.75 ...(ii)
s0 (15K + 8)
(15K + 8) > 0 ⇒ K > –0.53 ...(iii)
• From conditions (i), (ii) and (iii), we can conclude that the given closed-loop system will be
stable for K > 0.75.
• The range of K obtained is same in both the methods.

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ESE-2018 Mains Test Series: Electrical Engineering Test No: 2

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ESE-2018 Mains Test Series: Electrical Engineering Test No: 2

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Detailed Solutions

ESE-2018 Electrical Engineering

Section A : Electrical Circuits + Microprocessors

Q.1 (a) Solution:

VA2 (54 /7)2

VB2 (30 / 7)2

(VA − VB )2 (24 /7)2

Q.1 (b) Solution:

250 V 250 V R2 –jX2

To determine the values of R1 and X1 (also C1) of model-1 :

To determine the value of R2 and X2 (also C2) of model-2 :

Q.1 (c) Solution:

v1(t) + v2(t) = vc(t)

dv1 (0+ ) dvC (0 + ) dv2 (0 + )

v2(t) = (10 Ω) i1(t)

Q.1 (d) Solution:

Q.2 (a) Solution:

I1′ 8Ω 6Ω I2′ I1′′ 4Ω Ip I2′′

• From equations (i) and (ii), we get,

• By applying KVL in loop (1) of network - 2, we get,

• By applying KVL in loop (2) of network - 2, we get,

• From equations (iii) and (iv), we get,

V2 = 10I1 + 44I2 ...(viii)

V1 = 8Ia + 10Ia = 18Ia

When port-1 is open circuited:

By applying KVL in input side loop, we get,

Q.2 (b) Solution:

Using current division rule,

Using current division rule,

Vx′′ = I x′′ × 2 Ω = − 1.8 V

Using current division rule,

Vx = Vx′ + Vx′′ + Vx′′′ + Vx′′′′ = 1.2 – 1.8 – 3 + 3 = –0.6 V

Load register D with 0AH

HL register pair is pointed to

Move content of memory

8085 assembly language program:

Q.3 (a) Solution:

From the matrix Aa t , we can notice that,

So, the set of branches {1, 3, 4, 5} constitute a tree of the graph.

Where, Bl = U3 × 3 = identity or unit matrix of order 3 × 3

Q.3 (b) Solution:

By taking the inverse Laplace transform of I(s), we get,

Q.3 (c) Solution

ANI F0H ; Separate the MSD of the 2-digit BCD number

Q.4 (a) Solution:

So, VA – 4 V + 2[VA – 2VA + 8 V] = 6 V

Q.4 (b) Solution:

M=1H (L1 – M) = 1 H (L2 – M) = 0 H

• So, the given circuit can be equivalently drawn as,

• By using mesh analysis, we can write,

200 + j 200 j 200

Q.4 (c) Solution:

Q.4 (d) Solution:

Section B : Digital Electronics-1 + Control Systems-1

(iv) ABCD + AB(CD) + ( AB)CD = ABCD + AB(C + D) + ( A + B)CD

(v) ABC ⎡⎣ AB + C (BC + AC )⎤⎦ = ABC ⎡⎣ AB + BCC + ACC ⎤⎦

4 : 1 Multiplexer with low input at ‘G’ (enable)

Q.5 (c) Solution:

P i = Gain of ith forward path

Q.5 (d) Solution:

Q.5 (e) Solution:

So, the minimized expression of the given logic expression is,

Damping ratio (ξ) is equal to, ξ = cos φ