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Electronic Circuits I
By
Mr. J.SHANMUGASUNDARAM
ASSISTANT PROFESSOR
OUTCOMES:
REFERENCES:
1. Adel .S. Sedra, Kenneth C. Smith, “Micro Electronic Circuits”, 6th Edition, Oxford University
Press, 2010.
2. David A., “Bell Electronic Devices and Circuits”, Oxford Higher Education Press, 5th Editon,
2010
3. Behzad Razavi, “Design of Analog CMOS Integrated Circuits”, Tata Mc Graw Hill, 2007.
4. Paul Gray, Hurst, Lewis, Meyer “Analysis and Design of Analog Integrated Circuits”,
4thEdition ,John Willey & Sons 2005
5. Millman.J. and Halkias C.C, “Integrated Electronics”, Mc Graw Hill, 2001. 6. D.Schilling and
C.Belove, “Electronic Circuits”, 3rd Edition, Mc Graw Hill, 1989.
Sl.No Contents Page No
1.1 Introduction
BJT consists of 2 PN junctions. It has three terminals: emitter, base and collector.
Transistorcan be operated in three regions, namely cut-off, active and saturation by applying
proper biasing conditions.
When we bias a transistor we establish a certain current and voltage conditions for the
transistor. These conditions are known as operating conditions or d.c. operating point or
quiescent point. The operating point must be stable for proper operation of the transistor.
However, the operating point shifts with changes in transistor parameters such as β, Ico and
VBE. As transistor parameters are temperature dependent, the operating point also varies with
changes in temperature.
1.2 Need for biasing
Fig.1.1 (a)
Bias establishes the DC operating point for proper linear operation of an amplifier. If an
amplifier is not biased with correct DC voltages on the input and output, it can go into
saturation or cutoff when an input signal is applied. Figure 1.1 shows the effects of proper and
improper DC biasing of an inverting amplifier. In part (a), the output signal is an amplified
replica of the input signal except that it is inverted, which means that it is 180 0 out of phase
with the input. The output signal swings equally above and below the dc bias level of the
output, VDC(out).
Biasing is the application of dc voltages to establish a fixed level of current and voltage.
For transistor amplifiers the resulting dc current and voltage establish an operating point on the
characteristics that define the region that will be employed for amplification of the applied
signal. Since the operating point is a fixed point on the characteristics, it is also called the
quiescent point (abbreviated Q-point). The operating point of a device, also known as bias
point, quiescent point, or Q-point, is the point on the output characteristics that shows the DC
collector–emitter voltage (Vce) and the collector current (Ic) with no input signal applied.
Fig 1.2
We have,
We can draw a straight line on the graph of I C versus VCE which is having slope -1/Rc.To
determine the two points on the line we assume VCE = VCC and VCE =0
a) When VCE =VCC ; IC =0 and we get a point A
b) When VCE=0 ; IC=VCC/RC and we get a point B
The figure below shows the output characteristic curves for the transistor in CE mode. The DC
load line is drawn on the output characteristic curves. Load line - To draw load line, we have
to find saturation current and the cutoff voltage.
Saturation point - The point at which the load line intersects the characteristic curve near the
collector current axis is referred to as the saturation point . At this point of time, the current
through the transistor is maximum and the voltage across collector is minimum for a given
value of load. So, saturation current for the fixed bias circuit, Ic (sat) =Vcc/Rc .
Cutoff point -The point where the load line intersects the cutoff region of the collector curves
is referred as the cutoff point (i.e. end of load line). At this point, collector current is
approximately zero and emitter is grounded for fixed bias circuit. so, Vce (cut) = Vc = Vcc
Operating point - The "Q point" for a transistor amplifier circuit is the point along its
operating region in a "quiescent ", where no input signal gets amplified.
The figure below shows the output characteristic curves for the transistor in CE mode with
points A and B, and line drawn between them. The line drawn between points A and B is called
d.c load line. The d.c word indicates that only d.c conditions are considered, i.e input signal is
assumed to be zero.
Fig 1.3
The d.c load line is a plot of IC versus VCE. For a given value of Rc and a given value of
Vcc. So, it represents all collector current levels and corresponding collector emitter voltages
that can exist in the circuit. Knowing any one of Ic, IB, or VCE , it is easy to determine the other
two from the load line. The slope of the d.c load line depends on the value of RC. It is the
negative and equal to reciprocal of the RC.
Applying KVL to the base circuit, we get
The intersection of curves of different values IB of with d.c load line gives different operating
points. For different values of IB, we have different intersection points such as P, Q and R.
The operating point can be selected at different positions on the d.c load line, near
saturation region, near cut-off region or at the centre, i.e in the active region. The selection of
operating point will depend on its application. When transistor is used as an amplifier, the Q
point should be selected at the center of the d.c. load line to prevent any possible distortion in
the amplified output signal.
Case 1
Biasing circuit is designed to fix a Q point at point P which is very near to the
saturation region as shown in figure below 1.14. It results collector current is clipped at the
positive half cycle. i.e. distortion is present at the output. Therefore, point P is not a suitable
operating point.
Case 2
Biasing circuit is designed to fix a Q point at point R as shown in Fig. Point R is very
near to the cut-off region. Here, the collector current is clipped at the negative half cycle. So,
point R is also not a suitable operating point.
Case 3
Biasing circuit is designed to fix a Q point at point Q as shown in Fig.. The output signal is
sinusoidal waveform without any distortion. Thus point Q is the best operating point.
DC Load Line (Example)
Fig 1.7
The figure 1.7 shows the biasing of transistor in common emitter configuration.
In Figure 1.8, we assign three values to I B and observe what happens to IC and VCE.
First, VBB is adjusted to produce an IB of 200 A, as shown in Figure 1.8(a), Since I C = βDC IB, the
collector current is 20 mA, as indicated, and
Figure 1.9
Actually, there is a small voltage (VCE (sat)) across the transistor, and I C(sat) is slightly less
than 45.5 mA, as indicated in Figure 1.4. Note that Kirchhoff's voltage law applied around
the collector loop gives,
VCC - ICRC - VCE = 0.
These results in a straight line equation for the load line of the form y = mx + b as follow:
IC = - (1/RC) VCE +VCC / RC
Where, - (1/RC) is the slope and VCC / RC is the y-axis intercept point.
It is clear that the biasing circuit should be designed to fix the operating point or Q
point at the center of the active region. But only fixing of the operating point is not sufficient.
While designing the biasing circuit, care should be taken so that the operating point will not
shift into an undesirable region (i.e. into cut-off or saturation region). Designing the biasing
circuit to stabilize the Q point is known as bias stability.
Two important factors are to be considered while designing the biasing circuits which
are responsible for, shifting the operating point.
I. Temperature
1) Ico: The flow of current in the circuit produces heat at the junctions. This heat
increases the temperature at the junctions". We know that the minority carriers are temperature
dependent. They increase with the temperature. The increase in the minority carriers increases
the leakage current ICE0,
Specifically, ICB0 doubles for every 10°C rise in temperature. Increase in ICE0 in turn increases
the collector current
The increase in IC further raises the temperature at the collector junction and the same cycle
repeats. This excessive increase in IC shifts the operating point into the saturation region,
changing the operating condition set by biasing circuit.
As the power dissipated within a transistor is predominantly the Power dissipated at its
collector base junction, the power dissipation is given as
The increase in the collector current increases the power dissipated at the collector junction.
This, in turn further increases the temperature of the junction and hence increases
the collector current. The process is cumulative. The excess heat produced at the collector base
junction may even burn and destroy the transistor. This situation is called 'Thermal runaway’ of
the transistor. For any transistor, maximum Power dissipation is always a fixed value. That is
known as maximum power dissipation rating of a transistor. This value is specified by the
manufacturer in data sheet. If this limit is crossed, the device will fail.
2) VBE : Base to emitter voltage VBE changes with temperature at the rate of 2.5mV/°C
Base current, IB depends upon VBE .As base current IB depends on VBE, and Ic depends on IB, Ic
depends on VBE. Therefore collector current Ic. Change with temperature due to change in V BE.
The change in collector current change the operating point.
3)βdc: βdc of the transistor is also temperature dependent. As βdc varies, Ic also varies,
since Ic = βIB. The change in collector current change the operating point.
Therefore, to avoid thermal instability, the biasing circuit should be designed to provide a
degree of temperature stability i.e. even though there are temperature changes, the changes in
the transistor parameters (VCE , I CQ , PDmax )should be very less so that the operating point
shifting is minimum in the middle of the active region.
II) Transistor current gain hFE/β
Eventhough there is tremendous advancement in semiconductor technology, there are
changes in the transistor parameters among different units of the same type, same number. This
means if we take two transistor units of same fire (i.e. same number, construction, parameter
specified etc.) and use them in the circuit, there is change in the β value in actual practice. The
biasing circuit is designed according to the required β value. But due to change in β from unit
to unit, the operating point may shift
Figure shows the common emitter output characteristics for two transistors of the same type.
The dashed characteristics are for a transistor whose p is much larger than that of the transistor
represented by the solid curves.
So for stabilizing the operating point the factors discussed so far should be considered while
designing the biasing circuit.
The Figure shows the fixed bias circuit. It is the simplest d.c. bias configuration. For the d.c.
analysis we can replace capacitor with an open circuit because the reactance of a capacitor for
d.c. is
In this circuit VE =0
Stability factor S for Fixed bias circuit
Merits:
• It is simple to shift the operating point anywhere in the active region by merely
changing the base resistor (RB).
• A very small number of components are required.
Demerits:
• The collector current does not remain constant with variation in temperature or power
supply voltage. Therefore the operating point is unstable.
• Changes in Vbe will change IB and thus cause RE to change. This in turn will alter the
gain of the stage.
• When the transistor is replaced with another one, considerable change in the value of β
can be expected. Due to this change the operating point will shift.
• For small-signal transistors (e.g., not power transistors) with relatively high values of β
(i.e., between 100 and 200), this configuration will be prone to thermal runaway. In
particular, the stability factor, which is a measure of the change in collector current with
changes in reverse saturation current, is approximately β+1. To ensure absolute stability
of the amplifier, a stability factor of less than 25 is preferred, and so small-signal
transistors have large stability factors.
Usage:
Due to the above inherent drawbacks, fixed bias is rarely used in linear circuits (i.e., those
circuits which use the transistor as a current source). Instead, it is often used in circuits where
transistor is used as a switch. However, one application of fixed bias is to achieve crude
automatic gain control in the transistor by feeding the base resistor from a DC signal derived
from the AC output of a later stage.
Problems
1. Design the fixed bias circuit from the load line given in the figure.
2. For the circuit shown in figure. Calculate IB,IC,VCE,VB,VC and VBC. Assume VBE= 0.7V
and β=50.
3. Design a fixed biased circuit using a silicon transistor having β value of 100. Vcc is 10 V
and dc bias conditions are to be VCE = 5 V and IC = 5 mA,
Solution
Applying KVL to collector circuit,
IC = IB * β = 2.15 mA
VCE = VCC - (RC * IC)= 5.7V
To maintain the Q point stable by keeping IC and VCE constant so that the transistor will always
work in active region, the following techniques are normally used,
1. Stabilization technique
2. Compensation technique
1.7 Method of stabilizing the Q point
Stabilization technique:
It refers to the use of resistive biasing circuits which allow IB to vary so as to keep IC
relatively constant with variations in ICO, β and VBE.
Compensation technique:
It refers to the use of temperature sensitive devices such as diodes, transistors,
thermistors which provide compensating voltage and current to maintain Q point stable.
Stability factor S:
Stability Factor for Fixed bias circuits:
Stability factor S:
………(6)
Stability factor S’:
S” = IC(1+β)
_____
β(1+β)
S” = IC S
______
β(1+β)
also called as collector to base bias circuit. It is an improvement over fixed bias method. In this,
biasing resistor is connected between collector and base of the transistor to provide feedback
path.
Circuit analysis:
Base circuit:
Consider the base circuit and applying voltage law then we get,
Only the difference between the equation for IB and that obtained for fixed bias
configuration is βRC, so the feedback path results in a reflection of the resistance RC to the input
circuit.
Collector circuit:
Applying KVL to the collector circuit,
VCC – (IC + IB) RC – VCE = 0
VCE = VCC – (IC + IB) RC
Base circuit:
Only difference between the equation for IB and that obtained for the fixed bias
configuration is the term β (RC + RE).So feedback path results in a reflection of the resistance
RC back to the input circuit.
In general,
Collector circuit:
Applying KVL to collector circuit,
VCC – (IC+IB) RC – VCE – IERE = 0
VCE = VCC – IE (RC+RE)
S= 1+β
______________
1+β (RC/ (RC+RB))
Collector to base bias circuit is having lesser stability factor than for fixed bias circuit.
So this circuit provides better stability than fixed bias circuit.
Problem 1:
Locate the operating point of the given circuit with VCC = 15V, hfe = 200.
Solution:
IBQ = VCC - VBE
___________
RB+ (1+β) (RC+RE)
= 15-0.7
________________________
630*103 + (1+200) (4.7*103+680)
ICQ = β IBQ = 200*8.356*10-6
= 1.6712mA
IEQ = ICQ + IBQ = 1.6712*10-3 + 8.356*10-6
= 1.68mA
VCEQ = VCC – IE (RC+RE)
= 15-1.68*10-3 (4.7*103 + 680)
= 5.96V
1.11 Voltage divider bias circuit or self bias circuit:
Figure shows the voltage divider bias circuit. In this, biasing is provided by three
resistors R1, R2 and RE. The resistors R1 & R2 act as a potential divider giving a fixed voltage to
base. If collector current increases due to change in temperature or change in β, emitter current
IE also increases and voltage drop across RE increases thus reducing the voltage difference
between base and emitter. Due to reduction in base emitter voltage, base current and collector
current reduces. So we can say that negative feedback exists in emitter bias circuit. This
reduction in collector current compensates for the original change in IC.
Circuit analysis:
Basecircuit:
Collector circuit:
Apply KVL,
Problem 1:
For the given circuit β=100 for silicon transistor. Calculate VCE and IC.
Solution:
Problem 2:
For the given figure find Q point with VCC = 15V, VBE = 0.7V and β = 100.
Solution:
For determining stability factor S for voltage divider bias, consider the equivalent circuit.
Thevenin’s voltage is given by,
Solution:
R2 is not given. So assume R2 = 10KΩ
RB = R1*R2
______ = 9.09KΩ
R1+R2
IB = VT-VBE
_____________ = 114µA
RB+ (1+β)RE
IC = βIB = 5.7mA
Circuit analysis:
Base circuit:
1.12 Compensation technique:
It refers to the use of temperature sensitive devices such as diodes, transistors, thermistors
which provide compensating voltage and current to maintain Q point stable.
1.12.1 Diode Compensation Techniques
Compensation for VBE:
a) Diode in Emitter Circuit
Diagram shows the voltage divider bias with bias compensation technique.Here, separate
supply VDD is used to keep diode in forward If biased condition. If the diode used in the circuit
is of same material and type as the transistor, the voltage across the diode will have the same
temperature coefficient as the base to emitter voltage VBE . So when VBE changes by
with change in temperature, VD changes by
and , the changes tend to cancel each other.
Figure: Stabilization by means of voltage divider bias and diode Compensation Technique
As VD tracks VBE with respect to temperature it is clear that IC will be insensitive to variations
in VBE.
• Diode is connected in series with resistance R2 in the voltage divider circuit and
it is forward biased condition.
Here, thermistor is connected between emitter and Vcc to minimize the increase in
collector current due to changes in ICO, VBE, or beta with temperature .IC increases with
temperature and RT decreases with increase in temperature. Therefore, current flowing
through RE increases, which increases the voltage drop across it. E - B junction is forward
biased. But due to increase in voltage drop across R E, emitter is made more positive, which
reduces the forward bias voltage VBE. Hence, bias current reduces.
This method of transistor compensation uses temperature sensitive resistive element, sensistors
rather than diodes or transistors. It has a positive temperature coefficient, its resistance increases
exponentially with increasing temperature as shown in the Fig
is the temperature coefficient for thermistor and the slope is positive So we can say
that sensistor has positive temperature coefficient of resistance (PTC).
Fig above shows sensistor compensation R1 is replaced by sensistor RT in self bias circuit.
Now, RT and R2 resistors of the potential divider. As temperature increases, RT increases which
decreases the current flowing through it. Hence current through R2 decreases which reduces
the voltages drop across it. Voltage drop across R2 is the voltage between base and ground. So
VBE reduces which decreases 16. It means, when ICBO increases with increase in temperature, IB
reduces due to reduction in VBE, maintaining IC fairly constant.
Thermal stability:
Thermal resistance:
Condition for Thermal stability:
1.13 FET Biasing
• The Parameters of FET is temperature dependent .When temperature increases
drain resistance also increases, thus reducing the drain current.
• Unlike BJTs, thermal runaway does not occur with FETs
• However, the wide differences in maximum and minimum transfer
characteristics make ID levels unpredictable with simple fixed-gate bias voltage.
• Different biasing circuits of FET are
1) Fixed bias circuits
2) Self bias circuits
3) Voltage bias circuits
Fixed bias circuits
DC bias of a FET device needs setting of gate-source voltage V GS to give desired drain
current ID . For a JFET drain current is limited by the saturation current I DS. Since the FET
has such a high input impedance that no gate current flows and the dc voltage of the gate
set by a voltage divider or a fixed battery voltage is not affected or loaded by the FET.
Fixed dc bias is obtained using a battery VQG. This battery ensures that the gate is
always negative with respect to source and no current flows through resistor
RG and gate terminal that is IG =0. The battery provides a voltage V GS to bias the
N-channel JFET, but no resulting current is drawn from the battery V GG.
Resistor RG is included to allow any ac signal applied through capacitor C to
develop across RG. While any ac signal will develop across RG, the dc voltage
drop across RG is equal to IG RG i.e. 0 volt.
Calculate VGS
For DC analysis IG =0., applying KVL to the input circuits
VGS+ VGG=0
VGS= - VGG
As VGS is a fixed dc supply, hence the name fixed bias circuit
Calculate IDQ
IDQ= IDss(1- VGS/VGp)2
Calculate VDS
This current IDQ then causes a voltage drop across the drain resistor R D and is
given as
VDSQ = VDD – ID RD
Disadvantage
The fixed bias circuit of FET requires two power supplies.
Self-Bias circuits
Self-Bias circuits is the most common method for biasing a JFET. Self-bias
circuit for N-channel JFET is shown in figure
• The gate source junction of JFET must be always in reverse biased condition
.No gate current flows through the reverse-biased gate-source, the gate current
IG = 0 and, therefore,vG = iG RG = 0
• With a drai current I the voltage a the S is
Vs= ID n D t
Rs
1)The gate-source voltage is then
VGS = VG - Vs = 0 – ID RS = – ID RS
So voltage drop across resistance Rs provides the biasing voltage VGg and no external
source is required for biasing and this is the reason that it is called self-biasing.
2)Calculate IDQ
ID= IDSS(1- VGS/ VP)2
Substituting the value of VGS
ID= IDSS (1+ID RS / VP)2
3)The operating point (that is zero signal ID and VDS) can easily be determined from
equation given below :
VDS = VDD – ID (RD + RS)
Self biasing of a JFET stabilizes its quiescent operating point against any change in its
parameters like transconductance. Any increase in voltage drop across RS, therefore,
gate-source voltage, VGS becomes more negative and thus increase in drain current is
reduced.
Voltage -Divider Bias circuits
The resistors RGl and RG2 form a potential divider across drain supply VDD. The voltage
V2 across RG2 provides the necessary bias. The additional gate resistor R Gl from gate to
supply voltage facilitates in larger adjustment of the dc bias point and permits use of
larger valued RS.
The coupling capacitors are assumed to be open circuit for DC
analysis 1) The gate is reverse biased so that IG = 0 and gate
voltage
VG =V2 = (VDD/R G1 + R G2 ) *RG2
2) Applying KVL to the input circuit we get
VGS = VG – VS = VG - ID RS
3) IDQ= IDSS(1- VGS/ VP)2
4) VDS = VDD – ID (RD + RS)
The operating point of a JFET amplifier using the Voltage -Divider Bias is
determined by
IDQ= IDSS(1- VGS/ VP)2
VDSQ = VDD – ID (RD + RS)
VGSQ = VG – ID RS
Example Problems
1)Determine IDQ, VGSQ, VD, VS, VDS, and VDG
Solution
*Example 4
Example Problem
As Ig = 0 in VG is given as,
Assume VG > VT , MOSFET is biased in the saturation region, the drain current is,
The two end points of the load line are determine in the usual manner. If the drain
current = 0, then VDS= 10 v; if VDS = 0, then drain current = 10/40 = 0.25 mA. The Q-
point of the MOSFET is given by the d.c. drain current (ID) and drain-to-source voltage
(VDS) and it is always on the load line, as shown in the Fig. b).
If the gate-to-source voltage is less than V1, the drain current is zero and the MOSFET
is in cut-off. As the gate-to- source voltage becomes just greater than the threshold
voltage, the MOSFET turns ON and is biased in the saturation region. As V GS
increases, the Q-point moves up the load line. The transition point is the boundary
between the saturation and non-saturation regions. It is the point where,
Because ID = IS
Biasing Circuit for D MOSFET
Biasing circuits for depletion type MOSFET are quite similar to the circuits
used for JFET biasing. The primary difference between the two is the fact that depletion
type MOSFETs also permit operating points with positive value of V6s for n-channel
and negative values of V6s for p-channel MOSFET. To have positive value of V GS for
n-channel and negative value of V6s for p-channel self bias circuit is unsuitable.
Example problem-1
Example – 2
Example-3
Example-4
QUESTIONS
2 MARK
1. What is DC load line? Draw the DC load line of the circuit shown in fig.
2. Find the collector and base current of circuit diagram given in fig, having hfe = 100,
VBE(on) = 0.7V
16 MARK
1. Explain the voltage divider bias method & derive an expression for stability factors.
2. Why biasing is necessary in BJT amplifier? Explain the concept of DC & AC load line with
neat diagram.
3. How will you select the operating point, explain it using CE amplifier characteristics?
4. Explain the collector feedback bias amplifier & derive an expression for stability factors.
5. Explain the fixed bias method & derive an expression for stability factors.
6. Derive an expression for all stability factors & CE configuration S equation.
7. Explain about common source self- bias & voltage divider bias for FET.
8. Explain in details about biasing MOSFET.
9. Discuss the various types of bias compensation.
10.Explain constant current biasing used in JFET amplifier. (May,06)
11.Draw and explain voltage divider bias using FET and derive for its stability factors. Also
mention its advantages. (May,11)
12. How is a JFET used as a voltage variable resistance? Explain. (Nov,07) (May,07)
13.Explain the bias circuit for enhancement MOSFET and explain its operation.
(Nov,14; Nov,13)
14.With circuit diagram explain biasing of FET and MOSFET. (Nov,07)
15.Discuss the various techniques of stabilization of Q- point in a transistor. (Nov,09; May,13)
16. The fixed bias circuit as shown in figure is subjected to an increase in junction temperature
from 25oC to 75oC. If β is 125 at 75oC, determine the percentage change in Q point values
(VCE, IC) over temperature change. Neglect any change in VBE.
17. A self bias circuit has RE=1 kΩ, R1=130 kΩ, R2=10 kΩ. If VCC and RC are adjusted to give
IC=1mA at 10oC. Calculate the variation in Ic over temperature change of 10 oC to 100oC.
The transistor used has the parameters given below,
18. Design a collector to base bias circuit to have operating point (10v, 4mA). The circuit is
supplied with 20v and uses a silicon transistor of hfe is 250.
19. Design a voltage divider bias circuit for the specified conditions. VCC=12v, VCE=6v,
IC=1mA, S=20, β=100 and VE=1v.
20. The parameters for each transistor in the circuit in figure, are hfe = 100, and VBE(on) = 0.7V.
Determine the Q-point values of base collector and emitter currents in Q1 and Q2
(8)[AU, MAY,2015]
21. Determine the change in collector current produced in each bias referred to in fig 1 and 2,
when the circuit temperature raised from 25oC to 105oC and ICBO = 15nA @ 25oC
(8)[AU, MAY,2015]
22. Determine the quiescent current and voltage values in a P-Channel JFET circuit shown in
fig. (8)[AU, MAY,2015]
23. The circuit shown in Fig, let hfe = 100, (1). Find VTH and RTH for the base circuit. (2).
Determine ICEQ and VCEQ. (3). Draw the DC load line. (8)[AU, MAY,2015]
2.1 Introduction
An amplifier is used to increase the signal level. It is used to get a larger signal
output from a small signal input. Assume a sinusoidal signal at the input of the amplifier.
At the output, signal must remain sinusoidal in waveform with frequency same as that of
input. To make the transistor work as an amplifier, it is to be biased to operate in active
region. It means base-emitter junction is forward biased and base-collector junction is
reverse biased.
Let us consider the common emitter amplifier circuit using voltage divider bias.
In the absence of input signal, only D.C. voltage is present in the circuit. It is
known as zero signal or no signal condition or quiescent condition. D.C. collector-emitter
voltage VCE, D.C. collector current IC and base current I B is the quiescent operating point
for the amplifier. Due to this base current varies sinusoidaly as shown in the below figure.
Fig. IBQ is quiescent DC base current
If the transistor is biased to operate in active region, output is linearly proportional
to the input. The collector current is β times larger than the input base current in CE
configuration. The collector current will also vary sinusoidally about its quiescent value
ICQ. The output voltage will also vary sinusoidally as shown in the below figure.
Variations in the collector current and voltage between collector and emitter due
to change in base current are shown graphically with the help of load line in the above
figure.
Phase reversal:
The phase relationship between the input and output voltages can be determined by
considering the effect of positive and negative half cycle separately. The collector
current is β times the base current, so the collector current will also increases. This
increases the voltage drop across RC.
VC = VCC - ICRC
From above circuit, D.C. biasing is provided by R1, R2 and RE. The load resistance is
capacitor coupled to the emitter terminal of the transistor. When a signal is applied to
base of the transistor, VB is increased and decreased as the signal goes positive and
negative respectively.
From figure, VE = VB - VBE
Consider VBE is constant, so the variation in VB appears at emitter and emitter voltage VE
will vary same as base voltage VB. In common collector circuit, emitter terminal follows
the signal voltage applied to the base. It is also known as emitter follower.
2.4 Common Base Amplifier Circuit:
From above circuit, the signal source is coupled to the emitter of the
transistor through C1. The load resistance RL is coupled to the collector of the transistor
through C2. The positive going pulse of input source increases the emitter voltage. As
base voltage is constant, forward bias of emitter-base junction reduces. This reduces I b, Ic
and drop across Rc.
Vo = VCC - ICRC
Reduction in IC results in an increase in Vo. Positive going input produces positive going
output and vice versa. So there is no phase shift between input and output in common
base amplifier.
Input current is an independent variable. Input voltage and output current are dependent
variables. Input current and output voltage are independent variables.
Definitions of h-parameter:
The parameters in the above equations are defined as follows:
Benefits of h-parameters:
1. Real numbers at audio frequencies
2. Easy to measure
3. Can be obtained from the transistor static characteristic curve
4. Convenient to use in circuit analysis and design
5. Most of the transistor manufacturers specify the h-parameters
The basic circuit of hybrid model is same for all three configurations, only parameters
are different.
The circuit and equations are valid for either NPN or PNP transistor and are
independent of the type of load or method of biasing.
The input characteristic curve gives the relationship between input voltage
VBE and input current I B for different values of output voltage VCE. The following figure
shows the typical input characteristic curve for CE configuration.
Parameter hre:
The output characteristic curve gives the relationship between output current IC and
output voltage VCE for different values of input current IB.
Parameter hoe:
hoe =
Let us analyze the hybrid model to find current gain, input resistance, voltage gain and
output resistance.
Current gain (Ai):
It is given by,
Substituting
Then we get,
From this equation, note that the input impedance is a function offload impedance.
Voltage gain (Av):
It is the ratio of output voltage to input voltage. It is given by,
By substituting V2 = -I2RL = Ai I1 RL
Since
We get,
From equation,
Substituting the value of I1/V2 from above equation in the equation of Yo. We obtain,
From this equation, note that the output admittance is a function of source resistance.
It is the ratio of average power delivered to the load to the input power. Output
power is given as,
Avs = and
We have,
&
Solution:
Change the given figure into h-parameter equivalent model.
a) Current gain
b) Input Resistance
c) Voltage gain
f) Output Resistance
Ai =
Ri =
Av =
Avs =
Ais =
Yo =
Ro =
Problem 3:
Consider a single stage CE amplifier with Rs = 1k, R1 = 50k, R2 = 2k, Rc = 2k, RL =
2K, hie = 1.1k, hoe = 25µA/V, hfe = 50 and hre = 2.5*10-4 as shown in the figure.
Find Ai, Ri, Av, Ai, Avs and Ro.
Solution:
Since hoe RL’ = 25*10-6*(2K || 2K) = 0.25, which is less than 0.1, so use approximate
analysis.
Consider the simplified hybrid model for the given circuit.
a) Current gain
b) Input Impedance
c) Voltage gain
d) Output Impedance
technology is well known now a days, due to which the design of complex circuits
become very simple. The IC version of operational amplifier is inexpensive, takes up less
space and consumes less power. The. differential amplifier is the basic building block of
such IC operational amplifier.
Basics of Differential Amplifier
The Differential Amplifier amplifies the difference between two input voltage
signal. Hence it is also called as difference amplifier. Consider an ideal differential
amplifier shown in the Fig. A
V1 and V2 are the two input signals while Vo is the output. Each signal is measured with
respect to the ground.
In an ideal differential amplifier, the output voltage Vo is proportional to the
difference between the two input signals. Hence we can write,
where AD is the constant of proportionality. The AD is the gain with which differential
amplifier amplifies the difference between two input signals. Thus it is called differential
gain of the differential amplifier.
Thus, Ad = Differential gain
The difference between the two inputs (V1 - V2) is generally called difference
voltage and denoted as Vd.
...(3)
Hence the differential gain can be expressed as,
...(4)
Generally the differential gain is expressed in its decibel (dB) value as,
...(5)
Common Mode Gain Ac
If we apply two input voltages which are equal in all the respects to the
differential amplifier i.e. V1 = Vz then ideally the output voltage Vo = (V 1 - V2) Ad, must
be zero.But the output voltage of the practical differential amplifier not only
depends on thedifference voltage but also depends on the average common level of the
two inputs.
Such an average level of the two input signals is called common mode signal denoted
as VC
...(6)
Practically, the differential amplifier produces the output voltage proportional to such
common mode signal, also. The gain with which it amplifies the common mode signal to
produce the output is called common mode gain of the differential amplifier AC.\
..(7)
Thus there exists some finite output for V1 = V2 due to such common mode gain AC,
in case of practical differential amplifiers.
When the same voltage is applied to both the inputs, the differential amplifier is
said to be operated in a common mode configuration. Many disturbance signals, noise
signal appear as a common input signal to both the input terminals of the differential
amplifier. Such a common signal should be rejected by the differential amplifier. The
ability of a differential amplifier to reject a common mode signal is expressed by a ratio
called common mode rejection ratio denoted as CMRR. It is defined as the ratio of the
differential voltage gain Ad to common mode voltage gain AC
….(9)
…..(10)
The transistorised differential amplifier basically uses the emitter biased circuits
which are identical in characteristics. Such two identical emitter biased circuits are
The magnitudes of + Vcc and – V EE are also same. The differential amplifier can be
obtained by using such two emitter biased circuits. This is achieved by connecting emitter
E1 of Q1 to the emitter E2 of Q2. Due to this, R E1 appears in parallel with R E2 and the
combination can be replaced by a single resistance denoted as R E. The base B1 of Q1 is
connected to the input 1 which is V S1 while the base B 2 of Q2 is connected to the input 2
which is Vs2. The supply voltages are measured with respect to ground. The balanced
output is taken between the collector C1 of Q1 and the collector C2 of Q 2. Such an
amplifier is called emitter coupled differential amplifier. The two collector resistances are
same hence can be denoted as R C..
The output can be taken between two collectors or in between one of the two
collectors and the ground. When the output is taken between the two collectors, none of
them is grounded then it is called balanced output, double ended output or floating output.
When the output is taken between any of the collectors and the ground, it is called
unbalanced output or single ended output. The complete circuit diagram of such a basic
dual input, balanced output differential amplifier is shown in the Fig.
As the output is taken between two output terminals, none of them is grounded, it is
called balanced output differential amplifier.
In the differential mode, the two input signals are different from each other.
Consider the two input signals which are same in magnitude but 180" out of phase. These
signals, with opposite phase can be obtained from the center tap transformer. The circuit
used in differential mode operation is shown in the Fig..
Assume that the sine wave on the base of Q 1is positive going while on the base of
Q 2 is negative going. With a positive going signal on the base of Q 1 , m amplified
negative going signal develops on the collector of Q1. Due to positive going signal,
current through R E also increases and hence a positive going wave is developed across R
E. Due to negative going signal on the base of Q2, an amplified positive going signal
develops on the collector of Q 2 . And a negative going signal develops across R E,
because of emitter follower action of Q 2. So signal voltages across R E, due to the effect
of Q1 and Q2 are equal in magnitude and 180o out of phase, due to matched pair of
transistors. Hence these two signals cancel each other and there is no signal across the
emitter resistance. Hence there is no a.c. signal current flowing through the emitter
resistance. Hence R E in this case does not introduce negative feedback. While Vo is the
output taken across collector of Q1 and collector of Q 2. The two outputs on collector L
and 2 are equal in magnitude but opposite in polarity. And Vo is the difference between
these two signals, e.g. +10 - (-10) = + 20.
Hence the difference output Vo is twice as large as the signal voltage from
either collector to ground
In this mode, the signals applied to the base of Q1 and Q2 are derived from the
same source. So the two signals are equal in magnitude as well as in phase. The circuit
diagram is shown in the Fig.
In phase signal voltages at the bases of Q1 and Q2 causes in phase signal voltages
to appear across R E, which add together. Hence R E carries a signal current and provides
a negative feedback. This feedback reduces the common mode gain of differential
amplifier.
While the two signals causes in phase signal voltages of equal magnitude to appear across
the two collectors of Q 1 and Q2. Now the output voltage is the difference between the
two collector voltages, which are equal and also same in phase, Eg. (20) - (20) = 0. Thus
the difference output Vo is almost zero, negligibly small. ideally it should be zero.
The differential amplifier, in the difference amplifier stage in the op-amp, can be
used in four configurations :
• Dual input balanced output differential amplifier.
• Dual input, unbalanced output differential amplifier.
• Single input, balanced output differential amplifier.
• Single input, unbalanced output differential amplifier.
The differential amplifier uses two transistors in common emitter configuration. If
output is taken between the two collectors it is called balanced output or double ended
output. While if the output is taken between one collector with respect to ground it is
called unbalanced output or single ended output. If the signal is given to both the input
terminals it is called dual input, while if the signal is given to only one input terminal and
other terminal is grounded it is called single input or single ended input. Out of these four
configurations the dual input, balanced output is the basic differential amplifier
configuration. This is shown in the Fig. (a). The dual input, unbalanced output differential
amplifier is shown in the Fig.(b). The single input, balanced output
differential amplifier is shown in the Fig (c) and the single input, unbalanced output
differential amplifier is shown in the Fig. (d).
.
The transistors Q1 and Q 2 are matched transistors and hence for such a matched pair
we can assume :
i) Both the transistors have the same characteristics.
ii) R E1 = R E2 hence R E= R E1 ll R E2.
iii) R C1 = R c 2 hence denoted as R C.
iv) lV CCI = lV EE I and both are measured with respect to ground.
As the two transistors are matched and circuit is symmetrical, it is enough to find out
operating point I CQ and V CEQ, for any one of the two transistors. The same is applicable
for the other transistor.
Apply-g KVL to base-emitter loop of the transistor Q1,
….(1)
….(2)
….(3)
For the differential gain calculation, the two input signals must be different from
each other. Let the two a.c. input signals be equal in magnitude but having 180" phase
difference in between them. The magnitude of each a.c. input voltage V S1 and V S2 beVs /
2. The two a.c. emitter currents I e 1 and I e2 are equal in magnitude and 180' out of phase.
Hence they cancel each other to get resultant a.c. current through the emitter as zero. For
the a.c. purposes emitter terminal can be grounded. The a.c. small signal differential
amplifier circuit with grounded emitter terminal is shown in the Fig1 As the two
transistors are matched, the a.c. equivalent circuit for the other transistor is identical to the
one shown in the Fig..1. Thus the circuit can be analyzed by considering only one
transistor. This is called as half circuit concept of analysis. The approximate hybrid model
for the above circuit can be shown as in the Fig.2, neglecting hoe,
The negative sign indicates the phase difference between input and output. Now two
input signal magnitudes are VS /2 but they are opposite in polarity, as 180" out of phase.
This is the differential gain for balanced output dual input differential amplifier
circuit.
2. Common Mode Gain (A C)
Let the magnitude of both the a.c. input signals be VS and are in phase with each
other. Hence the differential input Vd = 0 while the common mode input Vc is the
average value of the two.
But now both the emitter currents flows through R E in the Same direction. Hence the
total current flowing through R E is 2I e. considering only one transistor, as in the Fig
Once the differential and common mode gains are obtained, the expression for the CMRR
can be obtained as,
Figure shows the direct coupling of two stages of emitter follower amplifier. This
cascaded connection of two emitter followers is called the Darlington connection.
Assume that the load resistance RL is such that RL hoe < 0.1, therefore we can use
approximate analysis method for analyzing second stage.
Figure shows approximate h-parameter (AC) equivalent circuit for common emitter
configuration. The same circuit can be redrawn by making collector common to have
approximate h-parameter equivalent circuit for common collector configuration.
From table, we can say that Darlington connection improves input impedance as well as
current gain of the circuit
Overall Voltage gain
We know that
We know that the overall voltage gain in multistage amplifier is a product of individual
voltage gain
As we know, input resistance Ri1 >> Ri2 we can neglect term 3 and term 4 in the above
equation.
Since
And
Looking at Figure we can see that the Ri1 of the first stage is the source resistance
for second stage, i.e. RS2= RO1
Key Point:
• In above analysis we have assumed that the h-parameter of T1 and T2 are
identical,
• From the above analysis we have seen that Darlington connection of two
transistorimproves current gain and input resistance of the circuit.
In emitter follower, the input resistance of the amplifier is reduced because of the
shunting effect of the biasing resistors. To overcome this problem the emitter follower
circuit is modified, as shown in the Figure. Here, two additional components are used,
resistance R, and capacitor C .The capacitor, is connected between the emitter and the
junction of R1,R2 and R3.
For d.c. signal, capacitor C acts as a open circuit and therefore resistance R1,R2
and R3 provides necessary biasing to keep the transistor in active region.
For ac signal, the capacitor acts as a short circuit. Its value is chosen such that it
provides very low reactance nearly short circuit at lowest operating frequency. Hence for
ac, the bottom of R3 is effectively connected to the output(the emitter), whereas the top
of R3 is at the -input. (the base). In other words, R3 is connected between input node and
output node. For such connection effective input resistance is given by Miller's theorem.
The two components are
R3 is the impedance between output voltage and input voltage and K is the
voltage gain.
These are
Since, for an emitter follower, Av, approaches unity, then RM2 becomes extremely large.
The above effect, when Av tends to unity is called bootstrapping. The name arises from
the fact that, if one end of the resistor R 3 changes in voltage, the other end of R 3 moves
through the same potential difference; it is as if R3 is pulling itself up by its bootstraps.
Because of the capacitor, biasing resistances R1 and R2, come on output side shunting
effective load resistance. The resistance RM2 is very large and hence it is often neglected.
Problem
1. For the circuit shown in Figure calculate RLeff , Ri, and Ri’
2. Analyze the following circuit for the following values of resistors and h-parameters
Solution
Analysis of second stage
Multistage Amplifiers
In practice, we need amplifier which can amplify a signal from a very weak source such
as a microphone, to a level which is suitable for the operation of another transducer
such as loudspeaker . This is achieved by cascading number of amplifier stages, known as
multistage amplifier
Vi1 is the input of the first stage and Vo2 is the output of second stage.
So,Vo2/Vi1 is the overall voltage gain of two stage amplifier.
Voltage gain :
The resultant voltage gain of the multistage amplifier is the product of voltage gains of
the various stages.
Av = Avl Av2 ... Avn
Gain in Decibels
In many situations it is found very convenient to compare two powers on logarithmic
scale rather than on a linear scale. The unit of this logarithmic scale is called decibel
(abbreviated dB). The number N decibels by which a power P2 exceeds the power P1 is
defined by
Decibel, dB denotes power ratio. Negative values of number of dB means that the power
P2 is less than the reference power P1 and positive value of number of dB means the
power P2 is greater than the reference power P1.
For an amplifier, P1 may represent input power, and P2 may represent output power.
Both can be given as
Where Ri and Ro are the input and output impedances of the amplifier respectively.Then,
If the input and output impedances of the amplifier are equal i.e. Ri = Ro= R, then
The coupling does not affect the quiescent point of the next stage since the coupling
capacitor Cc blocks the d.c. voltage of the first stage from reaching the base of the second
stage. The RC network is broadband in nature. Therefore, it gives a wideband frequency
response without peak at any frequency and hence used to cover a complete A.F amplifier
bands. However its frequency response drops off at very low frequencies due to coupling
capacitors and also at high frequencies due to shunt capacitors such as stray capacitance.
Transformer Coupling
Figure shows transformer coupled amplifier using transistors. The output signal of
first stage is coupled to the input of the next stage through an impedance matching
transformer
This type of coupling is used to match the impedance between output and input cascaded
stage. Usually, it is used to match the larger output resistance of AF power amplifier to a
low impedance load like loudspeaker. As we know, transformer blocks d.c, providing d.c.
isolation between the two stages. Therefore, transformer coupling does not affect the
quiescent point of the next stage. Frequency response of transformer coupled amplifier is
poor in comparison with that an RC coupled amplifier. Its leakage inductance and inter
winding capacitances does not allow amplifier to amplify the signals of different
frequencies equally well. Inter winding capacitance of the transformer coupled may give
rise resonance at certain frequency which makes amplifier to give very high gain at that
frequency. By putting shunting capacitors across each winding of the transformer, we can
get resonance at any desired RF frequency. Such amplifiers are called tuned voltage
amplifiers. These provide high gain at the desired of frequency, i.e. they amplify selective
frequencies. For this reason, the transformer-coupled amplifiers are used in radio and TV
receivers for amplifying RF signals. As d.c. resistance of the transformer winding is very
low, almost all d.c. voltage applied by Vcc is available at the collector. Due to the
absence of collector resistance it eliminates unnecessary power loss in the resistor.
Direct Coupling
Figure shows direct coupled amplifier using transistors. The output signal of first
stage is directly connected to the input of the next stage. This direct coupling allows the
quiescent d.c. collector current of first stage to pass through base of the next stage,
affecting its biasing conditions.
QUESTIONS
2 MARKS
16 MARKS
1. Draw a CE amplifier & its small signal equivalent. Derive its Avs, Ai, Rin, Ro.
2. For the CC amplifier circuit, Find the expressions for input impedance and
voltage gain. Assume suitable model for transistor.
3. Explain with circuit diagram of Darlington connection and derive the expression
for Ai, Av, Ri &Ro.
4. Explain the emitter coupled differential amplifier with neat diagram & Derive
expression for CMRR.
5. Discuss transfer characteristics of differential amplifier. Explain the methods used
to improve CMRR.
6. Derive the expressions for the common mode and differential mode gains of a
differential amplifier in terms of h-parameters.
7. Compare CE, CB, CC amplifiers.
8. Derive the expressions for the voltage gain, current gain, input and output
impedance of emitter follower amplifier.
9. Derive expression for voltage gain of CS & CD amplifier under small signal low
frequency condition.
10. Draw a two stage RC coupled amplifier and explain. Compare cascade and
cascode amplifier?
11. Consider a single stage CE amplifier with Rs=1kΩ, R1=50KΩ, R2=2KΩ,
RC=2KΩ, RL=2KΩ, hfe=50, hie=1.1 KΩ, hoe=25µmho, hre=2.5×10-4. Find
Ai,Ri,Av,Ais,Avs and R0.
12. The Darlington amplifier has the following parameters, Rs=3kΩ, RE=3kΩ,
hie=1.1 KΩ, hfe=50, hre=2.5×10-4, hoe=25µmho. Then calculate Ai, Ri, Av and
R0.
13. The dual input balanced output differential amplifier having Rs=100Ω,
RC=4.7KΩ, RE=6.8KΩ, hfe=100, Vcc=+15v and VEE=-15v. Calculate operating
point values, differential & common mode gain, CMRR, and output if VS1=
70mV(p-p) at 1 KHz & VS2= 40mV(p-p) at 1 KHz
UNIT 3
JFET AND MOSFET AMPLIFIERS
Input Impedance Zi
Zi = RG
Output Impedance Zo
It is the impedance measured looking from the output side with input voltage Vi equal to Zero.
As Vi=0,Vgs =0 and hence gmVgs =0 . And it allows current source to be replaced by an open
circuit.
So,
Figure shows Common Source Amplifier With self Bias. The coupling capacitor C1 and
C2 which are used to isolate the d.c biasing from the applied ac signal act as short circuits for ac
analysis. Bypass capacitor Cs also acts as a short circuits for low frequency analysis.
The following figure shows the low frequency equivalent model for Common Source Amplifier
With self Bias.
Fig3.6 Small signal model for Common source amplifier model of JFET
The negative sign in the voltage gain indicates there is a 180 o phase shift between input and
output voltages.
Fig3.8 Small signal model for Common source amplifier model of JFET
Input Impedance Zi
Zi = RG
Output Impedance Zo
It is given by
3.6 Common source amplifier with Voltage divider bias (Bypassed Rs)
Figure shows Common Source Amplifier With voltage divider Bias. The coupling capacitor C1
and C2 which are used to isolate the d.c biasing from the applied ac signal act as short circuits
for ac analysis. Bypass capacitor Cs also acts as a short circuits for low frequency analysis.
The following figure shows the low frequency equivalent model for Common Source Amplifier
With voltage divider Bias
Fig3.10 small model of Common source amplifier with Voltage divider bias(Bypassed Rs)
The negative sign in the voltage gain indicates there is a 180o phase shift between input and
output voltages.
3.7 Common source amplifier with Voltage divider bias (unbypassed Rs)
Fig3.11 small model of Common source amplifier with Voltage divider bias(without
Bypassed Rs)
Now Rs will be the part of low frequency equivalent model as shown in figure.
Input Impedance Zi
But
Common drain circuit does not provide voltage gain.& there is no phase shift between input and
output voltages.
Table summarizes the performance of common drain amplifier
In this circuit, input is applied between source and gate and output is taken between drain and
gate.
It is given by
And
And
2. Output Impedance Zo
It is given by
In practice, we need amplifier which can amplify a signal from a very weak source such as a
microphone, to a level which is suitable for the operation of another transducer
such as loudspeaker . This is achieved by cascading number of amplifier stages, known as
multistage amplifier
Voltage gain :
The resultant voltage gain of the multistage amplifier is the product of voltage gains of the
various stages.
Gain in Decibels
In many situations it is found very convenient to compare two powers on logarithmic scale rather
than on a linear scale. The unit of this logarithmic scale is called decibel (abbreviated dB). The
number N decibels by which a power P2 exceeds the power P1 is defined by
Decibel, dB denotes power ratio. Negative values of number of dB means that the power P2 is
less than the reference power P1 and positive value of number of dB means the power P2 is
greater than the reference power P1.
For an amplifier, P1 may represent input power, and P2 may represent output power.
Both can be given as
Where Ri and Ro are the input and output impedances of the amplifier respectively.Then,
If the input and output impedances of the amplifier are equal i.e. Ri = Ro= R, then
This configuration serves as the gain stage. The disadvantage is high output impedance.
Capacitor CS is included such that the stage is connected to a current source for biasing
Common-Gate Configuration
This amplifier provides gain and is useful when a specific (low) Rin is required. This is,
e.g., the case when the impedance needs to be matched, as with transmission lines (e.g. to 50 Ω).
Another application of the CG configuration is that it acts as a current buffer (current gain close
to unity, small Rin, large Rout).
Source Follower (Common-Drain Configuration)
This configuration acts as a voltage buffer. It provides no gain, but has low output
impedance. It is typically the last stage in a multi-stage amplifier.
By grouping the different factors in this expression, we can find a physical interpretation
for the cascading. This physical interpretation can be used to guide simulation or analysis of the
different stages separately, before combining them into a cascaded amplifier.
QUESTIONS
2 MARKS
1. What is meant by small signal?
2. What is the physical meaning of small signal parameter ro?
3. Write the equation for small signal condition that must be satisfied for linear amplifiers.
4. Draw the small signal equivalent circuit common source NMOS.
5. What is another name for common drain amplifier?
6. Draw the source follower amplifier circuit.
7. List the applications of MOSFET amplifiers.
8. Compare the characteristics of three MOSFET amplifier configurations.
9. Draw the small signal equivalent JFET common source circuit.
10. How does a transistor width-to-length ratio affect the small signal voltage gain of a common
source amplifier?
11. How a MOSFET can be used to amplify a time varying voltage?
12. How does body effect change the small signal equivalent of the MOSFET?
13. Why in general the magnitude of the voltage gain of a common source amplifier relatively
small?
14. What is voltage swing limitation?
15. What is the general condition under which a common gate amplifier would be used?
16. State the general advantage of using transistors in place of resistors in integrated circuits.
17. Give one reason why a JFET might be used as an input device in a circuit as proposed to a
MOSFET.
18. What are features of cascode amplifiers?
19. What are the applications of BiCMOS?
20. Discuss one advantage of BiCMOS circuit.
16 MARKS
1. Describe the operation and analyze the basic JFET amplifier circuits.
2. Derive the small signal analysis of common source amplifier.
3. Develop a small signal model of JFET device and analyze basic JFET amplifiers.
4. Explain graphically the amplification process in a simple MOSFET amplifier circuit.
5. Describe the small signal equivalent circuit of the MOSFET and determine the values of small
signal parameters?
6. Sketch the small signal high frequency circuit of a common source amplifier & derive the
expression for a voltage gain, input & output admittance and input capacitance.
7. Sketch a simple source-follower amplifier circuit and discuss the general ac circuit
characteristics.
8. Characterize the voltage gain and output resistance of a common-gate amplifier.
9. Apply the MOSFET small signal equivalent circuit in the analysis of multistage amplifier
circuits.
10. Explain common source amplifier with source resistor and source bypass capacitor.
11. Write short notes Voltage swing limitations, general conditions under which a source
follower amplifier would be used.
12. Describe the characteristics of and analyze BiCMOS circuits.
UNIT IV
FREQUENCY ANALYSIS OF BJT AND MOSFET AMPLIFIERS
To plot this curve, input voltage to the amplifier is kept constant and frequency of
input signal is continuously varied. The output voltage at each frequency of input signal
is noted and the gain of the amplifier is calculated. For an audio frequency amplifier, the
frequency range is quite large from 20 Hz to 20 kHz. In this frequency response, the gain
of the amplifier remains constant in mid-frequency while the gain varies with frequency
in low and high frequency regions of the curve. Only at low and high frequency ends,
gain deviates from ideal characteristics. The decrease in voltage gain with frequency is
called roll-off.
The range of frequencies can be specified over which the gain does not deviate
more than 70.7% of the maximum gain at some reference mid-frequency.
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EC6304 Electronic Circuits I
From above figure, the frequencies f1 & f2 are called lower cut-off and upper cut-off
frequencies.
Bandwidth of the amplifier is defined as the difference between f2 & f1.
Bandwidth of the amplifier = f2 - f1
The frequency f2 lies in high frequency region while frequency f1 lies in low
frequency region. These two frequencies are also called as half-power frequencies since
gain or output voltage drops to 70.7% of maximum value and this represents a power
level of one half the power at the reference frequency in mid-frequency region.
123
EC6304 Electronic Circuits I
At lower and higher frequencies the decrease in the gain of amplifiers is often indicated
in terms of db/decades or db/octaves. If the attenuation in gain is 20 db for each decade,
then it is indicated by line having slope of 20 db/decade. A rate of -20 db/decade is
124
EC6304 Electronic Circuits I
In midband,
Midband:
Below midband:
Above midband,
Above midband:
Problem:
For an amplifier, midband gain = 100 and lower cutoff frequency is 1 kHz. Find the gain
of an amplifier at frequency 20 Hz.
Solution:
Below midband:
125
EC6304 Electronic Circuits I
126
EC6304 Electronic Circuits I
From above figure, it has three RC networks that affect its gain as the frequency is
reduces below midrange. These are,
1. RC network formed by the input coupling capacitor C1 and input impedance of
the amplifier.
2. RC network formed by the output coupling capacitor C2, resistance looking in at
the collector and load resistance.
3. RC network formed by the emitter bypass capacitor CE and resistance looking in
at the emitter.
Input RC network:
The following figure shows the input RC network formed by C1 and the
input impedance of the amplifier.
The resistance value is Rin = R1 || R2 || Rin(base)
127
EC6304 Electronic Circuits I
A critical point in the amplifier response is generally accepted to occur when the output
voltage is 70.7 % of the input. At critical point,
The frequency fc at this condition is called lower critical frequency and it is given by,
If the resistance of input source is taken into account the above equation becomes,
Output RC network:
The above figure shows the output RC network formed by C2, resistance looking in at the
collector and load resistance.
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EC6304 Electronic Circuits I
Bypass network:
Where RTH = R1 || R2 || Rs. It is the thevenin’s equivalent resistance looking from the base
of the transistor towards the input.
The critical frequency for the bypass network is
Problem:
Determine the low frequency response of the amplifier circuit shown in the figure.
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EC6304 Electronic Circuits I
Solution:
It is necessary to analyze each network to determine the critical frequency of the
amplifier.
The above analysis shows that the input network produces the dominant lower critical
frequency. Then the low frequency response of the given amplifier is shown in the
following figure.
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EC6304 Electronic Circuits I
From above figure, it has two RC networks that affect its gain as the frequency is reduced
below midrange. These are,
1. RC network formed by the input coupling capacitor C1 and input impedance of
the amplifier.
2. RC network formed by the output coupling capacitor and the output impedance
looking in at the drain.
`Input RC network:
Lower critical frequency of this network is given as,
The value of Rin(gate) can be determined from the data sheet as follows:
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The phase shift in low frequency input RC circuit is θ = tan-1 (XC1 / Rin )
Output RC network:
Lower critical frequency of this network is given as,
The phase shift in low frequency output RC circuit is θ = tan-1 (XC2 / RD + RL)
Due to the above reasons, modified T model and hybrid ∏ models are used for high
frequency analysis of the transistor. These models give a reasonable compromise
between accuracy and simplicity to do high frequency analysis of the transistor.
4.4.1 Hybrid - π common emitter transistor model:
Common emitter circuit is most important practical configuration and this
is useful for the analysis of transistor using hybrid - ∏ model. The following figure
shows the hybrid - ∏ model for a transistor in CE configuration. For this model, all
parameters are assumed to be independent of frequency. But they may vary with the
quiescent operating point.
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rbb’: The internal node b’ is physically not accessible bulk node b represents external base
terminal.
rb’e: It is the portion of the base emitter which may be thought of as being in series with
the collector junction. This establishes a virtual base b’ for junction capacitances to be
connected instead of b.
rb’c: Due to early effect, varying voltages across collector to emitter junction results in
base-width modulation. A change in the effective base -width causes the emitter current
to change. This feedback effect between output and input is taken into account by
connecting gb’c or rb’c between b’ and c.
gm: Due to small changes in voltage Vb’e across emitter junction, there is excess minority
carrier concentration injected into the base which is proportional to V b’e. So resulting
small signal collector current with collector shorted to the emitter is also proportional to
Vb’e.
gm is also called as transconductance and it is given as,
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Let us consider a p-n-p transistor in CE configuration with Vcc bias in the collector circuit
as shown in the above figure.
Transconductance gm is given as,
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First consider h-parameter model for CE configuration. Applying KCL to output circuit,
Making Vce = 0, the short circuit current gain hfe is defined as,
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Vce =
I1 =
Voltage between b’ and e, Vb’e can be given as,
Vb’e =
With Ib = 0,
Vi = Vb’e
hreVce =
rb’c =
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1/rce = gce =
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Ce = gm
--------
2πft
4.4.4 CE short circuit current gain using hybrid- π model:
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fβ (Cutoff frequency):
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It is the frequency at which the transistor short circuit CE current gain drops by
3dB or 1/√√2 times from its value at low frequency. It is given as,
fα (Cut-off frequency):
It is the frequency at which the transistor short circuit CB current gain drops
by 3dB or 1/√√2 times from its value at low frequency. The current gain for CB
configuration is given as,
Parameter fT:
It is the frequency at which short circuit CE current gain becomes unity.
At f = fT,
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Ai =
fH is the frequency at which the transistor gain drops by 3dB or 1/√2 times from its value
at low frequency. It is given as,
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For RL = 0,
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= RL fT
* --------
--------
Rs+rbb ’ 1 + 2πfTCCRL
4.8.9.2 Gain Bandwidth Product for current:
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Voltage gain:
Input Admittance:
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This increase in input capacitance Ci over the capacitance from gate to source is called
Miller effect.
This input capacitance affects the gain at high frequencies in the operation of cascaded
amplifiers. In cascaded amplifiers, the output from one stage is used as the input to a
second amplifier. The input impedance of a second stage acts as a shunt across output of
the first stage and Rd is shunted by the capacitance Ci.
Output Admittance:
From above figure, the output impedance is obtained by looking into the drain with the
input voltage set equal to zero. If Vi = 0 in figure, r d , Cds and Cgd in parallel. Hence the
output admittance with RL considered external to the amplifier is given by,
Fig. Common Drain Amplifier Circuit & Small signal equivalent circuit at high
frequencies
Voltage gain:
The output voltage Vo can be found from the product of the short circuit
and the impedance between terminals S and N. Voltage gain is given by,
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Input Admittance:
Input Admittance Yi can be obtained by applying Miller’s theorem to Cgs.
It is given by,
Output Admittance:
Output Admittance Yo with Rs considered external to the amplifier, it is
given by,
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Let us consider a typical common source amplifier as shown in the above figure.
From above figure, it shows the high frequency equivalent circuit for the given amplifier
circuit. It shows that at high frequencies coupling and bypass capacitors act as short
circuits and do not affect the amplifier high frequency response. The equivalent circuit
shows internal capacitances which affect the high frequency response.
Using Miller theorem, this high frequency equivalent circuit can be further simplified as
follows:
The internal capacitance Cgd can be splitted into Cin(miller) and Cout(miller) as shown in the
following figure.
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EC6304 Electronic Circuits I
Where
From simplified high frequency equivalent circuit, it has two RC networks which affect
the high frequency response of the amplifier. These are,
1. Input RC network
2. Output RC network
Input RC network:
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Output RC network:
fc =
It is not necessary that these frequencies should be equal. The network which has lower
critical frequency than other network is called dominant network.
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Problem:
Determine the high frequency response of the amplifier circuit shown in the following
figure.
Solution:
Before calculating critical frequencies it is necessary to calculate mid frequency gain of
the given amplifier circuit. This is required to calculate Cin(miller) and Cout(miller).
Av = -gmRD
Here RD should be replaced by RD || RL
Av=
Cin(miller)=
Cout(miller)=
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fc(input) =
The above analysis shows that the output network produces the dominant higher critical
frequency. High frequency response of the given amplifier is shown in the following
figure.
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The time required for Vo to reach one-tenth of its final value is calculated as,
The difference between these two values is called as rise time t r of the circuit. The rise
time is given as,
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From above equation, it shows that upper 3dB frequency is inversely proportional to the
rise time tr.
Problem:
If the rise time of BJT is 35ns, what is the bandwidth that can be obtained using this BJT.
Solution:
tr = 0.35 / f2 = 0.35 / BW
BW = 0.35 / tr = 0.35 / (35 * 10-9) = 10MHz
4.9 Sag and its Relation to Lower Cut-off Frequency:
The amplifier low frequency RC network consists of coupling and bypass
capacitors make amplifier output to decrease with large time constant. As a result, the
output voltage has sag or tilt associated with it as shown in the following figure.
The lower 3 dB frequency can be determined from the output response by carefully
measuring the tilt.
The lower 3 dB frequency is given as,
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So, the lower 3 dB frequency can be represented in terms of tilt is measured from the
following figure.
= πfL / f * 100
fL = Pf
____
100π
Problem 1:
For a circuit shown in the following figure, calculate percentage tilt. Assume approximate
h-parameter circuit for the transistor.
Solution:
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fL =
Here R1 = RC + RL = 4K + 2K
= 6KΩ
fL =
We know that, P = (∏fL / f) * 100
Assuming f = 200 Hz
P = (∏ * 2.65 / 200) * 100
P = 4.1%
QUESTIONS
2 MARKS
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EC6304 Electronic Circuits I
16 MARKS
1. With neat sketch explain hybrid π CE transistor model. Derive the expression for
various components in terms of ‘h’ parameters.
2. Discuss the frequency response of multistage amplifiers. Calculate the overall upper &
lower cutoff frequencies.
3. Discuss the low frequency response & the high frequency response of an amplifier.
Derive its cutoff frequencies.
4. Discuss the terms rise time and sag.
5. Write short notes on high frequency amplifier.
6. Derive the gain bandwidth for high frequency FET amplifiers.
7. Derive the expression for the CE short circuit current gain of transistor at high
frequency
8. What is the effect of Cb’e on the input circuit of a BJT amplifier at High frequencies?
Derive the equation for gm which gives the relation between gm, Ic and temperature.
9. Explain the high frequency analysis of JFET with necessary circuit diagram & gain
bandwidth product.
10. Discuss the frequency response of MOSFET CS amplifier.
11. Determine the bandwidth of CE amplifier with the following specifications.
R1=100kΩ, R2=10kΩ, RC=9kΩ, RE=2kΩ, C1= C2=25µF, CE=50µF, rbb’=100Ω,
rb’e=1.1KΩ, hfe=225, Cb’e=3pF and Cb’c=100pF.
12. At Ic=1mA & VCE=10v, a certain transistor data shows Cc=Cb’c=3pF, hfe=200, &
ωT=-500M rad/sec. Calculate gm, rb’e, Ce=Cb’e & ωβ.
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Effect of VO on IO
Current mismatch due to channel-length modulation
I
ref
= Kn
K
ref
K
n
= I
ref
K
ref
The drain current is a scaled value of Iref
if K1 is twice that of Kref (i.e., K 1 = 2Kref ), then ID1 will be twice as large as
Iref (i.e., I 1 = 2Iref ).
SCE 164 Dept of ECE
EC6304 Electronic
Circuits I
From the standpoint of integrated circuit design, we can change the value of K
by modifying the MOSFET channel width-to-length ratio (W/L) for each transistor.
(W
= ( L))n
W
1 k ′(
W
) L ref
Kn 2 Ln
K W
ref = 1 k ′( )
2 L ref
5.5 NMOS Current Sources and Sinks
Characteristics of Current Sources
• A well controlled output current
• Supplied current does not depend on output voltage and has High
Norton Resistance
• Connect a voltage source to the gate of another MOSFET:
Hence, IREF depends on the supply voltage VDD. If the supply is a battery or similar
device, then this will change over time, causing the reference current to also vary with time.
IOUT scales with IREF by W/L ratios of two MOSFETs
Same operation and characteristics as NMOS voltage source. PMOS needs to be larger to
attain the same Rout.
Problem
1.Find the CMRR for the circuit with given data.
2 MARKS
1. What are the basic processes in integrated circuit fabrication?
2. Define common mode rejection ration? What is the ideal value?
3. Sketch the DC transfer characteristics of a MOSFET differential amplifier.
4. What are the advantages of an active load?
5. What is the impedance seen looking into a simple active load?
6. How the reference portion of the circuit can be designed with MOSFETs only.
7. How should a MOSFET be biased so as to operate as a stable current source?
8. Draw the circuit of MOSFET differential amplifier with active load.
9. What is the need for MOSFET differential amplifier with cascode active load?
10. What is meant by matched transistors?
11. Define common mode and differential mode input resistance and voltages.
12. What are the limiting factors for the maximum current in MOSFET?
13. Define enhancement and depletion mode of MOSFET.
14. Define saturation and non- saturation bias regions.
15. How do you prove that a MOSFET is biased in the saturation region?
16. Draw MOSFET cascode current source circuit.
17. What is another name of two transistor current source?
18. Draw the two transistor MOSFET current source.
19. What is Widlar current source
20. What is cascode current mirror?
16 MARKS
1. Describe the operation of an NMOS amplifier with either an enhancement load, a
depletion load, or a PMOS load.
2. Explain the basic MOSFET two transistor current circuits and discuss its operation.
3. Draw the MOSFET cascode current source circuit, explain and discuss the
advantage of this design.
4. Sketch and describe the advantages of a MOSFET cascode current source used
with a MOSFET differential amplifier.
5. Explain CMOS differential amplifier and derive CMRR.
7. Draw a Widlar current source and explain the operation.
8. Describe the operation of a PMOS amplifier with an enhancement load, a depletion
load.
9. Explain the CMOS common source and source follower with neat diagram.
10. Explain the large signal behavior of MOSFETs and compare the operating regions of Bipolar
and MOS transistors.
11. Discuss the operation of active load and discuss the advantages of MOSFET cascode current
circuit.
12. Explain in detail about CMOS common source and source follower with neat diagram.
10. What are the advantages and disadvantages of fixed bias circuits?
Merits:
• It is simple to shift the operating point anywhere in the active region by merely changing
the base resistor (RB).
• A very small number of components are required.
Demerits:
• The collector current does not remain constant with variation in temperature or power
supply voltage. Therefore the operating point is unstable.
• Changes in Vbe will change IB and thus cause RE to change. This in turn will alter the gain
of the stage.
• When the transistor is replaced with another one, considerable change in the value of β
can be expected. Due to this change the operating point will shift.
• For small-signal transistors (e.g., not power transistors) with relatively high values of β
(i.e., between 100 and 200), this configuration will be prone to thermal runaway. In
particular, the stability factor, which is a measure of the change in collector current with
changes in reverse saturation current, is approximately β+1. To ensure absolute stability
of the amplifier, a stability factor of less than 25 is preferred, and so small-signal
transistors have large stability factors.
Z1 =
It states that the effect of resistance Z on the output circuit is the ratio of output
voltage to the current which flows from the output to input.
Z2 =
the value of RE, lesser is the value of Ac and higher is the value of CMRR. The differential gain
Ad is not dependent on RE
17. What are the other methods to improve CMRR without RE?
• Constant current bias method
• Current mirror circuit.
18. List the advantage of current mirror circuit?
• Provides very high emitter resistance RE.
• Requires fewer components than the constant current bias.
• Simple to design
• Easy to fabricate.
• With properly matched transistors, collector current thermal stability is
• achieved.
For any inverting amplifier, the input capacitance will be increased by a miller effect
capacitance, sensitive to the gain of the amplifier and the inter electrode capacitance connected
between the input and output terminals of the active device. CMi = (1- AV) Cf CM0 = Cf Cf =
Inter electrode capacitance between input and output.
PART A
At high frequency the reactance of coupling capacitor is very low. Therefore it behaves like
a short circuit. As a result of this the loading effect of the next stage increase which reduces the
voltage gain. Hence the voltage gain rolls off at high frequencies.
MOSFETs can also be used for most applications where JFET is used. MOSFETs have
become very popular for digital logic circuits due to high density of fabrication and low power
dissipation.
(1) MOSFET is used in Sample and Hold circuit as a switch.
(2) P-MOSFET and N-MOSFET are used in digital logic circuits
(3) C-MOSFET is very popular in fabricating of MSI and
LSI technology.
11. Draw a single stage amplifier circuit using JFET
The circuit of a Single Stage Common Source N-channel JFET amplifier using self bias
is shown in fig
12. What is the purpose of input capacitor, Cin in single stage common source JFET
amplifier?
An ac signal is supplied to the gate of the FET through an electrolytic capacitor called input
capacitor Cin. This capacitor allows only ac signal enter the gate but isolates the signal source
from RG. If this capacitor is not used, the signal source resistance will come across the resistor
RG and thus changing the biasing conditions.
13. What is the purpose of Biasing Network (Rs and Cs) in single stage common source
JFET amplifier?
The JFET is self-biased by using the biasing network Rs- Cs. The desired bias voltage is
obtained when dc component of drain current flows through the source-biasing resistor Rs.
whereas, the capacitor Cs bypasses the ac component of drain current.
14. What is the purpose of Coupling Capacitor (Cc) in single stage common source JFET
amplifier?
It is an electrolytic capacitor used to couple one stage of amplification to the next stage or
load. It allows only amplified ac signal to pass to the other side but blocks the dc voltage. If this
capacitor is not used, the biasing conditions of the next stage will be drastically changed due to
the shunting effect of Rd.
15. Give the expression for ID for E-MOSFET.
ID = (K(VGS - VT)2
PART –A
Why an NPN transistor has a better high frequency response than the PNP transistor?
2.
An NPN transistor has a better frequency response than the PNP transistor because the
mobility of electron is more and capacitive effect is less.
3. Define fT and f.
Unity gain frequency (fT) or frequency parameter. It is defined as the frequency at
which the common emitter shirt circuit current gain has dropped to unity and is denoted by the
symbol (fT)
4. Beta cut-off frequency (fT).
It is defined as the high frequency at which -of a CE transistor drops to 0.707 or 3dB
from its lower frequencies
5. What is the need for having a high value of fT?
Bandwidth of the amplifier is directly proportional to fT. Hence tp have larger bandwidth, the
value of fT should be high.
7. Write the relation between the sag and lower cutoff frequency?
13. Write the relation between the sag and lower cut-off frequency.
The tilt of sag in time t1 is given by
fL = Pf
___
100∏
P = Y of tilt
F = input signal frequency
14. Give the voltage gain for CE configuration including source resistance.
Avs = =
.
15. Why thermal runaway is not there in MOSFETs? (NOV/DEC-2005)
MOSFET is temperature dependent. In MOSFET, as temperature increases drain
resistance also increases’, reducing the drain current. So thermal runaway does not occur in
MOSFET.
signal passing through REwill cause a voltage drop across it. This will reduce the output voltage,
reducing the gain of the amplifier.
23. Why the Darlington connection is not possible for more number of stages?
In Darlington connection of two transistors, emitter of the first transistor is directly
connected to the base of the second transistor. Because of direct coupling dc output current of the
first stage is (1+hfe)Ib1. If Darlington connection for n stage is (1+hfe)n times I b1. Due to very
large amplification factor even tow stage Darlington connection has large output current and
output stage may have to be a power stage. As power amplifiers are not used in the amplifier
circuits it is not possible to use more than two transistors in the Darlington connection.
24. Briefly explain why dominant pole high frequency compensation method used in
amplifiers. (May,07)
• As the noise frequency components are outside the smaller bandwidth, the noise
immunity of the system improves.
• Adjusting value of fd adequate phase margin and stability of the system is assured.
25. Write the equation for the output voltage and voltage gain for CS amplifier.
The output voltage is given by
Vo = -RD µVgs
RD + rd
Where µ is the amplification factor,
Rd is the drain resistance
Vgs = Vi, the input voltage
SCE 183 Dept of ECE
EC6304 Electronic
Circuits I
26.Write the equations for the output voltage and voltage gain for CD amplifier.
The output voltage is given by
Vo = µ RsVgd
(µ + 1)Rs + rd
Where Vgd = Vi, the input voltage.
The voltage gain for CD amplifier is given by
Av = µ Rs
(µ + 1)Rs + rd
27. Write the equations for the output voltage and voltage gain for CG amplifier.
The output voltage is given by
Vo = -Vo
+ gm Vi rd + Vi
Rd
10. State the advantages of NMOS amplifier with depletion load over enhancement load.
The voltage gain of NMOS amplifier with depletion load is significantly larger than that
with the enhancement load, however, like NMOS amplifier with enhancement load, the body
effect lowers the small-signal voltage gain.