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This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2016.2598251, IEEE
Transactions on Power Electronics
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A Highly Reliable and High Efficiency Quasi


Single-Stage Buck-Boost Inverter
Ashraf Ali Khan, Student Member, IEEE, Honnyong Cha, Member, IEEE, Hafiz Furqan Ahmed,
Juyong Kim, and Jintae Cho

Abstract— To regulate an output ac voltage in inverter systems
having wide input dc voltage variation, a buck-boost power
conditioning system is preferred. This paper proposes a novel Vin +
_ I dc
high efficiency quasi single-stage single-phase buck-boost
inverter. The proposed inverter can solve current shoot-through
problem and eliminate PWM dead-time, which leads to greatly
enhanced system reliability. It allows bidirectional power flow
or or
and can use MOSFET as switching device without body diode
conducting. The reverse recovery issues and related loss of the (a) (b)
MOSFET body diode can be eliminated. The use of MOSFET Fig. 1. Traditional single-phase dc to ac inverters. (a) Voltage source inverter
contributes to the reduction of switching and conduction losses. (VSI). (b) Current source inverter (CSI).
Also, the proposed inverter can be operated with simple PWM
control and can be designed at higher switching frequency to conditioning system is preferred. The buck-boost inverters
reduce the volume of passive components. The detailed
(BBIs) are also used for plug-in hybrid electric vehicles,
experimental results are provided to show the advantages of the
proposed inverter. Efficiency measurement shows that using uninterruptible power supplies, ac motor drives, and
simple PWM control the proposed inverter can obtain peak bidirectional buck-boost rectifier. Fig. 2 shows a two-stage BBI
efficiency of 97.8 % for 1.1 kW output power at 30 kHz switching obtained by cascading a boost dc-dc converter with a VSI. It
frequency. requires a bulky intermediate power decoupling capacitor Cdc ,
to decouple the power between the boost dc-dc converter and
Index Terms— Buck-boost, dual-buck, efficiency, inverter, VSI. Fig. 3 shows a two-stage BBI obtained by cascading a
MOSFET, reliability, switching cell, single-stage, Z-source.
buck dc-dc converter with a CSI. It requires a bulky input
inductor Lin , which decreases the power density. Fig. 4 shows
I. INTRODUCTION
qZ-source inverter (qZSI) [35] which can be viewed as quasi
T RADITIONALLY, for dc to ac power conversion, there
exist two converters: voltage source inverter (VSI) and
current source inverter (CSI) as shown in Fig. 1 [1-3], [5].
single-stage BBI. It can obtain both the buck and boost
functions by placing impedance network between main power
source and inverter bridge [4-8]. It is immune to EMI noise and
The VSI has only buck (or step-down) function and is
has no shoot-through and dead-time problems. However,
vulnerable to shoot-through (or arm short) problem caused by
during the boost operation it has high switch voltage and
electromagnetic interference (EMI) noise. Similarly, the CSI
current stresses (see Table I) which go against its efficiency,
has only boost (step-up) function and is vulnerable to
and its attainable voltage gain is practically limited. In [9-10],
open-circuit (or arm open) problem caused by EMI. In order to
an active BBI is developed. It has the desired buck-boost
avoid the shoot-through problem, a finite dead-time in gate
function by using more active switches in the output. However,
signals is required for the VSI. Likewise, a finite overlap-time
like the traditional VSI, it is not resistant to the shoot-through
is required for the CSI to prevent the open-circuit problem. The
problem at dc side and has commutation problem at ac side.
dead-time or overlap-time causes output waveform distortion.
Therefore, finite dead-time has to be used at the dc side and
Output voltages of renewable energy sources change in a
lossy snubber circuits have to be attached to switches at the ac
wide range. To regulate an inverter output voltage in systems
side in order to avoid the commutation problem. Alternatively,
having wide input dc voltage variation, a buck-boost power
as with conventional ac-ac converters, soft commutation
strategy has to be used for the switches at the ac side by sensing
This research was supported by the KEPCO under the project entitled by output voltage polarity. The sensing technique increases
“Demonstration Study for Low Voltage Direct Current Distribution Network in control complexity and decreases converter reliability and
an Island” (D3080). quality of output waveforms.
A. A. Khan, H. Cha, and H. F. Ahmed are with the School of Energy
Engineering, Kyungpook National University, 1370 Daegu, Korea (email:
For a power level at which the resistive conduction voltage
08beeashrafa@seecs.edu.pk;chahonny@knu.ac.kr;furqanhmd164@gmail.com drop of MOSFET is lower than the nearly fixed voltage drop of
;). IGBT, the use of MOSFET is preferred because of its fast
J. Kim and and J. Cho are with the Korea Electric Power Corporation Research switching and lower switching loss.
Institute, Daejeon, Korea (email:juyong@kepco.co.kr;jintaecho@kepco.co.kr).

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2016.2598251, IEEE
Transactions on Power Electronics
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regulated ac output voltage for wide input dc voltage variation


S6 Din S1 S3 owing to its buck-boost capability, and can solve the limited
Lf
gain problem of the VSIs and CSIs. Unlike the conventional
Lin
Cdc two-stage BBI in Fig. 2, it does not require intermediate power
decoupling capacitor. The proposed inverter has no current
Vin C in shoot-through problem and can eliminate the pulse width
S5 S2 S4
modulation (PWM) dead-time, which lead to greatly enhanced
system reliability. The body diodes of MOSFETs do not
Fig. 2. Boost type dc-dc converter followed by a VSI. conduct in the proposed topology, which avoids the risk of
MOSFETs failure associated with the poor reverse recovery of
Lin MOSFET body diode. By using power MOSFETs in
S5 S1 S3 conjunction with externally selected fast recovery diodes, the
Lo
proposed inverter can realize high frequency and high
efficiency operation. The topology derivation, switching
Vin C in Cdc Co
strategies for buck and boost operations, operation principle,
and circuit analysis are given in the paper. A 1.1 kW hardware
S6 Din S2 S4
prototype is tested and detailed experimental results are
provided to verify the advantages of the proposed inverter.
Fig. 3. Buck type dc-dc converter followed by a CSI.
II. CIRCUIT TOPOLOGY OF THE PROPOSED BUCK-BOOST
L1
S5 C2 L2
INVERTER
MOSFET has such benefits as fast switching, low switching
Din S1 S3 loss and nearly resistive conduction voltage drop. However, it
Lf
has failure risk due to reverse recovery issues of body diode
Vin C1 especially in high voltage and hard switching applications.
Therefore, the use of MOSFET in the traditional hard switching
inverter is normally not suggested [37, 19-20]. For a power
S2 S4 level at which the resistive conduction voltage drop of
MOSFET is lower than the fixed voltage drop of IGBT, the use
Fig. 4. Quasi-Z-source inverter (qZSI).
of MOSFET as switching device is preferred for high frequency
and high efficiency operation, provided that the risk of
The single-phase MOSFET based inverter called HERIC MOSFET failure due to reverse recovery of body diode is
inverter in [11-12] can reduce switching and conduction losses prevented. The topologies of VSI [21-27], ac-dc rectifier [28],
with simple structure. However, it has the risk of MOSFET and ac-ac converters [29-32, 36, 38] are implemented with
failure due to reverse recovery of body diodes. The H5 and H6 MOSFETs and external fast recovery diodes to obtain high
inverters in [13] and [14], respectively, prevent the risk of efficiency.
MOSFETs failure at the cost of more conduction losses. The The dual-buck inverter patented by Xantrex technology [15]
HERIC, H5 and H6 inverters have the risk of current
is shown in Fig. 5. It uses four MOSFETs S1  S4 , four
shoot-through in phase-legs. In [15], a reliable and MOSFET
based inverter called dual-buck inverter is proposed. The body external fast recovery diodes D1  D4 , and four split-phase
diodes of MOSFETs are prevented from conducting by use of inductors L1a  L2b . Due to the use of D1  D4 and L1a  L2b ,
external diodes and reverse recovery problem of body diodes is body diodes of the MOSFETs never conduct with this topology.
eliminated. The dual-buck inverter is immune from Therefore, the benefits of MOSFET can be achieved without
shoot-through problem of voltage source, therefore eliminates the reverse recovery issues of body diode. In addition, the
the dead-time. dual-buck inverter has no current shoot-through problem, thus
However, all of the aforementioned inverters are buck type. does not require dead-time. For these reasons, the dual-buck
Therefore, in order to use these inverters in systems having inverter can be considered as one of the high reliability and high
wide input voltage variation, an additional boost dc-dc efficiency inverter. The research on the dual-buck inverter has
converter is cascaded with these inverters, as have been done been focused on the development of new topologies, efficiency
for the dual-buck inverter in [16]. In [17], a three-stage improvement, and PWM control [21-27]. All the topologies
buck-boost dc-ac inverter which can cover wide variation of developed with the dual-buck structure have step-down
input dc voltage is proposed. It has three power stages function. In order to achieve the buck-boost operation, a boost
consisting of cascaded connection of a boost converter, buck dc-dc converter is required in the front-end with Cdc as
converter and line frequency inverter. In [18], a modified
three-stage MOSFET based BBI named ‘Aalborg inverter’ depicted in Fig. 6(a). Fig. 6(b) is a bidirectional BBI obtained
obtained by interchanging position of the buck and boost from Fig. 6(a) where the MOSFET and diode are replaced with
converters in the BBI in [17] is proposed. It can save one IGBTs to avoid the issues of MOSFET body diode during hard
inductor and reduces the overall conduction loss of inductors. switching.
In this paper, a new MOSFET based bidirectional quasi Recently, novel ac-ac converters termed as switching cell
single-stage single-phase BBI is proposed. It can provide a (SC) ac-ac converters are developed in [29]. The boost-type SC

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Transactions on Power Electronics
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io
S1 D1 L S3 D3 S1 D1 L1a S5 D5
1a
-

+
i L1 +
Vin C in - L2a vC1 C
+ 1

+
L2a -
Vin C in Co RL vo i L2
L2b D2 S2 D6 S6
-
+
Co RL vo
L1b -
D2 S2 D4 S4
S3 D3 - L1b S7 D7

+
-
i vC 2 C
Fig. 5. Dual-buck dc-ac inverter [15]. L2b - L3 2

+
+
i L4
D4 S4 D8 S8
Din S1 D1 L S3 D3
1a
Fig. 8. Proposed buck-boost inverter.
Lin L2a +
Cdc Co RL vo
L2b
- vs S1 , S 3
Vin C in vtri 1
0
S5 D2 S2 D4 S4
L1b
-1
S2 , S4
Vc S6 , S7
(a)
vtri 1
0
S5 , S8
S6 S1 D1 L S3 D3 Fig. 9. Gate signal generation of the proposed inverter.
1a

Lin
Cdc
L2a
Co RL
+
vo
current/voltage rating devices. The proposed inverter can be
L2b
- designed with MOSFET, therefore, high frequency and high
Vin
efficiency operation can be realized. As shown in Fig. 8, each
C in L1b
S5 D2 S2 D4 S4 switching device is connected in series with an external diode,
therefore no shoot-through current is possible in the proposed
(b) inverter. The inductors L1a , L1b , L2a , L2b split the phase legs
Fig. 6. Dual-buck dc-ac inverter cascaded with a boost dc-dc converter.
(a) Unidirectional. (b) Bidirectional. and serve as buck, boost and current limiting inductors. The
vo - two capacitors C1 and C2 in the output are added to provide a
+

safe path for inductor currents when dead-time occurs in the


S1 D1
Co
S3 D3 gate signals of ( S5 , S6 ) or ( S7 , S8 ) or ( S5  S8 ). They also
CL1
Lin
serve as both output filter capacitor and lossless snubbers
reducing the voltage spikes caused by the stray inductances in
+

vin C in C1 C2
- CL2 the circuit layout.
The gate signal generation of the proposed inverter is shown
D2 S2 D4 S4
in Fig. 9. The switches S1  S4 are switched with simple
bipolar sinusoidal PWM (SPWM) scheme, and the switches
Fig. 7. Boost-type switching cell (SC) ac-ac converter [29]. S5  S8 are switched with simple complementary PWM
scheme. The gate signals of S1  S4 are obtained by comparing
ac-ac converter is shown in Fig. 7. Similar to the dual-buck
a sinusoidal control signal vs with a carrier signal vtri , and the
inverter and unlike the conventional ac-ac converters, this
converter is highly reliable because it has no current gate signals of S5  S8 are obtained by comparing a dc control
shoot-through and dead-time problems. It can also obtain high signal Vc with vtri .
efficiency by using MOSFET as switching device. In addition,
it does not require lossy snubbers or current/voltage polarity III. OPERATION OF THE PROPOSED BUCK-BOOST INVERTER
sensing modules for commutation. The research on the SC
ac-ac converters are focused on the development of new ac-ac The voltage vspwm produced by the input dc bridge
converter topologies, efficiency improvement, and magnetic ( S1  S4 ) for a given input voltage Vin can be expressed as:
volume reduction [30-33, 36, 38].
Fig. 8 shows the circuit topology of the proposed quasi
single-stage BBI. It is a combination of the dual-buck and SC vspwm  MVin sin(t ) (1)
structures. The dc input of the proposed inverter takes the
dual-buck structure and the ac output takes the SC ac-ac In (1), M is modulation index. The voltage gain of the output
structure. Similar to the qZSI and the dual-buck inverter, the ac bridge ( S5  S8 ) can be obtained the same as that of the
proposed inverter is very resistant to EMI noise’s misgating-on
traditional boost-type ac-ac or dc-dc converter [29], [31] as:
or -off. However, as shown in Table I, unlike the qZSI, the
proposed inverter requires relatively low

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2016.2598251, IEEE
Transactions on Power Electronics
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20
vtri
15 vs Vc
Boost Region
10 M 1 t
5
vo 1 S1, S3
Buck Region t
Vin 0.8
S2 , S4
0.6 D0 t
S5 , S8
0.4 t
0.2 S6 , S7
t
Mode 1 Mode 2
0 0.5 10 0.5 1
M D Fig. 11. PWM strategy during buck operation.
Fig. 10. Voltage gain of the proposed inverter.

io
vo 1 S1 D1 S5 D5
 (2) L1a
-

+
vspwm 1  D Vin
iL1
vC1 C
+
Cin - L2a 1

+
-
iL2
D2 S2 D6 S6
where vo is the output ac voltage, and D is the duty ratio +
RL vo
defined as the ON time of switches S6 , S7 . From (1) and (2), -
voltage gain of the proposed inverter can be expressed as: S3 D3 - L1b S7 D7

+
i -
L2b - L3 vC2 C
2

+
vo M +
 sin(t ) (3) D4 S4
iL4
D8 S8
Vin 1  D
Fig. 12. Equivalent circuit of the proposed inverter during buck operation.
The voltage gain in (3) is plotted in Fig. 10. As shown in Fig.
10, the proposed inverter can operate both in buck and boost
io
modes based on the values of M and D. When Vin is greater S1 D1 S5 D5
L1a
-

+
than the peak vo , the proposed inverter operates in the buck Vin iL1
vC1 C
+
Cin - L2a 1

+
mode by keeping D=0 and adjusting M. When Vin is lower -
iL2
D2 S2 D6 S6
than the peak vo , the proposed inverter operates in the boost +
RL vo
mode by keeping M=1 and adjusting D. -
S3 D3 - L1b S7 D7
+

i -
L2b - L3 vC2 C
2
+

A. Buck Operation +
iL4
PWM strategy during the buck operation is depicted in Fig. D4 S4 D8 S8
11. The switches S6 , S7 are always OFF and S5 , S8 are ON,
(a)
that is, D=0. The diodes D6 , D7 are reverse biased and
D5 , D8 are forward biased. The equivalent circuit during the io
S1 D1 L1a S5 D5
buck operation is shown in Fig. 12. During the buck operation, -
+

iL1 +
the proposed inverter reduces to the dual-buck inverter in Fig. 5 Vin Cin - L2a vC1 C
1
+

with only one extra MOSFET and diode conducting the main iL2
-
D2 S2 D6 S6
current at a time. The inductors L1a and L1b conduct the main +
RL vo
current during the positive half-cycle of output current with the -
direction shown in Fig. 13, and L2a and L2b conduct current S3 D3 - L1b S7 D7
+

i -
during the negative half-cycle of output current. During the L2b - L3 vC2 C
2
+

buck operation, the proposed inverter has two consecutive +


iL4
D4 S4 D8 S8
modes as discussed below.
In the following mode analysis, all the inductors are
(b)
assumed to have an equal inductance, L / 2 . Fig. 13 shows the Fig. 13. Buck operation of the proposed inverter. (a) Mode 1 (Mode 1 & 5 for
operation when the output current is positive and the same boost operation). (b) Mode 2 (Mode 2 & 4 for boost operation).
analysis can be made for the negative half-cycle of current.

1) Mode 1 As shown in Fig. 13(a), the switches S1, S3 are turned-on


and S2 , S4 are turned-off, thus the diodes D2 , D4 are reverse
biased. The current relation is given as follows:

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vtri Vc io
vs
S1 D1 L1a S5 D5
-

+
iL1 +
Vin Cin - L2a vC1 C
t 1

+
-
iL2
S1 , S3 D2 S2 D6 S6
t +
S2 , S4 RL vo
t -
S3 D3 L1b S7 D7
S5 , S8 -

+
t i -
L2b - L3 vC2 C
S6 , S7 2

+
t iL4
+
D4 S4 D8 S8
Mode 1 Mode 2 Mode 3 Mode 4

(a) (a)

vtri io
vs Vc S1 D1 L1a S5 D5
-

+
iL1 +
Vin Cin - L2a vC1 C
1

+
t -
iL2
D2 S2 D6 S6
S1 , S3 +
t RL vo
S2 , S4 -
t S3 D3 - L1a S7 D7

+
S5 , S8 -
t i
L2b - L3 vC2 C
2

+
S6 , S7 +
t iL4
D4 S4 D8 S8
Mode 5 Mode 6 Mode 7 Mode 8
(b)
(b) Fig. 15. Boost operation of the proposed inverter. (a) Mode 3&7. (b) Mode
Fig. 14. PWM strategy during boost operation. (a) Vin  vo (or Vc  vs ). (b) 6&8.
Vin  vo (or Vc  vs ).
( L2a and L2b ) are in series, therefore the voltage across L1a
(or L1b ) becomes Vin / 2 , Vin / 2 , (Vin  vo ) / 2 , and
diL1 V v (Vin  vo ) / 2 . Similarly, during the negative half-cycle, the
 in o (4)
dt L voltage across L2a (or L2b ) becomes Vin / 2 , Vin / 2 ,
2) Mode 2 (Vin  vo ) / 2 , and (Vin  vo ) / 2 . Modes 1-4 for Vin  vo are
As shown in Fig. 13(b), the switches S1, S3 are OFF and shown in Fig. 14(a), and modes 5-8 for Vin  vo are shown in
S2 , S4 are ON, and the diodes D2 , D4 are forward biased due Fig. 14(b).
to freewheeling action. The current relation is given as follows:
1) Mode 1&5
These modes are the same as mode 1 of the buck operation
diL1 Vin  vo
 (5) shown in Fig. 13(a).
dt L
2) Mode 2&4
B. Boost Operation These modes are the same as mode 2 of the buck operation
During the boost operation, M is set to 1, and D is varied to shown in Fig. 13(b).
regulate vo . The switching states are shown in Fig. 14. In Fig.
3) Mode 3&7
14, Vc is defined as ( 1  Vc ) and it is the dc control signal that In mode 3 and 7, as shown in Fig. 15(a), the switches
determines the duty cycle of switches S5 , S8 , that is, (1-D). S1, S3 , S5 , and S8 are OFF and the switches S2 , S4 , S6 , and
Fig. 14(a) shows the switching signals when Vc  vs (or when S7 are ON. The inductor current decreases with a slope as:
the instantaneous output voltage is lower than Vin ). Fig. 14(b)
diL1 V
shows the switching signals for vs  Vc . In this paper, the   in (6)
dt L
voltages before and after inductors are designated as dc-bridge 4) Mode 6&8
and ac-bridge voltages, respectively. The dc-bridge voltage is In mode 6 and 8, as shown in Fig. 15(b), the switches
varied between Vin and Vin , whereas the ac-bridge voltage S1, S3 , S6 , and S7 are ON, and S2 , S4 , S5 , and S8 are OFF.
is varied between 0 and vo . The inductors ( L1a and L1b ), and The inductor current rises with a slope as:

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io
diL1 V S1 D1 L1a S5 D5
 in -

+
(7) iL1 +
dt L Vin Cin - L2a vC1 C
1

+
-
iL2
D2 S2 D6 S6
The following two modes show the operation of the +
proposed inverter when dead- or overlap-time caused either by RL vo
-
purpose or by EMI noise’s misgating-on or -off occurs although S3 D3 - L1b S7 D7

+
they are not the desired modes of operation of the proposed i vC2 C
-
L2b - L3 2
inverter.

+
+
iL4
D4 S4 D8 S8

C. Overlap-time Mode (a)


As shown in Fig. 16(a), when all the switches S1  S8 are
ON, the freewheeling diodes D1  D8 become reverse biased, io
S1 D1 L1a S5 D5
and the inductors L1(a,b)  L2(a,b) limit the shoot-through -

+
iL1 +
Vin Cin - L2a vC1 C
1

+
current by providing opposition. Thus, when multiple switches -
iL2
D2 S2 D6 S6
are turned-on simultaneously, there is no shoot-through current +
problem. As a result, the dead-time in gate signals can be RL vo
-
eliminated and high quality output waveforms can be obtained. S3 D3 - L1b S7 D7

+
i -
L2b - L3 vC2 C
2

+
+
D. Dead-time Mode iL4
D4 S4 D8 S8
Similar to the overlap-time mode, when S1  S8 are all OFF
either by purpose or EMI noise as shown in Fig. 16(b), (b)
Fig. 16. Operation of the proposed inverter when dead- or overlap-time occurs
D1  D8 become forward biased. The capacitors C1 and C2 due to EMI noise. (a) Overlap-time. (b) Dead-time.
provide safe path for inductor currents. Thus, when two or more
switches are turned-off simultaneously, the inductor current
finds safe path to flow. Vin.max
iL.max  T (10)
2L
IV. CONTROL STRATEGY AND PARAMETER DESIGN OF THE
PROPOSED INVERTER Where T is the switching period.
Consider that iL.max is restricted to x% of I L.max , i.e.,
A. Inductor Design
iL.max  x%I L.max . Thus, the required inductance is obtained
The inductors L1a , L1b , L2a and L2b are designed based as:
on their maximum current handling capacity and maximum L Vin.max
permitted current ripple. The maximum inductor current  2  4 x% I T
I L.max for output power Po occurs during the boost operation  L.max
 (11)
with minimum input voltage ( Vin.min ) and expressed as:  L  Vin.max  Vin.min T
 2 4 x% Po
Po
I L.max  (8) B. Capacitor Design
Vin.min
The capacitors C1 and C2 provide safe path for inductor
currents during dead-time, and they also serve as output filter
The maximum inductor current ripple iL.max occurs
capacitors. If Co in Fig. 8 is removed, then C1 and C2 can be
during the buck mode with maximum input voltage Vin.max .
designed to serve as output filter capacitor. In this paper, Co is
Since the inductors L1a and L1b (or L2a and L2b ) are always
used as the main output filter capacitor, thus C1 and C2 can be
in series and the inductance of each inductor is defined as L / 2 ,
designed for the dead-time ( td ) in gate signals of S5  S8 . The
the inductor current slope during mode 1 (see Fig. 13(a)) is
obtained as: sum of voltages across C1 and C2 is always vo regardless of
diL Vin  vo the operation modes. During td , the current iL1 (= iL3 ) is
 (9)
dt L flowing through C1 (see Fig. 16(b)) when io  0 , and the
current iL2 (= iL4 ) is flowing through C2 when io  0 ,
At zero crossing point, vo becomes zero and the ON-time of
S1, S3 becomes T/2. Thus, from (9), iL.max is obtained as: respectively. Thus, the voltage ripples vC1 and vC2 of C1

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and C2 can be obtained as:  


Vdc

S1 S5
 I L1 S2 S6

vC1 
SPWM S3 S7 PWM
td S4 S8
 C Proposed
 (12) vs (t )
inverter
v  I L2 t
 sin( wt ) Voltage peak
C2 d  
 C detection vo
Vc  D(t )
M (t )

where C is the capacitance of C1 and C2 . The maximum PI Vref yes (1  D) no Vref PI


 Vo Vo  Vref ? Vo 
voltage ripples vC1.max and vC2 .max occurs during the ue 
M
 ve

boost mode when Vin.min and I L.max as given by (8). set D  0 set M  1
Buck mode Boost mode

Consider that vC1.max and vC2 .max are restricted to


vC1.max , vC2 .max  y%vo . To maintain these voltage Fig. 17. Control block diagram.

ripples, the capacitance is obtained as

 I L.max where k p and ki are the proportional and integral gain of


C  y %vo td the PI controller. During the buck operation, M  Vref / Vin .

 (13)
C  ( Po / Vin.min ) t The M (t ) is multiplied with sinusoidal signal sin( t) to
 y %vo
d
get vs which is compared with vtri to generate the pulsating
signals for S1  S4 .
C. Rating of Semiconductor Devices
 In boost mode, M is set to 1 and Vo is compared with Vref
The voltage and current stress of MOSFETs and relevant
external diodes are the same, and the inductor currents to generate the error signal ve . The ve is fed into the PI
I L1  I L4 flow through the switches. Therefore, the maximum controller for compensation,
and Vc is determined
current stress for all switches is equal to I L.max as given by (8). accordingly which is compared with vtri to generate the
The voltage stress of S1  S4 is Vin , therefore the maximum pulsating signals for switches S5  S8 .
voltage stress of S1  S4 is determined by maximum input
voltage. On the other hand, the maximum voltage stress of
S5  S8 is determined by maximum output voltage.
Vc (t )  k p (Vref  Vo )  ki (Vref  Vo )dt (15)

During boost operation, Vc  1  Vin / Vref .


D. Modulation Strategy of the Proposed Inverter
Fig. 17 shows control block diagram of the proposed V. COMPARISON WITH THE CONVENTIONAL SINGLE-PHASE
standalone inverter. As shown, vo is sensed and fed into peak BUCK-BOOST INVERTERS
voltage detector. The sensed peak output voltage Vo is then The traditional cascaded buck-boost inverter (TCBBI), qZSI,
and cascaded dual-buck boost inverter (CDBBI) are shown in
multiplied by (1  D) / M to get Vo for the ideal condition (i.e.,
Figs. 2, 4, and 6, respectively. Table I summarizes the basic
D=0 and M=1). The resultant (1  D)Vo / M is compared with features of the proposed and the aforementioned single-phase
reference voltage ( Vref ) to determine the buck or boost BBIs.
operating mode. The inverter operates in buck mode when
A. Comparison of Basic Functionality and Reliability
(1  D)Vo / M  Vref , and in boost mode when  The TCBBI and CDBBI are two-stage inverters. The
(1  D)Vo / M  Vref . proposed inverter, similar to the qZSI, is quasi single-stage.
 The shoot-though duty cycle DZSI and modulation index M
 During the buck operation, Vc is zero, and Vo is compared are interdependent (i.e., M=1-DZSI) in the qZSI. Therefore, M
decreases with increase in DZSI (with increase in gain G),
with Vref to generate the error signal ue , which is fed into
which results in lower output power quality and higher
proportional-integral (PI) controller for compensation, and voltage stress on inverter bridge with poor utilization of
the modulation index M (t ) is determined as follows, inverter bridge voltage. On the other hand, similar to the
TCBBI and CDBBI, the M and D are independent in the
proposed inverter. Therefore, the voltage gain of the

M (t )  k p (Vref  Vo )  ki (Vref  Vo )dt (14) proposed inverter can be increased by increasing D while
keeping M to its maximum value (M=1), which results in

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better power quality with better utilization of inverter bridge 4 


VSx TCBBI
voltage. 
3.5 VSx CDBBI

Normalized switch voltage stresses


In the TCBBI and qZSI, current flow through body diodes of V Sx qZSI
3 VSx
switches. Therefore, they usually use IGBTs as switching Proposedinverter

devices to avoid reverse recovery issues of MOSFET body 2.5


VS1 S 5
diode. In the proposed inverter, current does not flow through 2 VS1 S 6
body diodes of switches, therefore power MOSFETs can be VS1 S 6 VS1 S 4
1.5
used as switching devices to utilize its benefits (see Fig. 20).
VS 5 S 8
 In the proposed inverter, external diodes are used for current 1
freewheeling. They can be selected with the features of 0.5
negligible reverse recovery loss and low forward voltage
0
drop to decrease the power loss and realize the use of higher 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
switching frequency. V o ltag e g ain G ( vˆ o / V in )

 The proposed inverter allows bidirectional power flow (a)


without conducting body diodes of switches, and any short-
2.5 
or open-circuit problems. For unidirectional power flow, the VSx Proposedinverter VSx TCBBI
boost dc-dc converter of the TCCBI and CDBBI can be V Sx qZSI 
VSx CDBBI

Normalized switch voltage stresses


2
designed with MOSFET and external fast recovery diode.
For bidirectional power flow, to avoid the reverse recovery V S1 S 5
issues of MOSFET body diode, the boost dc-dc converter 1.5
should be designed with IGBTs. Therefore, for hard
V S1 S 6 V S1 S 6 VS 5 S 8
switching and bidirectional power flow, the boost dc-dc 1
converter of the TCBBI and CDBBI cannot benefit from high
speed MOSFETs. 0.5
 The ZSI has start-up inrush current problem [33], which can VS1 S 4

be solved with the qZSI. The TCBBI and CDBBI use boost
0
dc-dc converter which has the start-up inrush current 1 1.5 2 2.5 3 3.5 4 4.5 5
problem. The existence of uncontrollable range when the Voltagegain G (vˆo / Vin )

output voltage of boost dc-dc converter is below the peak (b)


value of the source voltage results in the start-up inrush Fig. 18. Comparison of normalized switch voltage stresses of four inverters. (a)
Buck mode. (b) Boost mode.
current [34]. The proposed inverter takes the structure of the
dual-buck inverter at the input side which is buck type, 1
iLf TCBBI
therefore it has no start-up inrush current problem. 
0.9 iLf
 The TCBBI has current shoot-through problem and needs 0.8
CDBBI
iLf qZSI
dead-time. The proposed inverter, similar to the qZSI, does
0.7 iLx ( a,b) Proposedinverter
not suffer from the shoot-through or open-circuit problem.
Inductor current ripple

Therefore, it does not require dead time. The unidirectional


0.6 iLx ( a,b)

CDBBI (see Fig. 6(a)) does not require dead time. However, 0.5 iLf iLx ( a,b)

for bidirectional power flow, the boost dc-dc converter has 0.4 iLf
the risk of current shoot-through due to the use of active 0.3
iLx ( a,b)
switches (see Fig. 6(b)). Thus, finite dead time is required 0.2
iLf
between S5 and S6 . 0.1
0
B. Voltage and Current Stresses of Switching Devices 1 1.5 2 2.5 3 3.5 4 4.5 5
Voltagegain G (vˆo / Vin )
From Table I, the switch voltage stresses normalized with
Fig. 19. Ratio of inductor current ripple of the proposed inverter to the current
vˆo for buck and boost modes are plotted in Figs. 18(a) and (b), ripple of other inverters during boost mode.
respectively. During the buck mode, only S1  S4 are switched
at high frequency in all inverters and the voltage stress of proposed inverter have lower voltage stress than the switches in
S1  S4 is equal to Vin . Therefore, the voltage stress increases all other three inverters and the difference becomes significant
as voltage gain (G) decreases. On the other hand, the S5  S8 in with increase in gain G (as Vin becomes lower).
the proposed inverter have lower voltage stress than the During the buck operation, the current stress of switches in
switches in other three inverters because their voltage stress is the proposed inverter is iˆo , which is the same as those of
only determined by vˆo (see Fig. 18(a)).
S1  S4 in the TCCBI, CDBBI, and qZSI. In the boost
During the boost mode as shown in Fig. 18(b), S5  S8 of
operation, the current stress of switches in the proposed inverter
the proposed inverter have the same voltage stress as that of all is I in , which is the same as those of the switches in the boost
the switches in the TCBBI and CDBBI, and lower than that of
dc-dc converter in the TCBBI and CDDBI while smaller than
switches in the qZSI. While the switches S1  S4 in the
that of in the qZSI.

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TABLE I
COMPARISON OF THE PROPOSED AND CONVENTIONAL BUCK-BOOST INVERTERS
qZSI TCBBI CDBBI Proposed inverter
Parameters
(Fig. 4) ( Fig. 2) (Fig. 6) (Fig. 8)
Power conversion Quasi single-stage Two-stage Two-stage Quasi single-stage
Relation between M and D M=1-DZSI independent independent independent
Shoot-through risk
(unidirectional power no yes no no
flow)
Reverse recovery issues of
MOSFET body diode
yes yes no no
(unidirectional power
flow)
Independent selection of
active switches and
freewheeling diodes no no yes yes
(unidirectional power
flow)
No. of switches
4 ( S1  S4 ) 5 ( S1  S5 ) 5 ( S1  S5 ) 8 ( S1  S8 )
(unidirectional power flow)
No. of switches
5 ( S1  S5 ) 6 ( S1  S6 ) 6 ( S1  S6 ) 8 ( S1  S8 )
(bidirectional power flow)
External fast recovery
diodes (unidirectional 1 ( Din ) 1 ( Din ) 5 ( Din , D1  D4 ) 8 ( D1  D8 )
power flow)
No. of inductors 3 ( L1, L2 , L f ) 2 ( Lin , L f ) 5 ( Lin , L1a , L1b , L2a , L2b ) 4 ( L1a , L1b , L2a , L2b )
No. of inductors 3 ( Lin , L1a, L1b or
conducting current at a 3 ( L1, L2 , L f ) 2 ( Lin , L f ) 2 ( L1a, L1b or L2a, L2b )
time Lin , L2a , L2b )
Energy storing or dc link 2 ( C1, C2 ) 2 ( Cin , Cdc ) 2 ( Cin , Cdc ) 1( Cin )
capacitors
Voltage gain M M M M
G(vˆo / Vin ) 1  2 Dzsi 1 D 1 D 1 D
VS1 S 5  Vin ( Buck )
VS1 S 5  (2G  1)Vin VS1S 6  GVin  vˆo VS1S 6  GVin  vˆo (Boost) VS1S 4  Vin
Switch voltage stresses
(2G  1)vˆo (Boost) VS1S 6  Vin (Buck) VS 5S 8  vˆo
 ( Boost )
GVin VS1S 6  Vin (Buck)

I S1 S 4  iˆo , I S 5  Iin (Buck)


I S1 S 4  2 I in , I S 5 I S 5S 6  Iin , I S1 S 8  iˆo (Buck)
Switch current stresses I S 5S 6  Iin , I S1S 4  iˆo
(2G  1) I in I S1S 4  iˆo I in (Boost)
 (Boost )
G
VC1,C 2  Vin (Buck) VCin  Vin VCin  Vin
Capacitor voltage stresses VC 2  (G  1)Vin VCdc  Vin (Buck) VCdc  Vin (Buck) VCin  Vin
VC1  GVin (Boost) VCdc  GVin (Boost) VCdc  GVin (Boost)
I L1, L2  Iin I Lin  Iin I Lin  Iin I L1aL2b  iˆo (Buck)
Inductor currents
I Lf  iˆo I Lf  iˆo I L1aL2b  iˆo I L1aL2b  Iin (Boost)

vˆo (G  1)
vˆo (G  1) iLin  T vˆo (G  1)
iL1, L 2  T G2 L iLin  T (Boost)
(2G  1) L G2 L vˆo
(Boost) iL1a L2b  T (Buck)
(Boost) vˆ 2ML
vˆ iL1a L2b  o T (Buck)
vˆ iLf  o T vˆ
Inductor current ripples iLf  o T (Buck) 2ML
2ML
iL1a L 2b  o T (Boost)
2ML vˆ 2GL
vˆ (2G  1)
(Buck) iL1a L2b  o T (Boost)
iLf  o T (Boost) vˆ 2 L Where, Lxa , Lxb  L / 2 ,
2GL iLf  o T (Boost)
2L L
Where, in  L Lxa , Lxb  L / 2 x=1, 2
Where, L1, L2 , L f  L
Where, Lin , L f  L x=1, 2

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C. Inductor Requirement and Current Ripples io


The number of inductors required is summarized in Table I. S1 D1 L1a S5 D5
-

+
Compared with the L f in the TCBBI, the two inductors L1a iL1
vC1 C
+
VB Cin - L2a 1

+
-
and L1b (or L2a and L2b ) in both the dual-buck inverter of the D2 S2
iL2
D6 S6
CDBBI and the proposed inverter are always in series. Co
vac
Therefore, the required inductance for L1a and L1b or ( L2a
S3 D3 - L1b S7 D7

+
and L2b ) becomes L f / 2 . Therefore, the magnetic volume of iL3 vC2 C
-
L2b - 2

+
the proposed inverter and the TCCBI could be comparable, and +
iL4
D4 S4 D8 S8
the magnetic volume of the proposed inverter could be smaller
that of the qZSI and CDBBI.
Fig. 20. Bidirectional power flow without body diode conducting.
The inductor current ripples of filter inductors ( L f for the
qZSI and TCBBI, L1a  L1b (or L2a  L2b ) for the CDBBI and
the proposed inverter) are given in Table 1. During the buck
operation, the current ripples of filter inductors are the same for
all inverters. Fig. 19 shows the ratios of the inductor current
ripples of the proposed inverter to those of the qZSI, CDBBI,
and TCBBI during the boost operation. It can be seen that the
inductor current ripple of the proposed inverter is smaller than
those of other three inverters for same value of inductance L,
and the difference becomes significant as the voltage gain
increases (as Vin becomes lower).

D. Capacitor Requirement
The qZSI requires two energy storing capacitors C1 and C2
. The TCBBI and CDBBI require two capacitors, an input
capacitor Cin and Cdc . The Cdc can be designed to handle the
low frequency current component and to filter the pulsating
voltage of boost dc-dc converter. The proposed inverter does
not require Cdc . However, like the single-phase dual-buck and
H-bridge inverters, the proposed inverter requires an input Fig. 21. Simulated dynamic response of the proposed inverter with step input
capacitor Cin , which can be designed to handle the low change at the peak of vo (or vs ).
frequency current component. If the low frequency current
component is ignored, then the proposed inverter can be
operated without dc link capacitors. changes from 0.78 to 1, and Vc changes from 0 to 0.4. Fig. 21(b)
The proposed inverter has one extra MOSFET or diode in shows the results for mode change at the zero crossing of vo or
the conduction loop, while the CDBBI and TCBBI have one vs . From the simulation results, it is found that by changing the
extra inductor Lin in the conduction loop, and the qZSI has
operational mode no noticeable distortion occur in the output
two extra inductors L1 and L2 in the conduction loop. In voltage.
comparison with the conventional inverters, the proposed
inverter allows bidirectional power flow without body diodes TABLE II.
ELECTRICAL SPECIFICATIONS OF THE PROPOSED INVERTER
conducting and current shoot-through problem (see Fig. 20).
Output voltage 220 Vrms/60 Hz
Input voltage 185-400 Vdc

VI. SIMULATION RESULTS Output power 1.1 kW


The electrical specifications of the proposed inverter are Switching frequency 30 kHz
listed in Table II. Simulation results of the proposed MOSFETs ( S1  S8 ) 47N60CFD
closed-loop standalone inverter are given in Fig. 21. Fig. 21
Diodes ( D1  D8 ) RURG3060
shows the results for the worst case when Vin step up instantly
Inductors ( L1a  L2b ) 0.5 mH
from 185 V to 400 V at the peak of vo or vs . To regulate vo at
Capacitors ( C1, C2 ) 2.2  F
311 V, magnitude of vs , M changes from 1 to 0.78, and Vc
Output capacitor ( Co ) 8 F
changes from 0.4 to 0. At t= 0.2 s, Vin step down instantly from
400 V to 185 V. To regulate vo at the rated output voltage, M

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VII. EXPERIMENTAL RESULTS input voltage Vin , output voltage vo , and inductor currents.
A hardware prototype of the proposed inverter is Fig. 22(b) shows the waveforms of drain-source voltages of
fabricated and tested in standalone mode using open-loop switches S1 , S2 , S5 and S7 , respectively. Fig. 22(c) shows
control with the electrical specifications listed in Table II. the expanded waveforms of Fig. 22(b).
Although the proposed inverter can be operated properly Fig. 23 shows the same waveforms of the proposed inverter
without PWM dead-time and the risk of shoot-through current, in the boost mode when D=0.4, M=1, Vin  185V .
a small dead-time in the gate signals of S1  S4 is used in the
experiment to decrease the circulating current which occurs B. No Load Condition
when the upper and lower switches are turned-on
simultaneously. Fig. 24 shows the no load waveforms of Vin , vo , iL1 and
vDS6 during the boost mode with D=0.4, M=1, Vin  185V .
A. Resistive Load
Fig. 22 shows experimental waveforms of the proposed
inverter with resistive load during the buck operation when
D=0, M=0.78, Vin  400V . Fig. 22(a) shows the waveforms of
iL1 [10 A / div] iL2 [10 A / div]

iL1 [10 A / div] iL2 [10 A / div]

vo [200V / div]
vo [200V / div] Vin [200V / div]

Vin [200V / div]

[10 m sec/ div] [10 m sec/ div]

(a) (a)

vDS1 [200V / div]


vDS1 [220V / div]

vDS2 [200V / div]

vDS2 [220V / div]


vDS7 [200V / div]

vDS7 [220V / div]

vDS5 [200V / div]

vDS5 [220V / div]


[10 m sec/ div] [10 m sec/ div]
(b) (b)

vDS1 [220V / div]


vDS1 [200V / div]

vDS2 [200V / div]


vDS2 [220V / div]

vDS7 [220V / div]


vDS7 [200V / div]
vDS5 [200V / div]
vDS5 [220V / div]
[10  sec/ div]
[10  sec/ div]
(c) (c)
Fig. 22. Experimental results with resistive load when M=0.78, D=0 and Vin Fig. 23. Experimental results with resistive load when M=1, D=0.4 and Vin
=400 V. (a) Inductor currents, input and output voltages. (b) Drain-source =185 V. (a) Inductor currents, input and output voltages. (b) Drain-source
voltages of switches. (c) Expanded waveforms of (b). voltages of switches. (c) Expanded waveforms of (b).

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vDS6 [200V / div]


vDS5 [200V / div]

vo [200V / div] vo [200V / div] Vin [200V / div]

Vin [200V / div]

iL1 [10 A / div] io [200V / div]

[10 m sec/ div] [10 m sec/ div]

Fig. 24. Experimental results for no load conditions: M=1, D=0.4 and Vin =185 (a)
V.

vDS6 [200V / div] vDS5 [200V / div]

Vin [200V / div]


io [10 A / div] vo [200V / div] Vin [200V / div]

vo [200V / div]

iL1 [10 A / div] io [200V / div]

[0.5 m sec/ div]


[10 m sec/ div] (b)
Fig. 25. Experimental results with partially inductive load: M=1, D=0.4 and Vin
=185 V.
vDS5 [200V / div]

C. Partially Inductive Load Vin [200V / div]


vo [200V / div]
Fig. 25 shows the waveforms of Vin , vo , iL1 , vDS6 and
output current io during the boost mode for partially inductive
load ( RL  44  , L  10 mH ).
io [200V / div]
D. Dynamic Experimental Results
Fig. 26 shows the dynamic experimental results for instant
mode change when Vin  185V . Fig. 26(a) shows the results [10 m sec/ div]

when mode changes from the boost (M=1, D=0.4, Po  1.1kW ) (c)
Fig. 26. Dynamic experimental results for step mode change when Vin  185V
to buck (M=0.78, D=0, Po  200W ). Fig. 26(b) shows the
. (a) Boost to buck. (b) Expanded waveforms of (a) at the transition point. (c)
expanded waveforms of Fig. 26(a) at the transition region. Fig. Buck to boost at the peak of vo .
26(c) shows the waveforms for the worst case when mode

TABLE III. PARAMETERS OF THE CONVENTIONAL INVERTERS

Parameters TCBBI (Fig. 2) CDBBI (Fig. 6) qZSI (Fig. 4)


Boost dc-dc
Switching 25 kHz Boost dc-dc converter 25 kHz
converter 20 kHz
frequency
H-bridge VSI 25 kHz Dual-buck inverter 30 kHz
Lin 1.5 mH Lin 1.5 mH L1, L2 1mH
Inductors
Lf 1.2 mH L1a  L2b 0.5 mH Lf 1.5 mH
S5  S6 IGW40N60H3
Switches S1  S6 IGW40N60H3 S1  S4 CM100TL_24NF
S1  S4 47N60CFD
IXYS DSEI
Diodes - D1  D4 RURG3060 Din
2X61-12B

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changes instantly from the buck (M=0.78, D=0, Po  200W ) to


boost (M=1, D=0.4, Po  1.1kW ) at the peak of vo . The
experimental results in Fig. 26 confirmed that similar to the
simulation results in Fig. 21, the proposed inverter has no
noticeable distortion when the mode is changed.

E. Power Transfer Efficiency


Table III shows the parameters of the conventional inverters 10
for efficiency measurement. The TCBBI, qZSI, and boost dc-dc
converter of the CDBBI are designed with IGBTs to avoid the
reverse recovery issues and relevant loss of MOSFET body
diode. The qZSI is operated at 20 kHz. The TCBBI and boost
dc-dc converter of the CDBBI are operated at 25 kHz to keep Fig. 28. Measured efficiencies of the buck-boost inverters.
the switching loss of IGBTs lower. The proposed inverter is
designed with MOSFETs and is operated at 30 kHz.
The efficiency is measured using Yokogawa WT1600 power
meter. Fig. 27 shows the measured efficiency of the proposed
inverter at the rated and varied output power. The maximum
97.8 % and minimum 96.1 % efficiency are obtained for the
proposed inverter.
Fig. 28 shows the measured efficiencies of the four inverters
mentioned in Table I. The efficiencies of the proposed inverter
and the CDBBI are comparable and they are greater than the
efficiencies of the TCBBI and qZSI. The efficiencies could be
improved if the inverters are optimized properly. Fig. 29 shows
prototype photo of the proposed inverter.
Fig. 29. Prototype photo.

VIII. CONCLUSION
In this paper, a highly reliable and high efficiency quasi
single-stage single-phase bidirectional buck-boost inverter is
proposed. The proposed inverter takes the dual-buck structure
vDS5 [200 V / div]
at the input dc side and the switching cell structure at the ac
output side. It is immune from both short-circuit and
open-circuit problems. Therefore, PWM dead-times can be
eliminated in the proposed inverter, which results in high
quality output voltage waveforms. Moreover, it utilizes high
speed power MOSFETs along with externally selected fast
(a) recovery diodes, which decrease the switching and conduction
losses. Thus, high frequency and high efficiency operation is
realized. The operation principle and circuit analysis of the
proposed topology are presented in detail. To verify
performance of the proposed inverter, a 1.1 kW laboratory
1 prototype inverter is fabricated and experiments are performed
0.8 Buck Region for both buck and boost modes to obtain a 220 Vrms ac output
D0
voltage for wide range of input dc voltage (185 V-400 V) . The
efficiency measurement shows that the proposed inverter can
obtain maximum efficiency of 97.8 % and minimum efficiency
of 96. 1 % at 30 kHz frequency with simple PWM control.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2016.2598251, IEEE
Transactions on Power Electronics
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0885-8993 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2016.2598251, IEEE
Transactions on Power Electronics
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Hafiz Furqan Ahmed received his B.S.


in Electronics Engineering from National
University of Sciences and Technology (NUST),
Islamabad Pakistan, in 2012. He is currently
working towards his MS leading to Ph.D. degree
in the School of Energy Engineering, Kyungpook
National University, Korea. His current research
interests include high efficiency bidirectional
dc-dc converters, ZS inverters, and high reliable
ac-ac converters without commutation problem.

Juyong Kim received the M.S. and Ph.D. degrees from


Kyungpook National University in 1994 and in 2007,
respectively. He joined the KEPRI (Korea Electric
Power Corp. Research Institute) as a researcher in 1994.
His main research interests are DC distribution system
and DC microgrid. He is currently a principal researcher
at Smart Power Distribution Lab. of KEPRI.

Jintae Cho received the B.S. and M.S. degrees in


Electrical Engineering from Korea University, Seoul,
Korea, in 2006 and 2008, respectively, and he is in Ph.D
in the area of DC distribution. He is currently a senior
researcher at Smart Power Distribution Lab. of KEPRI
(Korea Electric Power Corp. Research Institute),
Daejeon, Korea. His research interests include protection,
monitoring and control of LVDC

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