TITLE:: FUNDAMENTAL DIGITAL

COURSE TITLE COURSE CODE: EECIM03

ELECTRONICS CIRCUITS
SUBJECT: INTRODUCTION TO DIGITAL TITLE: BASIC LOGIC GATES
LOGIC
TRAINING AIMS:
� Identify the basic logic gates AND, NAND, OR, NOR, NOT, EXOR, EXNOR through
drawing schematic symbols;
� Draw each of the logic gates illustrating 2 inputs (and 1 input for NOT) gates;
� Construct a truth table of operation for each of the basic logic gates;
� Locate MSI and SSI IC TTL chips containing each of the basic logic gates using
IC and ECG Manuals available;
� Locate the “Vcc” pin, Ground pin, Input pins, and output pins from a TTL IC chip
and identify what specific logic gate it provides;
� Differentiate TTL IC package from CMOS IC package;
� Enumerate safety measures in handling and working with digital TTL and CMOS
chips

Description of tasks:
A Digital Logic Gate is an electronic device that makes logical decisions based on the
different combinations of digital signals present on its inputs. A digital logic gate may
have more than one input but only has one digital output. Standard commercially
available digital logic gates are available in two basic families or forms, TTL which
stands for Transistor-Transistor Logic such as the 7400 series, and CMOS which
stands for Complementary Metal-Oxide-Silicon which is the 4000 series of chips. This
notation of TTL or CMOS refers to the logic technology used to manufacture the
integrated circuit, (IC) or a "chip" as it is more commonly called.

Generally speaking, TTL IC's use NPN (or PNP) type Bipolar Junction Transistors while
CMOS IC's use Field Effect Transistors or FET's for both their input and output
circuitry. As well as TTL and CMOS technology, simple digital logic gates can also be
made by connecting together diodes, transistors and resistors to produce RTL RTL,
Resistor-Transistor logic gates, DTL
DTL, Diode-Transistor logic gates or ECL
ECL, Emitter-
Coupled logic gates but these are less common now compared to the popularCMOS CMOS
family.

Digital Logic States

In digital logic design only two voltage levels or states are allowed. These states are
generally referred to as Logic "1" and Logic "0", High and Low, or True and False.
These two states are represented in Boolean Algebra and standard truth tables by the
binary digits of "1" and "0" respectively.

A good example of a digital state is a simple light switch as it is either "ON" or "OFF"
but not both at the same time. Then we can summarize the relationship between these

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various digital states as being:

Boolean Boolean Voltage

Algebra Logic State

Logic "1" True (T) High (H)

Logic "0" False (F) Low (L)

74xx or 74Nxx: Standard TTL - These devices are the original TTL family of logic gates
introduced in the early 70's. They have a propagation delay of about 10ns and a power
consumption of about 10mW.

74Lxx: Low Power TTL - Power consumption was improved over standard types by
increasing the number of internal resistances but at the cost of a reduction in
switching speed.

74Hxx: High Speed TTL - Switching speed was improved by reducing the number of
internal resistances. This also increased the power consumption.

74Sxx: Schottky TTL - Schottky technology is used to improve input impedance,

switching speed and power consumption (2mW) compared to the 74Lxx and 74Hxx
types.

74LSxx: Low Power Schottky TTL - Same as 74Sxx types but with increased internal
resistances to improve power consumption.

74ASxx: Advanced Schottky TTL - Improved design over 74Sxx Schottky types
optimised to increase switching speed at the expense of power consumption of about
22mW.

74ALSxx: Advanced Low Power Schottky TTL - Lower power consumption of about
1mW and higher switching speed of about 4nS compared to 74LSxx types.

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74HCxx: High Speed CMOS - CMOS technology and transistors to reduce power
consumption of less than 1uA with CMOS compatible inputs.

74HCTxx: High Speed CMOS - CMOS technology and transistors to reduce power
consumption of less than 1uA but has increased propagation delay of about 16nS due
to the TTL compatible inputs.

LOGIC GATE ANSI SYMBOL AND SWITCHING TRUTH TABLE

EQUIVALENT

AND A B Y=AB
0 0
0 1
Fig. 1a 1 0
1 1

Fig. 1b

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 A B Y=A+B
OR 0 0
0 1
1 0
1 1

Fig. 2a

NOT A Y = A
0
1

Fig. 3a The NOT gate is also called

INVERTER since its output
condition is inverse or opposite of
the condition of its input signal.

Fig. 3b shows that switch A is a

pushbutton type Normally Closed
(NC) which represents “0” or LOW
state. Pressing the button
represents “1” OR HIGH state .

Fig. 3b

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 NOR A B
0 0
0 1
1 0
Fig. 4a
1 1

While the NOR symbol resembles

that of the OR gate, a bubble is
placed after the NOR gate’s output
side. The bubble figure represents
a NOT or INVERTER function.

Fig. 4b

LOGIC GATE ANSI SYMBOL AND SWITCHING TRUTH TABLE

EQUIVALENT

NAND A B
0 0
0 1
1 0
1 1
Fig. 5a
While the NAND symbol resembles
that of the AND gate, a bubble is
placed after the AND gate’s output
side. The bubble figure represents
a NOT or INVERTER function.

Fig. 5b

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EXCLUSIVE- A B
OR
(EX-OR) 0 0
0 1
Fig. 2a 1 0
1 1

Fig. 2b

EXCLUSIVE
NOR A B
(EX-NOR)
0 0
Fig. 7a
0 1
1 0
1 1

Fig. 7b

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EXERCISE

1. Analyze the switching action of each logic symbol and complete the OUTPUT of
“Y” columns of all the truth tables.

2. After completing all data on all truth tables, write your conclusion/s for each of
basic gate’s logic function:

Note : Expected conclusions will be more or less similar to the

following responses derived:

1. The output of an AND gate is HIGH or “1” only when all input conditions are “1”
or HIGH at the same time;
2. A NOR gate will have a HIGH or “1” output when one or all input conditions are
“1”or HIGH;
3. An inverter, or NOT, gate is one that outputs the opposite state as what is input.
That is, a "low" input (0) gives a "high" output (1), and vice versa.
4. NAND implies “NOT” AND;
5. The NAND output conditions are opposite to those of the AND gate;
6. Output of the NAND gate will switch to LOW or “0” when all input conditions are
“1” or HIGH at the same time;
7. The Exclusive OR (EXOR) gate has a “1” or HIGH output when:
7.1 The input conditions are different ; and
7.2 The number of “1” input conditions are of ODD value (example: 1 HIGH
input, 3 HIGH inputs, 5 HIGH inputs…. and so on);
8. The Exclusive NOR (EXNOR) gate has a “1” or HIGH output when:
8.1 Either all input conditions are the same; and/or
8.2 The number of “1” or HIGH input conditions are of EVEN value (example: 0
or no HIGH inputs, 2 HIGH inputs, 4 HIGH inputs,… and so on);

IC PACKAGES AND DEVICES FOR IMPLEMENTING LOGIC CIRCUITS:

While there are varieties of IC packages that are available for implementing logic gates
and circuits, we will focus on using two groups of IC packages- The Transistor-
Transistor-Logic (TTL) and the Complementary Metal-Oxide-Semiconductor (simply
CMOS). Moreover, we will emphasize on making use more often, the TTL family of
logic ICs since this category are more durable and rugged than the CMOS type.

For this lesson, the 7400 series of logic gates are the most available. The following
presentation shows the list of TTL IC part number for each logic gate. Also presented
are the equivalent CMOS IC packages for each logic gate:

Page 7
 LOGIC GATE TTL IC CMOS IC DESCRIPTION OF IC PART
PART PART
NUMBER NUMBER
NAND 7400 4011 quad 2-input NAND gate
NOR 7402 4001 quad 2-input NOR gate
NOT 7404 4069 hex inverter
AND 7408 4081 quad 2-input AND gate
OR 7432 4071 quad 2-input OR gate
Exclusive OR 7486 4070 quad 2-input XOR gate
Quad 2-Input Exclusive-NOR Gate
Exclusive NOR 74266 4077
with Open-Collector Outputs

SAMPLE TASK : Implement the Fig. 8 below:

Figure 8.

Figure 7. Pin-out diagram of 74266

Exclusive NOR logic gate.

1. It will be necessary to code each of the pins accordingly in order to avoid

confusion in which of the gates and corresponding pins are to be used.
2. Naming each of the input and output pins may be done for example A,B,C,D…
for inputs and Q, Y, Z for output. Just make sure to label the pins that will not
confuse you later.
3. For 7400 TTL series, pin 14 will be connected to + 5Vcc
5Vcc, while pin 7 will be
ground or common (Gnd, COM);
4. For 4000 CMOS series, pin 14 will be connected to +6 – 18 VDD while pin 7
will be ground or common (Vss);

Page 8
EXERCISE: Label each of the pins accordingly. Be guided by the hint
provided in No. 2 given above.

Page 9
 TITLE:: FUNDAMENTAL DIGITAL
COURSE TITLE COURSE CODE: EECIM 03
ELECTRONICS CIRCUITS
SUBJECT: INTRODUCTION TO DIGITAL TITLE: IMPLEMENTING LOGIC GATE
LOGIC OPERATIONS
TRAINING AIMS:

� Implement operation of the AOI (AND, OR, INVERTER) logic gates;

� Construct logic circuits using the appropriate available trainer boards and
devices;
� Make the truth table for each logic gate operation;
� Verify the output conditions of each logic gate, given specific input conditions
through switching actions;
� Handle TTL/CMOS IC packages with care, following the safety precautions
prescribed;
� Describe the logic function of each logic gate as verified from the activity;
� Design and implement the needed logic circuit to satisfy a specific
requirement;

DESCRIPTION OF TASK:

� The manufacturer datasheet contains a logic gate’s general description,

connection diagram, and function table.
� Integrated circuits are categorized by their underlying circuitry, scale of
integration, and packaging style.
� Transistor-Transistor Logic (TTL) gates are available in a series of sub-families,
each having their own advantages and disadvantages related to speed and
power.
� Logic gates are depicted by their schematic symbol, logic expression, and truth
table.
� Combinational logic designs implemented with AND gates, OR gates, and
INVERTER gates are referred to as AOI designs.
� The flip-flop is the fundamental building block of sequential logic.

Page 10
SAMPLE EXERCISE:

Verifying the logic operation of an AND logic is done by making the circuit below:

This method is the “discrete” where the components

are obtained separately. This is available on the
MODEL : EFT-ETX-2 Electronic Trainer. On the IDL-
800 Digital Trainer, all components are integrated in
one base module. Refer to the respective user manual
of these trainers for detailed explanation on the use.

SOLUTION TO SAMPLE EXERCISE

Figure 2. Recommended wiring method for the

sample circuit.

NOTES ON SAFETY:
• Power OFF the trainer board during circuit construction
• Check and re-check connections before turning ON power to the device;
• Wear anti- static wrist strap when handling IC packages.
• Avoid output-to-output connections as previously discussed.

Page 11
WORKSHEET

� Construct the circuit for the AND gate as demonstrated.

� POWER ON. Verify the output of the AND gate while performing the switching
action shown in the truth table below. Complete the TRUTH TABLE.

A B Q
0 0
0 1
1 0 Write down Boolean AND logic expression
1 1

� Verify the logic operations of the remaining logic gate - OR, NOT, NAND,
NOR, EXOR, and EXNOR gates respectively, doing the same method done in
verifying AND gate operation;

� Complete the TABLES below and write down the equivalent logic expressions.

A B Q
0 0
0 1
1 0 Write down Boolean OR logic expression
1 1

OR Gate Truth Table

A B Q
0 0
0 1
1 0 Write down Boolean NAND logic expression
1 1

NAND Gate Truth Table

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 A B Q
0 0
0 1
1 0 Write down Boolean NOR logic expression
1 1

NOR Gate Truth Table

A B Q
0 0
0 1
1 0 Write down Boolean EXOR logic expression
1 1

EXOR Gate Truth Table

A B Q
0 0
0 1
1 0 Write down Boolean EXNOR logic
expression
1 1

EXNOR Gate Truth Table

A Q
0
1
Write down Boolean NOT logic expression
Truth Table
NOT Gate

Page 13
WORKSHEET
2 way switching means having two or more switches in different locations to
control one lamp. They are wired so that operation of either switch will control the
light. This arrangement is often found in stairways, with one switch upstairs and one
switch downstairs or in long hallways with a switch at either end.

Figure 3. Electrical diagram of a common two-way

switching control system. Any of the switches can
turn ON or turn OFF the lamp independently.

� Construct a logic circuit to show the operation of the two-way electrical switch
control system, using one logic gate. Show the schematic diagram of the
circuit design.

� Test the circuit and verify that it functions as specified.

Page 14
� Explain the difference between the following gates:

OR and NOR __________________________________________________

____________________________________________________________

____________________________________________________________

AND and NAND________________________________________________

____________________________________________________________

____________________________________________________________

EXOR and EXNOR ______________________________________________

____________________________________________________________

____________________________________________________________

� Write down one conclusion for each of the following logic gate functions:

LOGIC GATE CONCLUSIONS

AND

OR

NOT

NAND

NOR

EXOR

EXNOR

Page 15
 TITLE:: FUNDAMENTAL DIGITAL
COURSE TITLE COURSE CODE: EECIM 03
ELECTRONICS CIRCUITS
SUBJECT: COMBINATIONAL LOGIC TITLE: INTRODUCTION TO AND,
CIRCUITS OR, INVERTER COMBINATIONAL
LOGIC CIRCUITS
TRAINING AIMS:

� Convert numbers between the binary and decimal number systems.

� Translate design specifications into truth tables.
� Extract un-simplified logic expressions from truth tables.
� Construct truth tables from logic expressions.
� Use the rules and laws of Boolean algebra, including De Morgan’s Theorem to
simplify logic expressions.
� Analyze AOI (AND/OR/Invert) combinational logic circuits to determine their
equivalent logic expressions and truth tables.
� Design combinational logic circuits using AOI logic gates.
� Translate a set of design specifications into a functional AOI combinational
logic circuit following a formal design process.

DESCRIPTION OF TASK:

� An understanding of the binary number system and its relationship to the

decimal number system is essential in the combinational logic design process.
� The first step in designing a combinational logic circuit is to translate a set of
design specifications into a truth table.
� A truth table describes the behavior of a combinational logic design by listing
all possible input combinations and the desired output for each.
� Logic expressions can be derived from a given truth table; likewise, a truth
table can be constructed from a given logic expression.
� All logic expressions can be expressed in one of two forms: sum-of-products
(SOP) or products of sum (POS).
� All logic expressions, whether simplified or not, can be implemented using
AND, OR, & Inverter Gates.
� There is a formal design process for translating a set of design specifications
into a functional combinational logic circuit.

EXERCISE:

The available TTL IC packages that are available in your workshop are those having
logic gates, each having 2 inputs and one output. The circuit to be constructed is
that of an AND logic function that requires three inputs labeled E, F, G and output
Q. Two AND gates are needed to implement this exercise.

Page 16
WORKSHEET

� Draw the schematic diagram of the circuit mentioned, label each part
accordingly and write down the corresponding Boolean algebraic or logic
expression as part of the label of the circuit output.

Schematic Diagram

� Draw the wiring diagram to be implemented on the IDL-800 Digital Trainer,

also labeling the parts and connections to be made;

Page 17
 Wiring Diagram

� Implement the wiring diagram made on the IDL-800 Digital Trainer.

NOTES ON SAFETY:
• Power OFF the trainer board during circuit construction
• Check and re-check connections before turning ON power to the device;
• Wear anti- static wrist strap when handling IC packages.
• Avoid output-to-output connections as previously discussed.

� Check the circuit operation by implementing the switching conditions of the

inputs specified on the truth table. Write down the corresponding output
condition for each input combination.

TRUTH TABLE
E F G Q
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

� Did the truth table reveal that the logic function of the circuit is the same with
that of a two-inputs AND logic gate? ___________ (write YES or NO)

� Draw two methods of creating an OR gate with 4-inputs using dual input gate
of the same kind. Write down the Boolean or Logic expressions of the two
circuits.

Page 18
 TITLE:: FUNDAMENTAL DIGITAL
COURSE TITLE COURSE CODE: EECIM 03
ELECTRONICS CIRCUITS
SUBJECT: SEQUENTIAL LOGIC CIRCUITS TITLE: FLIP FLOPS
TRAINING AIMS:

� To construct an RS flip-flop using NOR gates

� To observe the action of a D flip-flop
� To observe the action of a T flip-flop
� To observe the action of a JK flip-flop

DESCRIPTION OF TASKS:

� Completion of the worksheets

� Defining the required components
� Drawing the layout, wiring and electrical circuit diagrams
� Labeling the connections
� Numbering the components in the circuit assembly
� Drawing the schematic symbols and excitation tables for the D and J/K flip-
flops.
� Describing the function of the D and J/K flip-flops.
� Describing the function of, and differences between, level sensitive and edge
sensitive triggers.
� Describing the function of, and differences between, active high and active low
signals.
� Describe the function of, and differences between, a flip-flop’s synchronous
and asynchronous inputs.
� Compiling the components lists
� Removing circuit connections and securing tools and equipment

EXERCISE

� The flip-flop and transparent latch are logic devices that have the capability to
store data and can act as a memory device.
� Flip-flops and transparent latches have both synchronous and asynchronous
inputs.
� Flip-flops can be used to design single event detection circuits, data
synchronizers, shift registers, and frequency dividers.

Page 19
WORKSHEET

� RS Latch

1. Prepare the equipment on your bench. Connect the NOR latch of Fig. 45-13.
2. Turn on the power. Set the R and S switches to the input combinations of
Table 45-7. Follow the order shown; record the Q and Q outputs for each
input.

Figure a:45-13. Experimental RS latch.

Table 45-7. RS latch

Page 20
� D Latch

1. Turn off the power. Connect the CLOCKED D latch of Fig. 45-14. Connect a
Square-wave generator to the CLK input. Set the generator for 5 V at1kHz.
2. Turn on the power. Set the D switch to the low input. Measure and record
Q and Qin Table 45-8.
3. Repeat the preceding step for the D switch at the high input.
4. Remove the square-wave generator and set this input high. Observe that
switching the D input does not cause the output to switch.

Page 21
� Edge-Triggered D Flip-Flop

1. Turn off the power. Connect the circuit of Fig. 45-15. Use components
available on the module.

Page 22
 2. Turn on the power. Close S1 and ground the CLK input. Open S2 and close
S3. Note that the flip-flop is in the reset state. Open S3, and the Q output
should remain low (green LED on).
3. Close S2 (preset), and the output Q should go to the set condition (red
LED
on). Open S2, and the flip-flop remains set.
4. Close Sl (low input). Remove the ground to CLK and replace it with the
squarewave generator set as in step 3. Record the Q output in Table 45-9.
5. Open S1 (high input). Record the Q output in Table 45-9.

� JKFlip-Flop

1. Turn off the power. Connect the circuit of Fig. 45-16. With a 7476, pin 5
connects to +5 V and pin 13 is ground. Set J and K inputs low. Connect
the square-wave generator to the CLK input and set it as in step 3.
2. Turn on the power. Close S2 and open S4. Note how this presets the Q
output. Open S2 and close S4, placing the J and K inputs into the reset
condition.
3. Open S2 and S4. Q should not change. If this is what happens, write "NC"
in Table 45-10.
4. Set up the other J and K inputs listed in Table 45-10. Record the Q outputs.
(Record "Toggle" for the last entry if it is working correctly.)
5. Leave both J and K high. Measure and calculate the frequency of the Q
output and record the value here:

f = ____________________

Page 23
� QUESTION

1. Describe what the Q output did when you changed the R and S switches.
2. Describe what a D latch does.
3. Is the D flip-flop positive- or negative-edge-triggered?
4. Describe what the D flip-flop of Fig. 45-15 did.
5. Are the PRESET and CLEAR active-low or active-high?
6. Use the data of Table 45-10 to describe the action of a JK flip-flop.

Page 24
 TITLE:: FUNDAMENTAL DIGITAL
COURSE TITLE COURSE CODE: EECIM 03
ELECTRONICS CIRCUITS
SUBJECT: SEQUENTIAL LOGIC CIRCUITS TITLE: DIGITAL COUNTER CIRCUITS
TRAINING AIMS:

� Know the advantages and disadvantage of counters designed using the

asynchronous counter method.
� Be able to describe the ripple effect of an asynchronous counter.
� Be able to analyze and design up, down and modulus asynchronous counters
using discrete D and J/K flip-flops.
� Be able to analyze and design up, down and modulus asynchronous counters
using medium scale integrated (MSI) circuit counters.
� To examine binary counting circuits
� To observe ring and Johnson counter operation
� Know the advantages and disadvantage of counters designed using the
synchronous counter method.
� Be able to analyze and design up, down and modulus synchronous counters
using discrete D and J/K flip-flops.
� Be able to analyze and design up, down and modulus synchronous counters
using medium scale integrated (MSI) circuit counters.

DESCRIPTION OF TASKS:

� Completion of the worksheets

� Defining the required components
� Drawing the layout, wiring and electrical circuit diagrams
� Labeling the connections
� Numbering the components in the circuit assembly
� Drawing the schematic symbols and excitation tables for the counter circuits.
� Describing the function of the asynchronous and synchronous counters.
� Describing the function of, and differences between, level sensitive and edge
sensitive triggers.
� Describing the function of, and differences between, active high and active low
signals.
� Describe the differences between, a flip-flop’s synchronous and asynchronous
inputs.
� Compiling the components lists
� Removing circuit connections and securing tools and equipment

Page 25
EXERCISE
� Asynchronous counters, also called ripple counters, are characterized by an
external signal clocking the first flip-flop. All subsequent flip-flips are clocked
by the output of the previous flip-flop.
� Asynchronous counters can be implemented using small scale integrated (SSI)
and medium scale integrated (MSI) logic gates.
� Asynchronous counters can be implemented with either D or J/K flip-flops.
� Up counters, down counters, and modulus counters all can be implemented
using the asynchronous counter method.
� Synchronous counters, also called parallel counters, are characterized by an
external signal clocking all flip-flops simultaneously.
� Synchronous counters can be implemented using small scale integrated (SSI)
and medium scale integrated (MSI) logic gates.
� Synchronous counters can be implemented with either D or J/K flip-flops
� Up counters, down counters, and modulus counters all can be implemented
using the synchronous counter method.

WORKSHEET

� Up Counter

1. Prepare the equipment on your bench. Construct the binary counter of Fig.
46-8.
2. Turn on the power. Close Sl and S2. Apply a 20 -Hz 5 -V square wave to
the CLK input. What is the state of the counter at this time?

Figure 46-8. Binary up counter

Page 26
 3. Open S2. Explain why the output does not change.
4. Open Sl. What is the count sequence of this counter? Does it count up or
down?
5. Close Sl and S2. Move the clock inputs of each flip-flop except FF0 from the
Q outputs to the Qoutputs. Be careful to leave the 1-kΩ resistors and LEDs
connected to the Q outputs.
6. Open Sl and S2. Is the counter counting up or down? What is the modulo
number for this counter?

� Down Counter

1. Modify the Binary UP counter shown in Figure 46-8 so that the circuit will
function as down-counter. Draw the diagram of your design.

Page 27
 2. Test the circuit and observe what happens. Does the circuit show down-
counting? _______ (write YES or NO). Explain your answer.

_________________________________________________________

_________________________________________________________

_________________________________________________________

_________________________________________________________

� Ring Counter

1. Turn off the power. Construct the ring counter of Fig. 46-9.
Apply the 20Hz 5 –V square wave to the CLK input.
2. Turn on the power. Close Sl. What is the state of the outputs of the counter?
3. Open S1. Draw a timing diagram for six clock cycles. What is the modulo
number for this counter? What would happen to the operation of the circuit if
the reset of FF0 were connected to the start input instead of the preset?
Perform this test and verify your answer.
4. Close S1. Switch the Q and Q connections of FF3. Keep the 1-kΩ resistor and
LED connected to the Q output. Remove the +5 V to the reset of FF0. Move
the start input to the preset of FF0 to its reset input and connect the preset
to +5 V What is the state of the outputs of the counter?
5. Open Sl. Draw the timing diagram for 10 clock cycles. What is the name and
modulo number of this counter?
6. Turn off the power. Remove the jumpers and module from the base station.
Return the equipment to their place and clean your work area.

Page 28
 Figure 46-9. Ring counter.

� QUESTION

1. Explain the output differences between a binary or ripple up counter and a

ring counter.
2. How does a Johnson counter differ from a ring counter?
3. List an advantage for each type of counter used in this worksheet.
4. List a disadvantage for each type of counter in this worksheet.

Page 29
COURSE TITLE: FUNDAMENTAL DIGITAL COURSE CODE: EECIM 03
ELECTRONICS CIRCUITS
SUBJECT: COMBINATIONAL LOGIC TITLE: ADDER-SUBTRACTOR
CIRCUITS LOGIC CIRCUITS
TRAINING AIMS:

� Build and verify half-adder circuits using AOI, EXOR and EXNOR
combinational logic gates;
� Build and verify the operation of full-adder circuits using EXOR and EXNOR
AOI combinational logic gates;
� Build and verify subtractor circuits using AOI combinational logic gates;
� Modify adder circuits according to specifications;
� Modify subtractor according to specifications;
� Verify and troubleshoot problems encountered by adder and subtractor
circuits;

DESCRIPTION OF TASKS:

� Completion of the worksheets

� Defining the required components
� Drawing the layout, wiring and electrical circuit diagrams
� Labeling the connections
� Numbering the components in the circuit assembly
� Familiarizing with the logic operation of Half and Full Adder and Subtractors
� Carrying out the practical implementation of the half and full adder and
subtractor circuits
� Compiling the components lists
� Removing circuit connections and securing tools and equipment

EXERCISE 1:

With the help of half adder, we can design circuits that are capable of performing
simple addition with the help of logic gates. Let us first take a look at the addition
of single bits.
0+0 = 0
0+1 = 1
1+0 = 1
1+1 = 10

These are the least possible single-bit combinations. But the result for 1+1 is 10.
Though this problem can be solved with the help of an EXOR Gate, if you do care
about the output, the sum result must be re-written as a 2-bit output.

Page 30
Thus the above equations can be written as
0+0 = 00
0+1 = 01
1+0 = 01
1+1 = 10

Here the output ‘1’of ‘10’ becomes the carry-out. The result is shown in a truth-
table below. ‘SUM’ is the normal output and ‘CARRY’ is the carry-out.
INPUTS OUTPUTS
A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

WORKSHEET 1.1

� Draw the schematic diagram of the half-adder circuit mentioned, label

each part accordingly and write down the corresponding Boolean algebraic
or logic expression as part of the label of the circuit output. Make the
following label specifications:

Inputs : A B
Carry Out : CO
Sum : Sum

Schematic Diagram

Page 31
 � Implement the circuit drawn on the trainer provided for.

NOTES ON SAFETY:
• Power OFF the trainer board during circuit construction
• Check and re-check connections before turning ON power to the device;
• Wear anti- static wrist strap when handling IC packages.
• Avoid output-to-output connections as previously discussed.

� Check the circuit operation by implementing the switching conditions of the

inputs specified on the truth table. Write down the corresponding output
condition for each input combination.

TRUTH TABLE
A B CO SUM
0 0
0 0
0 1
0 1

� At what input conditions does the CARRY IN output a “1” or HIGH?

� What will be the output conditions of CO and Sum if A = 0, B = 1?

� Is it possible to continue with adding three binary bits using the same
circuit? Explain your answer.

.....................................................................................................................................................................
......................................................................................................................................................................
......................................................................................................................................................................

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EXERCISE 2:

This type of adder is a little more difficult to implement than a half-adder. The
main difference between a half-adder and a full-adder is that the full-adder has
three inputs and two outputs. The first two inputs are A and B and the third input
is an input carry designated as Carry IN. When a full adder logic is designed we
will be able to string eight of them together to create a byte-wide adder and
cascade the carry bit from one adder to the next. The output carry is designated
as Carry OUT and the normal output is designated as S. Take a look at the truth-
table.

INPUTS OUTPUTS
A B CIN COUT S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

From the above truth-table, the full adder logic can be implemented. We can see
that the output S is an EXOR between the input A and the half-adder SUM output
with B and CIN inputs. We must also note that the COUT will only be true if any of
the two inputs out of the three are HIGH.
Thus, we can implement a full adder circuit with the help of two half adder
circuits. The first will half adder will be used to add A and B to produce a partial
Sum. The second half adder logic can be used to add Carry IN to the Sum
produced by the first half adder to get the final S output. If any of the half adder
logic produces a carry, there will be an output carry. Thus, Carry OUT will be an
OR function of the half-adder Carry outputs.

Page 33
WORKSHEET 2.1

� Draw the schematic diagram of the half-adder circuit mentioned, label

each part accordingly and write down the corresponding Boolean algebraic
or logic expression as part of the label of the circuit output. Label the inputs,
carry in, carry out and sum as shown in the exercise discussion.

Schematic Diagram

� Test the circuit by doing the switching sequence shown on the truth table of
this circuit. Check your circuit connection when the outputs do not
correspond to those indicated on the truth table.

� Does the circuit implement a “single” digit or “two” digits full- adder?

--------------------------------------------------------------------------------

Page 34
WORKSHEET 2.2

The block diagram shows how Multi-Bit Addition using Full Adders. The objective of this worksheet is
to build the equivalent combinational logic circuit to implement the logic function as shown in the
block diagram.

� How many valid inputs are present on this circuit?

----------------------------------------------------

� Is the circuit capable of adding more than two digit binary number? (write yes or no)
____________ If the answer yes, how many digits is this adder capable of handling? _______

� Explain why this circuit is also called “parallel adder”

Page 35
� Draw the corresponding diagram of the adder, using combinational logic
gates. Be sure to label each parts and components accordingly. Use the
block diagram as reference.

Page 36
� Make a truth table of the circuit.

� Implement the circuit on the trainer device as shown in the diagram.

� Test the circuit operation and verify the output using the truth table as
reference.

Page 37
EXERCISE 3:

Subtraction is the other basic function of arithmetic operations of information-

processing tasks of digital computers.

Subtraction of two binary digits also consists of four possible elementary

operations which are

0 – 0 = 0
0 – 1 = 1 with borrow of 1
1 – 0 = 1
1 – 1 = 0

The first, third and fourth operations produce a subtraction of one digit, but the
second operation produces a difference bit as well as a borrow bit.

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WORKSHEET 3.1

In a subtractor, the borrow bit is used for subtraction of the next higher bit. A
combinational circuit that performs the subtraction of two bits is called half
subtractor. The half subtractor to be constructed will have two inputs and two
outputs. Let one input be called Min (Minuend) and the other input as Sub
(Subtrahend). Let one output be called Dif (Difference) and other output as Brrw
(Borrow). The truth tables of the functions is as follows:

The Boolean logic expressions for both outputs can be written as:

Dif = X’ Y and

Brrw = X’ Y

� Make the correct schematic diagram of the half- subtractor being described
by the truth table and Boolean expressions; label each part accordingly.

Page 39
 TITLE:: FUNDAMENTAL DIGITAL
COURSE TITLE COURSE CODE: EECIM 03
ELECTRONICS CIRCUITS
SUBJECT: SEQUENTIAL LOGIC CIRCUITS TITLE: DIGITAL COUNTER CIRCUITS

TRAINING AIMS:

� Be able to analyze and design shift registers.

� To examine binary counting circuits
� To observe shift register operation
� To implement the shift register using flip flop and verifying the function of the
universal shift register (74194 chip).

DESCRIPTION OF TASKS:

� Completion of the worksheets

� Defining the required components
� Drawing the layout, wiring and electrical circuit diagrams
� Labeling the connections
� Numbering the components in the circuit assembly
� Drawing the schematic symbols and excitation tables for the shift register
circuits.
� Describing the function of the shift registers.
� Describing the function of, and differences between, level sensitive and edge
sensitive triggers.
� Describing the function of, and differences between, active high and active low
signals.
� Compiling the components lists
� Removing circuit connections and securing tools and equipment

EXERCISE

Shift register is a type of sequential logic circuit that is used mainly for storage of
digital data. It is a group of flip-flops connected in a chain so that the output from
one flip-flop becomes the input of the next flip-flop. All the flip-flops are driven by a
common clock, and all are set or reset simultaneously.

The basic types of shift registers are Serial In-Serial Out, Serial In-Parallel Out,
Parallel In-Serial Out, Parallel In-Parallel Out and bidirectional shift registers.

In these exercises the focus will be on implementing Serial In-Serial Out and
bidirectional shift registers.

Page 40
WORKSHEET

� Simple Shift Register

A simple 4-bit shift register can be constructed using four D flip-flops

(TTL – IC 74175), as shown below. The register is first cleared, forcing all four
outputs to be zero. The input data is then applied sequentially to the D input
of the first flip-flop on the left (FF0). With each clock pulse, one bit is
transmitted from left to right.

1. Collect all IC chips necessary to build the circuit from the IC drawers.
2. Bring some connection wires with varying lengths.
3. Derive the wiring diagram for this shown circuit.
4. Insure that the power switch of the IC trainer is turned off.
5. Plug the IC chips into the proper sockets.
6. Connect the voltage supply and ground lines to the chips.
7. Use the wires to connect the outputs of one IC to the input of another ICs
according to the derived wiring diagram, try to work from left to right.
8. Once all connections have been done, turn on the power switch of the IC
trainer .
9. Clear the register by applying a clear pulse.
10. Insert sequentially a digital data (bit by bit) to the serial input, apply a
clock pulse for each entry and observe the shift process from left to right.
11. After finishing the experiment, turn off the power switch, disconnect the
wires and take out all of the IC chips from the trainer.

Page 41
� Bidirectional Shift Register with Parallel Load

A register capable of shifting in both directions is called bidirectional; 4-bit

shift register can be constructed using D flip-flops as shown below. Each stage
consists of a D-flip-flop multiplexer. The two selection S1 and S0 select one
the multiplexer data inputs for the D flip-flop. The selection lines control the
mode of operation of the register according to the supplemental mode select
below.

The above logic circuit is enclosed in one chip (74194). The next step is to
verify the operation of this circuit using the 74194 chip according to the mode
select table.

Page 42
 1. Derive the wiring diagram for this circuit.
2. Insure that the power switch of the IC trainer is turned off.
3. Plug every IC chip into the proper socket.
4. Connect all IC's pins required for verifying the given function table.
5. Once all connections have been done, turn on the power switch of the IC
trainer.
6. According to the function table apply the four modes of the universal shift
register and verify the correct functioning of the chip.
7. After finishing the experiment, turn off the power switch, disconnect the
wires, take out all IC chips from the trainer, put back everything you have
used, close IC trainer and clean your table.

� Questions:

1. What is the difference between serial and parallel transfer?

2. Suppose we have a simple 4-bit shift register, and its content is initially
1001.
The register is shifted six times to the right, and the serial input has the
data
11010. What is the content of the register after each shift?
3. Draw a block diagram using two 74194 chips to produce an 8-bit universal
shift register.

Page 43
 TITLE:: FUNDAMENTAL DIGITAL
COURSE TITLE COURSE CODE: EECIM 03
ELECTRONICS CIRCUITS
SUBJECT: SEQUENTIAL LOGIC CIRCUITS TITLE: 555 TIMER CIRCUITS
TRAINING AIMS:

� To measure the frequency and duty cycle of an astable 555 timer

� To measure the pulse width out of a monostable 555 timer
� To examine the signal out of a voltage-controlled oscillator
� To build a sawtooth generator using a 555 timer

DESCRIPTION OF TASKS:

� Completion of the worksheets

� Defining the required components
� Drawing the layout, wiring and electrical circuit diagrams
� Labeling the connections
� Numbering the components in the circuit assembly
� Familiarizing with the logic operation of 555 Timer
� Carrying out the practical implementation of the 555 Timer operation
� Compiling the components lists
� Removing circuit connections and securing tools and equipment

EXERCISE

� A high set (S) input sets the output of an RS flip-flop to the high state. A
high reset (R) input resets the output to the low state.
� In a 555 timer the non-inverting input of the upper op amp is called the
threshold voltage; the inverting input is the control voltage.
� When the threshold voltage exceeds the control voltage, the RS flip-flop is
set. This saturates the discharge transistor.
� The inverting input of the lower op amp in a 555 is called the trigger. When
trigger voltage is less than + VCC/3, the RS flip-flop is reset. This cuts off
the discharge transistor.
� The 555 timer can be connected for astable or monostable operation.
� Normally, the control voltage of a 555 timer equals +2VCC/3 because of the
internal voltage divider. In VCO applications, however, an external voltage is
applied to the control pin to override the voltage from the internal voltage
divider.
� By using a PNP current source, the 555 timer can produce linear ramps.

Page 44
555 Timer Block Diagram

Monostable 555 Timer

Page 45
WORKSHEET

� Astable 555 Timer

1. Prepare the equipment on your bench. Calculate the frequency and duty
cycle in Fig. 41-10 for the resistances listed in Table 41-1. Record the
results under fcalc and Dcalc.
2. Connect the circuit of Fig. 41-10 with RA = 10kΩ and RB = 100 Ω. Use
Fig. 41-14 as guidance.
3. Turn on the power. Measure W and T. Work out the frequency and duty
factor.
4. Record under fmeas and Dcalc in Table 41-1.
5. Look at the voltage across the capacitor (pin 6). You should see an
exponentially rising and falling wave between 5 and 10 V.
6. Repeat steps 2 through 4 for the other resistances of Table 41-1.

Figure 41-10.

Page 46
� Voltage-Controlled Oscillator

6. Turn off the power. Connect the VCO of Fig. 41-11.

7. Turn on the power. Look at the output with an oscilloscope.
8. Vary the 1-kΩ potentiometer and notice what happens. Record the
minimum and maximum frequencies here:

fmin = __________________

fmax = __________________

Fig. 41-11.
� Monostable 555 Timer

9. Figure 41-12 shows a Schmitt trigger driving a monostable 555 timer.

Calculate the pulse width for each R listed in Table 41-2. Record the
results under Wcalc.
10. Turn off the power. Connect the circuit of Fig. 41-12 with an R of 33 kΩ.
11. Turn on the power. Look at the output of the Schmitt trigger (pin 6 of the
741C).
12. Set the frequency of the sine-wave input to 1 kHz. Adjust the sine-wave
level until you get a Schmitt-trigger output with a duty cycle of
approximately 90 percent.
13. Look at the output of the 555 timer. Measure the pulse width. Record this
value under Wmeas in Table 41-2.
14. Repeat steps 10 to 12 for the remaining R values of Table 41-2.

Page 47
 Fig 41-12.

� Sawtooth Generator

14. Turn off the power. Calculate the charging current in Fig. 41-13 for each
value of R shown in Table 41-3. Record the values.
15. Calculate the slope of capacitor voltage in volts per millisecond. Record
under Scalc in Table 41-3.
16. Connect the circuit of Fig. 41-13 with an R of 10 kΩ. This is almost the
same as Fig. 41-12 except for the PNP current source. Use Fig. 41-15 as
guidance.
17. Set the ac generator to 1 kHz. Adjust the level to get a duty cycle of
approximately 90 percent out of the Schmitt trigger.
18. Look at the output voltage; it should be a sawtooth. Measure the ramp
voltage and time. Then work out the slope in voltages per millisecond.
Record the value under Smeas in Table 41-3.
19. Repeat steps 16 through 18 for the remaining values of R in Table 41-3.

Page 48
 Figure 41-13.

Table 41-2. Sawtooth operation

※ QUESTION

1. How does ratio RA/RB affect the duty cycle of an astable 555 timer?
2. What effect does increasing the timing capacitor have on the frequency out
of an astable 555 timer?
3. How much ac voltage is there at pin 5 in Fig. 41-12? How much dc voltage is
there?
4. What happens to the width of the output if the timing resistor is decreased?
5. What is the output frequency in Fig. 41-13?
6. What effect does R have on the sawtooth?

Page 49