J Comput Electron
DOI 10.1007/s10825-017-1083-7
Analytical model of hot carrier degradation in uniaxial strained
triple-gate FinFET for circuit simulation
S. R. Sriram1 · B. Bindu1
© Springer Science+Business Media, LLC 2017
Abstract The triple-gate (TG) SOI FinFET has well sup-
pressed short-channel effects compared to planar MOSFET
due to increased gate voltage controllability. However, the
hot carrier injection (HCI) is a serious reliability issue for
nanoscale FinFET and this should be taken care for reli-
able circuit design. The introduction of uniaxial strain in
the channel of FinFET to enhance the performance further
limits the reliable design of VLSI circuits. Hence, there is
a great need to capture these device-level variations in cir-
cuits through physics-based models. In this paper, one such
analytical model of hot carrier (HC) degradation in uniaxial
strained TG FinFET based on reaction–diffusion mechanism
is developed, considering various geometrical aspects of the
device, for the first time. The developed model is validated
using experimentally calibrated Sentaurus TCAD simulation
results. The results show that the strain in the channel worsens
the degradation of threshold voltage due to HCI. The devel-
oped model is integrated in Cadence circuit simulator, and
the impact of HC degradation in strained TG FinFET-based
CMOS NAND logic circuit is analyzed.
Keywords Hot carrier degradation · Impact ionization ·
Reliability · Triple-gate FinFET · Threshold voltage model
The authors would like to thank Department of Science and
Technology (DST), Govt. of India, for its financial assistance (Grant
Number SERB/F/8492/2015-16) in carrying out these research
activities.
B B. Bindu
binduboby@gmail.com
S. R. Sriram
srsriramsrs@gmail.com
1 School of Electronics Engineering, VIT University – Chennai
Campus, Chennai, India
1 Introduction
The scaling of conventional bulk MOSFET to achieve better
performance in terms of speed and packing density leads to
various short-channel effects (SCE). The 3-D MOSFET like
FinFET provides better gate voltage controllability over the
channel and thus reduces SCE [1]. However, the nanoscale
FinFETs suffer from various reliability issues such as bias
temperature instability [2–5] and hot carrier injection [6–
8], similar to the planar MOSFET. The introduction of
uniaxial/biaxial strain in the channel to enhance device per-
formance further limited the hot carrier reliability due to
narrowing of bandgap and increased impact ionization rate
[8]. Hence, further scaling beyond nanoscale regime of FETs
can be sustained only through the reliable design of the VLSI
circuits. Hot carrier injection [6–8] plays a major role in hin-
dering the design of circuits with higher performance over the
past few decades. The scaling of channel length to enhance
the drive current without proper scaling of supply voltage
increases the lateral electric field in the channel. In the pres-
ence of high lateral electric field, the channel hot carriers with
large kinetic energy are generated. These highly energized
electrons can tunnel into the gate oxide, while the holes are
injected into the substrate. Few of the injected electrons get
trapped in the Si/SiO2 interface. The interface states caused
by these hot carriers degrade the MOSFET key character-
istics such as the threshold voltage VTH and drain current
IDS with respect to time, thereby affecting the circuit perfor-
mance causing failure of the circuits within a short period.
There is a clear need of analytical model of hot carrier
(HC) degradation in the FinFET devices for the proper esti-
mation of circuit failure and reliable VLSI circuit design.
The modeling of this hot carrier injection (i.e., gate cur-
rent and substrate current) based on lucky electron model
[9,10] was followed traditionally. The degradation due to
123

the trapping of electrons in the oxide interface depends on
the applied stress voltages VGS and VDS and increases contin-
uously with respect to time. The generation of interface traps
due to HC stress can be explained by the reaction diffusion
(RD) mechanism, and various extended hot carrier degrada-
tion models of NMOS transistors based on RD theory have
been developed [11–13]. It has been shown that the consider-
ation of various geometrical dependence of RD model for HC
degradation resolves the inconsistency of RD model with the
measurements [12]. An analytical HC degradation model of
DG FinFET [14] based on the reaction diffusion model [15–
19] which captures the various geometrical aspects of the
DG FinFET is reported. In [14], the DG FinFET HC model
is modified to TG FinFET by introducing a fitting parameter
for the sake of simplicity. The fitting parameter is used to
consider the modulation of pinch-off region length L P by the
top gate of TG FinFET, and diffusion of hydrogen atom into
the top gate is ignored. The interface states created in the top
gate oxide interface are excluded in [14], which leads to an
improper estimation.
In this paper, an HC degradation model for the uni-
axial strained channel TG FinFET using RD mechanism,
considering diffusion of hydrogen atom from the surfaces,
edges and corners of the interface region toward the top
and sidewall gate oxide, is developed. The developed model
is validated with results from TCAD simulations [20]. The
TCAD simulation of unstrained TG FinFET is calibrated with
experimental data [21] for different device dimensions and
biases in Sect. 2. The model is integrated in Cadence Spectre
simulator and used for analyzing the effect of HC degradation
in TG FinFET-based CMOS NAND logic circuit.
2 Simulation methodology
The trap degradation model which can capture reaction–
diffusion mechanisms with hydrogen atom transport in the
gate oxide is incorporated in the TCAD Sentaurus Device
simulator to simulate the trap generation process during HC
stress. The passivated dangling Si bonds at the oxide inter-
face by the hydrogen atoms get broken by the channel hot
carriers generated due to the HC stress applied during the
operation.
The trap generation process in the oxide interface and
diffusion of H atom into the gate oxide is accounted for
by solving the degradation model self-consistently with the
transport equations. The specifications of 30-nm technology
5-fin FinFET with 10 nm fin width (WF ) and 65 nm fin
height (HF ) are used for the simulation, and it is same as
the experimental work published in [21]. The simulation of
the degraded transfer characteristics of TG FinFET is shown
in Fig. 1 after the HC stress of VGS = VDS = 1.8 V for differ-
ent stress times. The VTH shift and drain current degradation
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J Comput Electron
Fig. 1 IDS –VGS characteristics of TG FinFET simulated at VDS =
0.03 V after HC stress of VGS = VDS = 1.8 V for different stress times
are clearly visible which is due to the generation of acceptor
type of interface traps.
The TCAD simulation of HC degradation in FinFET is
calibrated properly to match with the experimental data for
different stress conditions and fin widths WF . The compari-
son of hot carrier simulation of the 5-fin TG FinFET with the
experimental data under different stress conditions is shown
in Fig. 2. The HC degradation of the threshold voltage VTH
is normalized with the initial threshold voltage VTH0 . The
severity of HC degradation increases with the stress time and
bias. Initially, the number of unoccupied traps is higher in the
interface regime, so the probability of trapping is also higher
during the initial period of stress time. Thus, the interface
traps are occupied rapidly with the application of stress volt-
ages during initial short stress time and rate of degradation
becomes steady during the long time range.
The simulation and measurement data [21] of VTH degra-
dation due to HC stress for different fin widths (WF = 5,
10, and 15 nm) are shown in Fig. 3. The degradation of the
device at two different stress times of 1000 and 4000 s is
presented. It shows that the VTH degradation due to HCI in
the FinFET is almost independent of the fin width. The two
sidewall gates of TG FinFET get closer with a decrease in
fin width, and it should typically increase the channel electric
field and HC degradation. However, the decrease in fin width
increases the source/drain resistance which reduces the drain
current and thus HC degradation [21] and so it appears to be
independent.
The introduction of strain in the channel of TG Fin-
FET enhances its performance. The uniaxial strain tensors
ε = 1.153% and ε = 3% are applied in the Si fins and simu-
lated using Sentaurus TCAD. The comparison of the transfer
characteristics of strained and unstrained FinFET is shown
J Comput Electron
Fig. 2 Comparison of TCAD simulation (line) of hot carrier degrada-
tion in triple-gate FinFET with experimental data (symbols) [21] for
5000 s for different stress conditions
Fig. 3 Comparison of TCAD simulation (line) of HC degradation in
TG FinFET with experimental data (symbols) [21] for different fin
widths (WF ) at stress time of 1000 and 4000 s
Fig. 4. The increased performance due to the introduction of
strain adversely affects the HC reliability of the FinFET.
The HC degradation of strained FinFETs with 5 fins is
simulated in Sentaurus Device simulator and compared with
the degradation rate of unstrained FinFET. The compari-
son of HC degradation in strained and unstrained FinFET is
shown in Figs. 5 and 6 for different stress conditions. Figure 5
shows the HC degradation of unstrained and strained FinFET
with various gate voltages VGS at a constant drain voltage
of VDS = 1.8 V. The FinFET hot carrier degradation is
increased with the strain tensor of the fin because of increased
impact ionization rate due to strain-induced bandgap narrow-
ing in the Si channel [8]. Figure 6 shows the HC degradation
Fig. 4 Comparison of IDS –VGS characteristics of the unstrained and
strained FinFET
Fig. 5 HC degradation in unstrained and strained FinFET (ε =
1.154% and ε = 3%) for different gate voltages
of unstrained and strained FinFET with various VDS at a con-
stant VGS = 0.9 V. The HC degradation increases with an
increase in the drain voltage. These TCAD HC degradation
results will be used for the validation of the proposed model
described in Sect. 3.
3 HC degradation model of strained TG FinFET
The mechanism of interface trap generation due to HC stress
can be explained through the reaction–diffusion (RD) theory.
The channel hot carriers gain higher kinetic energy in the
presence of high lateral electric field, break the Si–H bonds,
and form the dangling bonds. The hot holes generated from
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 J Comput Electron

Fig. 6 HC degradation in unstrained and strained FinFET (ε =

1.154% and ε = 3%) for different drain voltages

the impact ionization break the Si–H bond in the interface

and release hydrogen atom. The hot electrons and released
H atom react with the Si–H bonds to create interface traps
which can be represented as follows [22,23]:

Si−H + H+ + e−  Si• + H2 , (1)

where Si• represents the dangling Si bond. The creation of

interface states by hot carriers increases with respect to the
stress time. The interface trap density due to HC stress is
(HCI)
dependent on the initial concentration of Si–H bonds N0
(0)
[14] and density of H atom in the oxide interface, NH , which
anneals the dangling bonds. The forward reaction rate kf and
reverse reaction rate kr are given by [15]

NIT NH(0) ≈ (kf /kr ) N0 . (2)
The Si–H density contribution in the hot carrier degradation
(N0 = N0(HCI) ) due to HC stress is given by [14]
 
(HCI) IDS −ϕ I T
N0 = N0 exp , (3)
(WF + 2HF ) qλE m
where ϕIT is the critical energy for interface state genera-
tion; λ = 7.8 × 10−9 m is the mean free path of an electron
[13]; and E m = (VDS − VDSAT )/L P is the maximum lat-
eral electric field in the pinch-off region, where VDSAT is the
saturation voltage and is formulated as in [13] and L P is the
length of pinch-off region. The high lateral electric field in the
pinch-off region energizes the channel carriers which create
the dangling bonds in the oxide interface releasing H atoms
into the gate oxide. The diffusion of hydrogen atoms in TG
FinFET from the pinch-off region is demonstrated in Fig. 7
in which Fig. 7a shows 1-D diffusions from the two channel
Fig. 7 Diffusion of H atom a as 1-D and 2-D nature from the surface
and edges into the sidewall gate oxides b as 1-D and 2-D nature from
the surface and edges into the top gate oxide c as 1-D and 2-D nature
into the sidewall and top gate oxides
surfaces into sidewall gate oxide, 2-D diffusions from the two
channel edges into the sidewall gate oxide, Fig. 7b shows the
1-D and 2-D diffusions into the top gate oxide, and Fig. 7c
shows the additional two 2-D diffusions from the edges of
pinch-off region into the top and sidewall gate oxide. The
1-D diffusions shown in Fig. 7c are the replications of 1-D
diffusions in Fig. 7a, b. Further, the diffusion of H atom from
the 2 corners (shown in Fig. 7a) of pinch-off region in 3-D
nature into the top and sidewall gate oxide at a channel posi-
tion L P from the drain side is observed. Hence, totally three
1-D, five 2-D, and two 3-D types of diffusions are seen in TG
FinFET. The diffusion of H atoms from the channel surface
toward the top and sidewall gate oxides in one direction is

123
J Comput Electron

√
said to be 1-D nature of diffusions. The released H atoms DH t  
(0) x
from the 5 edges of pinch-off regions diffuse in two direc- + NH 1− √ WF L p dx
tions, and the H atoms from two corners could diffuse in all DH t
0
the three directions (x, y, and z). From Eq. (1), it is clear that √
DH t  
release of each H atom is associated with an interface trap. 2 (0) r
So the interface trap density can be calculated by integrating + NH 1− √ 2πr L p dr
4 DH t
the number of H atoms released into the gate oxide and its 0
√
general case is given by [15] DH t  
2 (0) r
+ NH 1− √ 2πr HF dr
 4 DH t
1 (0) 0
NIT (t) = NH (r ) d3r , (4) √
WL 
DH t 
1 r
+ NH(0)
1− √ 2πr WF dr
4 DH t
where WL is the area of the degraded interface region. The 0
volume occupied by the hydrogen with 1-D, 2-D, and 3-D √ ⎫
DH t   ⎪
⎬
diffusion contains rectangular, one-fourth of cylindrical, and 2 (0) r
+ NH 1 − √ 4πr dr .
2
(8)
one-eighth of spherical form, respectively, as in [15]. The 8 DH t ⎪
⎭
interface trap densities associated with the hydrogen diffu- 0

sion profiles due to 1-D, 2-D, and 3-D nature of hydrogen

diffusion can be obtained using Eq. (4) as given by [15] The surface area of plane, edge, or corner from which H
diffuses after the Si–H bond breaking is considered for each
√ diffusion profiles, respectively. After integrating each term
DH t in Eq. (8) and putting the limits, the interface trap density
1 (0)
1-D
NIT (t) = NH generated due to HC stress can be obtained as
(WF + 2HF ) L P
 
0 
y (0) (DH t)1/2 π (DH t)
1− √ (AREC )dy (5) NIT (t) = NH +
DH t 2 6 (WF + 2HF )
√
DH t π (DH t) π (DH t)3/2
1 (0) + + . (9)
2-D
NIT (t) = NH 12L P 12L P (WF + 2HF )
4 (WF + 2HF ) L P
0
 
r (0)
1− √ (ACYL ) dr (6) Substituting N H from Eqs. (2) to (9) and rearranging for
DH t NIT (t) gives
√
DH t
1  
3-D
NIT (t) =
(0)
NH 
8 (WF + 2HF ) L P  kf N (HCI) (DH t)1/2 π (DH t)
0 NIT (t) =  0
+
  kr 2 6 (WF + 2HF )
r
1− √ (ASPH ) dr. (7) 1/2
DH t π (DH t) π (DH t)3/2
+ + . (10)
12L P 12L P (WF + 2HF )
The AREC , ACYL , and ASPH are surface areas of the rectan-
gular, cylindrical, and spherical form of hydrogen diffusion The forward and reverse reaction rates are given by [24]
profile in the gate oxide, respectively. Using Eqs. (5)– (7),
     
the volume occupied by the hydrogen profile is the combi- E ox −E ak f −E akr
k f ∝ exp exp and kr ∝ exp .
nation of three 1-D, five 2-D, and two 3-D diffusions, and by E0 kB T kB T
considering geometric dependence it can be expressed as
The first exponential term represents the dependence of kf
⎧ √ on the gate oxide electric field E ox = (VGS − VTH )/tox and
⎪
⎨ DH t
1 (0) reference electric field given by E 0 = 3.8 × 108 V/m. The
NIT (t) = 2 NH
(WF + 2HF )L P ⎪
⎩
second exponential term indicates the dependence on tem-
0 perature with activation energy E ak f . The reverse reaction
 
y rate depends on the temperature with activation energy E akr .
1− √ HF L p dy Substituting the kf and kr in Eq. (10) the interface trap density
DH t

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 J Comput Electron

can be written as

    
(HCI) E ox −E ak 1/2
NIT (t) = A × N0 exp exp
E0 kB T

(DH t)1/2
π (DH t) π (DH t)
× + +
2 6 (WF + 2HF ) 12L P
1/2
π (DH t)3/2
+ , (11)
12L P (WF + 2HF )

where A = 0.2×10−5 is the technology-dependent constant;

E ak is the combination of the activation energies of forward
and reverse reaction rates; WF and HF are the fin width and
height, respectively; and D H = D0 ex p(−E a /k B T ), where
D0 = 2.2 × 10−12 (m2 /s) is the diffusion constant of H atom Fig. 8 Validation of HC degradation model of TG FinFET under differ-
and E a is the activation energy. The degraded threshold volt- ent gate bias conditions for WF = 10 nm and HF = 65 nm. Simulation
data are denoted using symbols and model as solid lines
age after HC stress can be calculated as VTH = q NIT /Cox ,
where NIT is given in Eq. (11).

4 Results and discussion

The HC threshold voltage degradation is dependent mainly

on the applied stress voltages (VGS and VDS ) and diffusion
constant of H atom into the gate oxide as in Eq. (11). The
length of pinch-off region depends on the channel length and
the applied drain voltage. The developed HC threshold volt-
age degradation model is verified with the HC simulation
using Sentaurus TCAD 30-nm technology SOI 5-fin Fin-
FET which is already calibrated with experimental data in
Sect. 2. The HC simulation and model results for different
VGS and VDS stress conditions are shown in Figs. 8 and 9,
respectively. The threshold voltage degradation VTH is nor-
Fig. 9 Validation of HC degradation model of TG FinFET under differ-
malized with the initial threshold voltage VTH0 . The rate of ent drain bias conditions for WF = 10 nm and HF = 65 nm. Simulation
degradation increases with the applied HC stress. The analyt- data are denoted using symbols and model as solid lines
ical model matches well with the calibrated simulation data
under different stress conditions, which clearly proves the
validity of model. The comparison of hot carrier degradation The variation of flat band voltage due to strained FinFET
of TG FinFET with the fin width WF of 5 and 10 nm for is given by [25]
various stress conditions is shown in Fig. 10, and the com-
parison for different fin heights HF of 55 and 65 nm is shown VF Bs = ϕm − (χs + E g + E g + qϕ f s ), (12)
in Fig. 11. Figures 10 and 11 depict the negligible variation
of VTH degradation with different fin widths and heights. where ϕm is the work function of the metal gate, χs =
The introduction of strain in the Si fin reduces its bandgap χ0 − E C is the electron affinity of the strained channel, E g
by lowering and raising the energy level of conduction band is the energy bandgap of the unstrained Si, E g = − 0.619ε
and valence band, respectively. The decrease in the bandgap is the decrease in bandgap due to strain, and ϕ f s is the bulk
E g depends on the applied strain ε. The critical energy potential of strained channel. The initial threshold voltage
ϕIT = 3E g decreases with the narrowing of bandgap and VTH0 without HC degradation of the strained FinFET is cal-
increases the generation of high energy electron–hole pairs culated by incorporating the modified VF Bs due to strain
which adversely affect the HC reliability of the FinFET. in the threshold voltage model of the FinFET [26–28]. The

123
J Comput Electron
Fig. 10 Comparison of HC degradation of TG FinFET for different
fin widths under various stress conditions. Simulation data are denoted
using symbols and model as solid lines
Fig. 11 Comparison of HC degradation of TG FinFET for different
fin heights under various stress conditions. Simulation data are denoted
using symbols and model as solid lines
VTH0 model of unstrained TG FinFET and that of strained TG
FinFET incorporating modified VF Bs due to strain are veri-
fied using TCAD simulations in Fig. 12 for different channel
lengths L ch of 30, 45, and 65 nm.
The comparison of HC threshold voltage degradation of
strained FinFET with different strain tensors of ε = 1.154%,
ε = 3%, and unstrained FinFET for various gate bias and
drain bias stress conditions is shown in Figs. 13 and 14,
respectively. The model is modified with proper inclusion
of the bandgap narrowing and increased impact ionization
due to strain for strained channel FinFET. Figures 13 and 14
Fig. 12 Threshold voltage VTH0 of the strained and unstrained FinFET
for the different channel lengths: 30, 45, and 65 nm
Fig. 13 Comparison of HC degradation of strained and unstrained TG
FinFET under different gate bias conditions for WF = 10 nm and HF =
65 nm. Simulation data are denoted using symbols and model as solid
lines
validate the analytical model of strained TG FinFET with the
TCAD simulation results under different stress conditions.
The analytical model of strained TG FinFET is integrated
in the Cadence circuit simulator for the analysis of the HC
effect in FinFET-based VLSI circuits. The two input NAND
gates are designed using the BSIM-CMG model [29], and
the effect of HC degradation in the pull-down network is
analyzed for different stress conditions. The HC degradation
VTH for different stress conditions is calculated using the
analytical model for long time degradation and incorporated
in BSIM model of pull-down network. The delay degradation
TD of the NAND gate due to HCI in the pull-down network
123

Fig. 14 Comparison of HC degradation of strained and unstrained Fin-
FET under different drain bias conditions for WF = 10 nm and HF = 65
nm. Simulation data are denoted using symbols and model as solid lines
Fig. 15 HC degradation of propagation delay TD of strained FinFET
(ε = 3%)-based CMOS NAND gate under different stress conditions
is shown in Fig. 15. The propagation delay increases with an
increase in the HC VTH degradation due to an increase in the
fall time.
5 Conclusion
An analytical model of HC threshold voltage degradation in
TG FinFET suitable for circuit simulators is developed and
validated with TCAD simulations for different stress con-
ditions and device dimensions. The model is extended by
incorporating the modified flat band voltage due to strain and
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J Comput Electron
impact ionization rate for the uniaxial strained channel TG
FinFET. The results from the developed model match well
with the TCAD simulations which were initially calibrated
with the experimental data. Finally, the developed analyti-
cal model, after integration in the circuit simulator, is used
to predict the effect of HC degradation in strained FinFET-
based CMOS NAND gate logic circuit. This model can be
used for the reliable design of FinFET-based VLSI circuits.
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