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Project report on
In
ELECTRONICS AND COMMUNICATION ENGINEERING
By
G. BHARATH KUMAR (16311A04D5)
CH. SANATH KUMAR (16311A04C9)
G. DINESH (16311A04D4)
S. SHAMANTH BHARDWAJ (16311A0G1)
MD. ABU SUFIAN (16311A04E7)
K. VINAY (16311A04D9)
Of
ECIL-ECIT
ELECTRONICS CORPORATION OF INDIA LIMITED
2
ACKNOWLEDGEMENT
We wish to take this opportunity to express our deep gratitude to all those
who helped, encouraged, motivated and have extended their cooperation in
various ways during our project work. It is our pleasure to acknowledgement the
help of all those individuals who was responsible for foreseeing the successful
completion of our project.
We would like to thank Dr. T. THIRUMALAI ( DGM , CED) and express our
gratitude with great admiration and respect to our project guide Mr. T. NAVEEN
KUMAR REDDY and Ms. K. SIVA RAMALAKSHMI for their valuable
advice and help throughout the development of this project by providing us with
required information without whose guidance, cooperation and encouragement,
this project couldn’t have been materialized.
Last but not the least; we would like to thank the entire respondents for
extending their help in all circumstances.
3
TABLE OF CONTENTS
1 ORGANIZATION PROFILE 5
2 ABSTRACT 8
3 OBJECTIVE 9
4 INTRODUCTION 9
5 VLSI 10
6 VHDL Introduction 14
7 SENSORS USED 21
8 BLOCK DIAGRAM 24
9 MODULE DESCRIPTION 25
10 Using Xilinx Ise Brief procedure 27
11 FPGA Implementation 37
on hardware
12 CODE 49
13 RTL Schematic 56
14 SIMULATION 57
15 CONCLUSION 63
16 FUTURE SCOPE 63
17 REFERENCES 64
4
ORGANIZATION PROFILE
ECIL was setup under the department of Atomic Energy in the year 1967 with
a view to generate a strong indigenous capability in the field of professional grade
electronic. The initial accent was on self-reliance and ECIL was engaged in the
Design Development Manufacture and Marketing of several products emphasis on
three technology lines viz. Computers, control systems and communications. ECIL
thus evolved as a multi-product company serving multiple sectors of Indian economy
with emphasis on import of country substitution and development of products and
services that are of economic and strategic significance to the country.
Electronics Corporation of India Limited (ECIL) entered into collaboration
with OSI Systems Inc. (www.osi-systems.com) and set up a joint venture
"ECIL_RAPSICAN LIMITED". This Joint Venture manufacture the equipment’s
manufactured by RAPSICAN, U.K, U.S.A with the same state of art Technology,
Requisite Technology is supplied by RAPSICAN and the final product is
manufactured at ECIL facility.
Recognizing the need for generating quality IT professionals and to meet the
growing demand of IT industry, a separate division namely CED has been
established to impart quality and professional IT training under the brand name of
ECIT. ECIT, the prestigious offshoot of ECIL is an emerging winner and is at the
fore front of IT education in the country.
Mission
ECIL’s mission is to consolidate its status as a valued national asset in the area
of strategic electronics with specific focus on Atomic Energy, Defense, Security and
such critical sectors of strategic national importance.
5
Objectives
To continue services to the country’s needs for the peaceful uses Atomic
Energy. Special and Strategic requirements of Defence and Space, Electronics
Security System and Support for Civil aviation sector.
To establish newer Technology products such as Container Scanning Systems
and Explosive Detectors.
To re-engineer the company to become nationally and internationally
competitive by paying particular attention to delivery, cost and quality in all
its activities.
To explore new avenues of business and work for growth in strategic sectors
in addition to working realizing technological solutions for the benefit of
society in areas like Agriculture, Education, Health, Power, Transportation,
Food, Disaster Management etc.
Divisions
The Company is organized into divisions serving various sectors, national and
Commercial Importance. They are Divisions serving nuclear sector like Control &
Automation Division (CAD), Instruments & Systems Division (ISD), Divisions
Serving defence sector like Communications Division (CND), Antenna Products
Division (APD), Servo Systems Division (SSD) etc., Divisions handling
Commercial Products are Telecom Division (TCD), Customer Support Division
(CSD), Computer Education Division (CED).
6
Exports
ECIL is currently operating in major business EXPORT segments like
Instruments and systems design, Industrial/Nuclear, Servo Systems, Antenna
Products, Communication, Control and Automation and several other components.
Services
The company played a very significant role in the training and growth of high
calibre technical and managerial manpower especially in the fields of Computers and
Information Technology. Though the initial thrust was on meeting the Control &
Instrumentation requirements of the Nuclear Power Program, the expanded scope of
self-reliance pursued by ECIL enabled the company to develop various products to
cater to the needs of Defence, Civil Aviation, Information & Broadcasting, Tele
communications, etc.
7
ABSTRACT
In recent years, the home automation has seen a rapid introduction of network
enabled digital technologies. Home automation involves introducing a degree of
computerized or automatic control to certain electrical and electronic systems in a
building. This device had been modelled such that it takes care of home intrusion
detection and avoidance, while it also controls other home environment factors such
as temperature and smoke detection. A sequential pattern of controlling the door,
burglar alarm, fire alarm, temperature and luminosity is followed in a priority order.
In this paper we introduced an efficient design of home automation system using
Verilog HDL and a possible solution where the user controls device by employing a
central FPGA controller to which the devices and sensors are interfaced. We
simulated the design in Verilog HDL using Xilinx. The solution of this project is in
agreement with our expected output which is readily visible through our waves. We
also got the RTL schematic which shows that it can work on hardware.
8
OBJECTIVE
Our objective is to design a FPGA based home monitoring system. We are using the
FPGA other than the micro controller because we can connect many devices which
can be monitored and the FPGA can be used as a controller or a processor. The design
has been described using Verilog and implemented in hardware using FPGA (Field
Programmable Gate Array). Our system was designed to control the door, window,
garage door, fire alarm, luminosity, and temperature. It is not designed to control any
other device. The academic goal of this project is to develop specific skills in
designing, programming, testing and debugging.
INTRODUCTION
In the present time, everybody is always in great need of security. Mostly during
recession, crime rate like burglary and thief reaches its peak and so home needs to
be more secured. Such need can be fulfilled using a home automation system which
will provide secure and comfortable environment for living. The security system
engages itself to provide the security against any unwanted happening. The comfort
system is responsible for providing a comfortable environment for the host in the
house. Security had always been a particular word which is of great importance in
business and home. Whereas comfort is the prime word when a house is taken into
consideration, when these two words meet a house becomes a perfect place for living
The basic home automation system will try to meet host’s demand and make the
home as safe and comfortable as possible . Various products are available in the
market which is often very costly. Sometimes you need to pre plan about a home
automation before making a home. Also there are some product those are discrete.
This problem can be solved through a single program that checks security than
comfort. Therefore home automation system can control all the desired things in one
go. This will let the owner relax perfectly and will not have to panic around checking
doors and windows often
9
VLSI:
Before the introduction of VLSI technology, most ICs had a limited set of functions
they could perform. An electronic circuit might consist of a CPU, ROM, RAM and
other glue logic. VLSI lets IC designers add all of these into one chip.
The electronics industry has achieved a phenomenal growth over the last few
decades, mainly due to the rapid advances in large scale integration technologies and
system design applications. With the advent of very large scale integration (VLSI)
designs, the number of applications of integrated circuits (ICs) in high-performance
computing, controls, telecommunications, image and video processing, and
consumer electronics has been rising at a very fast pace.
The current cutting-edge technologies such as high resolution and low bit-rate video
and cellular communications provide the end-users a marvelous amount of
applications, processing power and portability. This trend is expected to grow
rapidly, with very important implications on VLSI design and systems design.
10
VLSI DESIGN FLOW:
The VLSI IC circuits design flow is shown in the figure below. The various levels of
design are numbered and the blocks show processes in the design flow.
Specifications comes first, they describe abstractly, the functionality, interface, and
the architecture of the digital IC circuit to be designed.
RTL description is done using HDLs. This RTL description is simulated to test
functionality. From here onwards we need the help of EDA tools.
RTL description is then converted to a gate-level netlist using logic synthesis tools.
A gatelevel netlist is a description of the circuit in terms of gates and connections
between them, which are made in such a way that they meet the timing, power and
area specifications.
Finally, a physical layout is made, which will be verified and then sent to fabrication.
11
Verilog HDL:
During the development cycle the description has to become more and more precise
until it is actually possible to manufacture the product. The (automatic)
transformation of a less detailed description into a more elaborated one is called
synthesis. Existing synthesis tools are capable of mapping specific constructs of
12
hardware description languages directly to the standard components of integrated
circuits. This way, a formal model of the hardware system can be used from the early
design studies to the final net list. Software support is available for the necessary
refinement steps.
Existing Systems
Most commercially available home automation systems are all-in-one solutions
which require that all controllable appliances are from the same company, or must be
approved as compatible with said company‟s system. Moreover these systems normally
come with a proprietary, dedicated device which acts as the control centre. To control
the system from multiple locations, additional control devices must be purchased.
Proposed Systems
The objective of the proposed system is to offer a low- cost solution for a home
automation system that overcomes the above drawbacks. The system provides basic
control of appliances at a fraction of the cost of commercially available systems.
The concept of a proprietary control device is done away with sensors such as LDR
,PIR sensor ,smoke sensor which gives input to the module, such as a mobile phone
or laptop. There is no need for a specialized server system as a typical desktop PC
can act as the server. Nowadays most users already own the requisites such as a
mobile phone and a desktop PC; hence the cost of the system is considerably reduced.
13
VHDL INTRODUCTION
VHDL is an acronym for Very high speed integrated circuit (VHSIC) Hardware
Description Language which is a programming language that describes a logic circuit
by function, data flow behaviour, and/or structure. This hardware description is used
to configure a programmable logic device (PLD), such as a field programmable gate
array (FPGA), with a custom logic design.
The general format of a VHDL program is built around the concept of BLOCKS
which are the basic building units of a VHDL design. Within these design blocks a
logic circuit of function can be easily described. A VHDL design begins with an
ENTITY block that describes the interface for the design. The interface defines the
input and output l1ogic signals of the circuit being designed.
The ARCHITECTURE block describes the internal operation of the design. Within
these blocks are numerous other functional blocks used to build the design elements
of the logic circuit being created. After the design is created, it can be simulated and
synthesized to check its logical operation.
SIMULATION is a bare bones type of test to see if the basic logic works according
to design and concept. SYNTHESIS allows timing factors and other influences of
actual field programmable gate array (FPGA) devices to effect the simulation thereby
doing a more thorough type of check before the design is committed to the FPGA or
similar device. 1.1 VHDL Application VHDL is used mainly for the development of
Application Specific Integrated Circuits (ASICs). Tools for the automatic
transformation of VHDL code into a gate-level net list were developed already at an
early point of time. This transformation is called synthesis and is an integral part of
current design flows. For the use with Field Programmable Gate Arrays (FPGAs)
several problems exist.
In the first step, Boolean equations are derived from the VHDL description, no
matter, whether an ASIC or a FPGA is the target technology. But now, this Boolean
code has to be partitioned into the configurable logic blocks (CLB) of the FPGA.
This is more difficult than the mapping onto an ASIC library. Another big problem
14
is the routing of the CLBs as the available resources for interconnections are the
bottleneck of current FPGAs. While synthesis tools cope pretty well with complex
designs, they obtain usually only suboptimal results. Therefore, VHDL is hardly used
for the design of low complexity Programmable Logic Devices(PLDs).
VHDL can be applied to model system behaviour independently from the target
technology. This is either useful to provide standard solutions, e.g. for micro
controllers, error correction (de-)coders, etc, or behavioural models of
microprocessors and RAM devices are used to simulate a new device in its target
environment. An ongoing field of research is the hardware/software co design. The
most interesting question is which part of the system should be implemented in
software and which part in hardware. The decisive constraints are the costs and the
resulting performance.
[declarations]
Begin
architecture body
15
end [architecture] [architecture-name];
ENTITY BLOCK
An entity block is the beginning building block of a VHDL design. Each design
has only one entity block which describes the interface signals into and out of the
design unit. The syntax for an entity declaration is:
entity entity_name is
end entity_name;
An entity block starts with the reserve word entity followed by the entity_name.
Names and identifiers can contain letters, numbers, and the under score character,
but must begin with an alpha character. Next is the reserved word is and then the port
declarations. The indenting shown in the entity block syntax is used for
documentation purposes only and is not required since VHDL is insensitive to white
spaces. A single PORT declaration is used to declare the interface signals for the
entity and to assign MODE and data TYPE to them. If more than one signal of the
same type is declared, each identifier name is separated by a comma. Identifiers are
followed by a colon (:), mode and data type selections.
In general, there are five types of modes, but only three are frequently used. These
three will be addressed here. They are in, out, and inout setting the signal flow
direction for the ports as input, output, or bidirectional. Signal declarations of
different mode or type are listed individually and separated by semicolons (;). The
last signal declaration in a port statement and the port statement itself are terminated
by a semicolon on the outside of the port's closing parenthesis.
The entity declaration is completed by using an end operator and the entity name.
Optionally, you can also use an end entity statement. In VHDL, all statements are
terminated by a semicolon.
end latch;
The set/reset latch has input control bits s and r which are define d as single input
bits and output bits q and nq. Notice that the declaration does not define the operation
yet, just the interfacing input and output logic signals of the design. A design circuit's
operation will be defined in the architecture block. We can define a literal constant
to be used within an entity with the generic declaration, which is placed before the
port declaration within the entity block. Generic literals than can be used in port and
other declarations. This makes it easier to modify or update designs. For instance if
you declare a number of bit_vector bus signals, each eight bits in length, and at some
future time you want to change them all to 16-bits, you would have to change each
of the bit_vector range. However, by using a generic to define the range value, all
you have to do is change the generic's value and the change will be reflected in each
of the bit_vectors defined by that generic. The syntax to define a generic is:
The reserved word generic defines the declaration statement. This is followed by an
identifier name for the generic and a colon.
Next is the data type and a literal assignment value for the identifier. := is the
assignment operator that allows a literal value to be assigned to the generic identifier
name. This operator is used for other assignment functions as we will see later. For
example, here is the code to define a bus width size using a generic literal.
entity my processor is
Presently, busWidth has the literal value of 7. This makes the documentation more
descriptive for a vector type in a port declaration:
ARCHITECTURE BLOCK
The architecture block defines how the entity operates. This may be described in
many ways, two of which are most prevalent:
The BEHAVIOR approach describes the actual logic behavior of the circuit. This is
generally in the form of a Boolean expression or process. The STRUCTURE
approach defines how the entity is structured - what logic devices make up the circuit
or design. The general syntax for the architecture block is:
declarations;
begin
statements
defining operation;
end arch_name;
example, we will use the set/reset NOR latch of figure 1. In VHDL code listings, --
(double dash) indicates a comment line used for documentation and ignored by the
compiler.
18
library ieee;
use ieee.std_logic_1164.all;
-- entity block
entity latch is
end latch;
-- architecture block
begin
-- assignment statements
end flipflop;
The first two lines imports the IEEE standard logic library std_logic_1164 which
contains predefined logic functions and data types such as std_logic and
std_logic_vector. The use statement determines which portions of a library file to
use. In this example we are selecting all of the items in the 1164 library. The next
block is the entity block which declares the latch's interface inputs, r and s and
outputs q and nq. This is followed by the architecture block which begins by
identifying itself with the name flipflop as a description of entity latch. Within the
architecture block's body (designated by the begin reserved word) are two
assignment statements.
The <= symbol is the assignment operator for assigning a value to a signal. This
differs from the := assignment operator used to assign an initial literal value to
generic identifier used earlier. In our latch example, the state of the signal q is
assigned the logic result of the nor function using input signals r and nq. The nor
operator is defined in the IEEE std_logic_1164 library as a standard VHDL function
to perform the nor logic operation.
Through the use of Boolean expressions, the operation of the NOR latch's behavior
is described and translated by a VHDL compiler into the hardware function
appearing in figure 1.
20
SENSORS USED
Temperature Sensor
Here we are using LM35 as temperature sensor. In this case we will get the output
which is proportional to the temperature, the value will be in degree celcius.LM35 is
more accurate than normal thermistor. There will not be occurrence of oxidation
because of the usage of sealing over the circuitry. On comparing with thermocouple
LM35 produces higher output voltages. Since it is producing higher output voltage,
there is no need of separate amplification. By means of using this increment as well
as decrement in the temperature can understand. It is having maximum supply
voltage of 35v and maximum output voltage of 6v.In addition, output current,
maximum junction temperature are 10mA, 150degree celcius respectively
21
Light Dependent Resistor
22
PIR Sensor
A passive infrared sensor (PIR sensor) is an electronic sensor that measures infrared
(IR) light radiating from objects in its field of view. They are most often used in PIR-
based motion Detectors. Usage of circuitry and time saving nature. In addition it is
having adjustable sensitivity and output LED indicator. All objects with a
temperature above absolute zero emit heat energy in the form of radiation. Usually
this radiation is invisible to the human eye because it radiates at infrared
wavelengths, but it can be detected by electronic devices designed for such a purpose.
The term passive in this instance refers to the fact that PIR devices do not generate
or radiate any energy for detection purposes. They work entirely by detecting the
energy given off by other objects. PIR sensors don't detect or measure "heat"; instead
they detect the infrared radiation emitted or reflected from an object.
23
BLOCK DIAGRAM:
Burglar Alarm
For adding security to the home, we included a burglar alarm module in the system
which buzzes when an unauthorized person enters the room.
Fire Alarm
The system comes along with a fire alarm module which buzzes when the room
temperature crosses 105 degrees Celsius.
Luminosity Control
The system can control the ambient light in the room by turning on and off different
light sources as and when needed.
Temperature Control
The system can automatically adjust the temperature inside the room by turning on
various appliances when certain pre-configured temperatures are reached.
24
MODULE DESCRIPTION:
Smart Home:
This module is the one that takes all the inputs and provides output to the outer
world. It also sets the security alarms high or low depending on the values from the
other module outputs.
Security module:
It is responsible for transferring the data from the sensors to the individual door,
garage, window, fire modules. For adding security to the home, we included a burglar
alarm module in the system which buzzes when an unauthorized person enters the
room. It also plays role in passing the outputs from the door, garage, window and
fire module to the smart_home module.
Door module:
in this state the door is monitored continuously. If the door is open and the magnetic
contact is broken. This is when the door alarm goes high. Both the window and
garage modules work similarly.
Fire module:
in this state the smoke detector is always set low (0). Upon coming in contact with
smoke the smoke detector automatically sends high signal which turns on the fire
alarm. The system comes along with a fire alarm module which switches on the water
extinguisher when smoke is detected.
25
Using Xilinx Ise A Brief procedure:
The ISE 13.2i Quick Start Tutorial provides Xilinx PLD designers with a quick
overview of the basic design process using ISE 13.2i. After you have completed the
tutorial, you will have an understanding of how to create, verify, and implement a
design.
• “Getting Started”
• “Design Simulation”
For an in-depth explanation of the ISE design tools, see the ISE In-Depth Tutorial
on the
26
Getting Started
Software Requirements:
• ISE 13.2i
For more information about installing Xilinx® software, see the ISE Release Notes
and
Hardware Requirements:
• Spartan-3 Startup Kit, containing the Spartan-3 Startup Kit Demo Board
Note: Your start-up path is set during the installation process and may differ from
the one above.
27
Accessing Help
At any time during the tutorial, you can access online help for additional information
• Press F1 to view Help for the specific tool or function that you have selected or
Highlighted.
• Launch the ISE Help Contents from the Help menu. It contains information about
28
Create a New Project
Create a new ISE project which will target the FPGA device on the Spartan-3e
Startup Kit demo board.
1. Select File > New Project... The New Project Wizard appears.
3. Enter or browse to a location (directory path) for the new project. A tutorial
subdirectory is created automatically.
4. Verify that HDL is selected from the Top-Level Source Type list.
♦ Family: Spartan3E
♦ Device: XC3S500E
♦ Package: FG320
♦ Speed Grade: -4
29
♦ Verify that Enable Enhanced Design Summary is selected.
When the table is complete, your project properties will look like the following:
7. Click Next to proceed to the Create New Source window in the New Project
Wizard. At the end of the next section, your new project will be complete.
In this section, I will create the a example top-level Verilog HDL file
30
2. Select Verilog Module as the source type in the New Source dialog box.
5. Click Next.
6. Declare the ports for the counter design by filling in the port information as shown
below:
Define Module
7. Click Next, then Finish in the New Source Information dialog box to complete
the new source file template.
31
The source file containing the counter module displays in the Workspace, and the
counter displays in the Sources tab, as shown below:
The next step in creating the new source is to add the behavioral description for
counter.
Use a simple counter code example from the ISE Language Templates and customize
it for the counter design.
1. Place the cursor on the line below the output [3:0] COUNT_OUT; statement.
Note: You can tile the Language Templates and the counter file by selecting
Window → Tile Vertically to make them both visible.
32
3. Using the “+” symbol, browse to the following code example:
4. With Simple Counter selected, select Edit → Use in File, or select the Use
Template in File toolbar button. This step copies the template into the counter source
file.
1. To declare and initialize the register that stores the counter value, modify the
2. Customize the template for the counter design by replacing the port and signal
name
33
3. Add the following line just above the endmodule statement to assign the register
value to the output port:
When you are finished, the code for the counter will look like the following:
input CLOCK;
input DIRECTION;
if (DIRECTION)
else
endmodule
You have now created the Verilog source for the tutorial project.
34
Checking the Syntax of the New Counter Module
When the source files are complete, check the syntax of the design to find errors and
typos.
Sources window.
2. Select the counter design source in the Sources window to display the related
3. Click the “+” next to the Synthesize-XST process to expand the process group.
Note: You must correct any errors found in your source files. You can check for
errors in the Console tab of the Transcript window. If you continue without valid
syntax, you will not be able to simulate or synthesize your design.
Design Simulation
Create a test bench waveform containing input stimulus you can use to verify the
functionality of the counter module. The test bench waveform is a graphical view of
a test bench.
3. In the New Source Wizard, select Verilog test fixture as the source type, and type
counter_tbw in the File Name field.
4. Click Next.
5. The Associated Source page shows that you are associating the test bench
waveform with the source file counter. Click Next.
6. The Summary page shows that the source will be added to the project, and it
displays the source directory, type and name. Click Finish.
36
HARDWARE IMPLEMENTATION ON FPGA
OVERVIEW OF FPGA
Before the advent of programmable logic, custom logic circuits were built at the
board level using standard components, or at the gate level in expensive
application-specific (custom) integrated circuits. FPGAs are a distinct from SPLDs
and CPLDs and typically offer the highest logic capacity. The FPGA is an
integrated circuit that contains many 64 to over 10,000 identical logic cells and an
even greater number of flip-flops that can be viewed as standard components. Each
logic cell can independently take on any one of a limited set of personalities. The
individual cells are interconnected by a matrix of wires and programmable
switches. A user's design is implemented by specifying the simple logic function
for each cell and selectively closing the switches in the interconnect matrix. The
arrays of logic cells and interconnect form a fabric of basic building blocks for logic
circuits. Complex designs are created by combining these basic blocks
to create the desired circuit.
37
Figure Basic Structure of an FPGA
38
The FPGA architecture consists of three types of configurable elements - a
perimeter
of input/output blocks (IOBs), a core array of configurable logic blocks (CLBs), and
resources
for interconnection as shown in fig 2(a). The IOBs provide a programmable interface
between the internal array of logic blocks (CLBs) and the device's external package
pins. CLBs perform user-specified logic functions, and the interconnect resources
carry signals among the block.
39
high engineering costs associated with application specific integrated
circuits.
Rapid prototyping
Shorter time to market
The ability to re-program in the field for
debugging
Lower NRE costs
Long product life cycle to mitigate
obsolescence risk
40
SPECIFICATIONS OF SPARTAN-3 FPGA
Because of their exceptionally low cost, Spartan-3 FPGAs are ideally suited
to a wide
range of consumer electronics applications, including broadband access, home
networking,
display/projection and digital television
equipment.
42
FEATURES OF SPARTAN 3E
43
• Logic resources
Abundant logic cells with shift register
capability
-Wide, fast
multiplexers
Fast look-ahead carry
logic
Dedicated 18 x 18
multipliers
JTAG logic compatible with IEEE
1149.1/1532
• SelectRAM™ hierarchical
memory
Up to 1,872 Kbits of total block
RAM
Up to 520 Kbits of total distributed
RAM
Digital Clock Manager (up to four
DCMs)
Clock skew
elimination
Frequency
synthesis
High resolution phase
shifting
45
The Spartan-3 family architecture consists of five fundamental programmable
functional
elements:
• Configurable Logic Blocks (CLBs) contain RAM-based Look-Up Tables
(LUTs) to
implement logic and storage elements that can be used as flip-flops or latches.
CLBs can be programmed to perform a wide variety of logical functions as well
as to store data.
• Input/Output Blocks (IOBs) control the flow of data between the I/O pins
and the
internal logic of the device. Each IOB supports bidirectional data flow plus
3-state operation.
• Digital Clock Manager (DCM) blocks provide self-calibrating, fully digital
solutions for
distributing, delaying, multiplying, dividing, and phase shifting clock
signals.
46
AES CODE ANALYSIS ON SPARTAN-3 FPGA KIT
47
Pinout and Area Constraints
Editor
• Assign Package
Pins
Assign I/O locations, specify I/O banks and I/O standards, prohibit I/O
locations
Verify the pin type to the logic assignment
Perform a DRC check to prevent illegal placements
• Create Area Constraints
Create area constraints for logic and display I/Os on the periphery to show
connectivity
Begin floor planning early in the design flow
Verify area constraints
48
Code:
module smartt_home(
input clock,
input reset,
input clk,
input motion_set,
input fire,
input door,
input window,
input garage,
input [7:0]lume_sen,
output firealarm,
output dooralarm,
output windowalarm,
output garagealarm,
output heater,
output cooler,
output light,
output light_low,
output light_high
);
comf C1 (clk,reset,motion_set,temp_sen,lume_sen,light,heater,cooler,light_high,light_low);
49
endmodule
module security(
input clock,
input reset,
input door,
input fire,
input window,
input garage,
output dooralarm,
output firealarm,
output windowalarm,
output garagealarm
);
fir f2 (clock,reset,fire,firealarm);
door f3 (clock,reset,door,dooralarm);
window f4 (clock,reset,window,windowalarm);
garage1 f5 (clock,reset,garage,garagealarm);
endmodule
module comf(clk,reset,motion_set,temp_sen,lume_sen,heater,cooler,light,light_low,light_high);
input clk;
input reset;
input motion_set;
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input [7:0] temp_sen;
output heater;
output cooler;
output light;
output light_low;
output light_high;
reg heater,cooler,light_high,light_low,light;
always @(*) // used when there are multiple parameters are changing
begin
if(reset==1)
begin
heater=0;
cooler=0;
light_high=0;
light_low=0;
light=0;
end
cooler=1;
else if (temp_sen<8'b00001111)
heater=1;
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light_low=1;
light_high=1;
end
endmodule
module fir(clock,reset,fire,firealarm);
input clock;
input reset;
input fire;
output firealarm;
reg firealarm;
begin
if (reset==1)
firealarm=0;
else if (fire==1)
firealarm=1;
else
firealarm=0;
end
endmodule
module door(clock,reset,door,dooralarm);
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input clock;
input reset;
input door;
output dooralarm;
reg dooralarm;
begin
if (reset==1)
dooralarm=0;
else if (door==1)
dooralarm=1;
else
dooralarm=0;
end
endmodule
input clock;
input reset;
input window;
output windowalarm;
reg windowalarm;
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always @(posedge clock)
begin
if (reset==1)
windowalarm=0;
else if (window==1)
windowalarm=1;
else
windowalarm=0;
end
endmodule
module garage1(clock,reset,garage,garagealarm );
input clock;
input reset;
input garage;
output garagealarm;
reg garagealarm;
begin
if (reset==1)
garagealarm=0;
else if (garage==1)
garagealarm=1;
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else
garagealarm=0;
end
endmodule
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RTL SCHEMATIC:
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SIMULATION:
No detection by sensor
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All sensors are active
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Smoke sensor (fire) is active
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LDR sensor (Window) is active
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Temperature below 15*C
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Light below 10 lumen
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CONCLUSION:
In our project we have integrated three sensors with FPGA i.e., LDR, PIR sensor
and LM35.LDR controls the lighting of the compound. IR sensors operate the
opening of garage door. It is also responsible for monitoring the interior lighting
and fan regulation. Temperature senor (LM35) manages the temperature control
of the air condition. There have been many assumptions all through, but efforts
have been put in to make it as practical as possible. This is a low cost and
effective device. This method is very easy to adapt and implement and can easily
be embedded to another device.
We used Verilog HDL to implement the code part has really helped since it not
only combines the hardware and software part, it also provides informative
graphs and waveforms which are helpful in understanding the real concept of
the project. Xilinx also has proved to be the most robust and learnable tool for
simulation and a great integrated development environment.
FUTURE SCOPE:
There are a few recommendations for making this system a marketable product.Use
the devices and the sensors and implement the hardware part. Convert this into a
high level language and write it onto a chip creating a device that can be embedded
to a PC, laptop, palm top etc. Make it web enabled to administer the system
remotely. Introduce a few more devices to control, for example the cookingrange,
water temperature control, garage doors, and lights etc.
63
REFERENCES
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