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DC BIASING BJT
KAPASITOR LANGKAH
Analisis DC maka sifat kapasitor menjadi
pembuka rangkaian 02 KAPASITOR = OPEN
LANKAH PERBAGIAN
ANALISIS
PERBAGIAN 04 Lakukan analisis perbagian pin transistor
FIXED BIAS
FIXED BIAS
𝑽𝒄𝒄 − 𝑽𝑩𝑬
𝑰𝑩 =
𝑹𝑩
Collctor-Emitter Loop
Collector current:
𝑰𝑩 = β𝑰𝑩
𝑽𝑪𝑬 = 𝑽𝑪𝑪 − 𝑰𝑪 𝑹𝑪
EMITTER-STABILIZED BIAS
CIRCUIT
EMITTER-STABILIZED BIAS
Since IE=(β+1)IB
𝑽𝑪𝑪 − 𝑰𝑩 𝑹𝑩 − (β+1)𝑰𝑩 𝑹𝑬 = 𝟎
Since IE≈IC
𝑽𝑪𝑬 = 𝑰𝑬 𝑹𝑬
𝑽𝑪 = 𝑽𝑪𝑬 + 𝑽𝑬 = 𝑽𝑪𝑪 − 𝑰𝑪 𝑹𝑪
𝑽𝑩 = 𝑽𝑪𝑪 − 𝑰𝑹 𝑹𝑩 = 𝑽𝑩𝑬 − 𝑽𝑬
VOLTAGE DIVIDER BIAS
EMITTER-STABILIZED BIAS
𝑹𝟐𝑽𝑪𝑪
𝑽𝑩 =
𝑹𝟏 + 𝑹𝟐
Where 𝛃𝐑 𝐁 >10R2
𝑽𝑬
𝑰𝑬 =
𝑹𝑬
𝑽𝑬 = 𝑽𝑩 − 𝑽𝑩𝑬
From Kirchhoff’s voltage law: