C55x+ CPUReferenceGuide SWPU086

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TMS320C55x ’C55x+’ CPU

Reference Guide
Technical Reference Manual
PRELIMINARY VERSION
May 2005
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Preface
Read This First
About This Manual

This manual describes the architecture, registers, and operation of the fixed-
point TMS320C55x digital signal processor (DSP) CPU.
About This Manual Release

This release is updated with the ’Ryujin’ Revision of the TMS320C55x DSP.
Information not affected by the revision remains identical to the previous
manual. The main new features of this revision are:
CPU architecture: new pipeline structure, program bus extension to 64−bit

(PB bus), enlarged IBQ size to 256 bytes, data computation unit enhance-
ments. All information on these features is in chapter 1.
CPU registers: 16 accumulators available, 15 auxiliary registers available,

and one coefficient data pointer, eight transition registers, and some other
new registers. All information on the register is in chapter 2.
Stack modes: the ’Ryujin’ revision introduces the linear−stack mode. All
information on the stack mode is in chapter 4.
Addressing modes: new addressing modes are available. All information

on addressing modes is in chapter 6.
Byte−pointer mode: the revision ’Ryujin’ introduces a byte addressing

mode. Word or byte−pointer addressing mode is supported by the
TMS320C55x DSP. All information on byte−pointer mode is in chapter 7.
(Chapters 1 to 6 are describing the DSP in word−pointer mode).
How to Use This Manual

Chapter 1 CPU Architecture
This chapter describes the CPU architecture of the TMS320C55x (C55x)
DSP.
Chapter 2 CPU Registers
This chapter describes the main registers in the C55x DSP CPU.
Read This First iii

Notational Conventions
Chapter 3 Memory and I/O Space
This chapter describes the unified data/program space and the I/O space in
the TMS320C55x DSP in word−pointer mode.
Chapter 4 Stack Operation
This chapter introduces the two stacks located on each TMS320C55x

(C55x) DSP.
Chapter 5 Interrupt and Reset Operation
This chapter describes the available interrupts of the TMS320C55x

(C55x) DSP, how some of them can be blocked through software, and how
all of them are handled by the CPU in word−pointer mode.
Chapter 6 Addressing Modes
This chapter describes the modes available for addressing the data space
(including CPU registers) and the I/O space of the TMS320C55x
(C55x) DSP in word−pointer mode.
Chapter 7 Byte−pointer Addressing Mode
This chapter describes the byte−pointer mode of the TMS320C55x

(C55x) DSP. All changes that may occur because of byte−addressing, in
chapters 1 to 6, are summarized in this chapter. (Not available in this prelimi-
nary release)
Notational Conventions
This document uses the following conventions.
The device number TMS320C55x is often abbreviated as C55x.
Active-low signals are indicated with an overbar (for example, RESET).
Program listings, program examples, and interactive displays are shown

in a special typeface.
In most cases, hexadecimal numbers are shown with the suffix h. For
example, the following number is a hexadecimal 40 (decimal 64):
40h
Similarly, binary numbers usually are shown with the suffix b. For example,
the following number is the decimal number 4 shown in binary form:
0100b
iv
Related Documentation From Texas Instruments
Bits and signals are sometimes referenced with the following notations:
Notation Description Example
Register(n−m) Bits n through m of Register AC0(15−0) represents the 16

least significant bits of the regis-
ter AC0.
Bus[n:m] Signals n through m of Bus A[21:1] represents signals 21

through 1 of the external ad-
dress bus.
The following terms are used to name portions of data:
Term Description Example
LSB Least significant bit In AC0(15−0), bit 0 is the LSB.
MSB Most significant bit In AC0(15−0), bit 15 is the MSB.
LSByte Least significant byte In AC0(15−0), bits 7−0 are the LSByte.
MSByte Most significant byte In AC0(15−0), bits 15−8 are the MSByte.
LSW Least significant word In AC0(31−0), bits 15−0 are the LSW.
MSW Most significant word In AC0(31−0), bits 31−16 are the MSW.
Related Documentation From Texas Instruments
The following books describe the TMS320C55x devices and related support
tools. To obtain a copy of any of these TI documents, call the Texas
Instruments Literature Response Center at (800) 477-8924. When ordering,
please identify the book by its title and literature number.
TMS320C55x DSP Algebraic Instruction Set Reference Guide (literature

number TBD) describes the TMS320C55x DSP algebraic instructions
individually. Also includes a summary of the instruction set, a list of the
instruction opcodes, and a cross-reference to the mnemonic instruction
set.
Trademarks
TMS320C54x, C54x, TMS320C55x, and C55x are trademarks of Texas In-

struments.
Read This First v

Contents
Contents
1 CPU Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.1 Overview of the CPU Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.1.1 Internal Data and Address Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.1.2 Memory Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.1.3 Instruction Buffer Unit (I Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.1.4 Program Flow Unit (P Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.1.5 Address-Data Flow Unit (A Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.1.6 Data Computation Unit (D Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.2 Instruction Buffer Unit (I Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.2.1 Instruction Buffer Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.2.2 Instruction Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.3 Program Flow Unit (P Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.3.1 Program-Address Generation and Program-Control Logic . . . . . . . . . . . . . . . . 1-8
1.3.2 P-Unit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.4 Address-Data Flow Unit (A Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.4.1 Data-Address Generation Unit (DAGEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.4.2 A-Unit Arithmetic Logic Unit (A-Unit ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.4.3 A-Unit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.5 Data Computation Unit (D Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
1.5.1 Shifter and D-Unit Arithmetic Logic Units (SALU) . . . . . . . . . . . . . . . . . . . . . . . 1-15
1.5.2 Two Multiply-and-Accumulate Units (MACs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
1.5.3 D-Unit Bit Manipulation Unit (D-Unit BIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
1.5.4 D-Unit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
1.6 Address Buses and Data Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
1.7 Instruction Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25
1.7.1 Pipeline Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25
1.7.2 Pipeline Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30
2 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.1 Alphabetical Summary of Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.3 Accumulators (AC0−AC15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.4 Transition Registers (TRN0−TRN7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.5 Temporary Registers (T0−T3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.6 Registers Used to Address Data Space and I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.6.1 Auxiliary Registers (XAR0–XAR15 / AR0–AR15) . . . . . . . . . . . . . . . . . . . . . . . 2-18
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Contents
2.6.2 Coefficient Data Pointer (XAR15 / AR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.6.3 Circular Buffer Start Address Registers
(BSA01, BSA23, BSA45, BSA67, BSAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.6.4 Circular Buffer Size Registers (BK03, BK47, BKC) . . . . . . . . . . . . . . . . . . . . . . 2-22
2.6.5 Data Page Register (XDP / DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2.6.6 Peripheral Data Page Register (PDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2.6.7 Stack Pointers (XSP / SP, XSSP / SSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2.7 Program Flow Registers (PC, RETA, CFCT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2.7.1 Context Bits Stored in CFCT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2.8 Registers For Managing Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
2.8.1 Interrupt Vector Pointers (IVPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
2.8.2 Interrupt Flag Registers (IFR0, IFR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
2.8.3 Interrupt Enable Registers (IER0, IER1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
2.8.4 Debug Interrupt Enable Registers (DBIER0, DBIER1) . . . . . . . . . . . . . . . . . . . 2-36
2.8.5 Interrupt ID Register (IIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39
2.8.6 Bus Error Register (BER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40
2.9 Registers for Controlling Repeat Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
2.9.1 Single-Repeat Registers (RPTC, CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
2.9.2 Block-Repeat Registers (BRC0–1, BRS1, RSA0–1, REA0–1) . . . . . . . . . . . . 2-42
2.10 Status Registers (ST0_55−ST3_55) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45
2.10.1 ST0_55 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47
2.10.2 ST1_55 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50
2.10.3 ST2_55 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61
2.10.4 ST3_55 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-66
3 Memory and I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.2.1 Byte Addresses (24 Bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.2.2 Instruction Organization in Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.2.3 Alignment of Fetches From Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.3.1 Word Addresses (23 Bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.3.2 Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.3.3 Data Organization in Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.4 I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.5 Boot Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
4 Stack Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1 Data Stack and System Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2 Stack Modes and Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.3 Fast Return Versus Slow Return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4.4 Automatic Context Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
4.4.1 Fast-Return Context Switching for Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
viii
Contents
4.4.2 Fast-Return Context Switching for Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11

4.4.3 Slow-Return Context Switching for Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
4.4.4 Slow-Return Context Switching for Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
5 Interrupt and Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.1 Introduction to the Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.2 Interrupt Vectors and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.3 Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.3.1 Bit and Registers Used To Enable Maskable Interrupts . . . . . . . . . . . . . . . . . . . 5-9
5.3.2 Standard Process Flow for Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.3.3 Process Flow for Time-Critical Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5.4 Nonmaskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
5.4.1 Standard Process Flow for Nonmaskable Interrupts . . . . . . . . . . . . . . . . . . . . . 5-15
5.5 DSP Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
5.5.1 DSP Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
5.5.2 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
6 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.1 Introduction to the Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.2 Absolute Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.2.1 k16 Absolute Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.2.2 k24 Absolute Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.2.3 I/O Absolute Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.3 Direct Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6.3.1 DP Direct Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
6.3.2 SP Direct Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
6.3.3 Register-Bit Direct Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
6.3.4 PDP Direct Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
6.4 Indirect Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
6.4.1 AR Indirect Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
6.4.2 Dual AR Indirect Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
6.4.3 Coefficient Indirect Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26
6.4.4 Addressing Data Memory and Memory−Mapped Registers . . . . . . . . . . . . . . . 6-29
6.4.5 Addressing MMRs, and Data Memory With Absolute Addressing Modes . . . 6-29
6.4.6 Addressing MMRs, and Data Memory With Direct Addressing Modes . . . . . 6-31
6.4.7 Addressing MMRs and Data Memory With Indirect Addressing Modes . . . . . 6-33
6.5 Restrictions on Accesses to Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . 6-49
6.6 Addressing Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50
6.6.1 Addressing Register Bits With the Register-Bit Direct Addressing Mode . . . 6-50
6.6.2 Addressing Register Bits With Indirect Addressing Modes . . . . . . . . . . . . . . . 6-51
6.7 Addressing I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-64
6.7.1 Addressing I/O Space With the PDP Direct Addressing Mode . . . . . . . . . . . . 6-64
6.7.2 Addressing I/O Space With Indirect Addressing Modes . . . . . . . . . . . . . . . . . . 6-66
6.8 Restrictions on Accesses to I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-77
Contents ix
Contents
6.9 Circular Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-78

6.9.1 Configuring AR0–AR7 for Circular Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . 6-80
6.9.2 Circular Buffer Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-80
6.9.3 TMS320C54x DSP Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-83
7 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index-1
x
Figures
Figures
1−1 CPU Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1−2 Instruction Buffer Unit (I Unit) Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1−3 Program Flow Unit (P Unit) Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1−4 Address-Data Flow Unit (A Unit) Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1−5 Data Computation Unit (D Unit) Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
1−6 First Segment of the Pipeline (Fetch Pipeline) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25
1−7 Second Segment of the Pipeline (Execution Pipeline) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26
2−1 Accumulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2−2 Transition Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2−3 Temporary Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2−4 Extended Auxiliary Registers and Their Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2−5 Extended Coefficient Data Pointer and Its Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2−6 Circular Buffer Start Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2−7 Circular Buffer Size Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2−8 Extended Data Page Register and Its Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2−9 Peripheral Data Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2−10 Extended Stack Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2−11 Interrupt Vector Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
2−12 Interrupt Flag Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
2−13 Interrupt Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
2−14 Debug Interrupt Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37
2−15 Interrupt ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39
2−16 Single-Repeat Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
2−17 Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46
3−1 -Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
4−1 Extended Stack Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4−2 Return Address and Loop Context Passing During Slow-Return Process . . . . . . . . . . . . . 4-8
4−3 Use of RETA and CFCT in Fast-Return Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
5−1 Standard Process Flow for Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5−2 Process Flow for Time-Critical Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5−3 Standard Process Flow for Nonmaskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
6−1 k16 Absolute Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6−2 k24 Absolute Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6−3 I/O Absolute Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6−4 DP Direct Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
6−5 SP Direct Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
Contents xi
Figures
6−6 Register-Bit Direct Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12

6−7 PDP Direct Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
6−8 Accessing Data Space With the AR Indirect Addressing Mode . . . . . . . . . . . . . . . . . . . . . 6-15
6−9 Accessing Register Bit(s) With the AR Indirect Addressing Mode . . . . . . . . . . . . . . . . . . . 6-16
6−10 Accessing I/O Space With the AR Indirect Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . 6-16
6−11 Circular buffer computation in 23-bit in word−pointer mode . . . . . . . . . . . . . . . . . . . . . . . . 6-82
xii
Tables
T ables
1−1 Instructions Performed in D-Unit BIT Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
1−2 Functions of the Address and Data Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
1−3 Bus Usage By Access Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
1−4 Examples to Illustrate Execution Pipeline Activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29
2−1 Alphabetical Summary of Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2−2 Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2−3 Extended Auxiliary Registers and Their Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2−4 Extended Coefficient Data Pointer and Its Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2−5 Circular Buffer Start Address Registers and The Associated Pointers . . . . . . . . . . . . . . . 2-22
2−6 Circular Buffer Size Registers and The Associated Pointers . . . . . . . . . . . . . . . . . . . . . . . 2-23
2−7 Extended Data Page Register and Its Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2−8 Stack Pointer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
2−9 Program Flow Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2−10 Vectors and the Formation of Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
2−11 Block-Repeat Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44
2−12 Categories of Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70
2−13 Minimum Number of Instruction Cycles Required Between an MPNMC-Update Instruction
and a Branch Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70
3−1 Byte Load and Byte Store Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
4−1 Stack Pointer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4−2 Stack and Mode Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
5−1 Interrupt Vectors Sorted By ISR Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5−2 Interrupt Vectors Sorted By Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5−3 Steps in the Standard Process Flow for Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . 5-11
5−4 Steps in the Process Flow for Time-Critical Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
5−5 Steps in the Standard Process Flow for Nonmaskable Interrupts . . . . . . . . . . . . . . . . . . . 5-16
5−6 Effects of a Reset on CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
6−1 Syntax Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6−2 Absolute Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6−3 DSP Mode Operands for the AR Indirect Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . 6-17
6−4 Dual AR Indirect Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
6−5 *abs16(#k16) Used For Data-Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30
6−6 *abs16(#k16) Used For Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30
6−7 (#k24) Used For Data-Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30
6−8 (#k24) Used For Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30
6−9 @Daddr Used For Data-Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31
Contents xiii
Tables
6−10 *SP(offset) Used For Data-Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32

6−11 @Daddr Used For Memory-Mapped Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33
6−12 Choosing an Indirect Operand For a MMR or a Data Memory Access . . . . . . . . . . . . . . 6-34
6−13 @bitoffset Used For Register-Bit Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50
6−14 Indirect Operands For Register-Bit Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-52
6−15 @Poffset Used For I/O-Space Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-65
6−16 Indirect Operands For I/O-Space Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-66
xiv
Chapter 1
CPU Architecture
This chapter describes the CPU architecture of the TMS320C55x+

(C55x+) DSP. It gives conceptual details about the four functional units of the
CPU and about the buses that carry instructions and data. It also describes the
parallel phases of the instruction pipeline and the pipeline protection mecha-
nism (which prevents read and write operations from happening out of the in-
tended order).
Topic Page
1.1 Overview of the CPU Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.2 Instruction Buffer Unit (I Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.3 Program Flow Unit (P Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.4 Address-Data Flow Unit (A Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.5 Data Computation Unit (D Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
1.6 Address Buses and Data Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
1.7 Instruction Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30
1-1
Overview of the CPU Architecture
1.1 Overview of the CPU Architecture

Figure 1−1 shows a conceptual block diagram of the CPU. Sections 1.1.1
through 1.1.6 describe the buses and units represented in the figure.
Figure 1−1. CPU Diagram

Data-Read Data Buses BB (32 Bits), CB (16 Bits), DB (16 Bits)
Data-Read Address Buses BAB, CAB, DAB (Each 24 Bits)
Program-Read Data Bus PB (64 Bits)
Program-Read Address Bus PAB (24 Bits)
CPU
External Data
Buses
Program Data
Instruction Address-
Flow Unit Computation
Memory Buffer Unit Data
(P Unit) Unit
Interface Unit (I Unit) Flow Unit
(D Unit)
(A Unit)
External
Program Buses
Data-Write Data Buses EB, FB (Each 16 Bits)
Data-Write Address Buses EAB, FAB (Each 24 Bits)
1-2 CPU Architecture

1.1.1 Internal Data and Address Buses

The buses shown in Figure 1−1 are:
Data-Read Data Buses (BB, CB, DB). The BB bus carries 32-bit data
from data space, the CB and DB buses carry 16-bit data from data space
or I/O space to the functional units of the CPU.
The 32-bit BB bus only carries data from internal memory to the data
computation unit (D unit) and to the dual multiply-and-accumulate (MAC)
units. Specific instructions enable you to use the BB, CB, and DB buses to
read four operands at the same time.
The CB and DB buses feed data to the program flow unit (P unit), the
address-data flow unit (A unit), and the D unit. Instructions that read two
operands at once use both the CB and DB buses. Instructions that perform
single read operations use the DB bus.
Data-Read Address Buses (BAB, CAB, DAB). These three buses carry
24-bit byte data addresses to the memory interface unit, which then
fetches the data from memory and transfers the requested values to the
data-read data buses. All data-space addresses are generated in the A
unit.
In word-pointer mode, all data-space addresses are computed and
generated in the A unit as word-aligned to ensure compatibility with the
previous revision. In this mode, the A unit manipulates 23-bit addresses.
In byte-pointer mode, all data-space addresses are computed and
generated in the A unit as byte-aligned to enable efficient processing of the
native C “char” datatype (8 bits). In this mode, the A unit manipulates 24-bit
addresses.
The BAB bus carries addresses for data that is carried from the internal
memory to the CPU on the BB bus.
The CAB bus carries addresses for data that is carried to the CPU on the
CB bus.
The DAB bus carries addresses for data that is carried to the CPU on only
the DB bus or both CB and DB buses.
Program-Read Data Bus (PB). The PB bus carries 64 bits (8 bytes) of
program code at a time to the instruction buffer unit (I unit) where the
instructions are decoded.
Program-Read Address Bus (PAB). The PAB bus carries the 24-bit byte
program address of the program code that is carried to the CPU by the PB
bus. The address carried on the PAB bus is aligned on a multiple of
8 bytes.
CPU Architecture 1-3

Data-Write Data Buses (EB, FB). These two buses carry 16-bit data from
functional units of the CPU to data space or I/O space.
The EB and FB buses receive data from the P unit, the A unit, and the D
unit. Instructions that write two 16-bit values to memory at once use both
EB and FB buses. Instructions that perform single 16-bit write operations
use the EB bus.
Data-Write Address Buses (EAB, FAB). These two buses carry 24-bit
addresses to the memory interface unit, which then receives the values
driven on the data-write data buses. All data-space addresses are
generated in the A unit.
The EAB bus carries addresses for data that is carried to memory on only
the EB bus or both EB and FB buses.
The FAB bus carries addresses for data that is carried to memory on the
FB bus.
1.1.2 Memory Interface Unit

The memory interface mediates all data transfers between the CPU and
program/data space or I/O space.
1.1.3 Instruction Buffer Unit

During each CPU cycle, the I unit receives an 8-byte long fetch packet of
program code from the PAB bus and stores it into its instruction buffer queue
(IU IBQ). At the same time, during each cycle, the I unit reads the IU IBQ and
decodes the program code bytes that were previously stored there. Since the
size of the decode packet (1 to 16 bytes) depends on the encoded instruction
and encoded parallelism size, the amount of already fetched and still to be
executed program code stored in the IU IBQ varies along the executed code
sequence.
For example, the IU IBQ content is flushed whenever the CPU branches to a
new location. The IU IBQ is loaded with a maximum of code fetch advance
when executing a single repeat or local repeat structure (but not necessarily
completely full: 256 bytes).
Once an instruction (or two parallel instructions) are decoded, the I unit passes
data to the P unit, the A unit, and the D unit for the execution of instructions.
For example, any constants that were encoded in instructions (for loading
registers, providing shift counts, identifying bit numbers, etc.) are isolated in
the I unit and passed to the appropriate unit.

1.1.4 Program Flow Unit

The P unit generates all program-space addresses and sends them out on the
PAB bus. It also controls the sequence of instructions by directing operations
such as hardware loops, branches, and conditional execution.
1.1.5 Address-Data Flow Unit

The A unit contains all the logic and registers necessary to generate the
data-space addresses and to send them out on the five data address buses
(BAB, CAB, DAB, EAB, and FAB). It also contains a 16-bit arithmetic logic unit
(AU ALU) that can perform arithmetical, logical, shift, and saturation
operations.
1.1.6 Data Computation Unit

The D unit contains the primary computational units of the CPU:
Two independent 40-bit units called DU SALU1 and DU SALU2. Each DU

SALU performs 40-bit shifting and 40-bit ALU (arithmetic and logic)
operations in one cycle. That is, shifting and ALU operations can be
cascaded within the same single-cycle instruction. Each DU SALU is
dedicated for each instruction slot in case of parallel instructions.
Note that the shifter and DU ALU units of previous revisions have been
merged and duplicated to improve parallelism flexibility.
A bit manipulation unit (DU BIT) that performs specific bit manipulation
operations.
Two independent multiply-and-accumulate units (DU MAC1 and DU

MAC2). Each DU MAC can perform a 17x17-bit signed multiplication and
a 40-bit accumulation (or subtraction) in a single cycle.

Instruction Buffer Unit (I Unit)
1.2 Instruction Buffer Unit (I Unit)

The I unit receives program code into its IU IBQ and decodes the instructions.
The I unit then passes data to the P unit, the A unit, and the D unit for the execu-
tion of instructions. Two instructions per cycle can be executed in parallel.
Figure 1−2 shows a conceptual block diagram of the I unit. Sections 1.2.1 and
1.2.2 describe the main parts of the I unit.
Figure 1−2. Instruction Buffer Unit Diagram
Program-Read Data Bus PB (8 Bytes of Code)
64-Bit
Memory
Interface
Unit
I Unit
Instruction Buffer Queue (IU IBQ)

256 Bytes
128-Bit
Instruction Decoder
Instruction 1 Instruction 2
A Unit D Unit P Unit
1.2.1 Instruction Buffer Queue (IU IBQ)

For every cycle, the CPU fetches 8 bytes of program code from the program
memory and stores them into the IU IBQ. The data are carried by the 64-bit
program read data bus (PB). The queue can hold up to 256 bytes of
undecoded instructions. When the CPU is ready to decode instructions, 1 to
16 bytes of program code are read and decoded from the IU IBQ depending
on the encoded instruction and encoded parallelism size.
In addition to helping with the pipelining of instructions, the queue enables:
A more efficient execution of a block of code withheld in the queue hold

in the queue with the usage of a local repeat instruction. When the local
repeat instruction is used, it defines a block of instructions to be repeated.
The code of the loop is only fetched once during the first iteration of the

Instruction Buffer Unit (I Unit)
loop. This fully benefits from C55x+ parallelism: up to 16 bytes per cycle
can be decoded while 8 bytes per cycle are fetched. The size of the local
repeat instruction must not exceed the IU IBQ size; that is, 256 bytes.
Speculative fetching of instructions while a condition is being tested for

one of the following instructions:
Conditional branch
Conditional call
Conditional return
1.2.2 Instruction Decoder

In the decode phase of the instruction pipeline, the instruction decoder accepts
1 to 16 bytes of program code from the IU IBQ and decodes those bytes. The
instruction decoder:
Identifies instruction boundaries so that it can decode 8-, 16-, 24-, 32-, 40-,
48-, 56-, 64-, 72-, 80-, 88-, 96-, 104-, 112-, 120-, or 128-bit instructions.
Determines whether the CPU has been instructed to execute two

instructions in parallel.
Sends decoded execution commands and immediate values to the P unit,

the A unit, and the D unit.

Program Flow Unit (P Unit)
1.3 Program Flow Unit (P Unit)

The P unit generates all program-space addresses. It also controls the
sequence of instructions. Figure 1−3 shows a conceptual block diagram of the
P unit. Sections 1.3.1 and 1.3.2 describe the main parts of the P unit.
Figure 1−3. Program Flow Unit Diagram

Data-Read Data Buses CB, DB (16 Bits of Data Each)
Program-Read Address Bus PAB (24-Bit Address)
Memory P Unit
Interface
Unit
I Unit Program-Address
Generation and
A Unit Program-Control
Logic
D Unit
P-Unit Registers
Data-Write Data Buses EB, FB (16 Bits of Data Each)
1.3.1 Program-Address Generation and Program-Control Logic

The program-address generation logic is responsible for generating 24-bit
addresses for program fetches from memory. Normally, it generates
sequential addresses. However, for instructions that require reads from
nonsequential addresses, the program-address generation logic can accept
immediate data from the I unit and register values from the D unit. Once an
address is generated, it is carried to memory by the 24-bit program-read
address bus (PAB).

The program control logic accepts immediate values from the I unit and test
results from the A unit or the D unit, and performs the following actions:
Tests whether a condition is true for a conditional instruction and

communicates the result to the program-address generation logic.
Initiates interrupt servicing when an interrupt is requested and properly

enabled.
Controls, through a hardware loop controller, the implementation of three

levels of loops with zero cycle overhead. This controller enables:
The repetition of a single instruction preceded by a single-repeat
instruction.
The repetition of a block of instructions preceded by a block-repeat
instruction (or local-repeat instruction).
You can implement three levels of loops by nesting a block-repeat
operation within another block-repeat operation and including a single
repeat operation in either one or both of the repeated blocks. All repeat
operations are interruptible.
Manages instructions that are executed in parallel. Parallelism within the

C55x+ DSP enables the execution of program-control instructions at the
same time as data processing instructions.
1.3.2 P-Unit Registers
The P unit contains and uses the registers listed below.
Access to the program flow registers is limited. You cannot read from or
write to PC. However, you can access the RETA and CFCT registers to
save and restore the return address and the control flow execution context
flags of the calling routine. You can access RETA and CFCT only with the
following instructions:
dbl(Smem) = RETA
RETA = dbl(Smem)
All the other registers can be loaded with immediate values (from the I unit)
and can be saved to (or loaded from) memory, I/O space, or A-unit
registers.
Program Flow Registers
PC Program counter
RETA Return address register
CFCT Control flow context register

Block-Repeat Registers
BRC0, BRC1 Block-repeat counters 0 and 1
BRS1 BRC1 save register
RSA0, RSA1 Block-repeat start address registers 0 and 1
REA0, REA1 Block-repeat end address registers 0 and 1
Single-Repeat Registers
RPTC Single-repeat counter
CSR Computed single-repeat register
Interrupt Registers
IFR0, IFR1 Interrupt flag registers 0 and 1
IER0, IER1 Interrupt enable registers 0 and 1
DBIER0, DBIER1 Debug interrupt enable registers 0 and 1
BER Bus error register
IIR Interrupt ID register
Status Registers
ST0_55–ST3_55 Status registers 0, 1, 2, and 3

Address-Data Flow Unit (A Unit)
1.4 Address-Data Flow Unit (A Unit)

The A unit contains the logic and registers necessary to generate the data-
space and I/O space addresses. It also contains a 16-bit arithmetic logic unit
(AU ALU) that can perform arithmetical (with or without saturation), logical,
shift, and rotation operations. Figure 1−4 shows a conceptual block diagram
of the A unit. Sections 1.4.1 through 1.4.3 describe the main parts of the A unit.
Figure 1−4. Address-Data Flow Unit Diagram

Data-Write Address Buses EAB, FAB (24-Bit Address Each)
Data-Read Address Buses BAB, CAB, DAB (24-Bit Address Each)
Memory
Interface A Unit
Unit
Data-Address Two Constant Buses KA1, KA2
Generation Units I Unit
Two Constant Buses KX1, KX2
(DAGEN X, Y ,C)
P Unit
A-Unit Registers AU ALU

D Unit
Data-Read Data Buses CB, DB (16 Bits of Data Each)

1.4.1 Data-Address Generation Units (DAGEN X, Y, C)

DAGEN generates all addresses for reads or writes from/to data space and
I/O space. The DAGEN units (X, Y, and C) can generate up to three addresses
within one cycle. The DAGEN units perform the following actions:
Within one cycle, two independent 16-bit data memory operands can be
read in parallel with one 32-bit data memory operand. In the example
below, the two Xmem and Ymem 16-bit data memory operands are read
in parallel with a single 32-bit data memory read operand formed by
HI/LO(coef).
ACa = m40(rnd(frct(uns(Xmem)*uns(LO(coef))))),
ACb = m40(rnd(frct(uns(Ymem)*uns(HI(coef)))))
Within one cycle, one 32-bit data memory operand can be read in parallel
with the writing to memory of a 32-bit data memory operand. In the
example below, the first instruction dbl(Smem) 32-bit data memory
operand is read in parallel with the write of the second instruction
dbl(Smem) 32-bit data memory operand.
ALLa = dbl(Smem)
||dbl(Smem) = ALLa
Within one cycle, two independent 32-bit data memory operands can be
read in parallel with the writing to memory of a 32-bit data memory
operand. In the example below, HI/LO(Smem) forms the first 32-bit data
memory read operand and HI/LO(coef) forms the second 32-bit data
memory read operand. These two 32-bit data memory reads occur in
parallel with the write of the second instruction dbl(Smem) 32-bit data
memory operand.
ACa = m40(rnd(frct(uns(LO(Smem))*uns(LO(coef))))),
ACb = m40(rnd(frct(uns(HI(Smem))*uns(HI(coef)))))
|| dbl(Smem) = ALLa
Within one cycle, the DAGEN units can accept two 24-bit immediate
values from the I unit through the two constant buses used in address
phase by instruction slots 1 and 2 (KA1, KA2). In the example below, two
A-unit registers can be initialized when using the following instructions in
parallel:
mar(XDAa = k24)
|| mar(XDAa = k24)
The three DAGEN units (X, Y, and C) can be configured to use linear or
circular addressing modes for an instruction using an indirect addressing
mode.
See Chapter 6 for more details on addressing modes and memory operands.

1.4.2 A-Unit Arithmetic Logic Unit (AU ALU)

The A unit contains a 16-bit arithmetic and logic unit (AU ALU) which enables
data processing in synchronism and in parallel with the D-unit operators. The
A unit performs the following actions:
Additions, subtractions, comparisons, saturations, signed shifts, and
absolute value calculations
Bitwise AND/OR/XOR complement operations, logical shifts, and rotation
operations
Bit tests, sets, clears, and complements of A-unit registers or memory
operands
Register content moves, rotations, and modifications
Moves of DU SALUx shifter result to an A-unit register
1.4.3 A-Unit Registers

The A unit contains and uses the registers listed below:
The number of auxiliary registers (XARx) has been increased from 8 to 16.
When the source code of previous revisions using the CDP register is
recompiled for C55x+ revision, it uses the XAR15 register instead. All of
these registers can accept immediate data from the I unit and can accept
data from or provide data to the D-unit registers, the P-unit registers
(through AU ALU), and data memory.
Within the A unit, the registers have bidirectional connections with the
DAGEN units and the AU ALU.
Data Page Registers
XDP(DPH DP) Data page registers
PDP Peripheral data page register, only avail-
able in word-pointer mode
Pointers
XSP (SPH SP), XSSP(SSPH: SSP) Stack pointer registers
XAR0–XAR15 Auxiliary registers
Previous coefficient data pointer register
(XCDP) has been mapped to the XAR15
register
AR8−AR14 cannot be used as circular
pointers
AR8−AR14 are not mapped in the
memory-mapped register (MMR) space

Circular Buffer Registers

BK03, BK47, BKC Circular buffer size registers
BSA01, BSA23, BSA45, BSA67, BSAC Circular buffer start address registers
(BKC and BSAC are used for circular
addressing with the XAR15 register)
Temporary Registers
T0–T3 Temporary registers 0, 1, 2, and 3

Data Computation Unit (D Unit)
1.5 Data Computation Unit (D Unit)

The D unit contains the primary computational units of the CPU. Figure 1−5
shows a conceptual block diagram of the D unit. Sections 1.5.1 through 1.5.4
describe the main parts of the D unit.
Figure 1−5. Data Computation Unit Diagram
Data-Read Data Buses BB (32 Bits of Data), CB, DB (16 Bits of Data)
D Unit
P Unit
D Unit
Registers
Memory
Interface
DU SALU2 DU SALU1
Unit
MAC1 MAC2
ACx Write Buses ACx Read Buses
DU BIT
A Unit
KX1 Bus KX2 Bus

I Unit

1.5.1 Shifter and D-Unit Arithmetic Logic Units (DU SALU1, DU SALU2)
The C55x+ revision introduces some changes in the D-unit modules. The
previous D-unit arithmetic logic unit (DU ALU) has been merged with the
previous D-unit shifter (DU SFT), and duplicated to form the two identical DU
SALU1 and DU SALU2 units. These two units, when operated in parallel, can
generate up to 12 results per cycle.
For example, in using the following instruction, you can perform four 16-bit
elements (low and high parts of accumulators) maximum search in parallel in
one cycle. When the following two instructions are executed in parallel:
max_diff(AC0, AC1, AC2, AC3, pair(TRN0))
|| max_diff(AC4, AC5, AC6, AC7, pair(TRN2))
AC3.H, AC3.L, AC7.H, and AC7.L contain the result of the following four
differences: AC1.H−AC0.H, AC1.L−AC0.L, AC5.H−AC4.H,
AC5.L−AC4.L, respectively.
AC2.H, AC2.L, AC6.H, and AC6.L contain the maximums of each of the
following four pairs: AC1.H−AC0.H, AC1.L−AC0.L, AC5.H−AC4.H,
AC5.L−AC4.L, respectively.
TRN1, TRN0, TRN2, and TRN3 track which of the AC1.H, AC0.H, AC1.L,
AC0.L, AC5.H, AC4.H, AC5.L, AC4.L source registers, respectively, were
found as the maximum of the above comparisons.
In case of parallel instruction execution, each unit is dedicated to its own

instruction slot. DU SALU1 is dedicated to instruction1 and DU SALU2 is
dedicated to instruction2.
Each DU SALU unit accepts its own immediate values from the I-unit (through
the KX1 and KX2 buses) and the A-unit registers. It also communicates
bidirectionally with memory and I/O space.
Each DU SALU unit performs the combined actions of previous architecture

revision DU shifter and DU ALU units. Each DU SALU:
Performs additions, subtractions, comparisons, rounding, saturation,

bitwise logical operations, and absolute value calculations.
Performs two arithmetical operations simultaneously when a dual 16-bit

arithmetic instruction is executed.
Tests, sets, clears, and complements D-unit register bits.
Moves register values.

Shifts 40-bit accumulator values to the MSBs by up to 31 bits or to the

LSBs by up to 32 bits.
The shift quantity can be read from one of the temporary registers (T0–T3)
or from one of the lowest 16 bits of the 8 first accumulators (AC0.L to
AC7.L). It can also be supplied as a constant in the instruction.
The shift target can be a 40-bit accumulator or a 16-bit register, memory
location, I/O space location, or a 16-bit immediate value supplied in the
instruction.
In the case of shift of immediate values, this shift quantity is always
specified as an immediate value in the instruction and shifts the MSBs by
up to 15 bits.
Rotates register values.
Rounds and/or saturates accumulator values before they are stored to

data memory.
Cascades shift operations with additions and subtractions in single cycle

instructions.
For C54x DSP-compatible mode (C54CM = 1), the overflow detection is only
performed for the final operation of a calculation. For C55x-DSP-native mode
(C54CM = 0), the overflow detection is performed on each operation (shifting,
rounding, and addition/subtraction).
1.5.2 Two Multiply-and-Accumulate Units (DU MAC1 and DU MAC2)

Two multiply-and-accumulate units (DU MAC1 and DU MAC2) support
multiplication and addition (or subtraction).
In a single cycle, each MAC can perform a 17x17-bit signed multiplication

(fractional or integer) and a 40-bit accumulation (or subtraction) with optional
32-bit (or 40-bit) saturation. Fractional multiplication and 40-bit saturation can
be performed independently on each instruction slot.
For each of the two MACs, the multiplier operand can be:
A 16-bit immediate value from the I unit (through the KX1 or KX2 internal
bus)
A 16-bit data value from memory or I/O space
A 16-bit A-unit register (Tx)
A 16-bit value extracted from the D-unit 40-bit accumulators (bits 0 to 15

or 16 to 31)

A 17-bit value extracted from the D-unit 40-bit accumulators (bits 16 to 32)
For each of the two MACs, the accumulation input operand can be any of the
16 D-unit 40-bit accumulator registers. All MAC results are stored in the D-unit
accumulators. The P-unit status registers bits are affected by the MAC
operations when an overflow is reported during a multiply and accumulate (or
subtract) operation.
In order to provide the most accurate saturated result on 32 bits, DU MACx

overflow detection can be performed for the final result of a multiply and
addition (or subtraction) instruction with intermediate computation on 40 bits.
1.5.3 D-Unit Bit Manipulation Unit (DU BIT)

The C55x+ revision features a D-unit module (DU BIT) which performs bit
manipulation operations in parallel with all arithmetic operations performed in
the DU SALUx or DU MACx units. The DU BIT unit can perform one bit
manipulation regardless of its position in a paralleled instruction pair. In
addition, it also supplies values to the DU ALU (as an input for further
calculation) and to the A unit through the AU ALU module.
The DU BIT unit performs the following operations:
Normalizes accumulator values.

Extracts, expands, and inserts bit fields.
Performs bit counting.

Table 1−1. Instructions Performed in D-Unit BIT Unit

Instructions Examples Comment
AC3.L = exp(AC13) Computes the number of leading bits of the AC13 register
and stores it in the AC3.L register so that AC13 can be
normalized as a 1Q13 number with the following instruction:
AC2 = AC13 << AC3.L
AC3.L = −exp(AC13), Computes the mantissa of the AC13 register in the AC2 reg-
AC2 = mant(AC13) ister and the exponent of AC13 in the AC3.L register. (AC3.L
will have the opposite value compared to the above exam-
ple, if AC13 is different from zero.)
T3 = field_expand(AC7.L,#05555h) According to the bit set to 1 in the 16-bit field mask (05555h),
AC7 source accumulator bits 0 to 15 are extracted, sepa-
rated with 0s towards the MSBs, and stored in T3. In this
example, T3 contains the 8 lowest bits of AC7, each sepa-
rated with 0.
AC7 = field_extract(AC8.L,#05555h) According to the bit set to 1 in the 16-bit field mask (05555h),
AC8 source accumulator bits 0 to 15 are extracted, packed
towards the LSBs, and stored in AC3. In this example, the 8
lowest bits of T3 contains the AC7.L even bits packed to the
LSBs.
ACL11.L = field_insert Combines the two complementary subfields of 16-bit regis-
(AC3.L,AC0.H,*AR14) ters AC11.L and AC3.L in order to update AC11.L with a new
16-bit constructed value.
The indirect addressing mode *AR14 defines the bit position
where the bit mask defined in AC0.H is used to extract the
to-be-kept bits of AC11.L.
The bits of AC3.L shifted to the MSBs by the AR14 value
and, corresponding to the bits of AC0.H which have been
discarded, are extracted and inserted at the free locations
into AC11.H.
T3 = count(AC0, AC1, TC1) Counts the number of bits set to 1 in the ANDed value of
AC0 and AC1, and stores it into T3. TC1 contains the parity
bit of T3.
Please see the C55x+ instructions set guide (TI Lit SWPU###) for more details
on instructions description.
1.5.4 D-Unit Registers

The D unit contains multiple and undifferentiated 40-bit accumulators that can
be used as source and destination of instructions executed in the DU SALUx,
DU MACx, DU BIT unit, or the AU ALU. They also can be used in instructions
performing load/store from/to memory, and in instructions performing register
initializations with immediate values. For example, you can initialize two
accumulators within one cycle in using the following instruction:

AC13 = #-1
|| AC7 = #0a8f7h
The number of accumulators has been increased from 4 to 16 in the C55x+

revision. The flexible instruction set programs these registers as 16
independent 40-bit (or 32-bit) registers, or 32 independent 16-bit registers.
In the following example showing a standard addition instruction, you can

choose the Ra register to be any of the 40-bit accumulators AC0 to AC15. In
that case, the CPU performs an addition with overflow detection on 40 or
32 bits depending on the state of certain status bits. Or you can also choose
the Ra register to be any of the 16-bit accumulator subparts AC0.L/AC0.H to
AC15.L/AC15.H. In that case, the CPU performs an addition with overflow
detection on 16 bits. (Note that only the designated 16 bits of the Ra register
are updated after the execution of the instruction.)
Ra = Ra + Rb
The number of transition registers has been also increased in the C55x+
revision from two to eight. These registers can be used in compare and select
extremum instructions for hard decision tracking in the Viterbi Algorithm.
In the C55x+ revision, the transition registers are mapped to the low and high
part of four accumulators (see details in the D-unit table) in order to enable their
efficient storage in all standard instructions operating on accumulators. (See
the C55x+ instructions set guide, Lit number ### for more details on compare
and select extremum instruction descriptions.)
Within one cycle, up to six different accumulators can be written to in parallel

with the read of six different other accumulators. The following instruction
sequence illustrates this D-unit architecture efficiency and flexibility.
During cycle #1 in X2 phase (see Section 1.7 for pipeline phases description),
six ACx accumulators are written: AC10, AC11, AC12, and AC13 as standard
SALUx output; AC14 and AC15 for TRNx registers update.
Also, six ACx accumulators are read: AC0, AC1, AC3, AC4, AC7, and AC9.
|| max_diff(AC12, AC13, AC12, AC13, pair(TRN2)) ;cycle #1
AC0 = AC0 + (AC1 <<AC2.L)
|| AC3 = AC3 + (AC4 << AC5.L) ;cycle #2
AC6 = AC6 + (AC6 << AC7.L)
|| AC8 = AC8 +(AC8 << AC9.L) ;cycle #3

D-unit registers
Accumulators
AC0–AC15 Accumulators 0−15, with high and low part of accumula-
tors accessible independently.
Transition Registers
TRN0−TRN7 Transition registers 0−7 are mapped to the low and high
parts of the following accumulators:
TRN0 mapped to AC15_H
TRN1 mapped to AC15_L

Address Buses and Data Buses
1.6 Address Buses and Data Buses

The CPU is supported by one 64-bit program bus (PB), two 16-bit data-read
buses (CB, DB), one 32-bit data-read bus (BB), two 16-bit data-write buses
(EB, FB), one 24-bit program-read address bus (PAB), and five 24-bit
data-address bus (BAB, CAB, DAB, EAB, FAB). This parallel bus structure
enables up to a 64-bit program read, four 16-bit data reads, and two 16-bit data
writes per CPU cycle. Table 1−2 describes the functions of the 12 buses, and
Table 1−3 through Table 1−5 show which bus or buses are used for a given
access type.
Note:
In the event of a dual data write to the same address, the result is undefined.

Table 1−2. Functions of the Address and Data Buses

Bus(es) Width Function
PAB 24 bits The program-read address bus (PAB) carries a 24-bit byte address for a read from
program space.
PB 64 bits The program-read data bus (PB) carries 8 bytes (64 bits) of program code from program
memory to the CPU.
CAB, DAB 24 bits Each of these data-read address buses carries a 24-bit byte address. DAB carries an
each address for a read from data space or I/O space. CAB carries a second address during
dual data reads (see Table 1−3).
CB, DB 16 bits The CB data-read bus carries a 16-bit data value and the DB data read bus carries a 16-bit
data value to the CPU. The DB bus carries a value from data space or from I/O-space.
The CB bus carries a second value during long data reads and dual data reads (see
Table 1−3).
BAB 24 bits This data-read address bus carries a 24-bit byte address for a coefficient read. All
instructions that use the coefficient indirect addressing mode Cmem use the BAB bus to
reference coefficient data values and use the BB bus to carry the data values. Only
multiply (and accumulate/subtract) instructions use Cmem addressing modes.
BB 32 bits This data-read data bus carries a 16-bit or 32-bit coefficient data value from internal or
external memory to the DU MAC1 or MAC2. Data carried by the BB bus is addressed
using the BAB bus.
Specific dual MAC instructions use the 3 data-read buses BB, CB, and DB to provide, in
one cycle, three or four 16-bit operands to the DU MAC1 and DU MAC2. In the example
below, AR1 and AR2 registers fetch two 16-bit data values through the CB and DB buses,
and AR10 register fetches one 32-bit value through the BB bus:
AC0 = *AR1 * LO(*AR10), AC3 = *AR2 * HI(*AR10)
More flexible parallelism combines specific dual MAC instructions with other standard
instructions to distribute the four 16-bit operands across various CPU units. In the
example below, AR1 register fetches one 32-bit data value through the CB and DB buses,
and AR10 fetches a second 32-bit data value through the BB bus:
AC0 = AC1.L * LO(AR10), AC3 = AC1.H * HI(*AR10)
||AC4 = AC4 + dbl(*AR1)
EAB, FAB 24 bits Each of these data-write address buses carries a 24-bit byte address. The EAB bus
each carries an address for a write to data space or I/O space. The FAB bus carries a second
address during dual data writes (see Table 1−3).
EB, FB 16 bits Each of these data-write data buses carries a 16-bit data value from the CPU. The EB bus
each carries a value to data space or to I/O-space. The FB bus carries a second value during
long data writes and dual data writes (see Table 1−3).

Table 1−3. Bus Usage By Single Access

Access Type Address Data Description
Bus(es) Bus(es)
Instruction fetch PAB PB 64-bit read from program space
Single byte data read DAB DB 8-bit read from data memory in byte-pointer mode
Single data read DAB DB 16-bit read from data memory
Single MMR read DAB DB 16-bit read from a memory-mapped register (MMR) in
word-pointer mode. (If there is no MMR read in byte-
pointer mode, then see Chapter 7 for byte-pointer
mode details.)
Single byte I/O read DAB DB 8-bit read from I/O space in byte-pointer mode
Single I/O read DAB DB 16-bit read from I/O space
Single (or long) coefficient BAB BB 16-bit (or 32-bit) read from internal memory with the
read coefficient (or double coefficient) indirect addressing
mode using the BAB and BB buses.
Single (or long) data read DAB CB, DB 32-bit read from data memory
Single (or long) MMR read DAB CB, DB 32-bit read from one 32-bit MMR or two adjacent 16-bit
MMRs in word-pointer mode. (If there is no MMR read
in byte-pointer mode, then see Chapter 7 for byte-
pointer mode details.)
Single byte data write EAB EB 8-bit write to data memory in byte-pointer mode
Single data write EAB EB 16-bit write to data memory
Single MMR write EAB EB 16-bit write to a memory-mapped register (MMR) in

word-pointer mode. (If there is no MMR read in byte-
pointer mode, then see Chapter 7 for byte-pointer
mode details.)
Single byte I/O write EAB EB 8-bit write to I/O space in byte-pointer mode
Single I/O write EAB EB 16-bit write to I/O space
Single (or long) data write EAB EB, FB 32-bit write to data memory
Single (or long) MMR write EAB EB, FB 32-bit write to one 32-bit MMR or two adjacent 16-bit
MMRs in word-pointer mode. (If there is no MMR read
in byte-pointer mode, then see Chapter 7 for byte-
pointer mode details.)

Table 1−4. Bus Usage By Dual Access Type

Bus(es) Bus(es)
Single byte data read CAB, DAB CB, DB Two simultaneous 8-bit reads from data space in byte-
|| Single byte data read pointer mode:
The first operand read uses the DAB and DB buses.
This read can be from data memory or from I/O
space.
The second operand read uses the CAB and CB
buses. This read must be from data memory.
Single byte data read CAB, DAB CB, DB The following two operations happen in parallel in byte-
|| Single data read pointer mode:
Single byte data read: 8-bit read from data memory
using the DAB and DB buses.
Single data read: 16-bit read from data memory us-
ing the CAB and CB buses.
Single byte data read DAB, BAB DB, BB The following two operations happen in parallel in byte-
|| Long coefficient read pointer mode:
Long coefficient read: 32-bit read from internal
memory with the double coefficient indirect address-
ing mode using the BAB and BB buses.
Single byte data read DAB, EAB DB, EB The following two operations happen in parallel in byte-
|| Single byte data write pointer mode:
Single byte data write: 8-bit write to data memory us-
ing the EAB and EB buses.
Single byte data read DAB, EAB DB, EB, The following two operations happen in parallel in byte-
|| Single (long) data write (FB) pointer mode:
Single data write: 16-bit (or 32-bit) write to data
memory using the EAB and EB (and FB) buses.

Table 1−4. Bus Usage By Dual Access Type (Continued)

Bus(es) Bus(es)
Single byte data write EAB, FAB EB, FB Two simultaneous 8-bit writes to data space in byte-
The first operand write uses the FAB and FB buses.
This write must be to data memory.
The second operand write uses the EAB and EB
buses. This write must be to data memory or I/O
space.
Single byte data write EAB, FAB EB, FB The following two operations happen in parallel in byte-
|| Single data write pointer mode:
ing the FAB and FB buses.
Single data write: 16-bit write to data memory using
the EAB and EB buses.
Single data write EAB, FAB EB, FB Two simultaneous 16-bit writes to data space.
|| Single data write
The first operand write uses the FAB and FB buses.
This write must be to data memory.
The second operand read uses the EAB and EB
buses. This write can be to data memory, an MMR,
or I/O space.
Single data read CAB, DAB CB, DB Two simultaneous 16-bit reads from data space.
|| Single data read
The first operand read uses the DAB and DB buses.
This read can be from data memory, an MMR, or I/O
space.
The second operand read uses the CAB and CB
buses. This read must be from data memory.
Single (or long) data read DAB, BAB (CB), The following two operations happen in parallel:
|| Long coefficient read DB, BB
Single (or long) data read: 16-bit (or 32-bit) read from
data memory using the DAB and DB (and CB) buses.

Table 1−4. Bus Usage By Dual Access Type (Continued)

Bus(es) Bus(es)
Single (or long) data read DAB, EAB (CB), The following two operations happen in parallel in byte-
|| Single byte data write DB, EB pointer mode:
Single (or long) data read DAB, (CB), The following two operations happen in parallel:
|| Single (or long) data write EAB, DB, EB,
(FB)
Single (or long) data write: 16-bit (or 32-bit) write to
data memory using the EAB and EB (and FB) buses.
Long coefficient read BAB, EAB BB, EB The following two operations happen in parallel in byte-
Long coefficient read BAB, EAB BB, EB The following two operations happen in parallel in:
|| Single (or long) data write
Single (or long) data write: 16-bit (or 32-bit) write to
data memory using the EAB and EB (and FB) buses.

Table 1−5. Bus Usage By Triple Access Type

Bus(es) Bus(es)
Single data read CAB, DAB, CB, DB, The following operations happen in parallel:
|| Single data read BAB BB
Dual data read: Two simultaneous 16-bit reads
|| Single (or long) coefficient
from data space. The first operand read uses the
data read
DAB and DB buses. The second operand read
uses the CAB and CB buses.
Single (or long) coefficient data read: 16-bit (or
32-bit) read from internal memory with the coeffi-
cient (or double coefficient) indirect addressing
mode using the BAB and BB buses.
Single data read CAB, DAB, CB, DB, The following operations happen in parallel in byte-
|| Long coefficient read BAB BB pointer mode:
|| Single byte data read
Dual data read: Simultaneous single data read
(16-bit read from data memory using the DAB and
DB buses) and long coefficient data read (32-bit
read from internal memory with the double coeffi-
cient indirect addressing mode using the BAB and
BB buses).
using the CAB and CB buses.
Single (or long) data read || DAB, BAB, (CB), DB, The following operations happen in parallel in byte
Long coefficient read EAB BB, EB pointer mode:
|| Single byte data write
Dual data read: Simultaneous single (or double)
data read (16-bit (or 32-bit) read from data memory
using the DAB and DB (and CB) buses) and long
coefficient data read (32-bit read from internal
memory with the double coefficient indirect ad-
dressing mode using the BAB and BB buses).
Single byte data write: 8-bit write to data memory
using the EAB and EB buses.
Single (or long) data read DAB, BAB, (CB), DB, The following operations happen in parallel:
|| Long coefficient read EAB, BB, EB,
Dual data read: Simultaneous single (or long) data
|| Single (or long) data write (FB)
read (16-bit (or 32-bit) read from data memory us-
ing the DAB and DB (and CB) buses) and long co-
efficient data read (32-bit read from internal
memory with the double coefficient indirect ad-
dressing mode using the BAB and BB buses).
Single (or long) data write:16-bit (or 32-bit) write to
data memory using the EAB and EB (and FB)
buses.

Table 1−6 lists some examples of instructions accessing buses by single- or

double- or triple-access types.
Table 1−6. Bus Usage Access Type Examples

Instruction Syntax Bus Usage Access Type
ACx = byte(Smem) Single byte data read

|| ACx = Smem || Single data read

|| Smem = ACx || Single data write

|| dbl(Smem) = ACx || Long data write
ACa = m40(rnd(frct(uns(ACc.L)*uns(LO(Cmem))))), Single data read

ACb = m40(rnd(frct(uns(ACc.H)*uns(HI(Cmem))))) || Long coefficient read
|| ACx = Smem
ACx = dbl(Smem) Long coefficient read

|| AC2 = AC2 + (uns(AC4.L)*LO(coef(*AR1+))), || Long data write
AC3 = AC3 + (uns(AC4.H)*HI(coef(*AR1+)))
ACa = m40(rnd(frct(uns(Xmem)*uns(Cmem)))), Single data read

ACb = m40(rnd(frct(uns(Ymem)*uns(Cmem)))) || Single data read
|| Single coefficient read
ACa = m40(rnd(frct(uns(Smem)*uns(LO(Cmem))))), Single data read

ACb = m40(rnd(frct(uns(Smem)*uns(HI(Cmem))))) || Long coefficient read
|| ACx = byte(Smem) || Single byte data read
ACa = m40(rnd(frct(uns(Smem)*uns(LO(Cmem))))), Single data read

ACb = m40(rnd(FRAT(uns(Smem)*uns(HI(Cmem))))) || Long coefficient read
|| Smem = ACx || Single data write
ACa = m40(rnd(frct(uns(LO(Smem))*uns(LO(Cmem))))), Single (or long) data read

ACb = m40(rnd(FRAT(uns(HI(Smem))*uns(HI(Cmem))))) || Long coefficient read
|| dbl(Smem) = ACx || Single (or long) data write

Instruction Pipeline
1.7 Instruction Pipeline

The C55x+ DSP CPU uses instruction pipelining. The C55x+ revision
introduces a deeper pipeline with four additional phases to enable a higher
operating clock frequency. Section 1.7.1 introduces the pipeline and the new
phases, and Section 1.7.2 describes how the CPU prevents conflicts that
might otherwise occur in the pipeline.
1.7.1 Pipeline Phases

The C55x+ DSP instruction pipeline is a protected pipeline that has two
decoupled segments:
The first segment, referred to as the program fetch pipeline, fetches 64-bit
instruction packets from memory, places them in the IU IBQ, and then
feeds the second pipeline segment with 128-bit instruction packets. The
program fetch pipeline is illustrated in Figure 1−6.
The second segment, referred to as the execution pipeline, decodes and

executes instructions. The execution pipeline is illustrated in Figure 1−7
where the pipeline phases have been regrouped to highlight the five
functional steps required to execute an instruction or a pair of parallel
instructions. The five functional steps are:
Instructions decoding phases (PD1, PD2, D)
Data address computation phases (AD1, AD2)
Data memory read access phases (AC1, AC2, R)
Data processing phases (R, X1, X2, W1)
Data memory write access phases (W1, W2, W3)
Sections 1.7.1.2 through 1.7.1.6 provide examples to help you understand
the activity in the key phases of the execution pipeline. The activity
description is detailed for each of the five functional steps of the execution
pipeline.

Figure 1−6. First Pipeline Segment: Program Fetch Phases
Prefetch 1 Prefetch 2 Fetch

(PF1) (PF2) (F)
Time
1.7.1.1 Program Fetch Phases Description
Pipeline Phase Operating Unit Activity Description
PF1 I unit Present program address to memory.
Branch Instructions Branch prediction mechanism is activated at each cycle to de-

tect if the conditional or unconditional branch program address
is stored in the history buffer or not.
If it is present, then the prediction occurs and the CPU begins
to prefetch in memory the corresponding predicted branch tar-
get instruction packet.
If it is not present, then the prediction does not occur and the
CPU waits for branch instruction decoding to obtain the branch
target address.
PF2 I unit Wait for memory to respond.
Branch Instructions No activity
F I unit Store the fetched instruction packet from memory into the IU
IBQ.
Figure 1−7. Second Pipeline Segment: Execution Pipeline Phases

Data Address Computation Phases Data Processing Phases
Predecode Predecode2 Decode Address1 Address2 Access1 Access2 Read Execute1 Execute2 Write1 Write2 Write3
PD1 PD2 D AD1 AD2 AC1 AC2 RD X1 X2 W1 W2 W3
Instructions Decoding Phases Data Memory Read Access Phases Data Memory Write Access Phases
Time
NOTE: Only for actual memory accesses (AC2 for reads, W3 for writes)

1.7.1.2 Instructions Decoding Phase Description
PD1 I unit Predecode instructions in the IU IBQ (identify where instructions

begin and end, and identify parallel instructions).
PD2 I unit Separate instruction1 and instruction2, and change program

flow when control instructions are detected (goto, call,
return).
D I unit Read 16 bytes from the IU IBQ.

Decode an instruction pair or single instruction; decode ad-
dressing mode fields and decode instruction source and des-
tination fields to detect conflict for the pipeline protection unit.
Dispatch instructions to the appropriate CPU functional units as
follows:
− Sequentially
− Repeatedly (repeat single or block of instructions)
− By branching (goto, call, return, interrupt in-
structions)
Branch Instructions Decode branch instruction in case of unconditional call/branch

instructions:
1) If the prediction occurred:
Compare extracted branch target instruction with the predicted
branch target instruction in order to verify the prediction.
−If the prediction is correct, then continue the execution of the
target instruction in the next cycle.
− If the prediction is not correct, then start prefetching the correct
2) If the prediction did not occur:
Start prefetching the extracted target instruction in the next
cycle.
Decode branch instruction in case of other call/branch instruc-
tions.

1.7.1.3 Data Address Computation Phases
AD1 AU DAGEN Read STx_55 bits associated with data address generation:
ST1_55(C54CM), ST2_55(ARnLC), ST2_55(CDPLC).
Read register or load address constant involved in the address
calculation.
Detect address phase resource conflicts.
MMR Access No activity
Conditional Executions Read and evaluate the condition of the execute (AD-unit) in-
struction.
Branch Instructions Conditional return/call/goto/if (ARn[mod] !=0)

goto instructions: Read the register involved in the condi-
tion evaluation.
Special Instructions No activity
AD2 AU DAGEN Perform address calculation and modify registers involved in

data address generation. For example:
− ARx in *(ARx + T0), SP during pushes and pops, SSP for call
instructions in the 32-bit stack mode.
Load with an immediate value auxiliary registers (XARx), cir-
cular registers (BKxx, BSAxx, BRCx, CSR, etc.).
Forward address computation result to the next instruction if
allowed.
MMR Access Detect indirect memory-mapped register (MMR) access.
Conditional Executions In case of conditional execute (AD_unit) instruction and

false condition:
− Suspend the execution of the parallel instruction.
− Replace the following instruction in the pipeline with NOP in-
struction (Null operation)

Branch Instructions Conditional return/call/goto/if (ARn[mod] !=0)

goto instructions: Evaluate the condition.
Compare the extracted branch target instruction with the pre-
dicted branch target instruction in order to verify the prediction.
− If the prediction is correct, then continue the execution of the
− If the prediction is not correct, then start prefetching the cor-
rect target instruction in the next cycle.
− Start prefetching the extracted target instruction in the next
cycle.
Modify AR register involved in if(ARn[mod] !=0) goto
instruction.
Special Instructions Read, process, and write back TAx registers in the case of
swap instructions.
1.7.1.4 Data Memory Read Access Phases
AC1 Memory Access Issue requests and data memory address for operand read,
and send them on the appropriate data buses.
AC2 Memory Access Allow one cycle for physical memory to read the data
RD Memory Access Capture memory operand from the relevant data read bus.
MMR access Read memory mapped registers.

1.7.1.5 Data Processing Phases
RD LOAD/STORE No activity
Conditional Executions No activity
Common to all proc- Read STx_55 bits that affects AU and DU instructions.
essing units
ACx are read in the RD phase. However, the data forwarding
mechanism considers these reads to be accomplished in the
X1 phase as described below.
Exceptions include:
− DU SALUs, exp(), −exp(), mant() instructions.
− Other exceptions are listed in Table 1−4.
DU MACs Read TAx and memory data.
DU SALUs Read TAx and memory data.

Read ACx when used as shift quantity.
DU BIT Read TAx and memory data.
AU ALU No activity
Special Instructions Read ACx in case of: exp(), −exp(), mant() instructions.
Read TCx in case of adsc() or ads2c() instructions.
X1 LOAD/STORE STORE: Read ACx.
Conditional Executions Read and evaluate the condition of the execute (D_unit)
instruction.
DU MACs Read ACx; Execute accumulator optional shift by 16 to the

LSBs and multiplication operations.
DU SALUs Read ACx; Perform shift operations.
DU BIT Read ACx; First stage for BIT operations.
AU ALU Read DU/AU registers.

Branch Instructions Read ACx in case of unconditional goto ACx instruction.

− If the prediction is not correct, then start prefetching correct
cycle.
Read register involved in the compare (uns(src RELOP
K8) goto instruction.
Special Instructions No activity
X2 LOAD/STORE LOAD: Write to register.

STORE: Export data to memory interface.
Conditional Executions In case of conditional execute(D_unit) instruction and

false condition:
− Suspend the parallel instructions.
− Replace the instructions in the pipeline with NOP instruc-
tions.
DU MACs Perform final additions.
DU SALUs Perform ALU operations.
DU BIT Second stage for BIT operations.
AU ALU Perform ALU operations.
Common to all proc- Update destination registers.

essing units
Update STx_55 flags.
Forward data to the next instruction if allowed (see Sec-
tion 1.7.2 for more details on data forwarding).

Branch Instructions Execute compare(uns(src RELOP K8)) goto instruc-

tion:
− If the prediction is not correct, then start prefetching correct
cycle.
Special Instructions Write to ACx/ARx/TRx in case of exp(), −exp(), mant(),

count(), field_extract(), field_expand(),
Read, process, and write back of ACx in case of swap instruc-
tion.
Read and update of TRNs registers when min/
max_diff(_dbl) instruction is executed.
1.7.1.6 Data Memory Write Access Phases
Pipeline Phase Operating Unit Description
W1 Memory Access Issue request and data memory address to the appropriate
CPU write buses.
MMR Access Write to memory-mapped registers.
W2 Memory Access Present the data to write on the relevant write bus.
W3 Memory Access Allow one cycle to the physical memory to write the data.
Table 1−7 lists some exceptional cases where ACx accumulator read data for-
warding from R phase to X1 phase does not occur.

Table 1−7. Data Forwarding Exception Table Examples
Sequence Syntax Example and Exception Description
ACx register read data forwarding rule does not apply when swap() instruction is used. This instruction se-
quence is executed in 4 cycles:
swap (ACx, ACy) ; Writes to ACx and ACy in X2 phase
ACx = ACx +#k ; Read ACx in RD phase with no data forwarding in X1 phase
Register data forwarding does not apply when AC12 to AC15 registers are read after TRN0 through TRN8
have been updated by min/max_diff[_dbl()] instructions. This instruction sequence is executed in
4 cycles:
min/max_diff(ACa, ACb, ACc, ACd, TRN0) ; Write AC15_H(TRN0) in X2 phase
AC15 = AC15 +#k ; Read AC15 in RD phase with no data forwarding in
; X1 phase
ACx register read data forwarding rule does not apply, as ACx is updated with an MMR write operation. This
instruction sequence is executed in 5 cycles:
mmap(@ACx_L) = #k ; Write ACx in W1 phase
ACx = ACx +#k ; Read ACx in RD phase with no data forwarding in X1 phase

Table 1−8 illustrates the pipeline activity with some instructions execution ex-
amples.
Table 1−8. Examples to Illustrate Execution Pipeline Activity

Example Syntax Pipeline Activity Explanation
mar(XARx = #k23) XARx is initialized with a constant and is updated in AD2 phase.
ARx = #k ARx is not MMR-addressed. ARx is initialized with a constant

and is updated in X2 phase.
mmap() || @ARx =#k ARx is MMR-addressed in W1 phase. ARx is initialized with a

constant in the W1 phase.
mar(ARx + #k) With this special instruction, ARx is added with a constant and
is updated in AD2 phase.
*ARx+ = #k The actual memory location pointed by ARx is updated in the

W3 phase.
AC0 = *ARx+ ARx is read in the AD1 phase, and is updated in the AD2 phase.
AC0 is loaded with the data memory location pointed by ARx
in the X2 phase.
ARx = ARx + #k ARx is read at the beginning of the X1 phase and is modified
at the end of the X2 phase.
ACx = ACy + ACx ACx and ACy are read in the X1 phase. ACx is updated in the
X2 phase.
ACx = @ARx || mmap() ARx is MMR-addressed and is read in the R phase. ACx is
modified in the X2 phase.
ACx = ARx ARx is not MMR-addressed and is read in the R phase. ACx
is modified in the X2 phase.
push(), pop(), return, SP is read in the AD1 phase and is modified in the AD2
mar(SP + #k8) phase. SSP is also affected if the 32-bit stack mode is se-
lected.
if(overflow(ACx)) execute(AD_unit) The condition is evaluated in the X1 phase.

|| AC1 = *AR1+ Note: AR1 is incremented only if the condition is true.
if(overflow(ACx)) execute(AD_unit) The condition is evaluated in the X1 phase.

|| *AR1+ = AC1 Note: AR1 is incremented only if the condition is true.
if(overflow(ACx)) execute(D_unit) The condition is evaluated in the AD1 phase.

|| AC1 = *AR1+ Note: AR1 is incremented regardless of wether the condition
is true or not.

1.7.2 Pipeline Protection

Multiple instructions are executed simultaneously in the pipeline, and different
instructions perform modifications to memory, I/O space, and register values
during different phases of completion. In an unprotected pipeline, this could
lead to pipeline conflicts—reads and writes at the same location occurring out
of the intended order. However, the C55x+ DSP pipeline has a mechanism that
automatically protects against pipeline conflicts. The pipeline-protection
mechanism adds inactive cycles between instructions that would cause con-
flicts.
Most pipeline-protection cycles are inserted based on two rules:
If an instruction is supposed to write to a location but a previous instruction
has not yet read from that location, then extra cycles are inserted so that
the read occurs first.
If an instruction is supposed to read from a location but a previous
instruction has not yet written to that location, then extra cycles are
inserted so that the write occurs first.
If an MMR access is detected as a result of address calculation, then an
additional cycle is inserted in order to have extra time to decode the MMR
address and detect the conflict.
In a repeat loop context, if an instruction, such as a load instruction
updating the repeat context, is right before the repeat instruction, then an
extra cycle is inserted in order to avoid any conflict in the repeat
mechanism.
Note:
The pipeline-protection mechanism cannot prevent pipeline conflicts
between two instructions that are executed in parallel.
The C55x+ pipelined architecture features a pipeline protection mechanism

which avoids pipeline conflicts for a large set of code sequences used in typical
digital signal processing algorithms, called data forwarding mechanism.
The following examples illustrate this pipeline protection mechanism:
AC1 = *AR1+ ; cycle #0
AC0 = *AR1+ || AC1 = max(AC0, AC1) ; cycle #1
None of these instructions in the above example will generate a pipeline stall.
Although each of the move instructions (from memory to AC0/AC1

accumulators) increments the AR1 register by reading its content in the AD1
phase and writing it back in the AD2 phase, the data forwarding mechanism
of the AU DAGEN module executes this sequence of instructions without any
pipeline stalls. Similarly, although each of the max instructions reads AC1
accumulator content in the X1 phase and writes to AC1 accumulator in the X2
phase, the data forwarding mechanism of the DU SALU executes this
sequence of instructions without any pipeline stalls as well.
Finally, although each of the max instructions reads AC0 and AC1 accumula-
tors content in the X1 phase and each of the load instructions writes to AC0
or AC1 accumulator in the X2 phase, the data forwarding mechanism occur-
ring between DU register files module, and DU SALU units, executes this se-
quence of instructions without any pipeline stalls occurring in the D unit.
All in all, this sequence is executed in five cycles only.
See the C55x+ instructions set TI document (LIT ####) for more details about
the data forwarding mechanism.

Chapter 2
CPU Registers
This chapter describes the main registers in the C55x+ DSP CPU. Section 2.1
lists the registers in alphabetical order, and Section 2.2 shows the register IDs,
and their corresponding memory-mapped addresses (when available). The
other sections contain additional details about the CPU registers.
Topic Page
2.1 Alphabetical Summary of Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.2 Memory-Mapped Registers and Register ID Concept . . . . . . . . . . . . . 2-4
2.3 Accumulators (AC0−AC15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.4 Transition Registers (TRN0−TRN7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.5 Temporary Registers (T0−T3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.6 Registers Used to Address Data Space and I/O − xI/O Spaces . . . 2-17
2.7 Program Flow Registers (PC, RETA, CFCT) . . . . . . . . . . . . . . . . . . . . 2-24
2.8 Registers for Managing Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
2.9 Registers for Controlling Repeat Loops . . . . . . . . . . . . . . . . . . . . . . . . 2-39
2.10 Status Registers (ST0_55−ST3_55) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
2-1
Alphabetical Summary of Registers
2.1 Alphabetical Summary of Registers

Table 2−1 lists the registers in alphabetical order. For more details about a
particular register, see the section given in the last column of the table.
Table 2−1. Alphabetical Summary of Registers

See
Register Name Description Size Section
AC0–AC15 Accumulators 0 through 15 40 bits each 2.3
AR0–AR15 Auxiliary registers 0 through 15 16 bits each 2.6.1
BER Bus error register 16 bits 2.8.6
BK03, BK47, BKC Circular buffer size registers 16 bits each 2.6.4
BRC0, BRC1 Block-repeat counters 0 and 1 16 bits each 2.9.2
BRS1 BRC1 save register 16 bits 2.9.2
BSA01, BSA23, BSA45, Circular buffer start address registers 16 bits each 2.6.3
BSA67, BSAC
CDP Coefficient data pointer (low part of XAR15) 16 bits
CDPH High part of XAR15 8 bits 2.6.2
CFCT Control-flow context register 8 bits 2.7
CSR Computed single-repeat register 16 bits 2.9.1
DBIER0, DBIER1 Debug interrupt enable registers 0 and 1 16 bits each 2.8.4
DP Data page register (low part of XDP) 16 bits 2.6.5
DPH High part of XDP 8 bits 2.6.5
IER0, IER1 Interrupt enable registers 0 and 1 16 bits each 2.8.3
IFR0, IFR1 Interrupt flag registers 0 and 1 16 bits each 2.8.2
IIR Interrupt ID register 16 bits 2.8.5
IVPD Interrupt vector pointer 16 bits 2.8.1
PC Program counter 24 bits 2.7
PDP Peripheral data page register 9 bits 2.6.6
REA0, REA1 Block-repeat end address registers 0 and 1 24 bits each 2.9.2
RETA Return address register 24 bits 2.7
2-2 CPU Registers

Alphabetical Summary of Registers
Table 2−1. Alphabetical Summary of Registers (Continued)

See
Register Name Description Size Section
RPTC Single-repeat counter 16 bits 2.9.1
RSA0, RSA1 Block-repeat start address registers 0 and 1 24 bits each 2.9.2
SP Data stack pointer (low part of XSP) 16 bits 2.6.7
SPH High part of XSP 8 bits 2.6.7
SSPH High part of XSSP 8 bits 2.6.7
SSP System stack pointer (low part of XSSP) 16 bits 2.6.7
ST0_55–ST3_55 Status registers 0 through 3 16 bits each 2.10
T0–T3 Temporary registers 16 bits each 2.5
TRN0−TRN7 Transition registers 0 through 7, mapped to AC12−AC15 16 bits each 2.4
XAR0–XAR15 Extended auxiliary registers 0 through 15 24 bits each 2.6.1
XCDP Extended coefficient data pointer (or XAR15) 24 bits 2.6.2
XDP Extended data page register 24 bits 2.6.5
XSP Extended data stack pointer 24 bits 2.6.7
XSSP Extended system stack pointer 24 bits 2.6.7
CPU Registers 2-3

Memory-Mapped Registers and Register ID Concept
2.2 Memory-Mapped Registers and Register ID Concept

On C55x+ DSP, some CPU registers are mapped to data memory space to
support source code compatibility with C55x+ DSP generations. These are
called memory-mapped registers (MMR).
The C55x+ DSP introduces the register ID concept to support the increased
number of registers of the architecture. This concept enables to access all
C55x+ DSP registers with the same flexibility as standard MMR access.
Table 2−2 shows the correspondence between the standard MMR addresses
and the global register ID of all CPU registers.
Notes:
1) Registers ST0_55, ST1_55, and ST3_55 are each accessible at two ad-
dresses. At one address, all the C55x+ DSP bits are available. At the oth-
er address (the protected address), certain bits cannot be modified. The
protected address is provided to support C54x DSP code that writes to
ST0, ST1, and PMST (the C54x DSP counterpart of ST3_55).
2) Registers T3, RSA0L, REA0L, and SP are each accessible at two ad-
dresses. For accesses using the DP direct addressing mode memory-
mapped register accesses, the assembler substitutes the higher of the
two addresses: T3 = 23h (not 0Eh), RSA0L = 3Dh (not 1Bh),
REA0L = 3Fh (not 1Ch), SP = 4Dh (not 18h).
3) Any C55x+ DSP instruction that loads BRC1 also loads the same value
to BRS1.
Table 2−2. Memory-Mapped Register Addresses and Register IDs

Register Register MMR MMR Bit See
ID ID Symbol Address Symbol Description Range Section
00h AC0 − − Accumulator 0 31−0 2.3
2-4 CPU Registers

Table 2−2. Memory-Mapped Register Addresses and Register IDs (Continued)

0Ah AC10 − − Accumulator 10 31−0 2.3
0Bh AC11 − − Accumulator 11 31−0 2.3
0Ch AC12 − − Accumulator 12 31−0 2.3
0Dh AC13 − − Accumulator 13 31−0 2.3
0Eh AC14 − − Accumulator 14 31−0 2.3
0Fh AC15 − − Accumulator 15 31−0 2.3
10h to − − − Reserved − −
1Fh Do not use these addresses
20h AR0 10h AR0_L Auxiliary register 0 15−0 2.6.1
28h AR8 − − Auxiliary register 8 15−0 2.6.1
29h AR9 − − Auxiliary register 9 15−0 2.6.1
2Ah AR10 − − Auxiliary register 10 15−0 2.6.1
2Bh AR11 − − Auxiliary register 11 15−0 2.6.1
2Ch AR12 − − Auxiliary register 12 15−0 2.6.1
2Dh AR13 − − Auxiliary register 13 15−0 2.6.1
2Eh AR14 − − Auxiliary register 14 15−0 2.6.1
2Fh AR15 27h CDP_L Auxiliary register 15 15−0 2.6.1/

(Coefficient data pointer) 2.6.2
30h T0 20h T0_L Temporary register 0 15−0 2.5
CPU Registers 2-5


33h T3 23h or T3_L Temporary register 3 15−0 2.5

0Eh
34h SSP 4Ch SSP_L System stack pointer 15−0 2.6.7
35h SP 4Dh or SP_L Data stack pointer 15−0 2.6.7

18h
36h DP 2Eh DP_L Data page register 15−0 2.6.5
37h − − − Reserved. Do not use this address − −
38h CSR 3Bh CSR_L Computed single-repeat register 15−0 2.9.1
39h RPTC 44h RPTC_L Single-repeat counter 15−0 2.9.1
3Ah BRC0 1Ah BRC0_L Block-repeat counter 0 15−0 2.9.2
3Bh BRC1 39h BRC1_L Block-repeat counter 1 15−0 2.9.2
3Ch to − − − Reserved − −
40h AC0.H 09h AC0_H High part of accumulator 0 31−16 2.3
41h AC1.H 0Ch AC1_H High part of accumulator 1 31−16 2.3
44h AC4.H − − High part of accumulator 4 31−16 2.3
4Ah AC10.H − − High part of accumulator 10 31−16 2.3
4Bh AC11.H − − High part of accumulator 11 31−16 2.3
2-6 CPU Registers


4Ch AC12.H/ − − High part of accumulator 12/ 31−16 2.3

TRN6 Transition register 6
4Dh AC13.H/ − − High part of accumulator 13/ 31−16 2.3

4Eh AC14.H/ − − High part of accumulator 14/ 31−16 2.3

4Fh AC15.H/ 0Fh TRN0_L High part of accumulator 15/ 31−16 2.3 / 2.4
60h AC0.L 08h AC0_L Low part of accumulator 0 31−16 2.3
61h AC1.L 0Bh AC1_L Low part of accumulator 1 31−16 2.3
64h AC4.L − − Low part of accumulator 4 15−0 2.3
6Ah AC10.L − − Low part of accumulator 10 15−0 2.3
6Bh AC11.L − − Low part of accumulator 11 15−0 2.3
6Ch AC12.L/ − − Low part of accumulator 12/ 15−0/ 2.3

TRN7 Transition register 7 15−0
6Dh AC13.L/ − − Low part of accumulator 13/ 15−0/ 2.3

6Eh AC14.L/ − − Low part of accumulator 14/ 15−0/ 2.3

6Fh AC15.L/ 38h TRN1_L Low part of accumulator 15/ 15−0/ 2.3 / 2.4
CPU Registers 2-7


80h XAR0 − − Extended auxiliary register 0 23−0 2.6.1
8Ah XAR10 − − Extended auxiliary register 10 23−0 2.6.1
8Bh XAR11 − − Extended auxiliary register 11 23−0 2.6.1
8Ch XAR12 − − Extended auxiliary register 12 23−0 2.6.1
8Dh XAR13 − − Extended auxiliary register 13 23−0 2.6.1
8Eh XAR14 − − Extended auxiliary register 14 23−0 2.6.1
8Fh XAR15 − − Extended auxiliary register 15 23−0 2.6.1/

(Extended coefficient data pointer) 2.6.2
93h Do not use these addresses
94h XSSP − − Extended system stack pointer 23−0 2.6.7
95h XSP − − Extended data stack pointer 23−0 2.6.7
96h XDP − − Extended data page register 23−0 2.6.5
97h − − − Reserved Do not use this address − −
98h RSA0 − − Block-repeat start address register 0 23−0 2.9.2
99h RSA1 − − Block-repeat start address register 1 23−0 2.9.2
9Ah REA0 − − Block-repeat end address register 0 23−0 2.9.2
2-8 CPU Registers


9Bh REA1 − − Block-repeat end address register 1 23−0 2.9.2
9Ch to − − − Reserved − −
9Eh Do not use these addresses
9Fh RETA − − Return address/context register 31−0 2.7

MMR access restricted
A0h XAR0.H − − High part of the extended auxiliary reg- 7−0 2.6.1
ister 0
ister 1
ister 2
ister 3
ister 4
ister 5
ister 6
ister 7
ister 8
ister 9
AAh XAR10.H − − High part of the extended auxiliary reg- 7−0 2.6.1
ister 10
ABh XAR11.H − − High part of the extended auxiliary reg- 7−0 2.6.1
ister 11
ACh XAR12.H − − High part of the extended auxiliary reg- 7−0 2.6.1
ister 12
ADh XAR13.H − − High part of the extended auxiliary reg- 7−0 2.6.1
ister 13
CPU Registers 2-9


AEh XAR14.H − − High part of the extended auxiliary reg- 7−0 2.6.1
ister 14
AFh XAR15.H 4Fh CDP_H High part of the extended auxiliary reg- 7−0 2.6.1/
ister 15 2.6.2
(High part of the extended coefficient
data pointer)
B0h to − − − Reserved − −
B3h Do not use these addresses
B4h XSSP.H 4Eh − High part of the extended system stack 7−0 2.6.7
pointer
B5h XSP.H 4Eh SP_H High part of the extended data stack 7−0 2.6.7
pointer
B6h XDP.H 2Bh DP_H High part of the extended data page 7−0 2.6.5
pointer
B7h PDP 2Fh PDP_L Peripheral data page register 8−0 2.6.6
B8h BSA01 32h BSA01_L Circular buffer start address register for 15−0 2.6.3
XAR0 and XAR1
B9h BSA23 33h BSA23_L Circular buffer start address register for 15−0 2.6.3
XAR2 and XAR3
BAh BSA45 34h BSA45_L Circular buffer start address register for 15−0 2.6.3
XAR4 and XAR5
BBh BSA67 35h BSA67_L Circular buffer start address register for 15−0 2.6.3
XAR6 and XAR7
BCh BSAC 36h BSAC_L Circular buffer start address register for 15−0 2.6.3
XAR15
BDh BKC 31h BKC_L Circular buffer size register for XAR15 15−0 2.6.4
BEh BK03 19h BK03_L Circular buffer size register for 15−0 2.6.4
XAR0−XAR3
Note: In the C54x−DSP compatible mode (C54CM = 1), BK03 is used for the auxiliary registers AR0 through
AR7. C54CM is a bit in a status register 1 (ST1_55). The status registers are described in Section 2.10.
BFh BK47 30h BK47_L Circular buffer size register for 15−0 2.6.4
XAR4−XAR7
C0h AC0.G 0Ah AC0_G Guard part of accumulator 0 39−32 2.3
2-10 CPU Registers


C1h AC1.G 0Dh AC1_G Guard part of accumulator 1 39−32 2.3
C2h AC2.G 26h AC2_G Guard part of accumulator 2 39−32 2.3
C3h AC3.G 2Ah AC3_G Guard part of accumulator 3 39−32 2.3
C4h AC4.G − − Guard part of accumulator 4 39−32 2.3
CAh AC10.G − − Guard part of accumulator 10 39−32 2.3
CBh AC11.G − − Guard part of accumulator 11 39−32 2.3
CCh AC12.G − − Guard part of accumulator 12 39−32 2.3
CDh AC13.G − − Guard part of accumulator 13 39−32 2.3
CEh AC14.G − − Guard part of accumulator 14 39−32 2.3
CFh AC15.G − − Guard part of accumulator 15 39−32 2.3
D0h to − − − Reserved − −
DFh Do not use these addresses
E0h ST0 06h ST0P_L Status register 0 (For C54 DSP code) 15−0 2.10.1
Note: Address 06h is the protected address of ST0_55. This address is for C54x DSP code that was written to
access ST0. Native C55x/C55x+ DSP code must use address 02h to access ST0_55.
E1h ST1 07h ST1P_L Status register 1 (For C54x DSP code) 15−0 2.10.2
Note: Address 07h is the protected address of ST1_55. This address is for C54x DSP code that was written to
access ST1. Native C55x/C55x+ DSP code must use address 03h to access ST1_55.
E2h ST2 4Bh ST2_L Status register 2 15−0 2.10.3
E3h ST3 1Dh ST3P_L Status register 3 (For C54x DSP code) 15−0 2.10.4
(PMST_L)
Note: Address 1Dh is the protected address of ST3_55. This address is for C54x DSP code that was written to
access the processor mode status register (PMST). Native C55x/C55x+ DSP code must use address 04h to ac-
cess ST3_55.
CPU Registers 2-11


E4h ST0_55 02h ST0_L Status register 0 (For C54x DSP code) 15−0 2.10.1
Note: Address 02h is for native C55x/C55x+ DSP code that accesses ST0_55. C54x DSP code that was written
to access ST0 must use address 06h to access ST0_55.
E5h ST1_55 03h ST1_L Status register 1 (For C54x DSP code) 15−0 2.10.2
Note: Address 03h is for native TMS320C55x+ DSP code that accesses ST1_55. TMS320C54x DSP code that
was written to access ST1 must use address 07h to access ST1_55.
E6h − 4Bh − Reserved Do not use this address − −
E7h ST3_55 04h ST3_L Status register 3 15−0 2.10.4
Note: Address 04h is for native C55x/C55x+ DSP code that accesses ST3_55. C54x DSP code that was written
to access the processor mode status register (PMST) must use address 1Dh to access ST3_55.
E8h IER0 00h IER0_L Interrupt enable register 0 15−0 2.8.3
E9h IER1 45h IER1_L Interrupt enable register 1 15−0 2.8.3
EAh IFR0 01h IFR0_L Interrupt flag register 0 15−0 2.8.2
EBh IER1 46h IFR1_L Interrupt flag register 1 15−0 2.8.2
ECh DBGIER0 47h DBIER0_L Debug interrupt enable register 0 15−0 2.8.4
EDh DBGIER1 48h DBIER1_L Debug interrupt enable register 1 15−0 2.8.4
EEh IVPD 49h IVPD_L Interrupt vector pointer for vectors 0−31 15−0 2.8.1
EFh − − − Reserved Do not use this address − −
F0h RSA0.H 3Ch RSA0_H High part of the block-repeat start ad- 15−0 2.9.2
dress register 0
F1h RSA1.H 40h RSA1_H High part of the block-repeat start ad- 15−0 2.9.2
dress register 1
F2h REA0.H 3Eh REA0_H High part of the block-repeat end ad- 15−0 2.9.2
dress register 0
F3h REA1.H 42h REA1_H High part of the block-repeat end ad- 15−0 2.9.2
dress register 1
F4h BIOS 37h BIOS_L Reserved Do not use this address − −
F5h BRS1 3Ah BRS1_L BRC1 save register 15−0 2.9.2
F6h IIR − − Interrupt ID register 15−0 2.8.5
F7h BER − − Bus error register 15−0 2.8.6
2-12 CPU Registers


F8h RSA0.L 3Dh or RSA0_L Low part of the block-repeat start ad- 15−0 2.9.2
1Bh dress register 0
F9h RSA1.L 41h RSA1_L Low part of the block-repeat start ad- 15−0 2.9.2
dress register 1
FAh REA0.L 3Fh or REA0_L Low part of the block-repeat end ad- 15−0 2.9.2
1Ch dress register 0
FBh REA1.L 43h REA1_L Low part of the block-repeat end ad- 15−0 2.9.2
dress register 1
FCh to − − − Reserved − −
FFh Do not use this address
CPU Registers 2-13

Accumulators (AC0−AC15)
2.3 Accumulators (AC0−AC15)

The CPU contains 16, 40-bit accumulators: AC0−AC15 (see Figure 2−1). The
primary function of these registers is to assist in data computation in the five
operators of the D unit: DU SALU1 and 2, DU MAC1 and 2, and DU BIT.
Each accumulator is partitioned into a low word (ACx.L), a high word

(ACx.H), and eight guard bits (ACx.G). You can access each of these por-
tions individually by using register IDs or addressing modes that access
the memory-mapped registers.
Accumulators AC12 to AC15 low and high parts are mapped to the eight
transition registers (TRN0−TRN7)
For source code migration purpose, the assembler maps C54x accumulators
A and B to C55x+ AC0 and AC1 accumulators, respectively.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 2−1. Accumulators and Transition Registers
ÁÁÁÁÁÁÁÁÁÁÎÎÎÎÎÎÎÎÎÎÎ
ÁÁÁÁÁÁÁÁÁÁÁÉÉÉÉÉÉÉÉÉÉÉÉ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
39−32 31−16 15−0
ÁÁÁ
AC0
ÎÎÎÎÎÎÎÎÎÎÎÉÉÉÉÉÉÉÉÉÉÉÉÁ
AC0.G AC0.H AC0.L
ÁÁÁ
AC1
ÁÁÁ ÎÎÎÎÎÎÎÎÎÎÎ
AC1.G
ÎÎÎÎÎÎÎÎÎÎÎÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÁ
Á
AC1.H AC1.L
ÁÁÁ ÎÎÎÎÎÎÎÎÎÎÎÉÉÉÉÉÉÉÉÉÉÉÉÁ
AC2 AC2.G AC2.H AC2.L
ÁÁÁ
AC4
AC4.G AC4.H AC4.L
ÁÁÁ
AC5
AC5.G
Á
AC5.H AC5.L
ÁÁÁ
AC8
AC8.G AC8.H AC8.L
ÁÁÁ
AC9
AC9.G
ÉÉÉÉÉÉÉÉÉÉÉÉ
AC9.H AC9.L
ÁÁÁ ÎÎÎÎÎÎÎÎÎÎÎ Á
ÁÁÁ
AC12
AC12.G AC12.H / TRN6 AC12.L / TRN7
ÁÁÁ
AC13
AC13.G
Á
AC13.H / TRN4 AC13.L / TRN5
AC14 AC14.G AC14.H / TRN2 AC14.L / TRN3
ÁÁÁ
AC15
AC15.G
AC15.H / TRN0 AC15.L / TRN1
2-14 CPU Registers

Transition Registers (TRN0−TRN7)
2.4 Transition Registers (TRN0−TRN7)

The CPU contains eight transition registers (TRN0−TRN7) mapped respec-
tively to the high and low parts of accumulators AC15−AC12. They can hold
transition decisions for the path to the new metrics in Viterbi algorithm imple-
mentations. The eight transition registers (see Figure 2−1) are used in the
compare and select extremum instructions.
max_diff() and min_diff() instructions perform two 16-bit extremum selec-

tions, and update two consecutive transition registers based on the com-
parison of two accumulators high words and low words. In the following
example, TRN0 is updated based on the comparison of AC1 and AC2 high
words; TRN1 is updated based on the comparison of AC1 and AC2 low
words:
max_diff_dbl() and min_diff_dbl() instructions perform a single extremum

selection, and update the selected transition register based on the com-
parison of two accumulators throughout their bit width. In the following ex-
ample, TRN0 is updated based on the comparison of AC1 and AC2:
max_diff_dbl(AC1, AC2, AC3, AC4, TRN0).
Note:
The transition registers are physically part of the accumulators from AC12
to AC15, as described in Figure 2−1. For that reason do not use instructions
involving accumulators AC12 to AC15 in parallel with instructions reading
from or writing to the corresponding TRNx registers. For example, the follow-
ing instruction pair is illegal:
AC15 = AC0 || max_diff(AC1, AC2, AC3, AC4, pair(TRN0))
CPU Registers 2-15

Temporary Registers (T0−T3)
2.5 Temporary Registers (T0−T3)

The CPU includes four 16-bit general-purpose temporary registers: T0–T3
(see Figure 2−2). With the temporary registers, you can:
Hold one of the memory multiplicands for multiply, multiply-and-accumu-

late, or multiply-and-subtract instructions
Hold the shift count used in shift-and-add, shift-and-subtract, and shift-

and-load instructions performed in the DU SALUx units
Keep track of more buffer element index values by swapping the contents
of the auxiliary registers (AR4–AR7) and the temporary registers by using
a swap instruction
Use them as indexes in indirect addressing modes
Hold the transition metric of a Viterbi butterfly for dual 16-bit operations
performed in the D-unit ALU
Note:
If C54CM = 1 (the TMS320C54x DSP-compatible mode is on), then T2 is
tied to the ASM bits of status register ST1_55 and cannot be used as a
general-purpose register. For details, see Section 2.10.2.1.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 2−2. Temporary Registers
ÁÁÁ
ÁÁÁÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Á
15−0
ÁÁÁ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÁ
T0
ÁÁÁÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÁ
T1
T2
Á
ÁÁÁÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
T3
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
2-16 CPU Registers

Registers Used to Address Data Space and I/O − xI/O Spaces
2.6 Registers Used to Address Data Space and I/O − xI/O Spaces
This section describes the following registers:
See
Register(s) Function Section
XAR0−XAR15 Point to a value in data, I/O − xI/O spaces for ac- 2.6.1
AR0−AR15 cesses made with indirect addressing modes
BSA01, BSA23, Specify a circular buffer start address 2.6.3

BSA45, BSA67,
BSAC
BK03, BK47, BKC Specify a circular buffer size 2.6.4
XDP Specify the start address for accesses made with 2.6.5
the XDP direct addressing mode
PDP Identify the peripheral data page for an access to 2.6.6

I/O space
XSP Point to a value on the data stack 2.6.7
XSSP Point to a value on the system stack 2.6.7
2.6.1 Extended Auxiliary Registers (XAR0–XAR15/AR0−AR15)

The CPU contains 16, 24-bit, extended auxiliary registers XARn (with
n = 0−15) (see Figure 2−3 and Table 2−3). To ensure source code compatibili-
ty with the C55x+ DSP generations, each extended auxiliary register XARn is
composed of ARnH part (8 lower bits of XARn) and the ARn register (16 lower
bits of XARn).
The XARn registers can be used to address any objects allocated in the
8-Mword data space.
XAR0−XAR15 are used in the XAR indirect addressing mode and the dual
XAR indirect addressing mode
The C55x+ DSP has a 24-bit flat data addressing mechanism. The data
address generation (AU DAGEN) units have a full 24-bit arithmetic unit.
This allows address generation to cross or span the 64-Kword data page
boundaries which allows data tables that are greater than 64 Kwords to
be addressed efficiently.
In C55x+ DSP, revision 2.x, if the pointer to a data table is incremented to

cross a 64-Kword data page boundary, then the arithmetic value returned
by the DAGEN has its 16 lower bits wrap around. For example, the pointer
CPU Registers 2-17

value 00 FFFFh + 1 becomes 00 0000h. This wrap-around feature is not

supported in C55x+ DSP. All arithmetic operations for data address gener-
ation are based on 24-bit arithmetic in both word- and byte-pointer modes.
The ARn registers can be used as:
A bit address (in instructions that access individual bits or bit pairs)
An index to select words relative to the start address of a circular buffer

(see Section 6.12, Circular Addressing)
A general-purpose register or counter. Basic arithmetical, logical, and shift

operations can be performed on AR0–AR15 in the A unit arithmetic logic
unit (AU ALU). These operations can be performed in parallel with address
modifications performed on the extended auxiliary registers in the data-
address generation unit (AU DAGEN).
ÁÁÁÁÁÁÁÁ Á
Figure 2−3. Extended Auxiliary Registers and Their Parts
ÁÁÁÁÁÁÁÁ Á 23−16 15−0
ÁÁÁÁÁÁÁÁ XAR0
Á AR0H AR0
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
XAR1
Á
Á
AR1H AR1
ÁÁÁÁÁÁÁÁ Á
XAR2 AR2H AR2
ÁÁÁÁÁÁÁÁ Á
XAR3 AR3H AR3
Á AR4H AR4
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
XAR5
Á
Á
AR5H AR5
ÁÁÁÁÁÁÁÁ Á
XAR6 AR6H AR6
ÁÁÁÁÁÁÁÁ Á
XAR7 AR7H AR7
Á AR8H AR8
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
XAR9
Á
Á
AR9H AR9
ÁÁÁÁÁÁÁÁ Á
XAR10 AR10H AR10
Á AR11H AR11
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
XAR12
Á
Á
AR12H AR12
ÁÁÁÁÁÁÁÁ Á
XAR13 AR13H AR13
ÁÁÁÁÁÁÁÁ Á
XAR14 AR14H AR14
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
XAR15
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
AR15H AR15
2-18 CPU Registers

Table 2−3. Extended Auxiliary Registers and Their Parts

Register Referred To As ... Comment
XARn Extended auxiliary register n XARn is not memory mapped
ARn Auxiliary register n ARn is not memory mapped (except

AR0−AR7 and AR15 for source code
compatibility with C55x+ DSP genera-
tions)
ARnH High part of extended auxiliary ARnH is not memory mapped (except
register n AR15H for source code compatibility
with C55x+ DSP generations)
Note:
XAR0−XAR7 can be configured for circular addressing mode (see Section
6.12 for more detail on the circular addressing mode). XAR8−XAR15 cannot
be configured for the circular addressing mode.
2.6.2 Extended Coefficient Data Pointer (XCDP/XAR15)

To ensure source code compatibility with C55x+ DSP generations, the XCDP
register is mapped to the XAR15 register on C55x+ DSP. See Section 2.6.1
for more details on the XAR15 register. This mapping brings more flexibility for
Cmem addressing mode. (See Section 6.5.3 for more details on coefficient in-
direct addressing mode.)
2.6.3 Circular Buffer Start Address Registers

(BSA01, BSA23, BSA45, BSA67, BSAC)
The CPU includes five 16-bit circular buffer start address registers (see
Figure 2−4) to enable you to define a circular buffer with a start address that
is not bound by any alignment constraint.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 2−4. Circular Buffer Start Address Registers
ÁÁÁÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÁÁ 15−0
ÁÁÁÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÁÁ
BSA01
BSA23
ÁÁÁÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
BSA45
ÁÁ
ÁÁÁ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÁÁ
BSA67
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
BSAC
CPU Registers 2-19
Each buffer start address register is associated with a particular extended aux-
iliary register (see Table 2−4). A buffer start address is only added to the regis-
ter value when the register is configured for circular addressing in status regis-
ter ST2_55, or if circular() qualifier is being applied to the instruction.
Table 2−4. Circular Buffer Start Address Registers and the Associated XARn
Register XARn Computed Circular Buffer Start Address
BSA01 XAR0 AR0H:BSA01 for XAR0

XAR1 AR1H:BSA01 for XAR1



BSAC XAR15 AR15H:BSAC for XAR15
As an example of using a buffer start address, consider the following

instruction:
T2 = *AR6 ; Load T2 with a value from the circular

; buffer of words referenced by XAR6.
In this example, with XAR6 configured for circular addressing, the generated
address is of the following form:
(AR6H:BSA67) + (00:AR6)
The start address of the circular buffer is composed of the 8 MSBs of the ex-
tended auxiliary register XAR6 (AR6H), and the 16 bits of its associated buffer
start address (BSA67). The 16 LSBs of XAR6 (AR6) contain the index of the
referenced element inside that circular buffer.
When you run TMS320C54x DSP code in the compatible mode (C54CM = 1),
make sure that the buffer start address registers contain 0.
2.6.4 Circular Buffer Size Registers (BK03, BK47, BKC)
Three 16-bit circular buffer size registers (see Figure 2−5) specify the number
of words (up to 65535) in a circular buffer. Each buffer size register is associat-
ed with a particular extended address register (see Table 2−5).
2-20 CPU Registers

Figure 2−5. Circular Buffer Size Registers
ÁÁÁÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 15−0
BK03
BK47
ÁÁÁ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÁÁ
ÁÁ
BKC
Table 2−5. Circular Buffer Size Registers and the Associated XARn
Register XARn
BK03 XAR0, XAR1, XAR2, or XAR3
BK47 XAR4, XAR5, XAR6, or XAR7
BKC XAR15
In the TMS320C54x DSP-compatible mode (C54CM = 1), BK03 is used for

the auxiliary registers XAR0−XAR7, and BK47 is not used.
2.6.5 Extended Data Page Register (XDP/DP)

The CPU contains one 24-bit XDP register which identifies the start address
of 128-word local data page which can be accessed with the XDP direct ad-
dressing mode. To ensure source code compatibility with C55x+ DSP genera-
tions, in C55x+ DSP, XDP is composed of the DPH part (8 higher bits of XDP)
and the DP register (16 lower bits of XDP).
Figure 2−6. Extended Data Page Register and Its Parts
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÁÁÁÁÁÁÁÎÎÎÎÎÎÎÎÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
23−16 15−0
ÁÁÁÁÁÁÁÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÁÁ
XDP DPH
DP
Table 2−6. Extended Data Page Register and Its Parts

XDP Extended data page register XDP is not memory mapped
DP Data page register DP is memory mapped
DPH High part of extended data page DPH is memory mapped

register
CPU Registers 2-21

Note that in the XDP direct addressing mode, XDP specifies a 24-bit address;
while in the k16 absolute addressing mode, only DPH is used and is concate-
nated with a 16-bit instruction defined constant to form a 24-bit address.
2.6.6 Peripheral Data Page Register (PDP)

The peripheral data page (PDP) register is a 9-bit register concatenated to a
7-bit instruction defined constant (@#k7) to form a 16-bit I/O address. As
shown in Figure 2−7, bits 15−9 are reserved and thus ignored by the CPU.
This register is accessible via dedicated instructions, its register ID, or its MMR
symbol. The PDP register can be used only in word-pointer mode for I/O ac-
cesses (and not for xI/O accesses).
Figure 2−7. Peripheral Data Page Register
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÁÁÎÎÎÎÎÎÎÎÎÎÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
15−9 8−0
ÁÁÎÎÎÎÎÎÎÎÎÎÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÉÉÉÉÉÉÉÉÉÉÉÉÉÁ
Reserved PDP
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
2.6.7 Extended Stack Pointers (XSP/SP, XSSP/SSP)
The CPU contains two 24-bit XSP and XSSP stack registers to access the data
stack and the system stack, respectively. When accessing the data stack, the
XSP register contains the address of the value last pushed onto the data stack.
Similarly, when accessing the system stack, the XSSP register contains the
address of the value last pushed onto the system stack.
XSP register is composed of the SPH part (8 higher bits of XSP) and the SP
register (16 lower bits of XSP). Similarly, the XSSP register is composed of the
SSPH part (8 higher bits of XSSP) and the SSP register (16 lower bits of
XSSP).
You can allocate the data stack and the system stack independently from each
other anywhere in the data space. For example:
mar(XSP = #010012h)
mar(XSSP = #020AE0h)
As mentioned in Section 2.6.1, the C55x+ DSP has a 24-bit flat data address
mechanism. The data address generation (AU DAGEN) units have a full 24-bit
arithmetic unit. This allows each stack to span over the 64-Kword data page
boundary.
To ensure source code compatibility with C55x+ DSP generations, C55x+
DSP features the paged-stack mode where SPH and SSPH are tied to each
other. (See Section 4.2.1 for more details on stack configurations.)
2-22 CPU Registers

Figure 2−8. Extended Stack Pointers
ÁÁÁÁÁÁÁÎÎÎÎÎÎÎÎÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 23−16 15−0
XSP SPH SP
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
XSSP SSPH SSP
Table 2−7. Extended Stack Pointer Registers
XSP Extended data stack pointer XSP is not memory mapped
SP Data stack pointer SP is memory mapped
SPH High part of XSP SPH is memory mapped
XSSP Extended system stack pointer XSSP is not memory mapped
SSP System stack pointer SSP is memory mapped
SSPH High part of XSSP SSPH is not memory mapped
XSP is used in the XSP direct addressing mode. The following instructions
read or modify the XSP and XSSP registers:
Instruction Type(s) Description
Software interrupt, software trap, software These instructions push data onto the data stack and the sys-
reset, conditional call, unconditional call tem stack. XSP and XSSP are decremented before each pair
of data values is pushed.
Push This instruction pushes data onto the data stack only. XSP is de-
cremented before the data is pushed.
Conditional return, unconditional return, re- These instructions pop data from the data stack and the system
turn from interrupt stack. XSP and XSSP are incremented after each pair of data
values is popped.
Pop This instruction pops data from the data stack only. XSP is in-
cremented after the data is popped.
CPU Registers 2-23

Program Flow Registers (PC, RETA, CFCT)
2.7 Program Flow Registers (PC, RETA, CFCT)
Table 2−8 describes three registers used by the CPU to maintain proper
program flow.
Table 2−8. Program Flow Registers
Register Description
PC Program counter. This 24-bit register holds the address of the 1 to

16 bytes of code being decoded in the I unit. When the CPU per-
forms an interrupt or call, the current PC value (the return address)
is stored, and then the PC is loaded with a new address. When the
CPU returns from an interrupt service routine or from a called sub-
routine, the return address is restored to PC.
RETA Return address register. If the selected stack configuration (see

Section 4.2) uses the fast-return process, then RETA is a temporary
holding place for the return address while a subroutine is being exe-
cuted. RETA, along with CFCT, enables the efficient execution of
multiple layers of subroutines. You can read from or write to RETA
and CFCT as a pair with dedicated 32-bit load and store instruc-
tions.
CFCT Control-flow context register. The CPU keeps a record of active re-
peat loops (the loop context). If the selected stack configuration
(see Section 4.2) uses the fast-return process, then CFCT is a tem-
porary holding place for the 8-bit loop context while a subroutine is
being executed. CFCT, along with RETA, enables the efficient exe-
cution of multiple layers of subroutines. You can read from or write
to RETA and CFCT as a pair with dedicated, 32-bit load and store
instructions.
Note:
RETA and CFCT are cleared to 0 by a DSP hardware reset, and are not
affected by push/pop instructions or by a software reset.
2.7.1 Context Bits Stored in CFCT
The CPU has internal bits for storing the loop context—the status (active or
inactive) of repeat loops in a routine. When the CPU follows an interrupt or a
call, the loop context is stored in CFCT. When the CPU returns from an inter-
rupt or a called subroutine, the loop context is restored from CFCT. The loop
context bits have the following form in the 8-bit CFCT.
2-24 CPU Registers

Program Flow Registers (PC, RETA, CFCT)
Bit(s) Description
7 This bit reflects whether a conditional or unconditional single-repeat loop

is active.
0 = Not active
1 = Active
6 This bit reflects whether a conditional single-repeat loop is active.

0 = Not active
1 = Active
5 Reserved.
4 BPTR bit: this bit reflects whether the CPU is in byte or word pointer ad-
dressing mode.
0 = Word-pointer mode
1 = Byte-pointer mode
3–0 This 4-bit code reflects the status of the two possible levels of block-re-
peat loops, the outer (level 0) loop and the inner (level 1) loop. Depend-
ing on which type of block-repeat instruction you choose, an active loop
is local (all its code is repeatedly executed from within the instruction buff-
er queue) or external (its code is repeatedly fetched and transferred
through the buffer queue to the CPU).
Block-Repeat Code Level 0 Loop Is ... Level 1 Loop Is ...

0 Not active Not active
2 Active, external Not active
3 Active, local Not active
7 Active, external Active, external
8 Active, external Active, local
9 Active, local Active, local
Other: Reserved – –
CPU Registers 2-25

Registers For Managing Interrupts
2.8 Registers For Managing Interrupts

This section describes the following registers:
Register(s) Function See Section
IVPD Points to interrupt vectors 0−31 2.8.1
IFR0, IFR1 Indicate which maskable interrupts have been re- 2.8.2
quested
IER0, IER1 Enable or disable maskable interrupts 2.8.3
DBIER0, Select maskable interrupts as time-critical interrupts 2.8.4

DBIER1 during debugging
IIR Indicates the interrupt ID 2.8.5
BER Indicates the bus error interrupt source 2.8.6
2.8.1 Interrupt Vector Pointers (IVPD)

The 16-bit interrupt vector pointer IVPD (see Figure 2−9) points up to 32 inter-
rupt vectors in program space. The IVPD register points to the 256-byte pro-
gram page for interrupt vectors 0−31.
A DSP hardware reset loads IVPD with FFFFh. IVPD is not affected by a soft-
ware reset instruction.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 2−9. Interrupt Vector Pointer
ÁÁÁ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Á
15−0
ÁÁÁ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á
IVPD
Before you modify IVPD, make sure that:
Maskable interrupts are globally disabled (INTM = 1). This prevents a
maskable interrupt from occurring before IVPD is modified to point to new
vectors.
Each hardware nonmaskable interrupt has a vector and an interrupt ser-
vice routine for the old IVPD value and for the new IVPD value. This pre-
vents fetching of an illegal instruction code if a hardware nonmaskable
interrupt occurs during the process of modifying the IVPD.
Table 2−9 shows how the vector addresses are formed for the different inter-
rupt vectors. The CPU concatenates the IVPD with a vector number coded on
5 bits (for example, 00001 for IV1 and 10000 for IV16) and shifted left by 3 bits.
2-26 CPU Registers

Table 2−9. Vectors and the Formation of Vector Addresses
Vector Address
Vector(s) Interrupt(s) Bits 23−8 Bits 7−3 Bits 2−0
IV0 Reset IVPD 00000 000
IV1 Nonmaskable hardware inter- IVPD 00001 000

rupt, NMI
IV2–IV23 Maskable interrupts IVPD 00010 000

to
10111
IV24 Bus error interrupt (maskable), IVPD 11000 000

BERRINT
IV25 Data log interrupt (maskable), IVPD 11001 000

DLOGINT
IV26 Real-time operating system in- IVPD 11010 000

terrupt (maskable), RTOSINT
IV27–IV31 General-purpose software-only IVPD 11011 000

interrupts, INT27–INT31 to
11111
2.8.2 Interrupt Flag Registers (IFR0, IFR1)
The 16-bit interrupt flag registers, IFR1 and IFR0, contain flag bits for all the
maskable interrupts. When a maskable interrupt request reaches the CPU, the
corresponding flag is set to 1 in one of the IFRs. This indicates that the interrupt
is pending or waiting for acknowledgement from the CPU. Figure 2−10 is a
general representation of the C55x+ DSP IFRs. To see which interrupts are
mapped to these bits, see the applicable C55x+ DSP data manual.
You can read the IFRs to identify pending interrupts, and write to the IFRs to
clear pending interrupts. To clear an interrupt request (and clear its IFR bit to
0), write a 1 to the corresponding IFR bit. For example:
; Clear flags IF14 and IF2:

mmap(@IFR0) = #0100000000000100b
All pending interrupts can be cleared by writing the current contents of the IFR
back into the IFR. Acknowledgement of a software or hardware interrupt re-
quest also clears the corresponding IFR bit. A device reset clears all IFR bits.
CPU Registers 2-27

Figure 2−10. Interrupt Flag Registers

IFR1
15 11 10 9 8
Reserved RTOSINTF DLOGINTF BERRINTF
R−0 R/W1C−0 R/W1C−0 R/W1C−0
7 6 5 4 3 2 1 0
IF23 IF22 IF21 IF20 IF19 IF18 IF17 IF16
R/W1C−0 R/W1C−0 R/W1C−0 R/W1C−0 R/W1C−0 R/W1C−0 R/W1C−0 R/W1C−0
IFR0
15 14 13 12 11 10 9 8
IF15 IF14 IF13 IF12 IF11 IF10 IF9 IF8
R/W1C−0 R/W1C−0 R/W1C−0 R/W1C−0 R/W1C−0 R/W1C−0 R/W1C−0 R/W1C−0
7 6 5 4 3 2 1 0
IF7 IF6 IF5 IF4 IF3 IF2 Reserved
R/W1C−0 R/W1C−0 R/W1C−0 R/W1C−0 R/W1C−0 R/W1C−0 R−0
Legend: R = Read access; W1C = Writing a 1 to this bit causes the CPU to clear this bit to 0; -n = Value after DSP hardware reset;
Reserved = A write to this bit has no effect, and the bits in this field always appear as 0s during read operations.
2.8.2.1 RTOSINTF Bit in IFR1

Bit Name Description Accessibility HW Reset
10 RTOSINTF Interrupt flag bit for the real- Read/Write 0
time operating system inter-
rupt, RTOSINT
When you read the RTOSINTF bit, interpret it as follows:

RTOSINTF Description
0 RTOSINT is not pending.
1 RTOSINT is pending.
To clear this flag bit to 0 (and clear its corresponding interrupt request), write
a 1 to the bit.
2-28 CPU Registers

2.8.2.2 DLOGINTF Bit in IFR1

9 DLOGINTF Interrupt flag bit for the data log Read/Write 0
interrupt, DLOGINT
When you read the DLOGINTF bit, interpret it as follows:

DLOGINTF Description
0 DLOGINT is not pending.
1 DLOGINT is pending.
a 1 to the bit.
2.8.2.3 BERRINTF Bit in IFR1

8 BERRINTF Interrupt flag bit for the bus Read/Write 0
error interrupt, BERRINT
When you read the BERRINTF bit, interpret it as follows:

BERRINTF Description
0 BERRINT is not pending.
1 BERRINT is pending.
a 1 to the bit.
2.8.2.4 IF16–IF23 Bits in IFR1

0 IF16 Interrupt 16 flag bit Read/Write 0
When you read these bits, interpret them as follows (x is a number from 16 to
23):
IFx Description
0 The interrupt associated with interrupt vector x is not pending.
1 The interrupt associated with interrupt vector x is pending.
To clear a flag bit to 0 (and clear its corresponding interrupt request), write a
1 to the bit.
CPU Registers 2-29

2.8.2.5 IF2–IF15 Bits in IFR0

When you read these bits, interpret them as follows (x is a number from 2 to
15):
IFx Description
0 The interrupt associated with interrupt vector x is not pending.
1 The interrupt associated with interrupt vector x is pending.
To clear a flag bit to 0 (and clear its corresponding interrupt request), write a
1 to the bit.
2.8.3 Interrupt Enable Registers (IER0, IER1)

To enable a maskable interrupt, set its corresponding bit in IER0 or IER1 to 1.
To disable a maskable interrupt, clear its corresponding enable bit to 0. At a
DSP hardware reset, all the IER bits are cleared to 0, disabling all the mask-
able interrupts. Figure 2−11 is a general representation of the C55x+ DSP
IERs. To see which interrupts are mapped to these bits, see the applicable
C55x+ DSP data manual.
Note:
IER1 and IER0 are not affected by a software reset instruction. Initialize
these registers before globally enabling (INTM = 0) the maskable interrupts.
2-30 CPU Registers

Figure 2−11.Interrupt Enable Registers
IER1
15 11 10 9 8
Reserved RTOSINTE DLOGINTE BERRINTE
R−0 R/W−0 R/W−0 R/W−0
7 6 5 4 3 2 1 0
IE23 IE22 IE21 IE20 IE19 IE18 IE17 IE16
R/W−0 R/W−0 R/W−0 R/W−0 R/W−0 R/W−0 R/W−0 R/W−0
IER0
15 14 13 12 11 10 9 8
IE15 IE14 IE13 IE12 IE11 IE10 IE9 IE8
7 6 5 4 3 2 1 0
IE7 IE6 IE5 IE4 IE3 IE2 Reserved
R/W−0 R/W−0 R/W−0 R/W−0 R/W−0 R/W−0 R−0
Legend: R = Read; W = Write; -n = Value after DSP hardware reset
2.8.3.1 RTOSINTE Bit in IER1

10 RTOSINTE Enable bit for the real-time oper- Read/Write 0
ating system interrupt, RTOSINT
The RTOSINTE bit enables or disables RTOSINT:

RTOSINTE Description
0 RTOSINT is disabled.
1 RTOSINT is enabled.
2.8.3.2 DLOGINTE Bit in IER1

9 DLOGINTE Enable bit for the data log inter- Read/Write 0
rupt, DLOGINT
The DLOGINTE bit enables or disables DLOGINT:

DLOGINTE Description
0 DLOGINT is disabled.
1 DLOGINT is enabled.
CPU Registers 2-31

2.8.3.3 BERRINTE Bit in IER1

8 BERRINTE Enable bit for the bus error Read/Write 0
interrupt, BERRINT
The BERRINTE bit enables or disables BERRINT:

BERRINTE Description
0 BERRINT is disabled.
1 BERRINT is enabled.
2.8.3.4 IE16–IE23 Bits in IER1

0 IE16 Interrupt 16 enable bit Read/Write 0
The functions of these bits can be summarized as follows, where x is a number

from 16 to 23:
IEx Description
0 The interrupt associated with interrupt vector x is disabled.
1 The interrupt associated with interrupt vector x is enabled.
2-32 CPU Registers

2.8.3.5 IE2–IE15 Bits in IER0


from 2 to 15:
IEx Description
0 The interrupt associated with interrupt vector x is disabled.
1 The interrupt associated with interrupt vector x is enabled.
2.8.4 Debug Interrupt Enable Registers (DBIER0, DBIER1)
The 16-bit debug interrupt enable registers, DBIER1 and DBIER0, are used
only when the CPU is halted in the real-time emulation mode of the debugger.
If the CPU is running in real-time mode, then the standard interrupt-handling
process is used and the DBIERs are ignored.
A maskable interrupt enabled in a DBIER is defined as a time-critical interrupt.

When the CPU is halted in the real-time mode, the only interrupts that are ser-
viced are time-critical interrupts that are also enabled in an interrupt enable
register (IER1 or IER0).
Read the DBIERs to identify time-critical interrupts. Write to the DBIERs to en-
able or disable time-critical interrupts. To enable an interrupt, set its corre-
sponding bit. To disable an interrupt, clear its corresponding bit. Figure 2−12
is a general representation of the C55x+ DSP DBIERs. To see which interrupts
are mapped to these bits, see the applicable C55x+ DSP data manual.
CPU Registers 2-33

Note:
DBIER1 and DBIER0 are not affected by a software reset instruction. Initial-
ize these registers before you use the real-time emulation mode.
All DBIER bits are cleared to 0 by a DSP hardware reset, disabling all time-
critical interrupts.
Figure 2−12. Debug Interrupt Enable Registers
DBIER1
15 11 10 9 8
Reserved RTOSINTD DLOGINTD BERRINTD
R−0 R/W−0 R/W−0 R/W−0
7 6 5 4 3 2 1 0
DBIE23 DBIE22 DBIE21 DBIE20 DBIE19 DBIE18 DBIE17 DBIE16
DBIER0
15 14 13 12 11 10 9 8
DBIE15 DBIE14 DBIE13 DBIE12 DBIE11 DBIE10 DBIE9 DBIE8
7 6 5 4 3 2 1 0
DBIE7 DBIE6 DBIE5 DBIE4 DBIE3 DBIE2 Reserved
R/W−0 R/W−0 R/W−0 R/W−0 R/W−0 R/W−0 R−0
2.8.4.1 RTOSINTD Bit in DBIER1

10 RTOSINTD Debug enable bit for the real- Read/Write 0
time operating system interrupt,
RTOSINT
The RTOSINTD bit enables or disables RTOSINT as a time-critical interrupt:

RTOSINTD Description
0 RTOSINT is disabled. It is not configured as a time-critical interrupt.
1 RTOSINT is enabled. It is configured as a time-critical interrupt.
2-34 CPU Registers

2.8.4.2 DLOGINTD Bit in DBIER1

9 DLOGINTD Debug enable bit for the data Read/Write 0
log interrupt, DLOGINT
The DLOGINTD bit enables or disables DLOGINT as a time-critical interrupt:

DLOGINTD Description
0 DLOGINT is disabled. It is not configured as a time-critical interrupt.
1 DLOGINT is enabled. It is configured as a time-critical interrupt.
2.8.4.3 BERRINTD Bit in DBIER1

8 BERRINTD Debug enable bit for the bus Read/Write 0
error interrupt, BERRINT
The BERRINTD bit enables or disables BERRINT as a time-critical interrupt:

BERRINTD Description
0 BERRINT is disabled. It is not configured as a time-critical interrupt.
1 BERRINT is enabled. It is configured as a time-critical interrupt.
2.8.4.4 DBIE16–DBIE23 Bits in DBIER1

0 DBIE16 Debug interrupt enable bit 16 Read/Write 0

from 16 to 23:
DBIEx Description
0 The interrupt associated with interrupt vector x is disabled. The in-
terrupt is not configured as a time-critical interrupt.
1 The interrupt associated with interrupt vector x is enabled. The in-
terrupt is configured as a time-critical interrupt.
CPU Registers 2-35

2.8.4.5 DBIE2–DBIE15 Bits in DBIER0


from 2 to 15:
DBIEx Description
0 The interrupt associated with interrupt vector x is disabled. The
interrupt is not configured as a time-critical interrupt.
1 The interrupt associated with interrupt vector x is enabled. The
interrupt is configured as a time-critical interrupt.
2.8.5 Interrupt ID Register (IIR)

The C55x+ features a 16-bit interrupt ID register (IIR).
It contains the interrupt service routine (ISR) number of the maskable interrupt
most recently taken by the CPU. When a maskable interrupt request reaches
the CPU, the corresponding interrupt service routine number (between 2 to 31,
see Table 5−1 for more details) is saved into bit[4:0] of the IIR register.
Figure 2−13. Interrupt ID Register

IIR
15 5 4 3 2 1 0
Reserved Interrupt ID
You can read, and save the IIR register content with the following instructions:
;the content of the IIR register is copied to the memory
;location pointed by XSP register
push (mmap(@IIR))
2-36 CPU Registers

You can not write to IIR register.
A software interrupt or a trap instruction update the IIR register as well. A hard-
ware reset clears the IIR register content.
2.8.6 Bus Error Register (BER)
The C55x+ DSP features a 16-bit bus error register (BER).

It stores the information of the source of the bus error interrupt detected by the
CPU. The CPU sets BER register bits according to the source of the bus error
interrupt.
The bits have the following form in the BER register:
Bit(s) Description
0 When set to 1, this bit reflects whether an indirect access to address zero
has been made. Otherwise, it is set to 0.
1 When set to 1, this bit reflects whether a byte access to MMR space (ad-
dress 00h−5Fh) has been made in word-pointer CPU mode. Otherwise, it
is set to 0.
2 When set to 1, this bit reflects whether a stack access to MMR space
(address 00h−5Fh) has been made in word-pointer CPU mode. Other-
wise, it is set to 0.
3 When set to 1, this bit reflects whether a BAB bus access to MMR space
(address 00h−5Fh) has been made in word-pointer CPU mode. Other-
wise, it is set to 0.
4 When set to 1, this bit reflects whether a dual write to MMR space (ad-
dress 00h−5Fh) has been made in word-pointer CPU mode. Otherwise, it
is set to 0.
5 When set to 1, this bit reflects whether a word/long access has been
made at unaligned address in byte-pointer CPU mode. Otherwise, it is set
to 0.
6 When set to 1, this bit reflects whether a decode program bus error has
occurring. Otherwise, it is set to 0.
7 When set to 1, this bit reflects whether the megacell has detected an er-
ror condition. Otherwise, it is set to 0.
8−15 Reserved.
You can read the BER bits to identify the bus error interrupt sources, and write
to the BER register to clear the bus error interrupt sources. To clear a bus error
CPU Registers 2-37

interrupt source (and clear its BER bit to 0), write a 1 to the corresponding BER
bit. For example:
; Clear bit #2 of BER:
mmap(@BER) = #0000000000000100b
A software interrupt or a trap instruction does not affect the BER bits (BER-
RINTF bits in the IFR1 register are affected in this case). A hardware or soft-
ware reset clears all BER bits.
Note:
When the CPU is detecting a bus error, it sets:
1) The corresponding bit of BER register.
2) The CPU bus error flag (CBERR bit in ST3_55 register).
3) The bus error interrupt flag (BERRINT bit in IFR1 register).
Note:
When the BER, ST3_55, or IFR1 registers are updated by a bus error, these
register accesses are not pipeline protected against any read or write opera-
tions involving these registers.
2-38 CPU Registers

Registers for Controlling Repeat Loops
2.9 Registers for Controlling Repeat Loops
This section describes registers that control the execution of repeat loops.
Single-repeat registers are used for the repetition of a single instruction or two
parallel instructions. Block-repeat registers are used for the repetition of
blocks of instructions.
2.9.1 Single-Repeat Registers (RPTC, CSR)
The 16-bit single-repeat instruction registers, RPTC and CSR, enable the rep-
etition of a single-cycle instruction (or two single-cycle instructions that are ex-
ecuted in parallel). The number of repetitions, N, is loaded into the single-re-
peat counter (RPTC) before the first execution. After the first execution, the
instruction is executed N more times; therefore, total number of executions is
N+1 times.
In some syntaxes of the unconditional single-repeat instruction, you can use

the computed single-repeat register (CSR) to specify the number N. The value
from CSR is copied into RPTC before the first execution of the instruction or
instruction pair to be repeated.
As shown in Figure 2−14, RPTC and CSR have 16 bits, enabling up to 65536
consecutive executions of an instruction (the first execution plus 65535
repetitions).
Figure 2−14. Single-Repeat Registers
ÁÁÁÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 15−0
RPTC
ÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
CSR
2.9.2 Block-Repeat Registers (BRC0–1, BRS1, RSA0–1, REA0–1)
The block-repeat instructions enable you to form loops that repeat blocks of
instructions. You can have one block-repeat loop nested inside another creat-
ing an inner (level 1) loop and an outer (level 0) loop. Table 2−10 describes the
C55x+ DSP registers associated with level 0 and level 1 loops. As described
in the following paragraphs, the use of these registers is affected by the C54x
DSP-compatible mode bit (C54CM), which is introduced in Section 2.10.2.4.
CPU Registers 2-39

2.9.2.1 If C54CM = 0: C55x+ DSP Native Mode

The CPU keeps a record of active repeat loops when an interrupt or call is per-
formed while the loop is active (see the description for CFCT in Section 2.7,
Program Flow Registers (PC, RETA, CFCT)). This enables the use of level 0
resources in subroutines. When the CPU decodes a block-repeat instruction,
it first determines whether a loop is already being executed. If the CPU detects
an active level 0 loop, then it uses the level 1 loop registers; otherwise, it uses
the level 0 loop registers.
2.9.2.2 If C54CM = 1: C54x DSP-Compatible Mode

Block-repeat instructions activate the level 0 loop registers only. Level 1 loop
registers are not used. Nested block-repeat operations can be implemented
as on the C54x DSPs, using context saving/restoring and the block-repeat ac-
tive flag (BRAF). A block-repeat instruction sets BRAF, and BRAF is cleared
at the end of the block-repeat operation when BRC0 contains 0. For more
details about BRAF, see Section 2.10.2.2, BRAF Bit of ST1_55.
When a block-repeat loop begins in the C54x DSP-compatible mode

(C54CM = 1), the BRAF bit is automatically set to indicate that a loop is in prog-
ress. If your program must switch modes from C54CM = 1 to C54CM = 0, then
the BRAF bit must be cleared before or during the switch. There are three op-
tions:
Wait until the loop is finished (when BRAF is cleared automatically) and
then clear C54CM.
Clear BRAF (this also stops the loop) and then clear C54CM.
Clear BRAF and C54CM at the same time with an instruction that modifies
status register ST1_55.
2.9.2.3 Pipeline Considerations for BRCx Register Updates Inside a Repeat Loop
There are two cases to consider when writing to the BRCx registers.
The BRCx register is explicitly updated by an instruction:

For example: BRC0 = #05h, or mmap(@BRC0) = #05h
The BRCx register is implicitly updated by an instruction:

For example: *AR0 = #03h with the XAR0 register pointing to the MMR ad-
dress of the BRC0 register.
Ensure that the last two instructions of a level 0 loop do not explicitly update
the BRC0 register. Similarly, the last two instructions of a level 1 loop must not
explicitly update the BRC1 register. Such operations are not pipeline pro-
tected.
2-40 CPU Registers

Ensure that the last four instructions of a level 0 loop do not implicitly update
the BRC0 register. Similarly, the last four instructions of a level 1 loop must not
implicitly update the BRC1 register. Such operations are not pipeline pro-
tected.
Note that in C55x+ DSP generations, it is the last two or three instructions that
are not pipeline protected against explicit or implicit BRCx register updates.
Note that you must not modify the RSAx or REAx registers when executing a
block-repeat loop.
Table 2−10. Block-Repeat Register Descriptions

Level 0 Loop Registers Level 1 Loop Registers (Not Used If C54CM = 1)
Register Description Register Description
BRC0 Block-repeat counter 0. This 16-bit regis- BRC1 Block-repeat counter 1. This 16-bit regis-
ter contains the number of times to repeat ter contains the number of times to repeat
the instruction block after its first execu- the instruction block after its first execu-
tion. tion.
RSA0 Block-repeat start address register 0. RSA1 Block-repeat start address register 1.
This 24-bit register contains the address This 24-bit register contains the address
of the first instruction in the instruction of the first instruction in the instruction
block. block.
REA0 Block-repeat end address register 0. This REA1 Block-repeat end address register 1. This
24-bit register contains the address of the 24-bit register contains the address of the
last instruction in the instruction block. last instruction in the instruction block.
BRS1 BRC1 save register. Whenever BRC1 is

loaded, BRS1 is loaded with the same
value. The content of BRS1 is not modi-
fied during the execution of the level 1
loop. Each time the level 1 loop is trig-
gered, BRC1 is reinitialized from BRS1.
This feature enables initialization of
BRC1 outside of the level 0 loop, reduc-
ing the time needed for each repetition.
Note: The 24-bit register values are stored in two consecutive 16-bit locations. Bits 23–16 are stored at the lower address (the
eight most significant bits in this location are ignored by the CPU). Bits 15–0 are stored at the higher address. For
example, RSA0(23–16) is accessible at address 00 003Ch, and RSA0(15–0) is accessible at address 00 003Dh.
CPU Registers 2-41

Status Registers (ST0_55−ST3_55)
2.10 Status Registers (ST0_55−ST3_55)

These four 16-bit registers (see Figure 2−15) contain control bits and flag bits.
The control bits affect the operation of the C55x+ DSP and the flag bits reflect
the current status of the DSP or indicate the results of operations.
ST0_55, ST1_55, and ST3_55 are each accessible at two addresses (see
Section 2.2, Memory-Mapped Registers). At one address, all C55x+ DSP bits
are available. At the other address (the protected address), the bits highlighted
in Figure 2−15 cannot be modified. The protected address is provided to sup-
port C54x DSP code that was written to access ST0, ST1, and PMST (the
C54x DSP counterpart of ST3_55). Reserved bits are not available for use.
Note:
Always write 1100b (Ch) to bits 11−8 of ST3_55.
Some C55x+ DSP devices do not have an instruction cache; these devices
do not use the CAFRZ, CAEN, and CACLR bits.
2-42 CPU Registers

Figure 2−15. Status Registers

ST0_55
15 14 13 12 11 10 9
ACOV2† ACOV3† TC1† TC2 CARRY ACOV0 ACOV1
R/W−0 R/W−0 R/W−1 R/W−1 R/W−1 R/W−0 R/W−0
8 7 6 5 4 3 2 1 0
DP[15:7]
R/W−0
ST1_55
15 14 13 12 11 10 9 8
BRAF CPL XF HM INTM M40† SATD SXMD
R−0 R−0 R/W−1 R/W−0 R/W−1 R/W−0 R/W−0 R/W−1
7 6 5 4 3 2 1 0
C16 FRCT C54CM† ASM
R/W−0 R/W−0 R/W−1 R/W−0
ST2_55
15 14 13 12 11 10 9 8
ARMS Reserved DBGM EALLOW RDM GOVF CDPLC
R/W−0 R−11b R/W−1 R/W−0 R/W−0 R−0 R/W−0
7 6 5 4 3 2 1 0
AR7LC AR6LC AR5LC AR4LC AR3LC AR2LC AR1LC AR0LC
ST3_55
15 14 13 12 11 10 9 8
CAFRZ†# CAEN†# CACLR†# HINT†‡ Reserved (always write as 1100b)
R/W−0 R/W−0 R/W−0 R/W−1 R/W−1100b
7 6 5 4 3 2 1 0
CBERR† MPNMC§ SATA† Reserved BPTR CLKOFF SMUL SST
R/W−0 R/W−pins R/W−0 R/W−0¶ R −§ R/W−0 R/W−0 R/W−0
† Highlighted bit: If you write to the protected address of the status register, then a write to this bit has no effect, and the bit always
appears as a 0 during read operations.
‡ The HINT bit is not used for all C55x+ DSP host port interfaces (HPIs). Consult the documentation for the specific C55x+ DSP.
§ The reset value of MPNMC may be dependent on the state of predefined pins at reset. To check this for a particular C55x+ DSP,
see its data manual. The reset value of BPTR bit is dependent of the configuration register value at reset time.
¶ Always write 0 to this bit.
# Some C55x+ DSP devices do not have an instruction cache; these devices do not use bits CAFRZ, CAEN, and CACLR.
CPU Registers 2-43

2.10.1 ST0_55 Bits
This section describes the bits of ST0_55 in alphabetical order.
2.10.1.1 ACOV0, ACOV1, ACOV2, and ACOV3 Bits of ST0_55
Each of the four accumulators has its own overflow flag in ST0_55:
9 ACOV1 AC1 overflow flag Read/Write 0
For each of these flags:
Overflow detection depends on the M40 bit in ST1_55:
M40 = 0: Overflow is detected at bit position 31.

M40 = 1: Overflow is detected at bit position 39.
If you need compatibility with TMS320C54x DSP code, then ensure that
M40 = 0.
ACOVx is set when an overflow occurs in ACx, where x is 0, 1, 2, or 3.
Once an overflow occurs, ACOVx remains set until one of the following
events occurs:
A DSP hardware or software reset is performed.
The CPU executes a conditional branch, call, return, or execute
instruction that tests the state of ACOVx.
ACOVx is explicitly cleared by a status bit clear instruction. For
example, you can clear ACOV1 by using the following instruction:
bit(ST0, #ST0_ACOV1) = #0; Clears ACOV1 bit
bit(ST0, #ST0_AC0V1) = #1; Sets ACOV1 bit
If AC0Vx is cleared by a status bit clear instruction, then it will not clear
the global overflow bit (GOVF) in the ST2_55 status register. You can
clear the global overflow bit by using the following instruction:
bit(ST2, #ST2_GOVF) = #0 ; Clears GOVF bit
bit(ST2, #ST2_GOVF) = #1 ; Sets GOVF bit
If one of the ACOVx bit is set, then it will set bit 9, the global overflow bit
(GOVF), in ST2_55 (bit number 9).
2-44 CPU Registers

2.10.1.2 CARRY Bit of ST0_55

11 CARRY Carry bit Read/Write 1
The following are main points about the carry bit:
Carry/borrow detection depends on the M40 bit in ST1_55:
M40 = 0: Carry/borrow is detected with respect to bit position 31.

M40 = 1: Carry/borrow is detected with respect to bit position 39.
If you need compatibility with TMS320C54x DSP code, then ensure that
M40 = 0.
When an addition is performed in the arithmetic and logic unit of the D unit
SALU1 or 2 and if the addition generates a carry, then the CARRY bit is
set. If no carry is generated, then the CARRY bit is cleared. There is one
exception to this behavior: When the following syntax is used (shifting
Smem by 16 bits), the CARRY bit is set for a carry but is not affected if no
carry is generated.
ACy = ACx + Smem <<#16
When a subtraction is performed in the D unit SALU1 or 2 and if the sub-

traction generates a borrow, then the CARRY bit is cleared; if no borrow
is generated, then the CARRY bit is set. There is one exception to this be-
havior: When the following syntax is used (shifting Smem by 16 bits), the
CARRY bit is cleared for a borrow but is not affected if no borrow is gener-
ated.
ACy = ACx − Smem <<#16
CARRY bit is modified by the logical shift instructions.
For signed shift instructions and rotate instructions, you can choose
whether CARRY bit is modified.
The following instruction syntaxes modify CARRY bit to indicate particular

computation results when the destination register (Ra) is an accumulator:
Ra = min(Rb, Ra) Minimum comparison
Ra = max(Rb, Ra) Maximum comparison
Ra = |Rb| Absolute value
Ra = −Rb Negate
You can clear and set the CARRY bit with the following instructions:
bit(ST0, #ST0_CARRY) = #0; Clears CARRY
bit(ST0, #ST0_CARRY) = #1; Sets CARRY
CPU Registers 2-45

2.10.1.3 DP Bit Field of ST0_55

Bits Name Description Accessibility HW Reset
8–0 DP Copy of the 9 most significant bits Read/Write 0
of the data page register (DP)
This 9-bit field is provided for compatibility with code transferred from the C54x
DSPs. C55x+ DSPs have an extended data page register (XDP) independent
of ST0_55. Any change to bits 15–7 of this extended data page register—
XDP(15–7)—is reflected in the DP status bits. Any change to the DP status bits
is reflected in XDP(15–7). When generating addresses for the XDP direct ad-
dressing mode, the CPU uses the full data page register, XDP(23−0). You are
not required to use the DP status bits; you can modify XDP directly.
Note:
If you want to load ST0_55 but do not want the access to change the content
of the data page register, then use an OR or an AND operation with a mask
value that does not modify the 9 least significant bits (LSBs) of ST0_55. For
an OR operation, put 0s in the 9 LSBs of the mask value. For an AND opera-
tion, put 1s in the 9 LSBs of the mask value.
2.10.1.4 TC1 and TC2 Bits of ST0_55

12 TC2 Test/control flag 2 Read/Write 1
13 TC1 Test/control flag 1 Read/Write 1
The main function of the test/control bit is to hold the result of a test performed
by specific instructions. The following are main points about the test/control
bits:
All the test instructions that affect a test/control flag allow you to choose
whether the TC1 or TC2 bit is affected.
TCx (where x = 1 or 2) or a Boolean expression of TCx can be used as

a trigger in any conditional instruction.
You can clear and set TC1 and TC2 bits with the following instructions:
bit(ST0, #ST0_TC1) = #0 ; Clears TC1

bit(ST0, #ST0_TC1) = #1 ; Sets TC1
bit(ST0, #ST0_TC2) = #0 ; Clears TC2
bit(ST0, #ST0_TC2) = #1 ; Sets TC2
2-46 CPU Registers

2.10.2 ST1_55 Bits

2.10.2.1 ASM Bit Field of ST1_55

Bits Name Description Accessibility HW Reset
4–0 ASM Accumulator shift mode bit Read/Write 00000b
ASM is not used by native C55x+ instructions but is available to support C54x
code running on the C55x+ DSP. In a C54x DSP, the ASM field supplies a
signed shift count for special instructions that shift an accumulator value. The
C55x+ DSP ASM field is used in the C54x DSP-compatible mode
(C54CM = 1).
Before reading further, it is important to know that the C55x+ DSP register that
contains ASM (status register ST1_55) is accessible at two addresses. One
address, 00 0003h, supports native C55x+ DSP instructions. The other ad-
dress, 00 0007h, supports C54x DSP code that accesses ST1 at 0007h.
If C54CM = 1 (C54x DSP-compatible mode):
When the ASM is loaded by a write to address 00 0007h, the 5-bit ASM
value is sign-extended to 16 bits and written to temporary register 2 (T2).
Clear/set status register bit instructions do not affect this bit field. When
a C54x DSP instruction requests the CPU to shift an accumulator accord-
ing to ASM, the CPU uses the shift count in T2.
When T2 is loaded, the five least significant bits are copied to ASM.
Because T2 is tied to ASM, T2 is not available as a general-purpose data

register.
If C54CM = 0:
ASM is ignored. During an accumulator shift operation, the CPU reads the
shift count from the temporary register (T0, T1, T2, or T3) that was speci-
fied in the C55x+ DSP instruction or from a constant embedded in the
C55x+ DSP instruction.
T2 can be used as a general-purpose data register. Writing to address

00 0007h does not affect T2, and writing to T2 does not affect ASM.
If the C54CM bit = 0, and an MMR write updates the C54CM bit to 1 and the
ASM field at the same time, then the sign extension of the value loaded in T2
is performed accordingly to the new value of the C54CM bit (that is,
C54CM = 1).
CPU Registers 2-47

2.10.2.2 BRAF Bit of ST1_55

Bit Name Description Accessibility Reset Value
15 BRAF Block-repeat active flag Read/Write 0
In the C54x DSP-compatible mode (C54CM = 1), the BRAF bit indicates/con-
trols the status of a block-repeat operation.
If C54CM = 0:
The BRAF bit is not used. The status of repeat operations is maintained auto-
matically by the CPU (see the description for CFCT in Section 2.7, Program
Flow Registers (PC, RETA, CFCT)).
If C54CM = 1:
Reading the BRAF bit indicates the status of a block-repeat operation:
BRAF Description
0 No block-repeat operation is active.
1 A block-repeat operation is active.
To stop an active block-repeat operation in the C54x DSP-compatible mode,

you can clear the BRAF bit with the following instruction:
bit(ST1, #ST1_BRAF) = #0 ; Clears BRAF
You can set BRAF with the following instruction:
bit(ST1, #ST1_BRAF) = #1 ; Sets BRAF
BRAF also can be set or cleared with an instruction that modifies ST1_55.
If the C54CM bit = 0, and an MMR write updates the C54CM bit to 1 and the
BRAF bit at the same time, then the BRAF bit modifications are performed ac-
cordingly to the new value of the C54CM bit (C54CM = 1).
Functionality of BRAF:
A block-repeat loop begins with a block-repeat instruction such as the
blockrepeat{} instruction. The BRAF bit is set at the decode phase of this
block-repeat instruction to indicate that a loop is active.
Each time the last instruction of the loop enters the decode phase of the
pipeline, the CPU checks the values of the BRAF bit and counter register
(BRC0). If BRAF = 1 and BRC0 > 0, then the CPU decrements BRC0 by 1 and
begins the next iteration of the loop. Otherwise, the CPU stops the loop. In
either case, the last instruction completes its execution through the pipeline.
2-48 CPU Registers

The BRAF bit is cleared in the following cases:
The last instruction of the loop enters the decode phase and BRC0 is de-
cremented to 0. BRAF is automatically cleared one cycle later.
An instruction writes 0 to the block-repeat counter, BRC0. BRAF is auto-

matically cleared one cycle later.
A far branch (goto || far()) or far call (call || far()) instruction is executed.
(The BRAF bit is not cleared by the execution of other call or branch in-
structions, or by the execution of an intr() or trap() instruction.)
The BRAF bit is manually cleared by a bit (ST1, #ST1_BRAF) = #0 instruc-

tion or an instruction that modifies status register ST1_55.
The BRAF bit is saved and restored with ST1_55 during the context switches
caused by an interrupt and a return-from-interrupt instruction. BRAF is not
saved when the CPU responds to a call instruction.
If a block-repeat loop is in progress and your program must switch modes from
C54CM = 1 to C54CM = 0, then the BRAF bit must be cleared before or during
the switch. There are three options:
Wait until the loop is finished (when BRAF is cleared automatically) and
then clear C54CM.
Clear BRAF (this also stops the loop) and then clear C54CM.
Clear BRAF and C54CM at the same time with an instruction that modifies
ST1_55.
Pipeline considerations. As already mentioned, the CPU clears BRAF one

cycle after executing an instruction that clears BRC0. This modification of
BRAF is not pipeline-protected. To ensure that BRAF is modified before anoth-
er instruction reads BRAF, you may need to insert instructions between the in-
struction that clears BRC0 and the instruction that reads BRAF. For example:
mmap(@BRC0) = #0h ; Clear BRC0 in W1 phase.

; BRAF bit is cleared in W2 phase.
nop
nop
nop
nop
AR0 = mmap(@ST1_55) ; Read ST1_55 in R phase, including
; correct value of BRAF bit.
CPU Registers 2-49

The number of cycles to insert depends on when the first instruction clears
BRC0:
Cycles to
Instruction Example Pipeline Phase When BRC0 Is Cleared† Insert
BRC0 = #3 Address 2-phase (AD2) 0
BRC0 = *AR0 Execute 2-phase (X2) 3
mmap(@BRC0) = #3 Write 1 phase (W1) 4
† Consult the instruction set documentation for the active pipeline phase of a given syntax.
This pipeline issue can also affect when the loop ends. To ensure that the
BRAF bit is modified before the last instruction of the loop reaches the decode
phase, you must insert 8 or 9 cycles between the instruction that clears BRAF
and the last instruction:
Cycles to
Instruction Example Pipeline Phase When BRAF Is Modified† Insert
bit(ST1, #ST1_BRAF) = #0 Execute 2-phase (X2) 8
mmap (@ST1_L) = #8700h Write 1 phase (W1) 9
† Consult the instruction set documentation for the active pipeline phase of a given syntax.
Updating the BRAF bit prior to a return instruction (RET or RETI) is protected
in the pipeline. After the return, if the next instruction reads the BRAF bit, then
it reads the updated value.
2.10.2.3 C16 Bit of ST1_55

7 C16 Dual 16-bit arithmetic mode bit Read/Write 0
In the C54x DSP-compatible mode (C54CM = 1), the execution of some in-
structions is affected by C16. C16 determines whether such an instruction is
executed in a single 32-bit operation (double-precision arithmetic) or in two
parallel 16-bit operations (dual 16-bit arithmetic).
If C54CM = 1: The arithmetic performed in the D-unit ALU depends on C16:

C16 Description
0 Dual 16-bit mode is Off. For an instruction that is affected by C16,
the D-unit ALU performs one 32-bit operation.
1 Dual 16-bit mode is On. For an instruction that is affected by C16,
the D-unit ALU performs two 16-bit operations in parallel.
2-50 CPU Registers

If C54CM = 0: The CPU ignores C16. The instruction syntax alone determines
whether dual 16-bit arithmetic or 32-bit arithmetic is used.
You can clear and set C16 with the following instructions:
bit(ST1, #ST1_C16) = #0 ; Clears C16 bit

bit(ST1, #ST1_C16) = #1 ; Sets C16 bit
2.10.2.4 C54CM Bit of ST1_55

5 C54CM TMS320C54x DSP-compatible Read/Write 1
mode bit
The C54CM bit determines whether the CPU will support code that was devel-
oped for a C54x DSP:
C54CM Description
0 C54x DSP-compatible mode is disabled. The CPU supports code
written for a C55x/C55x+ DSP.
1 C54x DSP-compatible mode is enabled. This mode must be set
when you are using code that was originally developed for a C54x
DSP. All the C55x/C55x+ DSP CPU resources remain available;
therefore, as you translate code, you can take advantage of the addi-
tional features on the C55x+ DSP to optimize your code.
Change modes with the following instructions and assembler directives:
bit(ST1, #ST1_C54CM) = #0 ; Clear C54CM bit

.C54CM_off ; Tell assembler C54CM = 0
bit(ST1, #ST1_C54CM) = #1 ; Set C54CM bit
.C54CM_on ; Tell the assembler C54CM = 1
Do not modify the C54CM bit within a local-repeat loop as shown in this exam-
ple:
localrepeat{ ; Start of loop 1

...
bit(ST1, #ST1_C54CM) = #1
...
dbl(*AR3+) = AC0
} ; End of loop 1
Also, do not modify C54CM bit in parallel with a block-repeat instruction such
as:
bit(ST1, #ST1_C54CM) = #0
|| Repeat end2 ; Start of loop 2
...
end2 dbl(*AR4+) = AC1 ; End of loop 2
CPU Registers 2-51

2.10.2.5 CPL Bit of ST1_55

14 CPL Compiler mode bit Read/Write 0
In C55x+ DSP generations, the CPL bit determines which of the XDP or XSP
registers is used for direct addressing modes. In C55x+ DSP, these two direct
addressing modes are independent from the CPL bit. The CPL bit is kept in
the C55x+ DSP for source compatibility purposes. A write or read to this bit
doesn’t do anything. The HW and SW reset values are the same as in the
C55x+ DSP generations.
2.10.2.6 FRCT Bit of ST1_55

6 FRCT Fractional mode bit Read/Write 0
The FRCT bit turns the fractional mode on or off:

FRCT Description
0 Fractional mode is Off. Results of multiply operations are not shifted.
1 Fractional mode is On. Results of multiply operations are shifted left
by 1 bit for decimal point adjustment. This is required when you mul-
tiply two signed Q15 values and you need a Q31 result.
You can clear and set FRCT with the following instructions:
bit(ST1, #ST1_FRCT) = #0 ; Clears FRCT bit

bit(ST1, #ST1_FRCT) = #1 ; Sets FRCT bit
2.10.2.7 HM Bit of ST1_55

12 HM Hold mode bit Read/Write 0
When the external memory interface (EMIF) of the DSP receives a HOLD
request, the DSP places the EMIF output pins in the high-impedance state.
Depending on the value of the HM bit, the DSP may also stop internal program
execution:
HM Description
0 Hold mode is On. The DSP continues executing instructions from the
internal program memory.
1 Hold mode is Off. The DSP stops executing instructions from the
internal program memory.
You can use the following instructions to clear and set the HM bit:
bit(ST1, #ST1_HM) = #0 ; Clears HM bit

bit(ST1, #ST1_HM) = #1 ; Sets HM bit
2-52 CPU Registers

2.10.2.8 INTM Bit of ST1_55

11 INTM Interrupt mode bit Read/Write 1
The INTM bit globally enables or disables the maskable interrupts as shown
below. This bit has no effect on nonmaskable interrupts (those that cannot be
blocked by software).
INTM Description
0 All unmasked interrupts are enabled.
1 All maskable interrupts are disabled.
The following are main points about the INTM bit:
Modify the INTM bit with status bit clear and set instructions (see the fol-
lowing examples). The only other instructions that affect INTM are the soft-
ware interrupt instruction and the software reset instruction, which set
INTM before branching to the interrupt service routine.
bit(ST1, #ST1_INTM) = #0 ; Clears INT bit
bit(ST1, #ST1_INTM) = #1 ; Sets INT bit
In CPU cores with revisions older than 2.2, there is no pipeline protection
by the hardware between the INTM bit update and an interrupt jamming.
Because the INTM bit is updated in the execute phase of the pipeline, an
interrupt can be taken in between any of the five instructions following the
INTM set instruction which globally disables interrupts. In CPU cores with
revisions 2.2 or newer, no interrupt is taken after the INTM set instruction.
The state of the INTM bit is automatically saved when the CPU approves
an interrupt request. Specifically, the INTM bit is saved when the CPU
saves ST1_55 to the data stack.
Before executing an interrupt service routine (ISR) triggered by either an

intr(#k5) instruction, the reset instruction, or a hardware interrupt source,
the CPU automatically sets the INTM bit to globally disable the maskable
interrupts. The trap(#k5) instruction does not affect the INTM bit. The ISR
can re-enable the maskable interrupts by clearing the INTM bit.
A return-from-interrupt instruction restores the INTM bit from the data

stack.
When the CPU is halted in the real-time emulation mode of the debugger,
INTM is ignored and only time-critical interrupts can be serviced (see the
description for the debug interrupt enable registers in Section 2.8.4).
CPU Registers 2-53

2.10.2.9 M40 Bit of ST1_55

10 M40 Computation mode bit for the D unit Read/Write 0
The M40 bit selects one of two computation modes for the D unit:
M40 Description
0 D-Unit computation mode is 32-bit mode. In this mode:
The sign bit is extracted from bit position 31.
During arithmetic, the carry is determined with respect to bit position 31.
Overflows are detected at bit position 31.
During saturation, the saturation value is 00 7FFF FFFFh (positive overflow) or FF 8000 0000h (neg-
ative overflow).
Accumulator comparisons versus 0 are performed using bits 31–0.
Shift or rotate operations are performed on 32-bit values.
During left shifts or rotations of accumulators, bits shifted out are extracted from bit position 31.
During right shifts or rotations of accumulators, bits shifted in are inserted at bit position 31.
During signed shifts of accumulators, if SXMD = 0, then 0 is copied into the accumulator’s guard bits;
if SXMD = 1, then bit 31 is copied into the accumulator’s guard bits. During any rotations or logical
shifts of accumulators, the guard bits of the destination accumulator are cleared.
Note: In the TMS320C54x DSP-compatible mode (C54CM = 1), there are some exceptions: An accumu-
lator’s sign bit is extracted from bit position 39. Accumulator comparisons versus 0 are performed using
bits 39–0. Signed shifts are performed as if M40 = 1.
1 D-Unit computation mode is 40-bit mode. In this mode:

The sign bit is extracted from bit position 39.
During arithmetic, the carry is determined with respect to bit position 39.
Overflows are detected at bit position 39.
During saturation, the saturation value is 7F FFFF FFFFh (positive overflow) or 80 0000 0000h (neg-
ative overflow).
Accumulator comparisons versus 0 are performed using bits 39–0.
Shift or rotate operations are performed on 40-bit values.
During left shifts or rotations of accumulators, bits shifted out are extracted from bit position 39.
During right shifts or rotations of accumulators, bits shifted in are inserted at bit position 39.
You can clear and set M40 with the following instructions:
bit(ST1, #ST1_M40) = #0 ; Clears M40 bit

bit(ST1, #ST1_M40) = #1 ; Sets M40 bit
2-54 CPU Registers

2.10.2.10 SATD Bit of ST1_55

9 SATD Saturation mode bit for the D unit Read/Write 0
The SATD bit determines whether or not the CPU saturates the results of com-
putation in the D unit which overflowed:
SATD Description
0 Saturation mode in the D unit is Off. No saturation is performed.
1 Saturation mode in the D unit is On. If an operation performed by the

D unit results in an overflow, then the result is saturated. The satura-
tion depends on the value of the M40 bit:
M40 = 0 The CPU saturates the result to 00 7FFF FFFFh (positive
overflow) or FF 8000 0000h (negative overflow).
M40 = 1 The CPU saturates the result to 7F FFFF FFFFh (positive
overflow) or 80 0000 0000h (negative overflow).
If you want compatibility with TMS320C54x DSP code, then make sure
M40 = 0.
You can clear and set SATD with the following instructions:
bit(ST1, #ST1_SATD) = #0 ; Clears SATD bit
bit(ST1, #ST1_SATD) = #1 ; Sets SATD bit
CPU Registers 2-55

2.10.2.11SXMD Bit of ST1_55

8 SXMD Sign-extension mode bit for the D unit Read/Write 1
The SXMD bit turns on or off the sign-extension mode which affects accumula-
tor loads and also additions, subtractions, and signed shift operations that are
performed in the D unit:
SXMD Description
0 Sign-extension mode is Off. When sign-extension mode is off:
For 40-bit operations, 16-bit or smaller operands are zero extended to 40 bits.
For the conditional subtract instruction, any 16-bit divisor produces the expected result.
When the D-unit arithmetic logic unit (ALU) is locally configured in its dual 16-bit mode (by a dual
16-bit arithmetic instruction):
16-bit values used in the higher part of the D-unit ALU are zero extended to 24 bits.
16-bit accumulator halves are zero extended if they are shifted right.
During a signed shift of an accumulator, if it is a 32-bit operation (M40 = 0), then 0 is copied
into the accumulator’s guard bits (39–32).
During a signed right shift of an accumulator, the shifted value is zero extended.
1 Sign-extension mode is On. In this mode:
For 40-bit operations, 16-bit or smaller operands are sign extended to 40 bits.
For the conditional subtract instruction, the 16-bit divisor must be a positive value (its most sig-
nificant bit (MSB) must be 0).
When the D-unit ALU is locally configured in its dual 16-bit mode (by a dual 16-bit arithmetic
instruction):
16-bit values used in the higher part of the D-unit ALU are sign extended to 24 bits.
16-bit accumulator halves are sign extended if they are shifted right.
During a signed shift of an accumulator, if it is a 32-bit operation (M40 = 0), then bit 31 is copied
into the accumulator guard bits (39–32).
During a signed right shift of an accumulator, the shifted value is sign extended, unless the uns()
expression qualifier designates the accumulator value as unsigned.
SXMD is ignored during some operations:
For unsigned operations (boolean logic operations, rotate operations, and

logical shift operations), input operands are always zero extended to
40 bits, regardless of the value of SXMD.
For operations performed in a multiply-and-accumulate unit (MAC), 16-bit

input operands are sign extended to 17 bits, regardless of the value of
SXMD.
2-56 CPU Registers

If an operand in an instruction is enclosed in the operand qualifier uns(),

then the operand is treated as unsigned, regardless of the value of SXMD.
You can clear and set SXMD with the following instructions:
bit(ST1, #ST1_SXMD) = #0 ; Clears SXMD bit
bit(ST1, #ST1_SXMD) = #1 ; Sets SXMD bit
2.10.2.12 XF Bit of ST1_55

13 XF External flag Read/Write 1
The XF bit is a general-purpose output bit. This bit is directly connected to the
XF pin on those C55x+ DSP devices that have an XF pin. Setting the XF bit
drives the XF pin high. Clearing the XF bit drives the XF pin low. The following
instructions clear and set XF:
bit(ST1, #ST1_XF) = #0 ; Clears XF bit
bit(ST1, #ST1_XF) = #1 ; Sets XF bit
2.10.3 ST2_55 Bits

2.10.3.1 AR0LC–AR7LC Bits of ST2_55

n ARnLC XARn linear/circular addressing Read/Write 0
configuration bit
Each ARnLC bit determines whether XARn is used for linear addressing or
circular addressing.
The CPU has 16 extended auxiliary registers, XAR0–XAR15. Only the XAR0
through XAR7 registers (n = 0, 1, 2, 3, 4, 5, 6, or 7) have a linear/circular
configuration bit in ST2_55. The XAR15 register has also a linear/circular con-
figuration: the CDPLC bit in ST2_55 (see Section 2.10.3.3).
ARnLC Description
0 XARn is used for linear addressing
1 XARn is used for circular addressing
For example, if AR3LC = 0, then XAR3 is used for linear addressing; if

AR3LC = 1, then XAR3 is used for circular addressing.
You can clear and set the ARnLC bits with the status bit set/clear instruction.
For example, the following instructions respectively clear and set AR3LC.
bit(ST2, #ST2_AR3LC) = #0 ; Clears AR3LC bit
bit(ST2, #ST2_AR3LC) = #1 ; Sets AR3LC bit
CPU Registers 2-57

2.10.3.2 ARMS Bit of ST2_55

15 ARMS AR mode switch Read/Write 0
In C55x+ DSP generations, the ARMS bit determines which of the two sets of
XAR indirect operands is used for XAR indirect addressing mode. In the C55x+
DSP, this addressing mode is independent from the ARMS bit. The ARMS bit
is kept in the C55x+ DSP for source compatibility purposes. A write or read to
this bit doesn’t do anything. The HW and SW reset values are the same as in
C55x+ DSP generations.
2.10.3.3 CDPLC Bit of ST2_55

8 CDPLC XAR15 linear/circular addressing Read/Write 0
configuration bit
The CDPLC bit determines whether the XAR15 register is used for linear ad-
dressing or circular addressing:
CDPLC Description
0 XAR15 is used for linear addressing
1 XAR15 is used for circular addressing
You can clear and set CDPLC with the following instructions:
bit(ST2, #ST2_CDPLC) = #0 ; Clears CDPLC bit
bit(ST2, #ST2_CDPLC) = #1 ; Sets CDPLC bit
2.10.3.4 DBGM Bit of ST2_55
12 DBGM Debug mode bit Read/Write 1
The DBGM bit provides the capability to block debug events during time-criti-
cal portions of a program:
DBGM Description
0 Debug events are enabled.
1 Debug events are disabled. The emulator cannot access memory or
registers. Software breakpoints still cause the CPU to halt, but hard-
ware breakpoints or halt requests are ignored.
The following are main points about the DBGM bit:
For pipeline protection, the DBGM bit can only be modified by status bit
clear and set instructions (see the following examples). No other instruc-
tions affect the DBGM bit.
bit(ST2, #ST2_DBGM) = #0 ; Clears DBGM bit
bit(ST2, #ST2_DBGM) = #1 ; Sets DBGM bit
The state of the DBGM bit is automatically saved when the CPU approves
an interrupt request or fetches the intr(#k5), trap(#k5), or reset instruction.
2-58 CPU Registers

Specifically, the DBGM bit is saved when the CPU saves ST2_55 to the
data stack.
Before executing an interrupt service routine (ISR) triggered by the

intr(#k5), reset instruction, or a hardware interrupt source, the CPU auto-
matically sets the DBGM bit to disable debug events. The ISR can reen-
able debug events by clearing the DBGM bit.
A return-from-interrupt instruction restores the DBGM bit from the data

stack.
2.10.3.5 EALLOW Bit of ST2_55

11 EALLOW Emulation access enable bit Read/Write 0
The EALLOW bit enables or disables write access to non-CPU emulation

registers:
EALLOW Description
0 Write access to non-CPU emulation registers is disabled
1 Write access to non-CPU emulation registers is enabled
The following are main points about the EALLOW bit:
The state of the EALLOW bit is automatically saved when the CPU ap-
proves an interrupt request or fetches the INTR #k5, TRAP #k5, or RESET
instruction. Specifically, the EALLOW bit is saved when the CPU saves
ST2_55 to the data stack.
Before executing an interrupt service routine (ISR) triggered by the INTR

#k5, TRAP #k5, or RESET instruction, or by a hardware interrupt source,
the CPU automatically clears the EALLOW bit to prevent accesses to the
emulation registers. The ISR can re-enable access by setting the
EALLOW bit:
bit(ST2, #ST2_EALLOW) = #0 ; Clears EALLOW bit
bit(ST2, #ST2_EALLOW) = #1 ; Sets EALLOW bit
A return-from-interrupt instruction restores the EALLOW bit from the data

stack.
CPU Registers 2-59

2.10.3.6 GOVF Bit of ST2_55

9 GOVF Global overflow flag Read/Write 0
The C55x+ revision features the GOVF bit to support the expanded number
of accumulators in the D-unit.
GOVF Description
0 Global overflow is not detected
1 Global overflow is detected
Some important points about this bit:
GOVF is set if an overflow occurs in any accumulator register (including

AC0−AC3)
Similar to the ACOVx flags in the ST0_55 register, the overflow detection
depends on the M40 bit status in ST1_55 (see Section 2.10.1.1).
Once an overflow occurs, GOVF remains set until one of the following
events occurs:
A DSP hardware or software reset is performed
The CPU executes a conditional goto, call, return, or execute instruc-
tion that tests the state of GOVF
The GOVF bit is explicitly cleared by a status bit clear instruction. For
example, you can clear GOVF with the following instruction:
bit(ST2, #ST2_GOVF) = #0 ; Clears GOVF bit
2-60 CPU Registers

2.10.3.7 RDM Bit of ST2_55

10 RDM Rounding mode bit Read/Write 0
Certain instructions executed in the D unit allow you to indicate whether the
40-bit result is to be rounded or not. The type of rounding performed depends
on the value of the RDM bit:
RDM Description
0 Rounding mode is not selected and rounds to the infinite. The CPU
adds 8000h (2 raised to the 15th power) to the 40-bit operand. Then
the CPU clears bits 15 through 0 to generate a rounded result in a
24- or 16-bit representation. For a 24-bit representation, only bits 39
through 16 of the result are meaningful. For a 16-bit representation,
only bits 31 through 16 of the result are meaningful.
1 Rounding mode is selected and rounds to the nearest. The rounding
depends on bits 15 through 0 of the 40-bit operand, as shown by the
following if statements. The rounded result is in a 24-bit representa-
tion (in bits 39 through 16) or a 16-bit representation (in bits 31
through 16).
If ( 0 =< bits 15–0 < 8000h )
CPU clears bits 15–0
If ( 8000h < bits 15–0 < 10000h )
CPU adds 8000h to the operand and then clears bits 15–0
If ( bits 15–0 == 8000h )
If bits 31–16 contain an odd value
CPU adds 8000h to the operand and then clears bits 15–0
If bits 31−16 contain an even value
CPU clears bits 15−0
If you need compatibility with TMS320C54x DSP code, then ensure RDM = 0
and C54CM = 1. When C54CM = 1 (C54x DSP-compatible mode enabled),
the following instructions do not clear bits 15–0 of the result after the rounding:
ACa = saturate(rnd(ACb)) Saturate with rounding

ACA = rnd(ACb) Round
frct(lms(Xmem,Ymem,ACa,ACb)) Least mean square
You can clear and set RDM with the following instructions:
bit(ST2, #ST2_RDM) = #0 ; Clears RDM bit
bit(ST2, #ST2_RDM) = #1 ; Sets RDM bit
CPU Registers 2-61

2.10.4 ST3_55 Bits

2.10.4.1 BPTR Bit of ST3_55

3 BPTR Byte/word-pointer bit Read/Write Configurable
This bit indicates whether the CPU is in byte or word-pointer mode (see Sec-
tion 3.1 for more details on data memory space referencing in both modes).
BPTR Description:
0 The CPU is in word-pointer mode:
Data memory locations are referenced by the A unit with 23-bit
effective word-addresses.
1 The CPU is in byte-pointer mode:
Data memory locations are referenced by the A unit with 24-bit
effective byte-addresses.
The following are the main points about the BPTR bit:
During a hardware or software reset, the bit 24 content of the 32-bit vector
location is copied into the BPTR bit, and reflects the default pointer mode
value of the CPU. When a software or hardware interrupt, or a software
trap() is taken, the CPU switches to this default pointer mode and executes
the corresponding ISR.
You can only switch byte- or word-pointer mode during the following un-
conditional function call (no other instruction can modify this bit):
call ACa || to_word ; Switches to word pointer mode
call L16 || to_word ; Switches to word pointer mode
call P24 || to_word ; Switches to word pointer mode
call ACa || to_byte ; Switches to byte pointer mode
call L16 || to_byte ; Switches to byte pointer mode
call P24 || to_byte ; Switches to byte pointer mode
When the CPU switches from one pointer mode to the other:
If BPTR is 1 (byte-pointer mode) and becomes 0 at the function call,
then the XSP/XSSP registers are shifted right by 1
If BPTR is 0 (word-pointer mode) and becomes 1 at the function call,
then the XSP/XSSP registers are shifted left by 1
If the BPTR bit status doesn’t change after using any of these instruc-
tions, then the shift on XSP/XSSP register doesn’t happen
When the CPU follows an interrupt or calls a function, BPTR bit is saved
in CFCT register at bit position 4 (see Section 2.7.1 for more details on the
2-62 CPU Registers

CFCT register). When the CPU returns from an interrupt or a called sub-
routine, the BPTR bit value is restored from the CFCT register.
2.10.4.2 CACLR Bit of ST3_55

13 CACLR Cache clear bit Read/Write 0
To clear (or flush) the instruction cache (invalidate all lines of its data arrays),
set the CACLR bit. You can set CACLR using the following instruction:
bit(ST3_55, #ST3_CACLR) = #1 ; Sets CACLR bit
Once set, CACLR remains 1 until the flush process is complete, at which time
CACLR is automatically reset to 0. Therefore, you can poll CACLR to get the
status:
CACLR Description
0 The cache flush process is completed
1 The cache flush process is not completed. All cache blocks are invalid.
The number of cycles required to flush the cache depends on the
memory architecture. When the cache is flushed, the content of the
prefetch queue in the instruction buffer unit is automatically flushed.
2.10.4.3 CAEN Bit of ST3_55

14 CAEN Cache enable bit Read/Write 0
The CAEN bit enables or disables the program cache:

CAEN Description
0 The cache is disabled. The cache controller never receives a program
request. All program requests are handled either by the internal
memory or the external memory, depending on the decoded address.
1 The cache is enabled. Program code is fetched from the cache, the
internal memory, or the external memory depending on the decoded
address.
Some important notes:
When the cache is disabled by clearing the CAEN bit, the content of the
I unit instruction buffer queue is automatically flushed.
You can clear and set CAEN using the following instructions
bit(ST3, #ST3_CAEN) = #0 ; Clears CAEN bit

bit(ST3, #ST3_CAEN) = #1 ; Sets CAEN bit
CPU Registers 2-63

2.10.4.4 CAFRZ Bit of ST3_55

15 CAFRZ Cache freeze bit Read/Write 0
CAFRZ enables you to lock the instruction cache, so that its contents are not
updated on a cache miss but are still available for cache hits. The contents of
the cache remain undisturbed until CAFRZ is cleared.
CAFRZ Description
0 The cache is in its default operating mode.
1 The cache is frozen (the cache content is locked).
You can clear and set CAFRZ using the following instructions:
bit(ST3, #ST3_CAFRZ) = #0 ; Clears CAFRZ bit
bit(ST3, #ST3_CARFZ) = #1 ; Sets CAFRZ bit
2.10.4.5 CBERR Bit of ST3_55

7 CBERR CPU bus error flag Read/Write 0
(Can only write 0)
CBERR Description
0 The flag has been cleared by your program or by a reset.
1 An internal bus error has been detected.
The CBERR bit is set when an internal bus error is detected. This error causes
the CPU to set the bus error interrupt flag (BERRINTF) in interrupt flag register
1 (IFR1). A bit in BER register is also set to identify the source of the bus error
interrupt.
Writing a 1 to the CBERR bit has no effect. This bit is 1 only if an internal
bus error has occurred.
The interrupt service routine for the bus error interrupt (BERRINT) must
clear the CBERR bit before it returns control to the interrupted program
code:
bit(ST3, #ST3_CBERR) = #0 ; Clears CBERR bit
Note:
When a bus error occurs, the functionality of the instruction that caused the
error, and of any instruction executed in parallel, can not be assured.
2-64 CPU Registers

2.10.4.6 CLKOFF Bit of ST3_55

2 CLKOFF CLKOUT disable bit Read/Write 0
When CLKOFF = 0, the CLKOUT pin is enabled; the associated clock signal
appears on the pin. When CLKOFF = 1, the CLKOUT pin is disabled.
You can clear and set CLKOFF with the following instructions:
bit(ST3, #ST3_CLKOFF) = #0 ; Clears CLKOFF bit
bit(ST3, #ST3_CLKOFF) = #1 ; Sets CLKOFF bit
2.10.4.7 HINT Bit of ST3_55

12 HINT Host interrupt bit Read/Write 1
Use the HINT bit to send an interrupt request to a host processor by way of the
host port interface. You produce an active-low interrupt pulse by clearing and
then setting the HINT bit:
bit(ST3, #ST3_HINT) = #0 ; Clears HINT bit
bit(ST3, #ST3_HINT) = #1 ; Sets HINT bit
Note:
The HINT bit is not used for all C55x+ DSP host port interfaces (HPIs). Con-
sult the documentation for the specific C55x+ DSP.
CPU Registers 2-65

2.10.4.8 MPNMC Bit of ST3_55

6 MPNMC Microprocessor/ Read/Write May be dependent on the
microcomputer state of predefined pins at
mode bit reset. To check this for a
particular C55x+ DSP, see
its data manual.
The MPNMC bit enables or disables the on-chip ROM:

MPNMC Description
0 Microcomputer mode. The on-chip ROM is enabled; it is addressable
in program space.
1 Microprocessor mode. The on-chip ROM is disabled; it is not in the
program-space map.
Some important notes:
The reset value of the MPNMC bit may be dependent on the state of prede-
fined pins at reset. To check this for a particular C55x+ DSP, see its data
manual.
The software reset instruction does not affect the MPNMC bit.
You can clear and set MPNMC using the following instructions:
bit(ST3, #ST3_MPNMC) = #0 ; Clears MPNMC bit
bit(ST3, #ST3_MPNMC) = #1 ; Sets MPNMC bit
An instruction that changes the MPNMC bit must not be followed too
closely by a branch instruction. Otherwise, the CPU may use the old
MPNMC value and, as a result, fetch the next instruction from the incorrect
memory location. The minimum number of instruction cycles needed to
separate an MPNMC-update instruction and a branch instruction depends
on the type of branch instruction used. Table 2−11 divides branch instruc-
tions into three categories, and Table 2−12 shows the minimum number
of separation cycles needed for each category.
2-66 CPU Registers

Table 2−11. Categories of Branch Instructions

Category I Category II Category III
goto L16 return (when slow return selected) goto (ACa)
goto P24 if (cond) return (when slow return selected) call ACa
if (cond) goto L8 return_int (when slow return selected)
if (cond) goto L16
if (cond) goto P24
call L16
call P24
if (cond) call L16
if (cond) call P24
return (when fast return selected)
if (cond) return (when fast return

selected)
return_int (when fast return selected)
Table 2−12. Minimum Number of Instruction Cycles Required Between an

MPNMC-Update Instruction and a Branch Instruction
Cycles Required Before Subsequent Branch

Instruction
MPNMC-Update Instruction Category I Category II Category III
One of the following instructions: 7 2 1

bit(ST3_55, #ST3_MPNMC) = #1 (Set MPNMC bit)
bit(ST3_55, #ST3_MPNMC) = #0 (Clears MPNMC bit)
An instruction that changes MPNMC when writing to 8 3 2

the memory-mapped address for ST3_55
CPU Registers 2-67

Consider the following example in which the bit set instruction changes
MPNMC. Table 2−11 specifies CALL as a category I branch instruction.
Table 2−12 indicates that six cycles are needed between the bit set MPNMC
instruction and a category I branch instruction. In this example, the six cycles
are provided by inserting six nop (no operation) instructions. Other instructions
could be placed here instead.
bit(ST3, #ST3_MPNMC) = #1 ;Sets MPNMC bit
nop
nop
nop
nop
nop
nop
call #Subroutine
2.10.4.9 SATA Bit of ST3_55

5 SATA Saturation mode bit for the A unit Read/Write 0
The SATA bit determines whether the CPU saturates the results of computa-
tion in the A unit which overflowed:
SATA Description
0 Saturation mode in the A unit is Off. No saturation is performed.
1 Saturation mode in the A unit is On. If a calculation in the A-unit ALU
results in an overflow, the result is saturated to 7FFFh (for overflow
in the positive direction) or 8000h (for overflow in the negative direc-
tion).
You can clear and set SATA with the following instructions:
bit(ST3, #ST3_SATA) = #0 ; Clears SATA bit
bit(ST3, #ST3_SATA) = #1 ; Sets SATA bit
2.10.4.10 SMUL Bit of ST3_55

1 SMUL Saturation-on-multiplication mode bit Read/Write 0
The SMUL bit turns the saturation-on-multiplication mode on or off:

SMUL Description
0 Saturation on multiplication is Off
1 Saturation on multiplication is On. When SMUL = 1, FRCT = 1,
and SATD = 1, the result of 18000h × 18000h is saturated to 00
7FFF FFFFh (regardless of the value of the M40 bit).
For multiply-and-accumulate/-subtract instructions, the saturation is

performed after the multiplication and before the addition/subtraction.
2-68 CPU Registers

You can clear and set SMUL with the following instructions:
bit(ST3, #ST3_SMUL) = #0 ; Clears SMUL bit
bit(ST3, #ST3_SMUL) = #1 ; Sets SMUL bit
2.10.4.11SST Bit of ST3_55

Bit Name Description Accessibility Reset Value
0 SST Saturate-on-store mode bit Read/Write 0
In the C54x DSP-compatible mode (C54CM = 1), the execution of some accu-
mulator-store instructions is affected by SST. When SST is 1, the 40-bit accu-
mulator value is saturated to a 32-bit value before the store operation. If the
accumulator value is shifted, then the CPU performs the saturation after the
shift.
If C54CM = 1: SST turns the saturation-on-store mode on or off.

SST Description
0 Saturation-on-store mode is Off
1 Saturation-on-store mode is On. For an instruction that is affected by
SST, the CPU saturates a shifted or unshifted accumulator value be-
fore storing it. The saturation depends on the value of the sign-exten-
sion mode bit (SXMD):
SXMD = 0 The 40-bit value is treated as unsigned. If the 40-bit val-
ue is greater than 00 7FFF FFFFh, then the CPU pro-
duces the 32-bit result 7FFF FFFFh.
SXMD = 1 The 40-bit value is treated as signed. If the 40-bit value
is less than 00 8000 0000h, then the CPU produces the
32-bit result 8000 0000h. If the 40-bit value is greater
than 00 7FFF FFFFh, then the CPU produces
7FFF FFFFh.
If C54CM = 0: The CPU ignores SST. The instruction syntax alone determines
whether saturation occurs or not.
You can clear and set SST with the following instructions:
bit(ST3, #ST3_SST) = #0 ; Clears SST bit
bit(ST3, #ST3_SST) = #1 ; Sets SST bit
CPU Registers 2-69

2-70 CPU Registers
Chapter 3
Memory and I/O Space
The TMS320C55x+ (C55x+) DSP provides access to a unified data/pro-

gram space and an I/O space. Data-space addresses access general-pur-
pose memory and the memory-mapped CPU registers. Program-space ad-
dresses are used by the CPU to read instructions from memory. I/O space is
available for two-way communication with peripherals. An on-chip boot loader
provides ways to help load code and data into internal memory.
Topic Page
3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.4 I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.5 Boot Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
3-1
Memory Map
3.1 Memory Map

All 16M bytes of memory are addressable as program space or data space
(see Figure 3−2).
The CPU uses 24-bit program address to reference program code bytes in
program space.
The CPU uses 24-bit data addresses to reference data memory locations (8,
16, or 32 bits). The way these addresses are generated within the A unit de-
pends on the BPTR bit of the ST3_55 register. This bit status defines the point-
er mode of the CPU: word- or byte-pointer mode. Below is an overview of the
differences between the two operating modes. Refer to Section 2.10.4.1 for
more details on the BPTR bit, and to Chapter 7 for a detailed description of the
CPU byte-pointer mode.
In both pointer modes, the data address buses carry a 24-bit value represent-
ing a 24-bit byte address.
When the CPU is in word-pointer mode:
All data-space addresses are computed and generated in the A unit as
word aligned to ensure compatibility with previous C55x+ generations.
The data memory locations are referenced by the A unit with 23-bit effec-
tive word address generated by the DAGEN with 24-bit address register
(XARx, XDP, XSP, XSSP).
Before being posted on the data address buses, the generated addresses
are shifted to the MSBs by one bit to produce the equivalent 24-bit byte
addresses.
Note that it is the user’s responsibility to ensure that, in word-pointer mode,
the 24th bit of the effective word address generated by the user’s program
is set to 0; in the case it is not, the CPU behavior is undefined.
When the CPU is in byte-pointer mode:
All data-space addresses are computed and generated in the A unit as
byte aligned to enable efficient processing of the native C “char” datatype
(8 bits).
The data memory locations are referenced by the A unit with 24-bit effec-
tive byte address generated by the DAGEN with 24-bit address register
(XARx, XDP, XSP, XSSP).
The generated addresses can be posted as is on the data address buses
without any shift, since in byte-pointer mode, the generated addresses are
24-bit byte addresses.
3-2 Memory and I/O Space

Memory Map
Figure 3−1 illustrates how generated addresses are carried to the address
buses in word- and byte-pointer modes.
Figure 3−1. 24-Bit Addresses Generated AU DAGEN in Word-/Byte-Pointer Mode
Data address buses BAB, CAB, DAB, EAB, FAB (each 24 bits)
Shift by 1 to MSBs
<< << <<
When BPTR is set to 0, word-pointer mode
X Y C
Three 24-Bit
AU DAGENS
AU Register File AU ALU

24-Bit Registers
C55x+ data memory addressing model is a flat (linear) 24-bit data memory ad-
dressing model with addresses going from:
00 0000h to 7F FFFFh in word-pointer mode
00 0000h to FF FFFFh in byte-pointer mode.
C55x+ addressing mode provides the ability to address applications with data
tables that are greater than 64 Kwords in length, and/or with data tables which
span over 64-Kword blocks.
In word-pointer mode, the first 96 addresses of data memory space are re-
served for the memory-mapped registers (MMRs). These reserved address
are going from:
00 0000h to 00 0005Fh in word-pointer mode, and
00 0000h to 00 00BFh in byte-pointer mode.
There is a corresponding block of 192 addresses (00 0000h–00 00BFh) in pro-

gram space.
It is recommended that you do not store program or data code to these ad-
dresses.
Memory and I/O Space 3-3

Memory Map
To see how the addresses are divided between internal memory and external
memory, and for the details regarding internal memory, see the data manual
for your C55x+ DSP.
Figure 3−2. Memory Map
Program Data Program Space Data Space Data Space

Memory Address Range Address Range Address Range
(Byte-Pointer (Byte Address in (Word Address in
Mode) Byte-Pointer Mode) Word-Pointer Mode)
00 0000 00 0000 00 0000
MMRs
00 00BFh 00 00BFh 00 005Fh
00 00C0h .... 00 00C0h .... 00 0060h ....
.... FF FFFFh .... FF FFFFh .... 7F FFFFh

Program Space
3.2 Program Space

The CPU accesses program space only when reading instructions from pro-
gram memory. The CPU uses byte addresses (see Section 3.2.1) to reference
instructions to be fetched (see Section 3.2.2), decoded and executed. In-
struction fetches are grouped by 64-bit fetch packets which are aligned on mul-
tiple of 8-byte program addresses (see Section 3.2.3).
3.2.1 Byte Addresses (24 Bits)

When the CPU references instructions from program memory, it uses byte ad-
dresses, which are addresses assigned to individual bytes. These addresses
are 24 bits wide. The following figure shows a row of 64-bit-wide memory. Each
byte is assigned an address. For example, byte 0 is at address 00 0100h and
byte 2 is at address 00 0102h.
Byte addresses Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7
00 0100h−00 0107h
3.2.2 Instruction Organization in Program Space

The DSP supports 8-, 16-, 24-, 32-, 40-, 48-, 56-, 64-, 72-, 80-, 88-, 96-, 104-,
112-, 120-, and 128-bit instructions. The following tables provide an example
of how instructions are organized in program space. Five instructions of vary-
ing sizes have been stored in 64-bit-wide memory. The address for each in-
struction is the address of its most significant byte (the opcode). No code is
stored in the shaded bytes.
Instruction Size Address
A 24 bits 00 0101h
B 16 bits 00 0104h
C 32 bits 00 0106h
D 8 bits 00 010Ah
E 24 bits 00 010Bh
00 0100h−00 0107h A(23−16) A(15−8) A(7−0) B(15−8) B(7−0) C(31−24) C(23−16)
00 0108h−00 010Fh C(15−8) C(7−0) D(7−0) E(23−16) E(15−8) E(7−0)

Program Space
3.2.3 Alignment of Fetch Packets in Program Space

You do not have to align instructions as you store them in program memory,
but the instruction fetches are grouped by 64-bit fetch packets, which are
aligned on multiples of 8-byte addresses. During an instruction fetch, the CPU
reads 64 bits from an address whose three least significant bits (LSBs) are 0s.
In other words, the least significant digit of a fetch address is always 0h or 8h.
When the CPU executes a discontinuity, the address written to the program
counter (PC) can be greater than or equal to the fetch address. The PC
address and the fetch address are the same only if the three LSBs of the PC
address are 0s. Consider the following assembly code segment, which calls
a subroutine:
call(#subroutineB)
Suppose the first instruction of the subroutine is instruction C at byte address

00 0106h, as shown below (no code is stored in the shaded bytes).
00 0100h−00 0107h A(23−16) A(15−8) A(7−0) B(15−8) B(7−0) C(31−24) C(23−16)
00 0108h−00 010Fh C(15−8) C(7−0) D(7−0) E(23−16) E(15−8) E(7−0)
At the functional call, the PC contains 00 0106h, but the program-read address
bus (PAB) carries the byte address at the immediate lower or equal 8-byte
aligned address: 00 0100h. The CPU reads 8-byte fetch packets of code
beginning at address 00 0100h. Instruction C is the first instruction executed.

Data Space
3.3 Data Space

When programs read from or write to memory or MMRs, the accesses are
made to data space.
In word-pointer mode, the CPU uses word addresses (see Section 3.3.1) to
read or write 8-bit, 16-bit, or 32-bit values (see Section 3.3.2). The address that
needs to be generated for a particular value depends on how it its stored within
the word boundaries in data space (see Section 3.3.3). The CPU supports data
read and write accesses to strongly ordered areas (see Section 4.3.4).
Refer to Chapter 7, Section 1.3 for more details on data space accesses in
byte-pointer mode.
3.3.1 Word Addresses (23-Bit Effective Word Addresses)

When the CPU accesses data space in word-pointer mode, it uses 23-bit effec-
tive word addresses to reference 16-bit words. The following figure shows a
row of 32-bit-wide memory. Each word is assigned an address. For example,
word 0 is at address 00 0100h and word 1 is at address 00 0101h.
Word addresses Word 0 Word 1
00 0100h−00 0101h
The address buses carry 24-bit byte addresses. In word-pointer mode, when
the CPU reads from or writes to data space, the 23-bit effective word address
is shifted to the MSBs by one bit to give the equivalent 24-bit byte address. For
example, suppose an instruction reads a word at the 23-bit word address
00 0102h. The appropriate data-read address bus carries the 24-bit value
00 0204h, which is the 23-bit word address shifted to the MSBs by one bit.
Effective word address: 000 0000 0000 0001 0000 0010
Data-read address bus value: 0000 0000 0000 0010 0000 0100
3.3.2 Data Types

The instruction set handles the following data types:
byte 8 bits
word 16 bits
long word 32 bits

Data Space
Dedicated instruction syntaxes (see Table 3−1) allow you to select high or low
bytes of particular words. The byte-load instructions read bytes and load them
into registers. The bytes that are read are zero extended (if the uns() operand
qualifier is used) or sign extended before being stored. The byte-store instruc-
tions store the 8 least significant bits of a register to a specified byte in memory.
Note:
In data space, when the CPU is in word-pointer mode, it uses 23-bit effective
addresses to access words. In that mode, to access a byte, the CPU must
manipulate the word that contains the byte.
Table 3−1. Byte Load and Byte Store Instructions

Instruction Syntax Byte Accessed Operation
Ra = uns(high_byte(Smem)) Smem(15–8) Byte load
Ra = uns(low_byte(Smem)) Smem(7–0) (Accumulator, auxiliary, or temporary register load

instructions)
ACa = high_byte(Smem) << S6 Smem(15–8)
ACa = low_byte(Smem) << S6 Smem(7–0)
high_byte(Smem) = Ra Smem(15–8) Byte store
low_byte(Smem) = Ra Smem(7–0) (Accumulator, auxiliary, or temporary register store

instructions)
When the CPU accesses long words, the address used for the access is the
address of the most significant word (MSW) of the 32-bit value. The address
of the least significant word (LSW) depends on the address of the MSW:
If the address of the MSW is even, then the LSW is accessed at the next
address. For example:
Word addresses
00 0100h−00 0101h MSW LSW
If the address of the MSW is odd, then the LSW is accessed at the previous
address. For example:
Word addresses
00 0100h−00 0101h LSW MSW

Data Space
Given the address of the MSW (LSW), complement its least significant bit to
find the address of the LSW (MSW).
3.3.3 Data Organization in Data Space

The following table and figure provide an example of how data are organized
in data space. Seven data values of varying sizes have been stored in 32-bit-
wide memory. No data value is stored in the shaded byte at address 00 0100h.
Important points about the example are:
To access a long word, you must reference its most significant word
(MSW). C is accessed at address 00 0102h. D is accessed at address
00 0105h.
Word addresses are also used to access bytes in data space. For
example, the address 00 0107h is used for both F (high byte) and G (low
byte). Specific byte instructions indicate whether the high byte or low byte
is accessed.
Data Value Data Type Address

A Byte 00 0100h (low byte)
B Word 00 0101h
C Long Word 00 0102h
D Long Word 00 0105h
E Word 00 0106h
F Byte 00 0107h (high byte)
G Byte 00 0107h (low byte)
Word addresses Word 0 Word 1

00 0100h−00 0101h A B
00 0102h−00 0103h MSW of C (bits 31−16) LSW of C (bits 15−0)
00 0104h−00 0105h LSW of D (bits 15−0) MSW of D (bits 31−16)
00 0106h−00 0107h E F G

Data Space
3.3.4 Strongly Ordered Data Memory Area (xI/O Space)

The C55x+ revision extends the concept of I/O space (see Section 3.4) by
introducing the extended I/O accesses (xI/O) inside the 16M-byte data space.
Depending on the memory configuration of your DSP subsystem, you can de-
fine some so-called strongly ordered memory areas inside the 16M-byte data
space. In this document these memory areas are called xI/O space. The xI/O
memory accesses made to xI/O space are fully ordered and pipeline protected
from any other memory accesses occurring in the pipeline.
Table 3−2 illustrates how a memory read instruction that follows a memory
write instruction is executed in C55x+ pipeline when all memory accesses are
performed in regular data memory space. (Refer to Section 1.7 for the pipeline
description.)
In this example, the actual memory read of instruction 2 is performed dur-

ing cycle 3, before the actual memory write of instruction 1 (performed dur-
ing cycle 8).
Table 3−3 illustrates how a memory read instruction that follows a memory
write instruction is executed in C55x+ pipeline when a memory read is per-
formed in xI/O space (xI/O read).
In this example, the CPU stalls the execution of instruction 2 during 6

cycles, so that the actual xI/O read of instruction 2 is performed after the
actual memory write of instruction 1.
Table 3−2. Memory Access in Regular Data Space

Cycle 1 2 3 4 5 6 7 8
Instruction 1 ... AC2 RD X1 X2 W1 W2 W3

Pipeline Phases
Memory Write Request Data Memory

Write Written Written
Instruction 2 ... AC1 AC2 RD X1 X2 W1 ...

Pipeline Phases
Memory Read Request Memory Data

Read Read Read

Data Space
Table 3−3. Memory Access in Strongly Ordered Area of Data Space

Cycle 4 5 6 7 8 9 10 11
Instruction 1 ... X2 W1 W2 W3
Pipeline Phases
Memory Write Request Data Memory

Write Written Written
Instruction 2 ... D AD1 AD2 AC1 AC2 RD ...

Pipeline Phases
xI/O Read Request Memory Data

Read Read Read

I/O Space
3.4 I/O Space

I/O space is separate from data/program space and is available only for ac-
cessing registers of the DSP peripherals. It accesses 64-Kword locations.
Addresses I/O space
0000h−FFFFh 64K words
For I/O space, the CPU uses the data-read bus DB for reads and data-write
bus EB for writes.
When the CPU is in word-pointer mode, the behavior is similar to the one ex-
plained in Section 3.1:
When the CPU reads from or writes to I/O space, the 16-bit word I/O ad-
dress is concatenated with leading 0s and shifted to the MSBs by 1 before
being posted on the address buses. For example, suppose an instruction
reads at the 16-bit word address 0102h. DAB carries the 24-bit value
00 0204h.
Because I/O space is limited to 64K words, an increment past FFFFh or

a decrement past 0000h causes the I/O address to wrap around, do not
make use of this behavior. It is not supported.
When the CPU is in byte-pointer mode, the behavior is similar to the one ex-
plained in Section 3.1:
When the CPU reads from or writes to I/O space, the 17-bit byte I/O ad-
dress is concatenated with leading 0s, and posted as it is on the address
buses. For example, suppose an instruction writes at the 17-bit byte ad-
dress 0102h. DAB carries the 24-bit value 00 0102h.
Because I/O space is limited to 64K words, an increment past 01 FFFFh

or a decrement past 0000h causes the I/O address to wrap around, do not
make use of this behavior. It is not supported.
Depending on the DSP subsystem memory configuration, the 64K-word I/O

space can be mapped to the regular data space in order to enable peripherals
to be accessible through both regular and extended I/O accesses.
Note that as compared to xI/O accesses, regular I/O space accesses do

not guarantee strongly ordered memory accesses.

Boot Loader
3.5 Boot Loader

An on-chip boot loader provides options for transferring code and data from
an external source to the RAM inside the C55x+ DSP at power up/reset. For
a list of boot options for a particular C55x+ DSP and for a description on how
to select the desired option, see the data manual for that DSP.

Chapter 4
Stack Operation
This chapter introduces the two stacks located on C55x+ DSP. It also explains
how they relate to each other and how they are used by the CPU during auto-
matic context switching (saving register values before executing an interrupt
or a subroutine and restoring those values when the return from interrupt or
subroutine is executed).
Topic Page
4.1 Data Stack and System Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

4.2 Stack Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.3 Fast Return Versus Slow Return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4.4 Automatic Context Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
4-1
Introduction to Data and System Stacks
4.1 Introduction to Data and System Stacks

The CPU supports two software stacks known as the data stack and the sys-
tem stack. Figure 4−1 and Table 4−1 describe the registers used for the stack
pointers.
For an access to the data stack, the XSP register contains the 24-bit ad-
dress of the value last pushed onto the data stack. The XSP register is
composed of the SPH part (8 higher bits of XSP) and the SP register
(16 lower bits of XSP). The CPU decrements the XSP register before
pushing a value onto the stack and increments the XSP register after pop-
ping a value off the stack.
Similarly, when accessing the system stack, XSSP contains the 24-bit ad-
dress of the value last pushed onto the system stack. The XSSP register
is composed of the SSPH part (8 higher bits of XSSP) and the SSP register
(16 lower bits of SSP). The CPU decrements XSSP before pushing a val-
ue onto the system stack and increments XSSP after popping a value off
the system stack.
C55x+ DSP features two main stack modes in order to:
Support full memory allocation flexibility for data and system stacks. This
is the 24-bit linear stack mode.
Support source code compatibility with C55x DSP generation. This is the
64-Kword paged-stack mode.
With the 24-bit linear stack mode:
You can allocate the data and system stacks independently from each oth-
er, and anywhere in the data space. As mentioned in Section 2.6.7, the
C55x+ DSP has a 24-bit flat data addressing mechanism. This allows
each stack to span over the 64-Kword data page boundaries, and to have
a size greater than 64 Kwords.
For best performance for subroutine call and return, the code operates in
dual 16-bit stack mode with fast return.
With the 64-Kword paged stack:
You must allocate the data and system stack in the same 64-Kword data
page. The stack size is limited to 64 Kwords.
C55x+ DSP supports the following three stack modes for source code
compatibility with C55x DSP generations:
Dual 16-bit stack with fast return
Dual 16-bit stack with slow return
32-bit stack with slow return
4-2 Stack Operation

Introduction to Data and System Stacks
The following sections describe the above four stack modes in detail.
Figure 4−1 illustrates the extended stack pointers XSP and XSSP.
Figure 4−1. Extended Stack Pointers
ÁÁÁÁÁÁÁÎÎÎÎÎÎÎÎÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 23−16 15−0
ÁÁÁÁÁÁÁÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
XSP
ÁÁ SPH SP
XSSP
SSPH SSP
Table 4−1. Extended Stack Pointer Registers
XSP Extended data stack pointer XSP is not memory mapped
SP Data stack pointer SP is memory mapped
SPH High part of XSP SPH is memory mapped
XSSP Extended system stack pointer XSSP is not memory mapped
SSP System stack pointer SSP is memory mapped
SSPH High part of XSSP SSPH is not memory mapped
Stack Operation 4-3

Stack Configurations
4.2 Stack Configurations

C55x+ DSP provides four possible stack configurations which are described
in Table 4−2. Notice that two configurations feature a fast return process and
the others use a slow return process. Section 4.3 explains the difference be-
tween the two processes. Notice that one configuration uses the 24-bit linear
stack addressing and the three others use the 64-Kword paged-stack ad-
dressing.
The stack configuration can only be changed during a hardware or software

reset at the same time as the CPU default pointer mode (see Section 2.10.4.1
for more details on the default pointer mode usage).
You can select a specific stack configuration and the default pointer mode by
placing the appropriate values in bits 24, 28, 29, and 30 of the 32-bit reset vec-
tor location. This can be accomplished in C55x+ DSP assembly code as part
of the .ivec assembler directive. This directive is described in the C55x+ As-
sembly Language User Guide (TI lit ###). The 24 LSBs of the reset vector loca-
tion must be the start address of the reset interrupt service routine (ISR).
Bit 24 selects the processor default pointer mode: 0 is for word-pointer

mode, and 1 is for byte-pointer mode.
Bit 28 selects fast or slow-return stack configuration: 0 is for fast-return

mode, and 1 is for slow return mode.
Bit 29 selects 16-bit or 32-bit stack configuration: 0 is for 32-bit stack

mode, and 1 is for 16-bit stack mode.
Bit 30 selects the linear or paged-stack configuration: 0 is for 64-Kword

paged-stack mode, and 1 is for 24-bit linear-stack mode.
4-4 Stack Operation

Table 4−2. Stack Configurations in Word-Pointer and Byte-Pointer Modes

Stack Description Reset Vector Value † Reset Vector Value †
Configurations (Binary) (Binary)
Word-Pointer Mode Byte-Pointer Mode
24-Bit Linear-Stack Mode
Dual 16-bit The data stack and the system stack can X110 XXX0: X110 XXX1:
stack with fast be allocated independently and anywhere (24-bit ISR address) (24-bit ISR address)
return in memory.
The data stack and the system stack are
independent: When you access the data
stack, XSP register is modified, but XSSP
register is not.
The registers RETA and CFCT implement
a fast return (see Figure 4−3).
64-Kword Paged-Stack Mode
Dual 16-bit The data stack and the system stack X010 XXX0: N/A
stack with fast must be allocated in the same 64-Kword (24-bit ISR address)
return data page.
accessed independently: when you ac-
cess the data stack, XSP register is modi-
fied, but XSSP register is not is not.
The registers RETA and CFCT implement
a fast return (see Figure 4−3).
Dual 16-bit The data stack and the system stack X011 XXX0: N/A
stack with slow must be allocated in the same 64-Kword (24-bit ISR address)
return data page.
accessed independently: when you ac-
cess the data stack, XSP register is modi-
fied, but XSSP register is not.
RETA and CFCT are not used (see
Figure 4−2).
32-bit stack with The data stack and the system stack X001 XXX0: N/A
slow return must be allocated in the same 64-Word (24-bit ISR address)
data page.
The data stack and the system stack act
as a single 32-bit stack: When you access
the data stack, XSP and XSSP registers
are modified by the same increment.
RETA and CFCT are not used (see
Figure 4−2).
† A bit shown as an X is reserved and may be 0 or 1.
Stack Operation 4-5

4.2.1 24-Bit Linear-Stack Addressing versus 64-KWord Paged-Stack Addressing
The following sections introduce the main difference between the two stack
addressing modes: the 24-bit linear-stack mode and the 64-Kword paged-
stack mode. (Refer to Section 7.2 for the differences occurring in byte-pointer
mode.)
4.2.1.1 24-Bit Linear-Stack Mode
When the 24-bit linear-stack mode is selected, the XSP and XSSP registers
are completely independent, meaning that SPH and SSPH can have different
values.
You can allocate the data and system stacks independently from each other
and anywhere in the data space. As mentioned in Section 2.6.7, the C55x+
DSP has a 24-bit flat data addressing mechanism. This allows each stack to
span over the 64-Kword data page boundaries, and to have a size greater than
64 Kwords.
Note:
When the CPU is in word-pointer mode, an increment past 7F FFFFh or a
decrement past 00 0060h causes the stack pointer to overflow out of legal
data memory locations; do not make use of this behavior, it is not supported.
4.2.1.2 64-KWord Paged-Stack Mode
The C55x+ features the 64-Kword paged-stack mode in order to emulate the
C55x DSP generations stack behavior.
When the 64-Kword paged-stack mode is selected, SPH and SSPH must have
the same values, meaning that XSP and XSSP registers are not independent.
You must allocate the data and system stack in the same 64-Kword data page.
The stack size is limited to 64 Kwords.
In the 64-Kword paged-stack mode, any initializations of SPH update SSPH,

and any initializations of SSPH update SPH. In other words, SPH content is
reflected on SSPH and vice versa. Follows some examples of such initializa-
tions:
A stack register load: mar(XSP = #01 0003h)

A register move to XSP: mar(XSP = XAR1)
A store to MMR address of SPH: @SP_H = AR1 || mmap()
4-6 Stack Operation

Note:
On C55x DSP generation, (conditional) call, intr(), trap(), (conditional) return,
push(), and pop() instructions are not expected to change the value of SPH.
If not, a stack overflow beyond a 64-Kword page boundary occurs; do not
make use of this behavior, it is not supported.
Stack Operation 4-7

Fast Return Versus Slow Return
4.3 Fast Return Versus Slow Return

The difference between the fast-return process and the slow-return process
is how the CPU saves and restores the value of two internal registers: the
program counter (PC) and the loop context register.
PC holds the 24-bit address of the 1 to 16 bytes of code being decoded in the
I unit. When the CPU performs an interrupt or call, the current PC value (the
return address) is stored and the PC is loaded with the start address of the in-
terrupt service routine or called routine. When the CPU returns from the rou-
tine, the return address is transferred back to PC so that the interrupted pro-
gram sequence can continue as before.
An 8-bit loop context register keeps a record of active repeat loops (the loop
context). When the CPU performs an interrupt or call, the current loop context
is stored and the 8-bit register is cleared to create a new context for the subrou-
tine. When the CPU returns from the subroutine, the loop context is transferred
back to the 8-bit register.
In the slow-return process, the return address and the loop context are stored
to the stacks (in memory). When the CPU returns from a subroutine, the speed
at which these values are restored is dependent on the speed of the memory
accesses.
In the fast-return process, the return address and the loop context are saved
to registers, so that these values can always be restored quickly. These special
registers are the return address register (RETA) and the control-flow context
register (CFCT). You can read from or write to RETA and CFCT as a pair with
dedicated, 32-bit, load and store instructions.
Figure 4−2 (slow return) and Figure 4−3 (fast return) show examples of how
the return address and the loop context are handled within several layers of
routines. In these figures, Routine 0 is the highest level routine, Routine 1 is
nested inside Routine 0, and Routine 2 is nested inside Routine 1.
4-8 Stack Operation

Figure 4−2. Return Address and Loop Context Passing During Slow-Return Process
Execute Routine 0
Call Routine 1 Return to Routine 1

Save Routine 0 return address Load PC and loop context bits from
and loop context on stacks. top of stack.
Execute Routine 1 Continue Routine 1

On top of stacks: On top of stacks:
Return address of Routine 0 Return address of Routine 0
Loop context of Routine 0 Loop context of Routine 0

Save Routine 1 return address Load PC and loop context bits from
and loop context on stacks. top of stack.
On top of stacks:
Return address of Routine 1
Loop context of Routine 1
Stack Operation 4-9

Figure 4−3. Use of RETA and CFCT in Fast-Return Process
Execute Routine 0
RETA: X
CFCT: Y

1 Save RETA to stacks. Save CFCT 1 Load PC from RETA. Load loop
to system stack. context bits from CFCT.
2 Save Routine 0 return address in 2 Restore RETA from stacks. Re-
RETA. Save Routine 0 loop con- store CFCT from system stack.
text to CFCT.

RETA: Return address of Routine 0 RETA: Return address of Routine 0
CFCT: Loop context of Routine 0 CFCT: Loop context of Routine 0

1 Save RETA to stacks. Save CFCT 1 Load PC from RETA. Load loop
to system stack. context bits from CFCT.
2 Save Routine 1 return address in 2 Restore RETA from stacks. Re-
RETA. Save Routine 1 loop con- store CFCT from stacks.
text to CFCT.

RETA: Return address of Routine 1 RETA: X
CFCT: Loop context of Routine 1 CFCT: Y
4-10 Stack Operation

Automatic Context Switching
4.4 Automatic Context Switching
Before beginning an interrupt service routine (ISR) or a called routine, the CPU
automatically saves certain values. The CPU can use these values to reestab-
lish the context of the interrupted program sequence when the subroutine is
finished.
Whether responding to an interrupt or a call, the CPU saves the return ad-
dress, the loop context bits, the pointer mode bit (BPTR). The return address,
taken from the program counter (PC), is the address of the instruction to be
executed when the CPU returns from the subroutine. The loop context bits are
a record of the type and status of repeat loops that were active when the inter-
rupt or call occurred. The pointer mode bit is record indicating whether the CPU
was executing in byte- or word-pointer mode when the interrupt or call oc-
curred. When responding to an interrupt, the CPU additionally saves status
registers 0, 1, and 2 and the debug status register (DBSTAT). DBSTAT is a
DSP register that holds debug context information used during emulation.
If the selected stack configuration (see Section 4.2) uses the fast-return pro-
cess, then RETA is used as a temporary storage place for the return address,
and CFCT is used as a temporary storage place for the loop context bits and
the pointer-mode bit. If the selected stack configuration uses the slow-return
process, then the return address, the loop context bits, and the pointer-mode
bit are saved to and restored from the stack.
4.4.1 Fast-Return Context Switching for Calls
Before beginning a called routine, the CPU automatically:
1) Saves CFCT and RETA to the system stack and the data stack in parallel,
as shown below. For each stack, the CPU decrements the stack pointer
(XSSP or XSP) by 1 before the write to the stack.
System Stack Data Stack
After After
→ XSSP = x − 1 CFCT:RETA(23−16) → XSP = y − 1 RETA(15−0)
Save Save
Before Before
→ XSSP = x Previously saved data → XSP = y Previously saved data
Save Save
Stack Operation 4-11

2) Saves the return address to RETA and saves loop context flags, as well
as the pointer mode bit in CFCT (see below).
RETA PC (return address) CFCT Ctrl. bits
A return instruction at the end of a subroutine forces the CPU to restore values
in the opposite order. First, the CPU transfers the return address from RETA
to PC and restores its loop context flags as well as its pointer mode bit from
CFCT. Second, the CPU reads the CFCT and RETA values from the stacks
in parallel. For each stack, the CPU increments the stack pointer (XSSP or
XSP) by 1 after the read from the stack.
4.4.2 Fast-Return Context Switching for Interrupts

Before beginning an interrupt service routine (ISR), the CPU automatically:
1) Saves ST2, ST0, ST1, DBSTAT, and CFCT registers to the data and sys-
tem stacks in parallel, as shown below. For each stack, the CPU decre-
ments the stack pointer (XSSP or XSP) by 1 before each write to the stack.

After → XSSP = x − 3 CFCT:RETA(23−16) After → XSP = y − 3 RETA(15−0)
Save XSSP = x − 2 DBSTAT Save XSP = y − 2 ST1_55
XSSP = x − 1 ST0_55 XSP = y − 1 ST2_55
Before → XSSP = x Previously saved data Before → XSP = y Previously saved data
Save Save
Note:
DBSTAT (the debug status register) holds debug context information used
during emulation. Make sure the ISR does not modify the value that will be
returned to DBSTAT.
2) Saves the return address (from PC) to RETA, and saves loop context flags
as well as the pointer mode bit in CFCT (see below).
RETA PC (return address) CFCT Ctrl. bits

A return-from-interrupt instruction at the end of an ISR forces the CPU to re-

store values in the opposite order. First, the CPU transfers the return address
from RETA to PC and restores its loop context flags as well as its pointer mode
bit from CFCT. Second, the CPU reads the CFCT, RETA, DBSTAT, ST1, ST0,
and ST2 values from the stacks in parallel. For each stack, the CPU incre-
ments the stack pointer (XSSP or XSP) by 1 after each read from the stack.
4.4.3 Slow-Return Context Switching for Calls

Before beginning a called routine, the CPU automatically saves the return ad-
dress (from PC) and the loop context bits, as well as the pointer mode bit to
the system stack and the data stack in parallel, as shown below. For each
stack, the CPU decrements the stack pointer (XSSP or XSP) by 1 before the
write to the stack.
After After
→ XSSP = x − 1 (Ctrl. bits):PC(23−16) → XSP = y − 1 PC(15−0)
Save Save
Before Before
→ XSSP = x Previously saved data → XSP = y Previously saved data
Save Save
A return instruction at the end of a subroutine forces the CPU to restore the
return address, the loop context, as well as the pointer mode from the stack.
For each stack, the CPU increments the stack pointer (XSSP or XSP) by 1 after
the read from the stack.
4.4.4 Slow-Return Context Switching for Interrupts

Before beginning executing an interrupt service routine (ISR), the CPU auto-
matically saves ST2, ST0, ST1, DBSTAT, CFCT, and RETA registers to the
system stack and the data stack in parallel, as shown below. For each stack,
the CPU decrements the stack pointer (XSSP or XSP) by 1 before each write
to the stack.

After → XSSP = x − 3 (Ctrl. bits):PC(23−16) After → XSP = y − 3 PC(15−0)
Save XSSP = x − 2 DBSTAT Save XSP = y − 2 ST1_55
XSSP = x − 1 ST0_55 XSP = y − 1 ST2_55
Before → XSSP = x Previously saved data Before → XSP = y Previously saved data
Save Save
Stack Operation 4-13

Note:
DBSTAT (the debug status register) holds debug context information used
during emulation. Ensure the ISR does not modify the value that will be re-
turned to DBSTAT.
A return-from-interrupt instruction at the end of an ISR forces the CPU to re-

store values in the opposite order. First, the CPU restores the return address,
the loop context bits, and the pointer mode bit from the stack. Second, the CPU
reads the CFCT, RETA, DBSTAT, ST1, ST0, and ST2 values from the stacks
in parallel. For each stack, the CPU increments the stack pointer (XSSP or
XSP) by 1 after each read from the stack.

Chapter 5
Interrupt and Reset Operations
This chapter describes the available interrupts of the C55x+ DSP, how some
of them can be blocked through software, and how all of them are handled by
the CPU. This chapter also explains the automatic effects of two types of reset
operations, one initiated by hardware and one initiated by software.
Topic Page
5.1 Introduction to the Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

5.2 Interrupt Vectors and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.3 Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.4 Nonmaskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
5.5 DSP Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
5-1
Introduction to the Interrupts
5.1 Introduction to the Interrupts
Interrupts are hardware- or software-driven signals that cause the DSP to sus-
pend its current program sequence and execute another task called an inter-
rupt service routine (ISR). The C55x+ DSP supports 32 ISRs. Some of the
ISRs can be triggered by software or hardware; others can be triggered only
by software. When the CPU receives multiple hardware interrupt requests at
the same time, the CPU services them according to a predefined priority rank-
ing (see Section 5.2).
All C55x+ DSP interrupts, whether hardware or software, can be placed in one
of two categories. Maskable interrupts can be blocked (masked) through soft-
ware. Nonmaskable interrupts cannot be blocked. All software interrupts are
nonmaskable.
The DSP handles interrupts in four main phases:
1) Receive the interrupt request. Software or hardware requests a suspen-

sion of the current program sequence.
2) Acknowledge the interrupt request. The CPU must acknowledge the

request. If the interrupt is maskable, then certain conditions must be met
for acknowledgment. For nonmaskable interrupts, acknowledgment is
immediate.
3) Prepare for the interrupt service routine. The main tasks performed by the
CPU are:
Complete execution of the current instruction and flush from the pipe-
line any instructions that have not reached the decode phase.
Automatically store certain register values to the data stack and the
system stack (see Section 4.4).
Automatically set the pointer mode (BPTR bit of ST3 register) to the
CPU default pointer mode in bit 24 of the 32-bit reset vector location
(see Section 5.2).
Fetch the interrupt vector that you store at a preset vector address.
The interrupt vector points to the interrupt service routine.
1) Execute the interrupt service routine. The CPU executes the ISR that you
have written. The ISR is concluded with a return-from-interrupt instruction,
which automatically restores the register values that were automatically
saved (see Section 4.4).
5-2 Interrupt and Reset Operations

Introduction to the Interrupts
Notes:
1) External interrupts must occur at least 3 cycles after the CPU exits reset
or they will not be recognized.
2) All interrupts (maskable and nonmaskable) are disabled following a
hardware reset, regardless of the setting of the INTM bit and the IER0
and IER1 registers. Interrupts will remain disabled until the stack point-
ers are initialized by a software write to each pointer (the XSP and XSSP
registers). After stack initialization, the INTM bit and the IER0 and IER1
registers determine interrupt enabling.
3) The interrupt service routine pointer mode (word- or byte-pointer mode)
is the pointer mode defined at hardware or software reset time.
Interrupt and Reset Operations 5-3

Interrupt Vectors and Priorities
5.2 Interrupt Vectors and Priorities

The C55x+ DSP supports 32 interrupt service routines (ISRs). After receiving
and acknowledging an interrupt request, the CPU generates an interrupt
vector address. At the vector address, the CPU fetches the vector that points
to the corresponding ISR. When multiple hardware interrupts occur
simultaneously, the CPU services them one at a time, according to their
predefined hardware interrupt priorities. Table 5−1 shows the vectors sorted
by ISR number. Table 5−2 shows the vectors sorted by priority. Both tables
show only a general representation of the C55x+ DSP vectors. To see which
interrupt corresponds to each of the vectors, see the data manual for your
C55x+ DSP.
You must write the desired interrupt vectors (ISR start address) at the vector
addresses. Each interrupt vector must contain 8 bytes. Byte 0 of the reset vec-
tor contains the setting for the stack mode, and the default pointer mode. Byte
0 of the remaining vectors is ignored. Bytes 1−3 encode the 24-bit byte ad-
dress of the interrupt service routine (ISR).
IVPD points to the 256-byte program page for interrupt vectors 0–31. See Sec-
tion 2.8.1 for a detailed description of this register.
Table 5−1. Interrupt Vectors Sorted By ISR Number

Hardware
Interrupt Vector Address
ISR Number Priority Vector Name (Byte Address) This ISR Is For ...
0 1 RESETIV(IV0) IVPD:0h Reset (hardware and software)

(highest)
1 3 NMIV (IV1) IVPD:8h Hardware nonmaskable interrupt

(NMI) or software interrupt 1
2 5 IV2 IVPD:10h Hardware or software interrupt

Table 5−1. Interrupt Vectors Sorted By ISR Number (Continued)

Hardware
20 21 IV20 IVPD:A0h Hardware or software interrupt
22 25 IV22 IVPD:B0h Hardware or software interrupt
24 4 BERRIV (IV24) IVPD:C0h Bus error interrupt or software

interrupt
25 27 DLOGIV (IV25) IVPD:C8h Data log interrupt or software

interrupt
26 28 RTOSIV (IV26) IVPD:D0h Real-time operating system

(lowest) interrupt or software interrupt
27 – IV27 IVPD:D8h Reserved
28 – IV28 IVPD:E0h Reserved
29 2 EMUINT2 (IV29) IVPD:E8h Hardware nonmaskable interrupt
30 – SIV3 0 IVPD:F0h Software (only) interrupt
31 – SIV31 IVPD:F8h Software (only) interrupt 31

Table 5−2. Interrupt Vectors Sorted By Priority

Hardware
0 1 RESETIV(IV0) IVPD:0h Reset (hardware and software)

(highest)
29 2 EMUINT2 (IV29) IVPD:E8h Hardware nonmaskable interrupt
1 3 NMIV (IV1) IVPD:8h Hardware nonmaskable interrupt

(NMI) or software interrupt 1
24 4 BERRIV (IV24) IVPD:C0h Bus error interrupt or software

interrupt

Table 5−2. Interrupt Vectors Sorted By Priority (Continued)

Hardware
25 27 DLOGIV (IV25) IVPD:C8h Data log interrupt or software

interrupt
26 28 RTOSIV (IV26) IVPD:D0h Real-time operating system

(lowest) interrupt or software interrupt
27 – IV27 IVPD:D8h Reserved
28 – IV28 IVPD:E0h Reserved
30 – SIV30 IVPD:F0h Software (only) interrupt
31 – SIV31 IVPD:F8h Software (only) interrupt 31

Maskable Interrupts
5.3 Maskable Interrupts

Maskable interrupts can be blocked (masked) or enabled (unmasked) through
software. All of the C55x+ DSP maskable interrupts are hardware interrupts:
Interrupt Description
Interrupts associated Each of these 22 interrupts is triggered at a pin or by a

with interrupt vectors 2 peripheral of the DSP.
through 23
BERRINT Bus error interrupt. This interrupt is triggered when a sys-

tem bus error is transmitted to the CPU or when a bus
error occurs in the CPU. The BER register bits are set
according to the bus error interrupt source (see Section
2.8.6).
DLOGINT Data log interrupt. DLOGINT is triggered by the DSP at

the end of a data log transfer. You can use the DLOGINT
interrupt service routine (ISR) to start the next data log
transfer.
RTOSINT Real-time operating system interrupt. RTOSINT can be

triggered by a hardware breakpoint or watchpoint. You
can use the RTOSINT ISR to begin a data log transfer in
response to an emulation condition.
When a maskable interrupt is requested by hardware, the corresponding inter-

rupt flag is set in one of the interrupt flag registers (see Section 2.8.2). Once
the flag is set, the interrupt is not serviced unless it is properly enabled (see
Section 5.3.1).
The ISRs for the maskable interrupts can also be executed by software (see
Section 5.4).
Note:
error, and of any instruction executed in parallel, cannot be assured.

Maskable Interrupts
5.3.1 Bit and Registers Used To Enable Maskable Interrupts

The following bit and registers are used to enable the maskable interrupts:
Bit/Registers Description
INTM Interrupt mode bit. This bit globally enables/disables the

maskable interrupts (see Section 2.10.2.8).
IER0 and IER1 Interrupt enable registers. Each maskable interrupt has an
enable bit in one of these two registers (see Section 2.8.3).
DBIER0 and DBIER1 Debug interrupt enable registers. Each maskable interrupt
can be defined as time-critical by a bit in one of these two
registers (see Section 2.8.4).
As shown in the next two sections, the roles of INTM, the IER bit, and the
DBIER bit depend on the operating condition of the DSP.
5.3.2 Standard Process Flow for Maskable Interrupts

The flow chart in Figure 5−1 provides a conceptual model of the standard pro-
cess for handling maskable interrupts. Table 5−3 describes each of the steps
in the flow chart. When the CPU is halted in the real-time emulation mode, only
time-critical interrupts can be serviced, and the process is different (see
Section 5.3.3).

Maskable Interrupts
Figure 5−1. Standard Process Flow for Maskable Interrupts
Interrupt request sent to CPU
Set corresponding IFR flag
No
Interrupt enabled in
IER?
Yes
No
INTM = 0?
Yes
Branch to interrupt service routine

(ISR). While branching:
Clear corresponding IFR flag.
Save the ISR number into IIR register.
Perform automatic context save.
Globally disable maskable
interrupts (INTM = 1).
Disable debug events
(DBGM = 1).
Disable access to non-CPU
emulation registers (EALLOW = 0).
Set the pointer mode (BPTR) to the
CPU default pointer mode.
Execute interrupt service routine
Restore context
Program continues

Maskable Interrupts
Table 5−3. Steps in the Standard Process Flow for Maskable Interrupts
Step Description
Interrupt request The CPU receives a maskable interrupt request.

sent to CPU
Set corresponding When the CPU detects a valid maskable interrupt request, it sets and latches the corre-
IFR flag sponding flag in one of the interrupt flag registers (IFR0 or IFR1). This flag stays latched
until the interrupt is acknowledged or until the flag is cleared by software or by a DSP hard-
ware reset (see Section 2.8.2).
Interrupt enabled in The CPU cannot acknowledge the interrupt unless the corresponding enable bit is 1 in
IER? one of the interrupt enable registers (IER0 or IER1) (see Section 2.8.3).
INTM = 0? The CPU cannot acknowledge the interrupt unless the interrupt mode bit (INTM) is 0. That
is, interrupts must be globally enabled (see Section 2.10.2.8).
Branch to interrupt The CPU follows the interrupt vector to the interrupt service routine. While branching, the
service routine CPU performs the following actions:
It completes instructions that have already made it to the decode phase of the pipe-
line. Other instructions are flushed from the pipeline.
It clears the corresponding flag in IFR0 or IFR1 to indicate that the interrupt has been
acknowledged.
It saves the interrupt service routine (ISR) number into the IIR register (see Section
2.8.5).
It saves certain registers values automatically, to record important mode and status
information about the interrupted program sequence (see Section 4.4).
It creates a fresh context for the ISR by forcing INTM = 1 (globally disables inter-
rupts), DBGM = 1 (disables debug events), and EALLOW = 0 (disables access to
non-CPU emulation registers).
Set the pointer mode (BPTR) to the CPU default pointer mode.
Execute interrupt The CPU executes the interrupt service routine (ISR) that you have written for the ac-
service routine knowledged interrupt. Some registers values were saved automatically during the branch
to the ISR. A return-from-interrupt instruction at the end of your ISR will force an automatic
context restore operation (see Section 4.4) to restore these register values. If the ISR
shares other registers with the interrupted program sequence, then the ISR must save
other register values at the beginning of the ISR and restores these values before return-
ing to the interrupted program sequence.
Program continues If the interrupt request is not properly enabled, then the CPU ignores the request and the
program continues uninterrupted. If the interrupt is properly enabled, then its interrupt ser-
vice routine is executed and the program continues from the point where it was inter-
rupted.

Maskable Interrupts
5.3.3 Process Flow for Time-Critical Interrupts

The flow chart in Figure 5−2 and the descriptions in Table 5−4 provide a con-
ceptual model of how time-critical interrupts are handled. When the CPU is
halted in the real-time emulation mode, the only maskable interrupts that can
be serviced are the time-critical interrupts. In all other cases, the CPU uses the
standard process flow that is described in Section 5.3.2.

Maskable Interrupts
Figure 5−2. Process Flow for Time-Critical Interrupts
Set corresponding IFR flag.
No
IER?
Yes
No
DBIER?
Yes

Clear corresponding IFR flag.
(DBGM = 1).
Execute interrupt service routine.
Restore context.
Program continues

Maskable Interrupts
Table 5−4. Steps in the Process Flow for Time-Critical Interrupts

Step Description
Interrupt request The CPU receives a maskable interrupt request.

sent to CPU
Set correspond- When the CPU detects a valid maskable interrupt request, it sets and latches the corre-
ing IFR flag sponding flag in one of the interrupt flag registers (IFR0 or IFR1). This flag stays latched
until the interrupt is acknowledged, or until the flag is cleared by software or by a DSP
hardware reset (see Section 2.8.2).
Interrupt enabled The CPU cannot acknowledge the interrupt unless the corresponding enable bit is 1 in
in IER? one of the interrupt enable registers (IER0 or IER1) (see Section 2.8.3).
Interrupt enabled The CPU cannot acknowledge the interrupt unless the corresponding enable bit is 1 in
in DBIER? one of the debug interrupt enable registers (DBIER0 or DBIER1) (see Section 2.8.4).
Branch to The CPU follows the interrupt vector to the interrupt service routine. While branching, the
interrupt service CPU performs the following actions:
routine
It completes instructions that have already made it to the decode phase of the pipeline.
Other instructions are flushed from the pipeline.
It clears the corresponding flag in IFR0 or IFR1 to indicate that the interrupt has been
acknowledged.
It saves the interrupt service routine (ISR) number into IIR register (see Section 2.8.5).
It saves certain registers values automatically to record important mode and status infor-
mation about the interrupted program sequence (see Section 4.4).
It creates a fresh context for the ISR by forcing INTM = 1 (globally disables interrupts),
DBGM = 1 (disables debug events), and EALLOW = 0 (disables access to non-CPU
emulation registers).
Set the pointer mode (BPTR) to the CPU default pointer mode.
Execute interrupt The CPU executes the interrupt service routine (ISR) that you have written for the ac-
service routine knowledged interrupt. Some registers values were saved automatically during the branch
to the ISR. A return-from-interrupt instruction at the end of your ISR will force an automat-
ic context restore operation (see Section 4.4) to restore these register values. If the ISR
shares other registers with the interrupted program sequence, then the ISR must save
other register values at the beginning of the ISR and restore these values before return-
ing to the interrupted program sequence.
Program If the interrupt request is not properly enabled, then the CPU ignores the request, and the
continues program continues uninterrupted. If the interrupt is properly enabled, then its interrupt
service routine is executed, and the program continues from the point where it was inter-
rupted.

Nonmaskable Interrupts
5.4 Nonmaskable Interrupts

When the CPU receives a nonmaskable interrupt request, the CPU acknowl-
edges it unconditionally and immediately branches to the corresponding inter-
rupt service routine (ISR). The nonmaskable interrupts are:
The hardware interrupt RESET. If you drive the RESET pin low, then you
initiate a DSP hardware reset plus an interrupt that forces execution of the
reset ISR. (Specific effects of a DSP hardware reset are described in
Section 5.5.)
The hardware interrupt NMI. If you drive the NMI pin low, then you force
the CPU to execute the corresponding ISR. NMI provides a general-pur-
pose, hardware method to interrupt the DSP unconditionally.
All software interrupts which are initiated by one of the following instruc-
tions.
Instruction Description
intr(#k5) You can initiate any of the 32 ISRs with this instruction. The
variable k5 is a 5-bit number from 0 to 31. Before executing
the ISR, the CPU performs an automatic context save (to save
important register values) and sets the INTM bit (to globally
disable maskable interrupts).
trap( #k5) This instruction performs the same function as intr(#k5), ex-
cept that it does not affect the INTM and DBGM bits.
reset This instruction performs a software reset operation, which is

a subset of the hardware reset operation, and then forces the
CPU to execute the reset ISR (specific effects of a software
reset are described in Section 5.5.2).
5.4.1 Standard Process Flow for Nonmaskable Interrupts

The following flow chart provides a conceptual model of the standard process
for handling nonmaskable interrupts.
Note:
If the interrupt was initiated by a trap instruction, then the INTM and DBGM
bits are not affected during the branch to the interrupt service routine.

Figure 5−3. Standard Process Flow for Nonmaskable Interrupts

(DBGM = 1).
Execute interrupt service routine.
Program continues

Table 5−5. Steps in the Standard Process Flow for Nonmaskable Interrupts
Step Description
Interrupt request sent to CPU The CPU receives a nonmaskable interrupt request.
Branch to interrupt service routine The CPU follows the interrupt vector to the interrupt service routine. While
branching, the CPU performs the following actions:
It completes instructions that have already made it to the decode
phase of the pipeline. Other instructions are flushed from the pipeline.
It saves certain registers values automatically, to record important
mode and status information about the interrupted program sequence
(see Section 4.4).
It creates a fresh context for the ISR by forcing INTM = 1 (globally dis-
ables interrupts), DBGM = 1 (disables debug events), and
EALLOW = 0 (disables access to non-CPU emulation registers).
Sets the pointer mode (BPTR) to the CPU default pointer mode.
Execute interrupt service routine The CPU executes the interrupt service routine (ISR) that you have writ-
ten for the acknowledged interrupt. Some registers values were saved
automatically during the branch to the ISR. A return-from-interrupt in-
struction at the end of your ISR will force an automatic context restore
operation (see Section 4.4) to restore these register values. If the ISR
shares other registers with the interrupted program sequence, then the
ISR must save other register values at the beginning of the ISR and
restore these values before returning to the interrupted program se-
quence.
Program continues After the interrupt service routine is executed, the program continues
from the point where it was interrupted.

DSP Reset
5.5 DSP Reset

This section covers DSP hardware and software reset. Table 5−6 summarizes
the effects of the hardware and software resets on the DSP registers.
Section 5.5.1 describes the DSP hardware reset, and Section 5.5.2 describes
the DSP software reset. Table 5−6 summarizes the effects of both types of
reset on the CPU registers.
Note:
A hardware reset loads the interrupt vector pointer called IVPD with FFFFh
and, thus, forces the CPU to fetch the reset vector from program address
FF FF00h. During a software reset, IVPD remains unchanged; the CPU
fetches the reset vector using the current IVPD value.
Table 5−6. Effects of a Reset on CPU Registers

Reset Value
Register Bit(s) Comments
H/W S/W
BER All 0 0
BSA01 all 0 †
BSA23 all 0 †
BSA45 all 0 †
BSA67 all 0 †
DBIER0, all 0 † All time-critical interrupts are disabled.
DBIER1
IER0 all 0 † All maskable interrupts are disabled.
IER1 all 0 †
IFR0 all 0 0 All pending interrupts are cleared.
IFR1 all 0 0
IIR all 0 0
IVPD all FFFFh † The vectors reference by IVPD are in the 256-byte
program page that begins with address FFFF00h.
RPTC all 0 †
† Not affected by a software reset

DSP Reset
Table 5−6. Effects of a Reset on CPU Registers (Continued)

Reset Value
H/W S/W
ST0_55 0–8: DP 0 0 Data page 0 is selected. Flags are cleared.
9: ACOV1 0 0
10: ACOV0 0 0
11: C 1 1
12: TC2 1 1
13: TC1 1 1
14: ACOV3 0 0
15: ACOV2 0 0
ST1_55 0–4: ASM 0 0 Instructions affected by ASM will use a shift count of 0
(no shift). When ASM is cleared, register T2 is also
cleared. This is due to the relationship between ASM
and T2 when C54CM = 1 (see Section 2.10.2.1).
5: C54CM 1 1 The TMS320C54x DSP-compatible mode is on.
6: FRCT 0 0 Results of multiply operations are not shifted.
7: C16 0 0 The dual 16-bit mode is off. For an instruction that is
affected by C16, the D-unit ALU performs one 32-bit
operation rather than two parallel 16-bit operations.
8: SXMD 1 1 The sign-extension mode is on.
9: SATD 0 0 The CPU will not saturate overflow results in the D
unit.
10: M40 0 0 The 32-bit (rather than 40-bit) computation mode is
selected for the D unit.
11: INTM 1 1 Maskable interrupts are globally disabled.
12: HM 0 0 When an active HOLD signal forces the DSP to place
its external interface in the high-impedance state, the
DSP continues executing code from internal memory.
13: XF 1 1 Pin XF is driven high.
14: CPL 0 0 This bit has no effect in C55x+ revision
15: BRAF 0 0 This flag is cleared. (BRAF indicates/controls the sta-
tus of a block-repeat operation.)

DSP Reset

Reset Value
Register Bit(s) H/W S/W Comments
ST2_55 0: AR0LC 0 0 AR0 is used for linear addressing (rather than circular ad-
dressing).
1: AR1LC 0 0 AR1 is used for linear addressing.
8: CDPLC 0 0 AR15 is used for linear addressing.
9: GOVF 0 0 GOVF is used for global overflow detected in any destina-
tion accumulator (AC0−AC15)
10: RDM 0 0 When an instruction specifies that an operand must be
rounded, the CPU uses rounding to the infinite (rather than
rounding to the nearest).
11: EALLOW 0 0 A program cannot write to the non-CPU emulation registers.
12: DBGM 1 1 Debug events are disabled.
13–14: Reserved NA NA
15: ARMS This bit has no effect in C55x+ revision
ST3_55 0: SST 0 † In the TMS320C54x DSP-compatible mode (C54CM = 1),
the execution of some accumulator-store instructions is af-
fected by SST. When SST is 0, the 40-bit accumulator value
is not saturated to a 32-bit value before the store operation.
1: SMUL 0 † The results of multiplications will not be saturated.
2: CLKOFF 0 † The output of the CLKOUT pin is enabled; it reflects the
CLKOUT clock signal.
3: BPTR config- config- When this flag is cleared, the CPU is in word-pointer mode
uration uration (rather than byte-pointer mode).
regis- regis-
ter val- ter val-
ue ue
4: Reserved NA NA
5: SATA 0 0 The CPU will not saturate overflow results in the A unit.
6: MPNMC pins † The reset value of MPNMC may be dependent on the state
of predefined pins at reset. To check this for a particular
C55x+ DSP, see its data manual.

DSP Reset

Reset Value
H/W S/W
ST3_55 7: CBERR 0 † This flag is cleared (CBERR indicates when an
(Continued) internal bus error is detected).
11−8: Reserved NA NA
12: HINT 1 † The signal used to interrupt the host processor at
the high level.
13: CACLR 0 † This bit is cleared. (CACLR is used to start and
then check the status of an instruction cache
flush.)
14: CAEN 0 † The program cache is disabled.
15: CAFRZ 0 † The cache is not frozen.
T2 all 0 0 T2 is cleared because the ASM field of ST1_55 is
cleared. This is due to the relationship between
ASM and T2 when C54CM = 1 (see Section
2.10.2.1).
XAR0 [23:16] 0 †
XAR1 [23:16] 0 †
XAR2 [23:16] 0 †
XAR3 [23:16] 0 †
XAR4 [23:16] 0 †
XAR5 [23:16] 0 †
XAR6 [23:16] 0 †
XAR7 [23:16] 0 †
XAR8 [23:16] 0 †
XAR9 [23:16] 0 †
XAR10 [23:16] 0 †
XAR11 [23:16] 0 †
XAR12 [23:16] 0 †
XAR13 [23:16] 0 †
XAR14 [23:16] 0 †
XAR15 [23:16] 0 †
XDP [23:16] 0 0t XDP[15:7] are cleared. Data page 0 is not se-
lected
XSP [23:16] 0 †
XSSP [23:16] 0 †

DSP Reset
5.5.1 DSP Hardware Reset

When asserted, the DSP reset signal places the DSP into a known state. As
part of a hardware reset, all current operations are aborted, the instruction
pipeline is emptied, and CPU registers are reset. Then the CPU executes the
reset interrupt service routine (see Section 5.4.1). When reading the reset in-
terrupt vector, the CPU uses bits 24, 28, 29, and 30 of the 32-bit reset vector
location to determine which stack configuration and default pointer mode to
use (see Section 7.2 for more details).
Table 5−6 summarizes the effects of a DSP hardware reset on DSP registers.
A software reset (see Section 5.5.2) performs a subset of these register modifi-
cations.
The RESET pin must be asserted for certain number of clock cycles (refer to
applicable data manual). If the RESET pin is asserted and deasserted while
the DSP is stopped for emulation purposes, then the reset is ignored.
Notes:
1) External interrupts must occur at least 3 cycles after the CPU exits reset
or they will not be recognized.
2) All interrupts (maskable and nonmaskable) are disabled following a
hardware reset. Interrupts will remain disabled until the stack pointers
are initialized by a software write to each pointer (the XSP and XSSP
registers). After stack initialization, the INTM bit and the IER0 and IER1
registers determine interrupt enabling.
5.5.2 Software Reset

A software reset is the reset operation initiated by the software reset instruc-
tion. A software reset only affects IFR0, IFR1, ST0_55, ST1_55, ST2_55, all
16 bits of T2 register, and the SATA bit in ST3. All other registers are unaf-
fected. The software reset values shown in Table 5−6 are the same as those
forced by a DSP hardware reset (see Section 5.5).
When reading the reset interrupt vector, the CPU uses bits 24, 28, 29, and 30
of the 32-bit reset vector location to determine which stack configuration and
default pointer mode to use (see Section 7.2 for more details).

Chapter 6
Addressing Modes
This chapter describes the modes available for addressing the data space
(including CPU registers) and the I/O space of the TMS320C55x+ (C55x+)
DSPs in word-pointer.
Topic Page
6.1 Important Note on Word-Pointer Mode Address Computation . . . . . 6-2

6.2 Introduction to the Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.3 Absolute Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.4 Direct Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
6.5 Indirect Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
6.6 Addressing Data Memory and Memory-Mapped Registers . . . . . . . 6-28
6.7 Restrictions on Accesses to Memory-Mapped Registers . . . . . . . . 6-52
6.8 Addressing Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-53
6.9 I/O − xI/O Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-69
6.10 Addressing I/O and xI/O Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-73
6.11 Restrictions on Accesses to I/O − xI/O Spaces . . . . . . . . . . . . . . . . . . 6-91
6.12 Circular Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-93
6-1
Important Note on Word-Pointer Mode Address Computation
6.1 Important Note on Word-Pointer Mode Address Computation

It is important to note that the addressing modes and pointer modifications de-
scribed in this chapter are performed when the CPU is in word-pointer mode.
As explained in Section 3.1, in word-pointer mode, data memory locations are
referenced by the A unit with a 23-bit effective word address generated by the
DAGEN with a 24-bit address register (XARx, XDP, XSP, XSSP).
Before being posted on the data address buses, the generated addresses are
shifted to the MSBs by one bit to produce the equivalent 24-bit byte address.
This operating mode enables the C55x+ CPU to recompile and execute C55x
DSP generation codes which uses the full range of its 23-bit word addressable
data space.
Note that this is the user’s responsibility to ensure that, in word-pointer mode,
the 24th bit of the effective word address generated by the user’s program is
set to 0; in case it is not, the CPU behavior is undefined.
All addresses given as hexadecimal in this chapter represent 23-bit effective

word addresses.
See Chapter 7 for the description of the addressing modes in byte-pointer

mode.
6-2 Addressing Modes

Introduction to the Addressing Modes
6.2 Introduction to the Addressing Modes

The C55x+ DSP supports three types of addressing modes that enable flexible
access to data memory, memory-mapped registers (MMRs), C55x+ registers,
register bits, and I/O − xI/O spaces.
Absolute addressing modes reference a location by supplying all or part

of an address as a constant in an instruction:
See Section 6.3 for data memory and MMR accesses
See Section 6.9.1 for I/O − xI/O spaces access
Direct addressing modes reference a location using an address offset:

See Section 6.4 for data memory, MMR, C55x+ register, and register bit
accesses
Indirect addressing modes reference a location using a pointer:

See Section 6.5 for data memory and MMR accesses
The I/O absolute, direct, and indirect addressing modes are detailed in Sec-
tion 6.8.
Note:
Be aware that certain parallel instructions perform several operations that
may need to make up to three data memory accesses within the same cycle.
These instructions will not be executed in one cycle, unless the memory ac-
cesses are adequately performed across different memory regions: banked
SARAM or SARAM blocks regions. Refer to your DSP memory subsystem
documentation for more details on your DSP internal memory structure.
Each addressing mode provides one or more types of operands. An instruction

that supports an addressing-mode operand has one of the syntax elements
listed in Table 6−1.
Addressing Modes 6-3

Introduction to the Addressing Modes
Table 6−1. C55x+ Addressing Modes Syntax Elements
Syntax
Element(s) Description
Smem When an instruction syntax contains the Smem operand, that instruction can access a single word
dbl(Smem) (16 bits) of data from data memory, I/O − xI/O spaces, a memory-mapped register, or a C55x+
HI(Smem) register. When an instruction syntax contains the dbl(Smem) operand or HI(Smem)/LO(Smem)
LO(Smem) operand, that instruction can access a long word (32 bits) of data from data memory, xI/O space,
a memory-mapped register, or a C55x+ register. As you write the instruction, replace Smem,
dbl(Smem), or HI(Smem)/LO(Smem) with a compatible addressing-mode operand.
Xmem When an instruction contains the Xmem and Ymem operands, that instruction can perform two
Ymem simultaneous 16-bit accesses to data memory. As you write the instruction, replace Xmem and
dbl (Ymem) Ymem operands with compatible addressing modes operands.
Cmem When an instruction contains the Cmem or HI(Cmem)/LO(Cmem) operand, that instruction can
HI(Cmem) access, respectively, a single word (16 bits) or a double word (32 bits) of data from memory. As
LO(Cmem) you write the instruction, replace the Cmem or HI(Cmem)/LO(Cmem) operand with a compatible
addressing mode operand.
NOTE 1: In C55x DSP generations, Cmem limits the addressing modes to 4 possibilities (each
one using indirect addressing mode with the XCDP register only). In the C55x+ DSP, the XCDP
register is mapped to the XAR15 register, and the Cmem addressing mode possibilities are
identical to the Xmem and Ymem addressing mode possibilities. You can chose from any of the
16 address registers with any of the 8 address register modifiers.
NOTE 2: The dbl(Ymem) operand is a 32-bit memory operand. This operand can be used only
in the following instruction:
dbl(Ymem) = dbl(Smem)
dbl(Smem) = dbl(Ymem)
Baddr When an instruction contains the Baddr operand, that instruction can access one or two bits in
an accumulator (AC0–AC15), an auxiliary register (AR0–AR15), or a temporary register (T0–T3).
Only the register bit test/set/clear/complement and bit field extract/insert instructions support the
Baddr operand. As you write one of these instructions, replace the Baddr operand with a
compatible addressing mode operand.

Absolute Addressing Modes
6.3 Absolute Addressing Modes

Two absolute addressing modes are available as described in Table 6−2.
Table 6−2. Absolute Addressing Modes
Addressing Mode Description See Section
k16 absolute This mode uses the 8-bit register called DPH (high part of the extended data 6.3.1
page register XPD) and a 16-bit unsigned constant to form a 24-bit
data-space address. This mode can access a memory location or a
memory-mapped register.
k2 absolute This mode enables you to specify a full address as a 24-bit unsigned 6.3.2
constant. This mode can access a memory location or a memory-mapped
register.
6.3.1 k16 Absolute Addressing Mode

The assembler syntax of the k16 absolute addressing mode is
*abs16(#k16) , where k16 is a 16-bit unsigned constant. Figure 6−1 shows
how DPH (the high part of the extended data page register XPD) and k16 are
concatenated to form a 24-bit data-space address. When an instruction uses
this addressing mode, the constant is encoded in a 2-byte extension to the in-
struction. Unlike C55x DSP generations, the C55x+ DSP executes an instruc-
tion using this addressing mode in parallel with another instruction.
As compared to the XDP direct addressing mode described in Section 6.4.1,

the k16 absolute addressing mode brings more flexibility by having the ability
to address the 65536-word long main data page pointed to by DPH.
Note that:
For k16 absolute addressing mode, although the generated address can
be 24 bits wide in word-pointer mode, only the 23 LSBs generate the 23-bit
effective word address.
When an instruction uses this addressing mode to refer to a memory-

mapped register (MMR), the AC1 pipeline phase of the instruction is
stalled for 1 cycle.

Figure 6−1. k16 Absolute Addressing Mode
DPH k16 Data Space (Word Addresses)

0000. 0000 0000 0000. 0000 0000
. . Main page 0: 000000h−00 FFFFh
. .
0000 0000 1111 1111 1111 1111
0000 0001 0000 0000 0000 0000
. .
. .
0000 0001 1111 1111 1111 1111
0000. 0010 0000 0000. 0000 0000
. .
0000 0010 1111 1111 1111 1111
. . . .
. . . .
. . . .
. . . .
. . . .
. . . .
0111 1111 0000 0000 0000 0000

. .
. . Main page 127: 7F0000h−7FFFFFh
. .
0111 1111 1111 1111 1111 1111
6.3.2 k24 Absolute Addressing Mode
The assembler syntax of the k24 absolute addressing mode is *(#k24),

where k24 is a 24-bit unsigned constant. Figure 6−2 shows how data space
is addressed using k24. When an instruction uses this addressing mode, the
constant is encoded in a 3-byte extension to the instruction. Unlike the C55x
DSP generations, the C55x+ DSP executes an instruction using this address-
ing mode in parallel with another instruction.
Note that:
For k24 absolute addressing mode, although the generated address can
be 24 bits wide in word-pointer mode, only the 23 LSBs generate the 23-bit
effective word address.
When an instruction uses this addressing mode to refer to a memory-

mapped register (MMR), the AC1 pipeline phase of the instruction is
stalled for 1 cycle.

Figure 6−2. k24 Absolute Addressing Mode

k24 Data Space (Word Addresses)
000000h ......
.........7F FFFFh

Direct Addressing Modes
6.4 Direct Addressing Modes

The following direct addressing modes are available:
Addressing
Mode Description See Section
XDP direct This mode uses an instruction-defined constant and 6.4.1

the extended data page register XDP to make an
indirect access (with offset) to a memory location or a
XSP direct This mode uses an instruction-defined constant and 6.4.2

the stack pointer register XSP to make an indirect
access (with offset) to the stack elements stored in
data memory.
MMR direct This mode uses an instruction-defined constant and 6.4.3

the mmap() qualifier to make a direct access to a
Register ID This mode uses an instruction-defined constant and 6.4.4

direct the mmap() qualifier to make a direct access to a
C55x+ register.
Register-bit This mode uses an instruction-defined constant to 6.4.5

direct specify a bit address. This mode accesses one
register bit or two adjacent register bits.
Note:
In C55x DSP generations, the XSP and XDP addressing modes are mutually
exclusive and dependent on the CPL bit in status register ST1_55.
The C55x+ DSP does not have this dependency in order to improve the C
compiler efficiency: all direct addressing modes are independent of the CPL
status bit value.
6.4.1 XDP Direct Addressing Mode

The assembler syntax of the XDP direct addressing mode is @Daddr where
Daddr is an address that you specify in the instruction.
When using this addressing mode, Daddr together with the .dp assembler di-
rective are used by the assembler to compute the 7-bit constant Doffset which
is encoded in the instruction. Figure 6−3 shows how, at instruction decoding,
the DSP generates the 24-bit address in the XDP direct addressing mode. It
is the 24-bit sum of two values:

The value in the data page register (XDP). XDP identifies the start address
of a 128-word local data page. This start address can be any address with-
in the 8-Mword data space.
The 7-bit offset (Doffset) calculated by the assembler. See Section 6.4.1.1
for details on the calculation.
To address elements stored in one of the 128-word local data pages, the XDP
direct addressing mode is more efficient than the k16 absolute addressing
mode described in Section 6.3.1 because of the 2-byte extension to the in-
struction which is not needed.
To ensure source code compatibility with the C55x DSPs in the C55x+ DSP,
XDP can be loaded with a single instruction or with 2 instructions loading sepa-
rately the DPH register (8 higher bits of XDP) or the DP register (16 lower bits
of XDP).
When an instruction uses this addressing mode to refer to a memory-mapped

register (MMR), the AC1 pipeline phase of the instruction is stalled for 1 cycle.
Note:
On C55x DSP generations, although an increment past FFFFh or a decre-
ment past 0000h causes the direct address to wrap around, this behavior is
not supported. This type of source code is not executed correctly on the
C55x+ DSP.

Figure 6−3. XDP Direct Addressing Mode

(XDP + Doffset) Data Space (Word Address)
000000h.......
XDP 20 FFF0h
.....20 FFFFh
Doffset = 2Fh
21 0000h− ....
(XDP + Doffset) 21 0010h
....7FFFFFh
6.4.1.1 How the Assembler Calculates Doffset for the XDP Direct Addressing Mode
Access Made To: Doffset Calculation Description
Data memory Doffset = (Daddr – .dp) & 7Fh Daddr is the 24-bit address for the read or write
operation; .dp is a value you assign with the .dp
assembler directive (.dp generally matches XDP);
the symbol & indicates a bitwise AND operation.
The following code example uses XDP direct addressing to access the data
memory:
XDP = #03FFF0h ;For run-time, XDP is 03 FFF0h
.dp = #03FFF0h ;For assembly time, .dp is 03 FFF0h
T2 = @03FFF4h ;Load T2 with the value at address 03 FFF4h
The assembler calculates Doffset:
Doffset = (Daddr – .dp) & 7Fh = (03FFF4h – 03FFF0h) & 7Fh
= 04h
Doffset is encoded in the instruction: T2 = @03FFF4h. At run time, the 24-bit
data-space address is generated:
24-bit address = XDP + Doffset = 03 FFF0h + 0004h = 03 FFF4h

6.4.2 XSP Direct Addressing Mode
The assembler syntax of the XSP addressing mode is *SP(#offset) where off-
set is a 7-bit unsigned constant.
When using the XSP direct addressing mode, 24-bit addresses are formed as
shown in Figure 6−4. It is the sum of the XSP value and a 7-bit offset that you
specified in the instruction. The offset can be a value from 0 to 127.
To ensure source code compatibility with C55x DSP generations in the C55x+
DSP, XSP can be loaded with a single instruction or with 2 instructions loading
separately the SPH register (8 higher bits of XSP) or SP (16 lower bits of XSP).
See Chapter 4 for more details on stack modes usage.
Note:
Data space addresses 00 0000h−00 005Fh are reserved for the memory-
mapped registers (MMR). Make sure that the data stack uses only address-
es 00 0060h−07 FFFFh.
Figure 6−4. XSP Direct Addressing Mode
(XSP + offset) Data Space (Word Address)
000000h.......
XSP 20 FFF0h
.....20 FFFFh
offset = 2Fh
21 0000h− ....
(XSP + offset) 21 001Fh
....7FFFFFh

6.4.3 MMR Direct Addressing Mode

The assembler syntax of the MMR direct addressing mode is mmap(@MMR)
where MMR is a 7-bit unsigned constant referencing one of the memory-
mapped registers (see Table 2−2 for the valid MMR symbols).
This addressing mode is a simpler way to access the MMR registers than the
XDP direct addressing mode (see Section 6.4.1) because with the XDP direct
addressing mode, you would need to ensure that:
The .dp assembler directive is set to 0 in your code
The DP register is initialized to 0 at execution time
The 24-bit address which is generated as described in Section 6.4.1 is one

of the valid MMR address locations
When using the MMR direct addressing mode, you only need to use the
mmap() qualifier.
When an instruction uses this addressing mode:
The mmap() qualifier is encoded as a 1-byte extension to the instruction

The AC1 pipeline phase of the instruction is stalled for 1 cycle
The following code example accesses the AR0_L MMR:

T2 = mmap(@AR0_L)
6.4.4 Register ID Direct Addressing Mode

The assembler syntax of the register ID direct addressing mode is
mmap(@RegisterID) where RegisterID is an 8-bit unsigned constant refer-
encing one of the C55x+ registers (see Table 2−2 for the valid register IDs).
When an instruction uses this addressing mode, the mmap() qualifier is en-
coded as a 1-byte extension to the instruction.
The following example accesses the 32 LSBs of the AC2 register with its regis-
ter ID:
AC3 = dbl(mmap(@AC2))

6.4.5 Register-Bit Direct Addressing Mode

In the register-bit direct addressing mode, the constant you supply in the oper-
and, @bit_position, is a bit position from the least significant bit (LSB) of the
register (see Figure 6−5). For example, if @bit_position is 0, then you are ad-
dressing the least significant bit (LSB) of a register. If @bit_position is 3, then
you are addressing bit 3 of the register.
Only the register bit test/set/clear/complement and bit field insert/extract in-
structions support this addressing mode. These instructions enable you to ac-
cess bits only in the accumulators (AC0−AC15), the auxiliary registers
(AR0−AR15), and the temporary registers (T0−T3).
Note:
Unlike the direct operands (@Daddr and *SP(offset)) that access data
memory with Smem and dbl(Smem) syntax elements, the register-bit direct
operand, @bit_position, does not use the XSP and XDP registers for ad-
dress computation. The register-bit direct operand, @bit_position, indicates
directly the address of one bit of data to access.
Figure 6−5. Register-Bit Direct Addressing Mode

bit_position: M ... 11 10 9 8 7 6 5 4 3 2 1 0
...
MSB Register LSB
Note: Bit address M is 39 or 15, depending on the size of the register.

Indirect Addressing Modes
6.5 Indirect Addressing Modes

The CPU supports the following indirect addressing modes. You may use
these modes for linear addressing or circular addressing (see Section 6.12 for
circular addressing).
Addressing Mode Description See Section
XAR indirect This mode uses 1 of 16 extended auxiliary 6.5.1

registers (XAR0–XAR15) to point to data. The
way the CPU uses the auxiliary register to
generate an address depends on whether you
are accessing data space (memory or memory-
mapped registers), individual register bits, or
I/O space (see Section 6.9.3 for I/O − xI/O
space indirect addressing modes description).
Dual XAR indirect This mode uses the same address-generation 6.5.2
process as the XAR indirect addressing mode.
This mode is used with an instruction that
accesses two or more data-memory locations at
the same time.
Coefficient indirect This mode uses the same address-generation 6.5.3

process as the dual XAR indirect addressing
mode. This mode is available to support
instructions that can access a coefficient in data
memory at the same time as they access other
data-memory values using the dual XAR
indirect addressing mode.
Note:
On C55x DSP generations, the XAR indirect addressing mode is dependent
on the ARMS bit in status register ST2_55. In order to improve the C compiler
efficiency, this dependency is removed in the C55x+ DSP: all XAR indirect
addressing modes are independent of the ARMS status bit value.

6.5.1 XAR Indirect Addressing Mode
This mode uses an extended auxiliary register XARn (n = 0−15) to point to

data. The way the CPU uses XARn to generate an address depends on the
access type:
For An Access To ... XARn Contains ...
Data space The 24-bit address, see Section 6.5.1.1

(memory or MMRs)
A register bit (or bit pair) A bit number, see Section 6.5.1.2
When an instruction uses this addressing mode to refer to a memory-mapped

register (MMR), the AC1 pipeline phase of the instruction is stalled for 1 cycle.
6.5.1.1 XAR Indirect Accesses to Data Space and MMRs
When the XAR indirect addressing mode accesses data space or MMRs, the
selected 24-bit extended auxiliary register, XARn, contains a 23-bit effective
word address.
XARn can be loaded with a single instruction. For circular addressing pur-
poses, ARn (16 lower bits of XARn) can be independently loaded (see Sec-
tion 6.12 for more details on circular addressing). ARnH (8 highest bits of
XARn) cannot be accessed individually.
6.5.1.2 XAR Indirect Accesses to Register Bits
When the XAR indirect addressing mode accesses a register bit, the selected
24-bit extended auxiliary register, XARn, contains a bit number (see
Figure 6−6). For example, if XAR2 contains 0, then XAR2 points to bit 0, the
least significant bit (LSB) of the register.
Only the register bit test/set/clear/complement and bit field insert/extract in-
structions support this mode. These instructions enable you to access bits in
the accumulators (AC0–AC15), the auxiliary registers (AR0–AR15), and the
temporary registers (T0–T3).
Figure 6−6. Accessing Register Bit(s) With the XAR Indirect Addressing Mode
XARn: M ... 11 10 9 8 7 6 5 4 3 2 1 0
...
MSB Register LSB
Note: Bit address M is 39 or 15, depending on the size of the register.

6.5.1.3 XAR Indirect Operands
The C55x+ DSP features 14 different indirect operands.
You can use four temporary registers (T0−T3) as an index in the following
addressing modes: *(ARn+Tx), *(ARn−Tx), and *ARn(Tx)
You can use *ARn(XAR15[23:4]) indirect addressing mode to support bit

field extraction for Huffman decoding
You can use bit reverse addressing modes *(ARn+T0B) and *(ARn−T0B)
for the FFT algorithm
You can choose between *ARn(K16) and *ARn
(short(k4)) to privilege code size versus addressing flexibility
Table 6−3 introduces all XAR indirect operands. When using the tables, keep
in mind that:
All address generations are performed on 24-bit whited
All pointer modifications are performed on 24 bits
Both pointer modification and address generation are linear or circular ac-
cording to the pointer configuration in status register ST2_55. The content
of the appropriate 16-bit buffer start address register (BSA01, BSA23,
BSA45, or BSA67) is added only if circular addressing is activated for the
chosen pointer.
Note:
Although an increment past 7F FFFFh or a decrement past 00 0000h causes
the indirect address to wrap around, do not make use of this behavior, it is
not supported. Also during circular addressing, the BSAxx addition must not
increment the address beyond 7F FFFFh (see Section 6.12 for more details
on circular addressing).

Table 6−3. Operands for the XAR Indirect Addressing Mode

Operand Pointer Modification Supported Access Types
*ARn XARn is not modified. Data-memory (Smem, dbl(Smem),

HI(Smem)/LO(Smem))
Memory-mapped register
(Smem, dbl(Smem), HI(Smem)/LO(Smem))
Register bit (Baddr)
I/O space (Smem)
xI/O-space (Smem, dbl(Smem),
HI(Smem)/LO(Smem))
*ARn+ XARn is incremented after the address Data-memory (Smem, dbl(Smem),

is generated. †‡ HI(Smem)/LO(Smem))
I/O space (Smem)
HI(Smem)/LO(Smem))
*ARn– XARn is decremented after the address Data-memory (Smem, dbl(Smem),

is generated.§¶ HI(Smem)/LO(Smem))
I/O space (Smem)
HI(Smem)/LO(Smem))
*+ARn XARn is incremented before the ad- Data-memory (Smem, dbl(Smem),

dress is generated. †‡ HI(Smem)/LO(Smem))
I/O space (Smem)
HI(Smem)/LO(Smem))
† If 16-bit/1-bit operation: XARn = XARn + 1; 1-bit operation: register bit access that reads or modifies a single bit in a register.
‡ If 32-bit/2-bit operation: XARn = XARn + 2; 2-bit operation: register bit access that reads or modifies a register bit-pair.
§ If 16-bit/1-bit operation: XARn = XARn − 1; 1-bit operation: register bit access that reads or modifies a single bit in a register.
¶ If 32-bit/2-bit operation: XARn = XARn − 2; 2-bit operation: register bit access that reads or modifies a register bit-pair.

Table 6−3. Operands for the XAR Indirect Addressing Mode (Continued)
*–ARn XARn is decremented before the ad- Data-memory (Smem, dbl(Smem),

dress is generated.§¶ HI(Smem)/LO(Smem))
I/O space (Smem)
HI(Smem)/LO(Smem))
*(ARn + T0/AR0) The 16-bit signed constant in T0 or AR0 Data-memory (Smem, dbl(Smem),
is sign extended to 24 bits and added to HI(Smem)/LO(Smem))
the XARn after the address is gener-
ated:
If C54CM = 0: XARn = XARn + T0
If C54CM = 1: XARn = XARn + AR0 Register bit (Baddr)
I/O space (Smem)
HI(Smem)/LO(Smem))
*(ARn – T0/AR0) The 16-bit signed constant in T0 or AR0 Data-memory (Smem, dbl(Smem),
is sign extended to 24 bits and sub- HI(Smem)/LO(Smem))
tracted from XARn after the address is
generated:
If C54CM = 0: XARn = XARn – T0
If C54CM = 1: XARn = XARn – AR0 Register bit (Baddr)
I/O space (Smem)
HI(Smem)/LO(Smem))
*ARn(T0/AR0) XARn is not modified. XARn is used as Data-memory (Smem, dbl(Smem),

a base pointer. The 16-bit signed HI(Smem)/LO(Smem))
constant in T0 or AR0 is 24-bit sign ex-
tended and is used as an offset from
that base pointer for the address gener-
ation: Register bit (Baddr)
If C54CM = 0, T0 is used I/O space (Smem)
If C54CM = 1, AR0 is used xI/O-space (Smem, dbl(Smem),
HI(Smem)/LO(Smem))

NOTE: For these addressing modes,

Tx can be T1, T2, or T3.
*(ARn + Tx) The 16-bit signed constant in Tx is sign- Data-memory (Smem, dbl(Smem),
extended to 24 bits and added to XARn HI(Smem)/LO(Smem))
after the address is generated.
XARn = XARn + Tx
I/O space (Smem)
HI(Smem)/LO(Smem))
*(ARn – Tx) The 16-bit signed constant in Tx is sign Data-memory (Smem, dbl(Smem),
extended to 24 bits and subtracted from HI(Smem)/LO(Smem))
XARn after the address is generated.
XARn = XARn – Tx
I/O space (Smem)
HI(Smem)/LO(Smem))
*ARn(Tx) XARn is not modified. XARn is used as Data-memory (Smem, dbl(Smem),

a base pointer. The 16-bit signed HI(Smem)/LO(Smem))
constant in Tx is 24-bit sign extended
and is used as an offset from that base
pointer for the address generation.
I/O space (Smem)
HI(Smem)/LO(Smem))

*(ARn + T0B/AR0B) The 16-bit signed constant in T0 or AR0 Data-memory (Smem, dbl(Smem),
is sign extended to 24 bits and added to HI(Smem)/LO(Smem))
XARn after the address is generated:
If C54CM = 0: XARn = XARn + T0
If C54CM = 1: XARn = XARn + AR0
(Either addition is done with reverse
carry propagation to create bit-reverse
addressing.)
Note: This addressing mode can be
used for FFT buffer elements address-
ing. When this bit-reverse operand is
used, XARn can be configured in
ST2_55 for circular addressing; this re-
moves alignment constraints on the
FFT buffer start address (see Section
6.9 for BSAxx addition computation).
However, in this case, XARn is not im-
pacted by circular addressing computa-
tion.
*(ARn – T0B/AR0B) The 16-bit signed constant in T0 or AR0 Data-memory (Smem, dbl(Smem),
is sign extended to 24 bits and sub- HI(Smem)/LO(Smem))
tracted from XARn after the address is
generated on 24-bit width:
If C54CM = 0: XARn = XARn – T0
If C54CM = 1: XARn = XARn – AR0
(Either subtraction is done with reverse
carry propagation.)
Note: This addressing mode can be
used for FFT buffer elements address-
ing. When this bit-reverse operand is
used, XARn can be configured in
ST2_55 for circular addressing; this re-
moves alignment constraints on the
FFT buffer start address (see Section
6.9 for BSAxx addition computation).
However in this case, XARn is not im-
pacted by circular addressing computa-
tion.

*ARn(#K16) ARn is not modified. ARn is used as a Data-memory (Smem, dbl(Smem),

base pointer. The 16-bit signed HI(Smem)/LO(Smem))
constant (K16) is 24-bit sign extended
pointer for address generation.
I/O space (Smem)
HI(Smem)/LO(Smem))
*+ARn(#K16) The 16-bit signed constant (K16) is Data-memory (Smem, dbl(Smem),

24-bit sign extended and added to HI(Smem)/LO(Smem))
XARn before the address is generated.
I/O space (Smem)
HI(Smem)/LO(Smem))

*ARn(short(#k4)) XARn is not modified. XARn is used as Data-memory (Smem, dbl(Smem),

a base pointer. The 4-bit unsigned HI(Smem)/LO(Smem))
constant (k4) is zero extended to
24 bits and is used as an offset from
that base pointer. k4 is in the range
0 to 15. Register bit (Baddr)
I/O space (Smem)
HI(Smem)/LO(Smem))
*ARn(XAR15[23:4]) XARn is not modified. XARn is used as Data-memory (Smem)

a base pointer. The 24-bit constant in
XAR15 is truncated from bit 4 to bit 24,
pointer.
Note: This new operand has been add-
ed to support the new field insert/ex-
tract instructions. It is only applicable
for 16-bit load /store/mar() instructions:
− copy (ALLa = Smem)
− Smem = ALLa
− XDa = mar(Smem)
See C55x instruction guide documenta-
tion: TI literature number TBD). It can-
not be used in any other instructions.

6.5.2 Dual XAR Indirect Addressing Mode

The dual XAR indirect addressing mode enables you to make two data-
memory accesses through the 16 extended auxiliary registers, XAR0–XAR15.
As with a single XAR indirect access to data space (see Section 6.5.1.1), the
CPU uses an extended auxiliary register to create each 24-bit address. You
can use linear addressing or circular addressing for each of the two accesses
(see Section 6.12 for circular addressing).
You may use the dual XAR indirect addressing mode for executing an instruc-
tion that makes two data-memory accesses. In this case, the two data-memory
operands are designated in the instruction syntax as Xmem and Ymem. For
example:
ACLHa = Xmem + Ymem
Unlike C55x DSP generations, the C55x+ revision allows parallel instructions
involving two Smem/dbl(Smem) operands to be executed without any restric-
tions on the XAR indirect operands. In the example below, any Smem oper-
ands listed in Table 6−3 can be used:
DAa = Smem
|| Smem = ALLa
The available dual XAR indirect operands are a subset of the XAR indirect op-
erands.
Note:
The assembler rejects code in which dual operands use the same auxiliary reg-
ister with two different auxiliary register modifications. You can use the same
XARn for both operands only if one of the operands does not modify XARn.

6.5.2.1 Dual XAR Indirect Operands
Table 6−4 introduces the operands available for the dual XAR indirect ad-
dressing mode. Note that:
of the appropriate 16-bit buffer start address register (BSA01, BSA23,
BSA45, or BSA67) is added only if circular addressing is activated for the
chosen pointer. The indirect data address generation arithmetic opera-
tions are based on 24-bit arithmetic.
Note:
the indirect address to wrap around, do not make use of this behavior. It is
on circular addressing mode).

Table 6−4. Dual XAR Indirect Operands

Operand Pointer Modification Supported Access Type
*ARn XARn is not modified. Data-memory:

Smem, dbl(Smem),
Xmem, Ymem, dbl(Ymem),
Cmem, HI(Cmem)/LO(Cmem)
*ARn+ XARn is incremented after the address is Data-memory :

generated.†‡ Smem, dbl(Smem),
*ARn– XARn is decremented after the address is Data-memory:

generated.§¶ Smem, dbl(Smem),
*(ARn + T0/AR0) The 16-bit signed constant in T0 or AR0 is sign Data-memory:

extended to 24 bits and added to XARn after the Smem, dbl(Smem),
address is generated . Xmem, Ymem, dbl(Ymem),
If C54CM = 0: XARn = XARn + T0 Cmem, HI(Cmem)/LO(Cmem)
If C54CM = 1: XARn = XARn AR0
*(ARn – T0/AR0) The 16-bit signed constant in T0 or XAR0 is sign Data-memory:

extended to 24 bits and subtracted from XARn after Smem, dbl(Smem),
the address is generated: Xmem, Ymem, dbl(Ymem),
If C54CM = 0: ARn = XARn – T0 Cmem, HI(Cmem)/LO(Cmem)
If C54CM = 1: ARn = XARn – AR0
*ARn(T0/AR0) XARn is not modified. XARn is used as a base Data-memory:

pointer. The 16-bit signed constant in T0 or AR0, is Smem, dbl(Smem),
24-bit sign extended and is used as an offset from Xmem, Ymem, dbl(Ymem),
that base pointer for the address generation. Cmem, HI(Cmem)/LO(Cmem)
If C54CM = 0, T0 is used
If C54CM = 1, AR0 is used
*(ARn + T1) The 16-bit signed constant in T1 is sign-extended to Data-memory:

24 bits and added to XARn after the address is Smem, dbl(Smem),
generated. Xmem, Ymem, dbl(Ymem),
XARn = XARn + T1 Cmem, HI(Cmem)/LO(Cmem)
*(ARn – T1) The 16-bit signed constant in T1 is sign-extended to Data-memory:

24 bits and subtracted from XARn after the address Smem, dbl(Smem),
is generated. Xmem, Ymem, dbl(Ymem),
XARn = XARn – T1 Cmem, HI(Cmem)/LO(Cmem)
† If 16-bit operation: XARn = XARn + 1

‡ If 32-bit operation: XARn = XARn + 2
§ If 16-bit operation: XARn = XARn − 1
¶ If 32-bit operation: XARn = XARn − 2

6.5.3 (Single/Long) Coefficient Indirect Addressing Mode

The coefficient indirect addressing mode is supported by the following
arithmetical instructions:
Finite impulse response filter
Multiply
Multiply and accumulate
Multiply and subtract
Dual multiply (and accumulate/subtract)
Instructions using the coefficient indirect addressing can be executed alone or

in parallel with other instructions, and bring up to four, 16-bit, memory oper-
ands to the MAC units. When an instruction syntax contains Cmem (or
HI(Cmem)/LO(Cmem)), these operands are accessed with the single (or long)
coefficient indirect addressing mode and are carried on the 32-bit BB bus of
the CPU (see Section 1.6).
The following examples illustrate how the coefficient indirect addressing
modes can be used in various ways.
Two memory operands (Xmem and Ymem) are accessed with the dual
XAR indirect addressing mode. The third operand (Cmem) is accessed
with the coefficient indirect addressing mode. In one cycle, two multiplica-
tions are performed in parallel. Cmem is common to both multiplications,
while Xmem and Ymem are used for the other values in the multiplication.
ACx = Xmem * Cmem,
ACy = Ymem * Cmem
Two memory operands HI(Smem)/LO(Smem) are accessed with the XAR
indirect addressing mode. The third and fourth operands
HI(Cmem)/LO(Cmem) are accessed with the long coefficient indirect ad-
dressing mode. In one cycle, two multiplications are performed in parallel
using four distinct 16-bit operands.
ACx = LO(Smem) * LO(Cmem),
ACy = HI(Smem) * HI(Cmem)
In one cycle, two multiplications are performed in parallel with two addi-
tions. The two MAC units uses two memory operands
HI(Cmem)/LO(Cmem) and the low and high part of one ACz register. The
SALU unit uses the remaining memory operands HI(Smem)/LO(Smem)
to perform the two additions.
ACx = ACz.L * LO(Cmem),
ACy = ACz.H * LO(Cmem)
|| HI(ACw) = HI(Smem) + HI(ACv),
LO(ACw) = LO(Smem) + LO(ACv)

Note:
The above example executes in one cycle provided the memory accesses
are adequately performed across different memory regions: banked SARAM
or SARAM blocks regions. Refer to your DSP data manual for more details
on internal memory structure and performance.
6.5.3.1 (Single/Long) Coefficient Indirect Operands

In the C55x+ DSP, the operands for the coefficient indirect addressing mode
are the same as the dual XAR indirect operands shown in Table 6−4.
Eight different coefficient indirect operands can be used instead of four on
C55x DSP generations
Any of the 16 extended auxiliary registers (XAR0−XAR15) can be used for
the coefficient indirect operands. For source code compatibility with C55x
DSP generations, the XAR15 extended auxiliary register is mapped to the
XCDP register (the XCDP register is not available in the C55x+ DSP).
of the 16-bit buffer start address register BSAC is added only if circular ad-
dressing is activated for the XAR15 register. The indirect data address
generation arithmetic operations are based on 24-bit arithmetic.
Note:
With algebraic instructions syntax, you must enclose each coefficient indi-
rect operand in the syntax element coef(), and enclose each long coefficient
indirect operand in the syntax LO(coef()), HI(coef()) (see Section 6.5.3.2).
6.5.3.2 coef() Keyword Required For Coefficient Indirect Operands in Algebraic Instruction
Syntax
With the algebraic instruction syntax, you must enclose each coefficient indi-
rect (Cmem) operand in the coef() syntax element. For example:
ACx = LO(Smem) * LO(Cmem),
ACy = HI(Smem) * HI(Cmem)
Assume AC0 is used for the ACx operand, AC9 for the ACy operand, *AR0 for
the Smem operand, and *(AR3 − T1) for the Cmem operand. The instruction
is written as follows:
AC0 = LO(*AR0) * LO(coef(*(AR3 − T1))),
AC9 = HI(*AR0) * HI(coef(*(AR3 − T1)))
Note that in the previous example, you must enclose the coef() syntax element
in both HI(Cmem)/LO(Cmem) operands.

Addressing Data Memory, MMRs, and C55x+ Registers
6.6 Addressing Data Memory, MMRs, and C55x+ Registers

Absolute addressing modes (described in Section 6.3), direct addressing
modes (described in Section 6.4), and indirect addressing modes (described
in Section 6.5) can address values in data memory and memory-mapped reg-
isters (MMRs). The following sections provide some examples for these ad-
dressing modes.
There are some restrictions on accesses to memory-mapped registers. See

Section 6.7 for more details.
6.6.1 Addressing Data Memory and MMRs With Absolute Addressing Modes
The k16 absolute addressing mode *abs16(#k16) or the k24 absolute ad-
dressing mode *(#k24) can access data memory in any instruction with one
of these syntax elements:
Smem Indicates one word (16 bits) of data
dbl(Smem) Indicates one long word (32 bits) of data
HI(Smem)/LO(Smem) Indicates one long word (32 bits) of data
Table 6−5 through Table 6−7 provide examples of how to use these operands.
Because the MMRs are mapped at the bottom of the 16-Mb data memory
space, to access them with *abs16(#k16) you must first ensure that DPH = 0.
Table 6−5. *abs16(#k16) Used For Data-Memory Access
Generated Address
Syntax Example Instruction Example For DPH = 3 Description
Ra = Smem T2 = *abs16(#2002h) DPH:k16 = 03 2002h The CPU loads the value at ad-
dress 03 2002h into T2.
Ra = HI(Smem), T2 = HI(*abs16(#2002h)), DPH:k16 = 03 2002h The CPU reads the values at

Ra+1 = LO(Smem)¶ T3 = LO(*abs16(#2002h)) addresses 03 2002h and
03 2003h and copies them into
T2 and T3, respectively.
Note: ¶ In instructions using HI(Smem)/LO(Smem) operands, Smem must refer to the same memory operand in both parts.

Table 6−6. *abs16(#k16) Used For Memory-Mapped Registers
Generated Address
Syntax Example Instruction Example DPH must be 0 Description
Ra = Smem T2 = *abs16(#12h) DPH:k16 = 00 0012h AR2 is at address 00 0012h. The

CPU loads the content of AR2 into
T2.
Ra = HI(Smem), T2 = HI(*abs16(#AR2)), DPH:k16= 00 0012h AR2 and AR3 are at addresses

Ra+1 = LO(Smem) ¶ T3 = LO(*abs16(#AR2)) 00 0012h and 00 0013h (but only
000012h is generated). The CPU
reads the contents of AR2 and
AR3 and copies them into T2 and
T3, respectively.
Table 6−7. (#k24) Used For Data-Memory Access
Syntax Example Instruction Example Generated Address Description
Ra = Smem T2 = *(#032002h) k24 = 03 2002h The CPU loads the value at ad-
dress 03 2002h into T2.
Ra = HI(Smem), T2 = HI(#032002h), k24 = 03 2002h The CPU reads the values at ad-
Ra+1 = LO(Smem) ¶ T3 = LO(#032002h) dresses 03 2002h and 03 2003h
(but only 03 2002h is generated)
and copies them into T2 and T3,
respectively.
Table 6−8. (#k24) Used For Memory-Mapped Registers
Ra = Smem T2 = *(#AC0_L) k24 = 00 0008h AC0L represents the address of

the 16 LSBs of AC0 (00 0008h).
The CPU loads the content of
AC0(15–0) into T2.
Ra = HI(Smem), T2 = HI(#AC0_L), k24 = 00 0008h AC0L represents the address of

Ra+1 = LO(Smem) ¶ T3 = LO(#AC0_L) the 16 LSBs of AC0 (00 0008h).
The CPU loads the content of
AC0(15–0) into T2 and the content
of AC0(31–16) into T3.

6.6.2 Addressing Data Memory, MMRs, and C55x+ Registers With Direct
Addressing Modes
You can use direct addressing modes to access data memory, memory-
mapped registers (MMRs), or C55x+ registers in any instruction with one of
these syntax elements:
Note that on the C55x+ DSP, the XDP direct operand @Daddr and the XSP
direct operand *SP(offset) are not CPL bit dependent. Depending on which di-
rect operand is being used, the XSP or XDP registers are used for the address
computation.
6.6.2.1 @Daddr Used For Data-Memory Access

For the XDP direct addressing mode, the assembler calculates Doffset for the
address as follows:
Doffset = (Daddr – .dp) & 7Fh
Where .dp is a value assigned by the .dp assembler directive and & indicates
a bitwise AND operation. For examples of using the .dp directive and the
Doffset calculation, see Section 6.4.1.1. As shown in Table 7−11, when
DP = .dp, Doffset is equal to Daddr (in this case, both are 0005h).
Instruction Generated Address

Syntax Example Example For XDP = 03 0001h = .dp Description
Ra = Smem T2 = @03 0005h XDP Doffset The CPU loads the value at ad-
= 03 0001h + 04h dress 03 0005h into T2.
= 03 0005h
Ra = HI(Smem), T2 = HI(@030005h), XDP + Doffset The CPU reads the values at

Ra+1 = LO(Smem) ¶ T3 = LO(@030005h) = 03 0001h + 04h addresses 03 0005h and
= 03 0005h 03 0004h (but only address
03 0005h is generated) and
loads these values into T2 and
T3, respectively. The second
word is read from the preceding
even address in accordance
with the alignment rule for long
words. §
Note: § For details about the alignment of long words in data memory, see Section 3.3.2.

6.6.2.2 *SP(offset) Used For Data-Memory Access
Generated Address
Syntax Example Instruction Example For XSP = 00FF00h Description
Ra = Smem T2 = *SP(5) XSP + offset The CPU loads the value at ad-
= 00 FF05h dress 00 FF05h into T2.
Ra = HI(Smem), T2 = HI(*SP(5)), XSP + offset The CPU reads the values at ad-
Ra+1 = LO(Smem) ¶ T3 = LO(*SP(5)) = 00 FF05h dresses 00 FF05h and 00 FF04h
(but only address 00 FF05h is gen-
erated) and loads these values into
T2 and T3, respectively. The sec-
ond word is read from the preceding
even address in accordance with
the alignment rule for long words. §
6.6.2.3 @RegisterID Used for C55x+ Registers Accesses
In the C55x+ DSP, you can access all CPU registers with their register ID sym-
bols qualified with mmap(). See Table 2−2 for the list of register ID symbols.
The example below loads the 16-bit LSBs of the AC14 accumulator into the
AR8 register:
AR8 = mmap(@AC14.L)
Ra = Smem AR8 = Register ID access The CPU loads the 16 LSBs of

mmap(@AC14.L) through 6Eh register ID AC14 accumulator into AR8.
address
Ra = HI(Smem), T2 = HI(mmap(@AC14)), Register ID access The CPU loads the 16 LSBs of

Ra+1 = LO(Smem) ¶ T3 = LO(mmap(AC14)) through 0Eh register ID the AC14 accumulators into T3
address and the 16 MSBs of AC14 into
T2.
6.6.2.4 @MMR Used for C55x Registers Accesses
Only the registers existing in the C55x DSP generation can be accessed with
an MMR symbol (see Table 2−2 for the list of MMR symbols).
The MMRs can be accessed through different ways in the C55x+ DSP:
With MMR symbols qualified with mmap().

On C55x DSP generation, registers can be accessed with their MMR sym-
bols qualified with mmap():
T2 = @AC0_L || mmap()

For source code compatibility, the C55x+ assembler accepts the MMR
symbol and encodes it as a register ID.
This operation is performed automatically when the MMR symbol rep-
resents a 16-bit MMR access. In the instruction below, the MMR sym-
bol (AC0_L) is encoded in the exact same form as the register ID sym-
bol (AC0.L).
T2 = @AC0_L || mmap()
This operation is performed for the 32-bit MMR accesses only when
the 32-bit MMR access has a corresponding 32-bit register ID. See
Table 2−2 for the list of these 32-bit register IDs. In the instruction be-
low, the MMR symbol (AC0_H) is encoded as the exact same form as
the register ID symbol (AC0)
AC3 = dbl(@AC0_H) || mmap()
The remaining 32-bit MMR accesses are encoded as a standard C55x
MMR access. The CPU decodes this MMR access with one extra
cycle (AC1 pipeline phase is stalled during one cycle). In the instruc-
tion below, the MMR symbol (AC1_H) is encoded as the standard
C55x MMR symbol (0Ch). The CPU executes this instruction in two
cycles.
AC3 = dbl(@AC1_H) || mmap()
With the XDP direct addressing mode (see Section 6.4.1):

You can access the MMR register without using the mmap() qualifier if the
XDP register is set to 0 (and the .dp assembler directive set to 0). The CPU
decodes the MMR access with one extra cycle (the AC1 pipeline phase
is stalled during one cycle). The example below uses the XDP direct ad-
dressing mode to load the 16-bit LSBs of the AC0 accumulator into the T2
register. The CPU executes the instruction in two cycles.
XDP = #0 ;For run-time, XDP is set to 0
.dp = 0 ;For assembly time, .dp is set to 0
T2 = @AC0_L ;Load T2 with the value at address 03FFF4h
Table 6−9 through Table 6−11 illustrate the different MMR access means.

Table 6−9. @Daddr Used for MMR Access through Register ID
Ra = Smem T2 = @AC0_L || mmap() MMR access through The CPU loads the 16 LSBs of
60h register ID en- the AC0 accumulator into T2.
coded address The assembler encodes the
16-bit MMR symbol AC0_L
with the corresponding regis-
ter ID (AC0.L).
Ra = HI(Smem), T2 = HI(@AC0_H), MMR access through The CPU loads the 16 LSBs of
Ra+1 = LO(Smem) ¶ T3 = LO(@AC0_H) || mmap() 00h register ID en- the AC0 accumulators into T3
coded address and the 16 MSBs of AC0 into
T2. The assembler encodes
the 32-bit MMR symbol
AC0_H with the corresponding
register ID (AC0).
Table 6−10. @Daddr Used For MMR Access through Standard C55x MMR Access
Ra = HI(Smem), T2 = HI(@AC1_H), MMR access through The CPU loads the 8 guard
Ra+1 = LO(Smem) T3 = LO(@AC1_H) || mmap() 0Ch standard MMR bits of the AC1 accumulator
address into T3 and the 16 MSBs of
AC1 into T2. The assembler
cannot encode the 32-bit
MMR symbol AC1_H with a
corresponding register ID.
Table 6−11. @Daddr Used for MMR Access through XDP Direct Addressing Mode
Generated Address
Syntax Example Instruction Example XDP = 0 = .dp Description
Ra = Smem T2 = @AC0_L XDP + Doffset The CPU loads the 16 LSBs of

= 00 0000h + 08h = 08h AC0 accumulator into T2.
Ra = HI(Smem), T2 = HI(@AC0_H), XDP + Doffset The CPU load the 16 LSBs of the
Ra+1 = LO(Smem) ¶ T3 = LO(@AC0_H) = 00 0000h + 09h = 09h AC0 accumulators into T3 and the
16 MSBs of AC0 into T2.

6.6.3 Addressing Data Memory and MMRs With Indirect Addressing Modes
When using the indirect addressing modes to access data memory or
memory-mapped registers (MMRs), it is important to know which operands
you can use for a given instruction. Each instruction syntax that supports the
indirect accesses to data memory includes one of the syntax elements shown
in Table 6−12. The last column of the table shows the indirect operands that
can be used in place of the syntax element(s) of the first column. After you have
found an operand in Table 6−12, you can find details about that operand in the
sections that follow the table. For details about the alignment of long words in
data memory, see Section 3.3.2.
Note:
If an access to the memory-mapped register IER0 (00h MMR address) is
made using an indirect addressing mode, then the CPU generates a bus-er-
ror interrupt (BERRINT) as this is not an allowed operation.
Note:
In word-pointer mode, the 24-bit XARn register references a 23-bit effective
word address. It is the user’s responsibility to ensure that in word-pointer
mode, the 24th bit is set to zero.

Table 6−12. Indirect Operands for Data Memory or MMR Access
Element Syntax Description Available Indirect Operands
Smem Smem indicates one word (16 bits) XAR indirect addressing mode:
dbl(Smem) of data. *ARn
HI(Smem)/LO(Smem) dbl(Smem) and *ARn+
HI(Smem)/LO(Smem) indicate one *ARn−
long word (32 bits) of data. *+ARn
*−ARn
*(ARn + T0/AR0)
*(ARn − T0/AR0)
*ARn(T0/AR0)
*(ARn + Tx) (Tx can be T1, T2, or T3)
*(ARn − Tx)
*ARn(Tx)
*(ARn + T0B/AR0B)
*(ARn − T0B/AR0B)
*ARn(#K16)
*+ARn(#K16)
*ARn(short(#k4))
*ARn(XAR15[23:4])†
Xmem, Ymem Xmem, Ymem indicates one word Dual XAR indirect addressing mode:
dbl(Ymem) (16 bits) of data. *ARn
HI(Cmem)/LO(Cmem) dbl(Ymem) and *ARn+
HI(Cmem)/LO(Cmem) indicate one *ARn−
long word (32 bits) of data. *(ARn + T0/AR0)
*(ARn − T0/AR0)
*ARn(T0/AR0)
*(ARn + T1)
*(ARn − T1)
† It is applicable for the following instructions only:

copy(ALLa = Smem), Smem = ALLa, XDa = mar(Smem).
† It is not allowed to used *ARn(XAR15[23:4]) addressing mode for MMR accesses.

6.6.3.1 *ARn Used For Data-Memory and MMR Access
Operand Description
*ARn Generated address in linear mode: XARn

Generated address in circular mode: (ARnH:BSAyy) + (00:ARn)
XARn is not modified.
Instruction Generate Address

Syntax Example Example (Linear Addressing) Description
Ra = Smem T2 = *AR4 XAR4 The CPU reads the value at address

XAR4 and loads it into T2. XAR4 is not
modified.
Ra = HI(Smem), T2 = HI(*AR4), XAR4 The CPU reads the values at address

Ra+1 = LO(Smem) ¶ T3 = LO(*AR4) XAR4 and the following or preceding ad-
dress (but only the first address is gener-
ated) and loads them into T2 and T3, re-
spectively. XAR4 is not modified. §

6.6.3.2 *ARn+ Used For Data-Memory and MMR Access
Operand Description
*ARn+ Generated address in linear mode: XARn

XARn modification: If 16-bit access: XARn = XARn + 1
If 32-bit access: XARn = XARn + 2

Ra = Smem T2 = *AR4+ XAR4 The CPU reads the value at address XAR4
and loads it into T2. After being used for
the address generation, XAR4 is increm-
ented by 1.
Ra = HI(Smem), T2 = HI(*AR4), XAR4 The CPU reads the values at address

Ra+1 = LO(Smem) ¶ T3 = LO(*AR4) XAR4 and the following or preceding ad-
dress (but only the first address is gener-
ated) and loads them into T2 and T3, re-
spectively. After being used for the address
generation, XAR4 is incremented by 2. §

6.6.3.3 *ARn– Used For Data-Memory and MMR Access
Operand Description
*ARn– Generated address in linear mode: XARn

XARn modification: If 16-bit access: XARn = XARn – 1
If 32-bit access: XARn = XARn – 2
Generated Address
Syntax Example Instruction Example (Linear Addressing) Description
Ra = Smem T2 = *AR4– XAR4 The CPU reads the value at address

XAR4 and loads it into T2. After be-
ing used for the address, XAR4 is
decremented by 1.
Ra = HI(Smem), T2 = HI(*AR4–) XAR4 The CPU reads the values at ad-

Ra+1 = LO(Smem) ¶ T3 = LO(*AR4−) dress XAR4 and the following or
preceding address (but only the first
one is generated) and loads them
into T2 and T3, respectively. After
being used for the addresses, XAR4
is decremented by 2. §

6.6.3.4 *+ARn Used For Data-Memory and MMR Access
Operand Description
*+ARn Generated address in linear mode: If 16-bit access: XARn + 1

If 32-bit access: XARn + 2
Generated address in circular mode: If 16-bit access: (ARnH:BSAyy) + (00:ARn) +1
If 32-bit access: (ARnH:BSAyy) + (00:ARn) + 2
Generated Address
Ra = Smem T2 =*+AR4 XAR4 + 1 Before being used for the address

generation, XAR4 is incremented
by 1. The CPU reads the value at
address XAR4 + 1 and loads it into
T2.
Ra = HI(Smem), T2 = HI(*AR4–), XAR4 + 2 Before being used for the address

Ra+1 = LO(Smem) ¶ T3 = LO(*AR4−) generation, XAR4 is incremented
by 2. The CPU reads the values at
address XAR4 + 2 and the follow-
ing or preceding address (but only
the XAR4 + 2 address is gener-
ated) and loads them into T2 and
T3, respectively. §

6.6.3.5 *–ARn Used For Data-Memory and MMR Access
Operand Description
*−ARn Generated address in linear mode: If 16-bit access: XARn − 1

If 32-bit access: XARn − 2
Generated address in circular mode: If 16-bit access: (ARnH:BSAyy) + (00:ARn) −1
If 32-bit access: (ARnH:BSAyy) + (00:ARn) − 2
XARn modification: If 16-bit access: XARn = XARn − 1
If 32-bit access: XARn = XARn − 2
Generated Address
Ra = Smem T2 = *–AR4 XAR4 – 1 Before being used for the address

generation, XAR4 is decremented
address XAR4 – 1 and loads it into
T2.
ALLa = dbl(Smem) copy(XAR9 = dbl(*–AR4)) XAR4 – 2 Before being used for the address
by 2. The CPU reads the values at
address XAR4 – 2 and the follow-
ing or preceding address (but only
the XAR4 − 2 address is gener-
ated) and loads them into XAR9. §

6.6.3.6 *(ARn + T0/AR0) Used For Data-Memory and MMR Access
C54CM = 0 (and .c54cm_off assembler directive) C54CM = 1 (and .c54cm_on assembler directive)
Operand Description Operand Description
*(ARn + T0) Generated address in linear *(ARn + AR0) Generated address in linear
mode: XARn mode: XARn
Generated address in circular Generated address in circular
mode: mode:
(ARnH:BSAyy) + (00:ARn) (ARnH:BSAyy) + (00:ARn)
XARn modification: XARn modification:
XARn = XARn + T0 XARn = XARn + AR0
T0 is a 16-bit signed value. AR0 is a 16-bit signed value.
Generated Address
Ra = Smem T2 = *(AR4 + T0) XAR4 The CPU reads the value at

address XAR4 and loads it
into T2. After being used for
the address generation, XAR4
is incremented by the number
in T0.
ALLa = dbl(Smem) copy(AR9 = dbl(*(AR4 + T0))) XAR4 The CPU reads the values at
address XAR4 and the follow-
ing or preceding address (but
only the XAR4 address is gen-
erated) and loads them into
XAR9. After being used for the
address generation, XAR4 is
decremented by the number in
T0. §

6.6.3.7 *(ARn – T0/AR0) Used For Data-Memory and MMR Access
*(ARn – T0) Generated address in linear mode: *(ARn – AR0) Generated address in linear mode:
XARn XARn
Generated address in circular mode: Generated address in circular mode:
XARn = XARn − T0 XARn = XARn − AR0
Generated Address
Ra = Smem T2 = *(AR4 – T0) XAR4 The CPU reads the value at

address XAR4 and loads it
into T2. After being used for
is decremented by the number
in T0.
ALLa = dbl(Smem) copy(XAR9 = dbl(*(AR4 – T0))) XAR4 The CPU reads the values at
address XAR4 and the follow-
ing or preceding address (but
only the XAR4 address is gen-
erated) and loads them into
AR9. After being used for the
T0. §

6.6.3.8 *ARn(T0/AR0) Used For Data-Memory and MMR Access
*ARn(T0) Generated address in linear mode: *ARn(AR0) Generated address in linear mode:
XARn + T0 XARn + AR0
(ARnH:BSAyy) + (00:ARn) + T0 (ARnH:BSAyy) + (00:ARn) + AR0
XARn is not modified. XARn is used as XARn is not modified. XARn is used as
a base pointer. T0 is a 16-bit signed val- a base pointer. AR0 is a 16-bit signed
ue added to the base pointer. value added to the base pointer.
Generated Address
Ra = Smem T2 = *AR4(T0) XAR4 + T0 The CPU reads the value at ad-

dress XAR4 + T0 and loads it
into T2. XAR4 is not modified.
ALLa = dbl(Smem) copy(XAR9 = dbl(*AR4(T0))) XAR4 + T0 The CPU reads the values at
address XAR4 + T0 and the fol-
lowing or preceding address (but
only the XAR4+ T0 address is
generated) and loads them into
XAR9. XAR4 is not modified. §

6.6.3.9 *(ARn + Tx), (Tx = T1, T2, or T3) Used For Data-Memory and MMR Access
Operand Description
*(ARn + Tx) Generated address in linear mode: XARn

XARn modification: XARn = XARn + Tx
Tx is a 16-bit signed value. Tx can be T1, T2, or T3.
Generated Address
Ra = Smem AR3 = *(AR7 + T1) XAR7 The CPU reads the value at ad-
dress XAR7 and loads it into AR3.
After being used for the address
generation, XAR7 is incremented
by the number in T1.
Ra = HI(Smem), AR2 = HI(*(AR5 + T2)), XAR5 The CPU reads the values at ad-
Ra+1 = LO(Smem) ¶ AR3 = LO(*(AR5 + T2)) dress XAR5 and the following or
preceding address (but only the
XAR5 address is generated) and
loads them into AR2 and AR3, re-
spectively. After being used for the
address generation, XAR5 is in-
cremented by the number in T2. §

6.6.3.10 *(ARn – Tx), (Tx= T1, T2. or T3) Used For Data-Memory and MMR Access
Operand Description
*(ARn – Tx) Generated address in linear mode: XARn

XARn modification: XARn = XARn − Tx
Generated Address
Ra = Smem AR3 = *(AR7 – T1) XAR7 The CPU reads the value at ad-
dress XAR7 and loads it into AR3.
Ra = HI(Smem), AR2 = HI(*(AR5 – T3)), XAR5 The CPU reads the values at ad-
Ra+1 = LO(Smem) ¶ AR3 = LO(*(AR5 − T3)) dress XAR5 and the following or
XAR5 address is generated) and
loads them into XAR2 and XAR3,
respectively. After being used for
the address generation, XAR5 is
T3. §

6.6.3.11 *ARn(Tx), (Tx= T1, T2, or T3) Used For Data-Memory and MMR Access
Operand Description
*ARn(Tx) Generated address in linear mode: XARn + Tx

Generated address in circular mode: (ARnH:BSAyy) + (00:ARn) + Tx
XARn is not modified. XARn is used as a base pointer.
Tx is a 16-bit signed value added to the base pointer. Tx can be T1, T2, or T3.
Generated Address
Ra = Smem AR3 = *AR7(T2) XAR7 + T2 The CPU reads the value at address
XAR7 + T2 and loads it into AR3.
XAR7 is not modified.
Ra = HI(Smem), AR2 = HI(*AR5(T1)), XAR5 + T1 The CPU reads the values at address
Ra+1 = LO(Smem) ¶ AR3 = LO(*AR5(T1) XAR5 + T1 and the following or pre-
ceding address (but only the XAR5 +
T1 address is generated) and loads
them into AR2 and AR3, respectively.
XAR5 is not modified.§

6.6.3.12 *(ARn + T0B/AR0B) Used For Data-Memory and MMR Access
*(ARn + T0B) Generated address in linear mode: *(ARn + AR0B) Generated address in linear mode:
XARn XARn
XARn modification: XAR modification:
(performed with reverse carry (performed with reverse carry
propagation) propagation)
Note: This addressing mode can be used for FFT buffer elements addressing. When this bit reverse operand is used, XARn can
be configured in the ST2_55 register for circular addressing; this removes alignment constraints on the FFT buffer start
address (see Section 6.9 for more details on BSAxx addition computation). However in this case, XARn is not impacted
by circular addressing computation.
Generated Address
Syntax Example Example Instruction (Linear Addressing) Description
Ra = Smem T2 = *(AR4 + T0B) XAR4 The CPU reads the value at address
XAR4 and loads it into T2. After being
used for the address generation, XAR4
is incremented by the number in T0.
Reverse carry propagation is used dur-
ing the addition.
Ra = HI(Smem), T2 = HI (*(AR4 + T0B)) XAR4 The CPU reads the values at address
Ra+1 = LO(Smem) ¶ T3 = LO(*(AR4 + T0B)) XAR4 and the following or preceding
address (but only the XAR4 address is
generated) and loads them into T2 and
T3, respectively. After being used for
the address generation, XAR4 is in-
cremented by the number in T0 with re-
verse carry propagation. §

6.6.3.13 *(ARn – T0B/AR0B) Used For Data-Memory and MMR Access
C54CM = 0 (and .c54cm_off assembler directive) C54CM = 1 (and .c54cm_off assembler directive)
*(ARn – T0B) Generated address in linear mode: *(ARn – AR0B) Generated address in linear mode:
XARn XARn
(performed with reverse carry (performed with reverse carry
propagation) propagation)
by circular addressing computation.
Generated Address
Ra = Smem T2 = *(AR10 – T0B) XAR10 The CPU loads the value at ad-
dress XAR10 into T2. After being
used for the address generation,
XAR10 is decremented by the
number in T0. Reverse carry
propagation is used during the
subtraction.
Ra = HI(Smem), T2 = HI(*(AR10 + T0B)), XAR10 The CPU reads the values at ad-
Ra+1 = LO(Smem) T3 = LO(*(AR10 + T0B)) dress XAR10 and the following or
XAR10 address is generated)
and loads them into T2 and T3,
respectively. After being used for
decremented by the number in T0
with reverse carry propagation. §

6.6.3.14 *ARn(#K16) Used For Data-Memory and MMR Access
Operand Description
*ARn(#K16) Generated address in linear mode: XARn + K16

Generated address in circular mode: (ARnH:BSAyy) + (00:ARn) + K16
XARn is not modified. XARn is used as a base pointer. The 16-bit signed
constant (K16) is 24-bit sign extended and is used as an offset from that base
pointer.
Note: When an instruction uses this operand, the constant, K16, is encoded in a 2-byte extension to the instruction.
Generated Address
Ra = Smem AR3 = *AR12(#8) XAR12 + 8 The CPU reads the value at address
XAR12 + 8 and loads it into AR3.
ALLa = dbl(Smem) copy(XAR2 = XAR5 + 20 The CPU reads the values at address
dbl(*AR5(#20))) XAR5 + 20 and the following or preced-
ing address (but only the XAR5 + 20
address is generated) and loads them
into AR2. XAR5 is not modified. §

6.6.3.15 *+ARn(#K16) Used For Data-Memory and MMR Access
Operand Description
*+ARn(#K16) Generated address in linear mode: XARn + K16

Generated address in circular mode: (ARnH:BSAyy) + (00:ARn) + K16
XARn modification: XARn = XARn + K16
Generated Address
Ra = Smem AR3 = *+AR7(#8) XAR7 + 8 Before XAR7 is used for the address
generation, the constant is added to
XAR7. The CPU reads the value at ad-
dress XAR7 + 8 and loads it into AR3.
ALLa = dbl(Smem) copy (XAR2 = XAR5 + 20 Before XAR5 is used for the address
dbl(*+AR5(#20))) generation, the constant is added to
XAR5. The CPU reads the values at
address XAR5 + 20 and the following or
XAR5 + 20 address is generated) and
loads them into XAR2. §

6.6.3.16 *ARn(short(#k4)) Used For MMRs and Data-Memory Access
Operand Description
*ARn(short(#k4)) Generated address in linear mode: XARn + k4

Generated address in circular mode: (ARnH:BSAyy) + (00:ARn) + k4
XARn is not modified. XARn is used as a base pointer. The 4-bit unsigned
constant (k4) is zero extended to 24 bits and is used as an offset from that base
pointer. k4 can be a number from 0 to 15.
Generated Address
Ra = Smem AR3 = *AR7(short(#1)) XAR7 + 1 The CPU reads the value at address
XAR7 + 1 and loads it into AR3. XAR7
is not modified.
ALLa = dbl(Smem) copy(XAR2 = XAR5 + 8 The CPU reads the values at address
dbl(*AR5(short(#8)))) XAR5 + 8 and the following or preced-
ing address (but only the XAR5 + 8
address is generated) and loads them
into XAR2−. XAR5 is not modified. §
6.6.3.17 *ARn(XAR15[23:4]) Used For Data-Memory Access Only
Operand Description
*ARn(XAR15[23:4]) Generated address in linear mode: XARn + XAR15[23:4]

Generated address in circular mode: (ARnH:BSAyy) + (00:ARn) + XAR15[23:4]
XARn is not modified. XARn is used as a base pointer. XAR15 has to be a positive
value for this addressing mode. The 20 bits from bit 4 to bit 23 of the XAR15 register is
24-bit zero extended and is used as an unsigned offset from that base pointer. This
offset addressing mode supports the C55x+ field insert/extract instructions. This oper-
and can be used only with 16-bit load/store/mar() instructions. It cannot be used with
any other instructions.
It cannot be used for MMR accesses.
Syntax Generated Address

Example Instruction Example (Linear Addressing) Description
Ra = Smem AC0_L = *AR1(XAR15[23:4]) XAR1 + XAR15[23:4] The CPU reads the value at address
XAR1 + 4 and loads it into AC0.L.
Assume XAR15 = 42,
then XAR15[23:4] = 4

Restrictions on MMRs and C55x+ Register Addressing
6.7 Restrictions on MMRs and C55x+ Register Addressing

In the following instructions, Smem cannot reference a memory-mapped reg-
ister (MMR) with absolute addressing modes, direct addressing modes, or in-
direct addressing modes. Similarly, the following instructions cannot be used
with the mmap() qualifier to perform MMR direct addressing mode or register
ID direct addressing mode. When detecting such occurrences during code ex-
ecution, the DSP sends a hardware bus-error interrupt (BERRINT) request to
the CPU.
Syntax in which Smem cannot re-

ference an MMR or a register ID Comment
Ra = uns(high_byte(Smem)) Ra can be: (full or low/high parts) of an ac-

cumulator, an auxiliary, or a temporary reg-
Ra = uns(low_byte(Smem)) ister.
ACa = high_byte(Smem) << S6
ACa = low_byte(Smem) << S6
high_byte(Smem) = Ra
low_byte(Smem) = Ra
In the following instructions, a memory-mapped register (MMR) location can-

not be referenced; otherwise, the DSP sends a hardware bus-error interrupt
(BERRINT) request to the CPU.
Syntax which cannot

be an MMR Reference Note
call When executing these instructions,

XSP, XSSP registers cannot point to the
return
MMR area (00h−5Fh)
intr
trap
push
pop
error, and of any instruction executed in parallel, cannot be assured.
Note:
No MMR access is allowed when the CPU is in byte-pointer mode. See Sec-
tion 7.7 for more details.

Addressing Register Bits
6.8 Addressing Register Bits

Direct addressing (see Section 6.8.1) and indirect addressing (see Sec-
tion 6.8.2) can address the individual register bits or pairs of register bits. None
of the absolute addressing modes support accesses to the register bits.
6.8.1 Addressing Register Bits With the Register-Bit Direct Addressing Mode
You can use the register-bit direct operand, @bit_position, to access a register
bit if an instruction has the following syntax element:
Baddr Indicates the address of one bit of data. Only the register bit
test/set/clear/complement and bit field insert/extract instructions
support Baddr, and these instructions enable you to access bits in
the accumulators (AC0–AC15), the auxiliary registers
(AR0–AR15), and the temporary registers (T0–T3).
Note:
Unlike the direct operands (@Daddr) and *SP(offset)) used to access data
memory with Smem, dbl(Smem), and HI(Smem)/LO(Smem) syntax ele-
ments, the register-bit direct operand, @bit_position, does not use the XSP
and XDP registers for address computation. The register-bit direct operand,
@bit_position, indicates directly the address of one bit of data to access.
Note:
the register-bit direct address to wrap around, do not make use of this behav-
ior. It is not supported.
Table 6−13 provides examples of using @bit_position to access register bits.
Table 6−13. @bit_position Used For Register Bit Access
Generated
Syntax Example Instruction Example Bit Address Description
bit(Ra, Baddr) = #1 bit(AC3, @0) = #1 0 The CPU sets bit 0 of AC3.
TC1, TC2 = bit(Ra, Baddr)¶ TC1, TC2 = bit(AC3, @30) 30 The CPU tests bits 30 and 31 of
AC3. It copies the content of
AC0(30) into the TC1 bit of status
register ST0_55 and the content of
AC0(31) into the TC2 bit of
ST0_55.
Note: ¶ In instructions using the Baddr and (Baddr+1) operands, Baddr must refer to two consecutive bits.

6.8.2 Addressing Register Bits With Indirect Addressing Modes

You can use indirect operands to access register bits if an instruction has the
following syntax element:
Baddr Indicates the address of one bit of data. Only the register bit
test/set/clear/complement and bit field extract/insert instructions
support Baddr, and these instructions enable you to access bits in
the accumulators (AC0–AC15), the auxiliary registers
(AR0–AR15), and the temporary registers (T0–T3).
You must first make sure the pointer contains the correct bit number. Note that:
The computed bit position is truncated to the 4 LSBs, in case of bit manipu-
lation using the A unit. In the following example, you want to clear bit 15
of the T3 register with an indirect addressing mode using the XAR6 regis-
ter.
AR6 = #Fh
bit(T3, *AR6) = #0
The computed bit position is truncated to the 6 LSBs, in case of bit manipu-
lation using the D unit. In the following example, you want to toggle bit 32
of the AC9 register with an indirect addressing mode using the XAR5 reg-
ister.
AR5 = #20h
cbit(AC9, *AR5)
Table 6−14 lists the indirect operands that support accesses of register bits,
and the sections following the table provide details and examples for the oper-
ands.
Note:
the register-bit indirect address to wrap around, do not make use of this be-
havior. It is not supported.

Table 6−14. Indirect Operands For a Register-Bit Access
Baddr Baddr indicates the address of one XAR indirect addressing mode:
bit of data *ARn
*ARn+
*ARn−
*+ARn
*−ARn
*(ARn + T0/AR0)
*(ARn − T0/AR0)
*ARn(T0/AR0)
*(ARn − Tx)
*ARn(Tx)
*ARn(#K16)
*+ARn(#K16)
*ARn(short(#k4))
6.8.2.1 *ARn Used For Register-Bit Access
Operand Description
*ARn Generated bit address in linear mode: XARn

Generated bit address in circular mode: (ARnH:BSAyy) + (00:ARn)
Generated Bit
Address
bit(Ra, Baddr) = #1 bit(AC10, *AR12) = #1 XAR12 The CPU sets bit 0 of AC10.
Assume XAR12 = 0 XAR12 is not modified.
TC1, TC2 = bit(Ra, TC1, TC2 = bit(AC3, XAR5 The CPU tests bits 30 and 31 of
Baddr) *AR5) Assume XAR5 = 30 AC3. It copies the content of
AC3(31) into the TC2 bit of ST0_55.
AR5 is not modified.

6.8.2.2 *ARn+ Used For Register-Bit Access
Operand Description
*ARn+ Generated bit address in linear mode: XARn

Generated Bit
Address
bit(Ra, Baddr) = #1 bit(AC3, *AR2+) = #1 XAR2 The CPU sets bit 0 of AC3. After be-
Assume XAR2 = 0 ing used for the address generation.
XAR2 is incremented by 1.
TC1, TC2 = bit(Ra, TC1, TC2 = bit(AC9, XAR5 The CPU tests bits 30 and 31 of AC9.
Baddr) *AR5) Assume XAR5 = 30 It copies the content of AC9(30) into
the TC1 bit of status register ST0_55
and the content of AC9(31) into the
TC2 bit of ST0_55. After being used
for the addressgeneration, XAR5 is
incremented by 2.

6.8.2.3 *ARn– Used For Register-Bit Access
Operand Description
*ARn– Generated bit address in linear mode: XARn

XARn modification: If 1-bit access: XARn = XARn – 1
If 2-bit access: XARn = XARn – 2
Generated Bit
Address
bit(Ra, Baddr) = #1 bit(AC3, *AR2–) = #1 XAR2 The CPU sets bit 0 of AC3. After be-
Assume XAR2 = 0 ing used for the address generation,
XAR2 is decremented by 1.
TC1, TC2 = bit(Ra, TC1, TC2= bit(AC3, XAR5 The CPU tests bits 30 and 31 of
Baddr) *AR5−) Assume XAR5 = 30 AC3. It copies the content of
by 2.

6.8.2.4 *+ARn Used For Register-Bit Access
Operand Description
*+ARn Generated bit address in linear mode: If 1-bit access: XARn + 1

Generated bit address in circular mode: If 1-bit access: (ARnH:BSAyy) + (00:ARn) + 1
XARn modified: If 1-bit access: XARn = XARn + 1
Generated Bit
Address
bit(Ra, Baddr) = bit(AC4, *+AR2) = #1 (XAR2 + 1) Before being used for the address
#1 Assume (XAR2 + 1) = 1 generation, XAR2 is incremented by
1. The CPU sets bit 1 of AC4.
TC1, TC2 = bit(Ra, TC1, TC2= bit(AC3, (XAR5 + 2) Before being used for the address
Baddr) *+AR5) Assume (XAR5 + 2) = 30 generation, XAR5 is incremented by
2. The CPU tests bits 30 and 31 of
AC3. It copies the content of

6.8.2.5 *–ARn Used For Register-Bit Access
Operand Description
*–ARn Generated bit address in linear mode: If 1-bit access: XARn − 1

Generated bit address in circular mode: If 1-bit access: (ARnH:BSAyy) + (00:ARn) − 1
XARn modified: If 1-bit access: XARn = XARn − 1
Generated Bit
Address
bit(Ra, Baddr) = #1 bit(AC14, *–AR2) = #1 (XAR2 – 1) Before being used for the ad-
Assume (XAR2 – 1) = 1 dress generation, XAR2 is de-
cremented by 1. The CPU sets
bit 1 of AC14.
TC1, TC2 = bit(Ra, TC1, TC2 = bit(AC5, (XAR5 – 2) Before being used for the ad-
Baddr) *–AR5) Assume (XAR5 – 2) = 30 dress generation, XAR5 is de-
cremented by 2. The CPU tests
bits 30 and 31 of AC5. It copies
the content of AC5(30) into the
TC1 bit of status register ST0_55
and the content of AC5(31) into
the TC2 bit of ST0_55.

6.8.2.6 *(ARn + T0/AR0) Used For Register-Bit Access
*(ARn + T0) Generated bit address in linear *(ARn + AR0) Generated bit address in linear
Generated bit address in circular Generated bit address in circular
mode: (ARnH:BSAyy) + (00:ARn) mode: (ARnH:BSAyy) + (00:ARn)
Generated Bit
Address
bit(Ra, Baddr) = #1 bit(AC3, *(AR2 + T0)) = #1 XAR2 The CPU sets bit 0 of AC3. Af-
Assume XAR2 = 0 ter being used for the address
generation, XAR2 is increm-
ented by the number in T0.
TC1, TC2 = bit(Ra, TC1, TC2= bit(AC3, *(AR5 XAR5 The CPU tests bits 30 and 31 of
Baddr) + T0)) Assume XAR5 = 30 AC3. It copies the content of
AC3(30) into the TC1 bit of sta-
tus register ST0_55 and the
content of AC3(31) into the TC2
bit of ST0_55. After being used
for the address generation,
XAR5 is incremented by the
number in T0.

6.8.2.7 *(ARn – T0/AR0) Used For Register-Bit Access
*(ARn – T0) Generated bit address in linear *(ARn – AR0) Generated bit address in linear
Generated bit address in circular Generated bit address in circular
mode: (ARnH:BSAyy) + (00:ARn) mode: (ARnH:BSAyy) + (00:ARn)
Generated Bit
Address
bit(Ra, Baddr) = #1 bit(AC3, *(AR2 – T0)) = #1 XAR2 The CPU sets bit 0 of AC3. After
Assume XAR2 = 0 being used for the address gener-
ation, XAR2 is decremented by
the number in T0.
Baddr) *(AR5 – T0) Assume XAR5 = 30 AC3. It copies the content of
register ST0_55 and the content
of AC3(31) into the TC2 bit of
ST0_55. After being used for the
address generation, XAR5 is de-
cremented by the number in T0.

6.8.2.8 *ARn(T0/AR0) Used For Register-Bit Access
*ARn(T0) Generated bit address in linear mode: *ARn(AR0) Generated bit address in linear mode:
XARn + T0 XARn + AR0
Generated bit address in circular mode: Generated bit address in circular mode:
a base pointer. T0 is a 16-bit signed a base pointer. AR0 is a 16-bit signed
value added to the base pointer. value added to the base pointer.
Generated Bit
Address
bit(Ra, Baddr) = #1 bit(AC6, *AR2(T0)) = #1 XAR2 + T0 The CPU sets bit 15 of AC6. XAR2
Assume XAR2 = 0 is not modified.
and T0 = 15
TC1, TC2 = bit(Ra, TC1, TC2 = bit(AC7, XAR5 + T0 The CPU tests bits 30 and 31 of
Baddr) *AR5(T0)) Assume XAR5 = 25 AC7. It copies the content of
and T0 = 5 AC7(30) into the TC1 bit of status

6.8.2.9 *(ARn + Tx), (Tx = T1, T2, or T3) Used For Register-Bit Access
Operand Description
*(ARn + Tx) Generated bit address in linear mode: XARn

Generated Bit
Address
bit(Ra, Baddr) = #0 bit(AC2, *(AR14 + T1)) = #0 XAR14 The CPU clears bit 0 of AC2. Af-
Assume XAR14 = 0 ter being used for the address
generation, XAR14 is increm-
Baddr) *(AR10 + T3)) Assume XAR10 = 30 AC2. It copies the content of
number in T3.

6.8.2.10 *(ARn – Tx), (Tx = T1, T2, or T3) Used For Register-Bit Access
Operand Description
*(ARn – Tx) Generated bit address in linear mode: XARn
Generated Bit
Address
bit(Ra, Baddr) = #0 bit(AC11, *(AR4 – T3)) = #0 XAR4 The CPU clears bit 0 of AC11.
Assume XAR4 = 0 After being used for the address
generation, XAR4 is decrem-
Baddr) *(AR11 – T2)) Assume XAR11 = 30 AC2. It copies the content of
number in T2.

6.8.2.11 *ARn(Tx), (Tx = T1, T2, or T3) Used For Register-Bit Access
Operand Description
*ARn(Tx) Generated bit address in linear mode: XARn + Tx

Generated bit address in circular mode: (ARnH:BSAyy) + (00:ARn) + Tx
XARn is not modified. XARn is used as a base pointer. Tx is a 16-bit signed val-
ue added to the base pointer. Tx can be T1, T2, or T3.
Generated Bit
Address
bit(Ra, Baddr) = #0 bit(AC2, *AR4(T3)) = #0 XAR4 + T3 The CPU clears bit 15 of

Assume XAR4 = 0 AC2. XAR4 is not modified.
and T3 = 15
TC1, TC2 = bit(Ra, TC1, TC2 = bit(AC2, *AR1(T3)) XAR1 + T3 The CPU tests bits 30 and
Baddr) Assume XAR1 = 25 31 of AC2. It copies the con-
and T3 = 5 tent of AC2(30) into the TC1
bit of status register ST0_55
and the content of AC2(31)
into the TC2 bit of ST0_55.

6.8.2.12 *ARn(#K16) Used For Register-Bit Access
Operand Description
*ARn(#K16) Generated bit address in linear mode: XARn + K16

XARn is not modified. XARn is used as a base pointer. The 16-bit signed
constant (K16) is sign extended to 24-bits and is used as an offset from that base
pointer.
Generated Bit
Address
bit(Ra, Baddr) = #0 bit(AC2, *AR4(#31)) = #0 (XAR4 + 31) The CPU clears bit 31 of AC2.
TC1, TC2 = bit(Ra, TC1, TC2 = bit(AC2, (XAR1 + 5) The CPU tests bits 21 and 22 of
Baddr) *AR1(#5)) Assume XAR1 = 16 AC2. It copies the content of
AC2(22) into the TC2 bit of
ST0_55. XAR1 is not modified.
Note: ¶ In instructions using the Baddr and (Baddr+1) operands, Baddr must refer to two consecutive bits.

6.8.2.13 *+ARn(#K16) Used For Register-Bit Access
Operand Description
*+ARn(#K16) Generated bit address in linear mode: XARn + K16

Generated bit address in circular mode: (ARnH:BSAyy) + (00:ARn) + K16
Generated Bit
Address
bit(Ra, Baddr) = #0 bit(AC2, +AR4(#31)) = #0 (XAR4 + 31) Before AR4 is used for the ad-
Assume XAR4 = 0 dress generation, the constant is
added to XAR4. The CPU clears
bit 31 of AC2.
TC1, TC2 = bit(Ra, TC1, TC2 = bit(AC2, (XAR1 + 5) Before AR1 is used for the ad-
Baddr) *+AR1(#5)), Assume XAR1 = 16 dress generation, the constant is
added to XAR1. The CPU tests
bits 21 and 22 of AC2. It copies
the content of AC2(21) into the
TC1 bit of status register ST0_55
and the content of AC2(22) into
the TC2 bit of ST0_55.

6.8.2.14 *ARn(short(#k4)) Used For Register-Bit Access
Operand Description
*ARn(short(#k4)) Generated bit address in linear mode: XARn + k4

Generated bit address in circular mode: (ARnH:BSAyy) + (00:ARn) + k4
Generated Bit
Address
bit(Ra, Baddr) = #0 bit(AC2, *AR4(short(#4))) = #0 (XAR4 + 4) The CPU clears bit 4 of AC2.
TC1, TC2 = bit(Ra, TC1, TC2= bit(AC2, (XAR1 + 5) The CPU tests bits 21 and 22
Baddr) *AR1(short(#5)) Assume XAR1 = 16 of AC2. It copies the content
of AC2(21) into the TC1 bit of
status register ST0_55 and
the content of AC2(22) into
the TC2 bit of ST0_55. XAR1
is not modified.

I/O − xI/O Addressing Modes
6.9 I/O − xI/O Addressing Modes

To access I/O space, the C55x+ revision features the regular I/O addressing
modes (see Section 3.4 for I/O space description). To access strongly ordered
memory areas, the C55x+ revision features the xI/O addressing modes (see
Section 3.3.4 for xI/O memory access description).
All xI/O addressing modes use the volatile() qualifier to differentiate them
from the regular I/O addressing modes which use port() qualifier. Using
port() or volatile() qualifier with an instruction adds one byte extension to
the instruction.
The regular I/O addressing modes are available in C55x+ DSP for source
code compatibility with C55x DSP generations.
Absolute, direct, and indirect addressing modes (described in Sections
6.3, 6.4, and 6.5, respectively) are also available to access I/O and xI/O
spaces. The following sections describe these addressing modes.
There are some restrictions/exceptions on accesses to I/O and xI/O
spaces. See Section 6.11 for more details.
6.9.1 I/O − xI/O Absolute Addressing Modes

6.9.1.1 k16 Absolute I/O Addressing Mode
The assembler syntax of the k16 absolute I/O addressing mode is *port(#k16),
where k16 is a 16-bit unsigned constant.
As compared to the PDP direct I/O addressing mode described in Section
6.8.2.1, the k16 I/O absolute addressing mode brings more flexibility by the
ability to address the 65536-word long I/O space.
Figure 6−7 shows how k16 is used to address I/O space. When an instruction
uses this addressing mode, the constant is encoded in a 2-byte extension to
the instruction.
Figure 6−7. I/O Absolute Addressing Mode

k16 I/O space (64KWords)
0000 0000. 0000 0000
. 0000h−FFFFh
.
1111 1111 1111 1111
6.9.1.2 k16 Absolute xI/O Addressing Mode

The assembler syntax of the k16 absolute xI/O addressing mode is vola-
tile(*abs16(#k16)) where k16 is an unsigned constant. The CPU concatenates
bits [23−16] of the XDP register to k16 to form the 24-bit xI/O address.

Similarly to the k16 absolute addressing mode for data space (see Section
6.3.1), although the generated address can be 24 bits wide in word-pointer
mode, only the 23 LSBs generate a 23-bit effective word address.
When an instruction uses this addressing mode, the constant is encoded in a

2-byte extension to the instruction.
As compared to the XDP direct xI/O addressing mode described in Section

6.9.2.2, the k16 xI/O absolute addressing mode brings more flexibility by the
ability to address the 65536-word long main data page pointed by DPH.
6.9.1.3 k24 Absolute xI/O Addressing Mode
The assembler syntax of the k24 absolute xI/O addressing mode is vola-
tile(*(#k24)), where k24 is an unsigned constant.
Similarly to the k24 absolute addressing mode for data space (see Section
6.3.2), although the generated address can be 24 bits wide in word-pointer
mode, only the 23 LSBs generate a 23-bit effective word address.

6.9.2 Direct I/O − xI/O Addressing Modes
6.9.2.1 PDP Direct I/O Addressing Mode
The assembler syntax of the PDP direct I/O addressing mode is port(@#k7).
This addressing mode uses the 9-bit peripheral data page register (PDP) con-
catenated with the 7-bit instruction-defined constant k7 to form a 16-bit I/O ad-
dress (see Figure 6−8).
To address elements stored in one of the 128-word peripheral page, PDP di-
rect I/O addressing mode is more efficient than the k16 absolute I/O address-
ing mode described in Section 6.9.1.1, because of the 2-byte extension to the
instruction which is not needed.
Note:
PDP direct addressing mode cannot be not used for xI/O addressing modes.
It cannot be used when the CPU is in byte-pointer mode.

Figure 6−8. PDP Direct Addressing Mode

PDP Offset I/O Space (64 Kwords)
0000. 0000 0 000. 0000
. . Peripheral page 0: 0000h−007Fh
. .
0000 0000 0 111 1111
0000 0000 1 000 0000
. .
. . Peripheral page 1: 0080h−00FFh
. .
0000 0000 1 111 1111
0000. 0001 0 000. 0000
. . Peripheral page 2: 0100h−017Fh
. .
0000 0001 0 111 1111
. . . .
. . . .
. . . .
. . . .
. . . .
. . . .
1111 1111 1 000 0000

. .
. . Peripheral page 511: FF80h−FFFFh
. .
1111 1111 1 111 1111
6.9.2.2 XDP Direct xI/O Addressing Mode
The assembler syntax for the XDP direct xI/O addressing mode is vola-
tile(@Daddr)). To form a 24-bit xI/O address, the CPU adds the XDP 24-bit
register and the 7-bit instruction defined constant Daddr. The computation pro-
cess of the XDP direct xI/O address is the same as the one described for the
XDP addressing mode, in Section 6.4.1.
To address elements stored in one of the 128-word local data pages, the XDP
direct xI/O addressing mode is more efficient than the two absolute xI/O ad-
dressing modes (k16 or k24) described in Section 6.10.2, because it does not
require any byte extension to the instruction.

6.9.3 XAR Indirect I/O − xI/O Addressing Modes
6.9.3.1 XAR Indirect I/O Addressing Mode
To access I/O space with the XAR indirect addressing mode, you can use an
XAR indirect operand with port() qualifier. See Table 6−20 for more details on
the XAR indirect operands that can be used for I/O space addressing.
In word-pointer mode, when the XAR indirect addressing mode accesses I/O
space, only the 16 LSBs of the selected auxiliary register XARn are used for
the I/O address.
Figure 6−9. Accessing I/O Space With the XAR Indirect Addressing Mode
XARn I/O Space (64 Kwords)
0000 0000 0000 0000. 0000 0000

. 0000h−FFFFh
.
0000 0000 1111 1111 1111 1111
Note:
Although an increment past 00 FFFFh or a decrement past 00 0000h causes
the XAR indirect I/O address to wrap around, do not make use of this behav-
ior. It is not supported. Also during circular addressing, the BSAxx addition
must not increment the address beyond 00 FFFFh (see Section 6.12 for
more details on circular addressing).
6.9.3.2 XAR Indirect xI/O Addressing Mode
To access strongly ordered data memory areas (xI/O space) with the XAR indi-
rect addressing mode, you can use an XAR indirect operand with the volatile()
qualifier. See Table 6−21 for more details on the XAR indirect operands that
can be used for xI/O space addressing.
In word-pointer mode, when the XAR indirect addressing mode accesses xI/O
space, only the 23 LSBs of the selected auxiliary register XARn are used for
the xI/O address.
Note:
the indirect address to wrap around, do not make use of this behavior; it is
on circular addressing).

Addressing I/O and xI/O Spaces
6.10 Addressing I/O and xI/O Spaces

Absolute addressing modes (described in Section 6.9.1), direct addressing
modes (described in Section 6.9.2), and indirect addressing modes (described
in Section 6.9.3) can address the peripheral registers in I/O and xI/O spaces.
The following sections provide some examples for the I/O − xI/O addressing
modes.
There are some restrictions/exceptions on accesses to the I/O and xI/O

6.10.1 Addressing I/O Space with the I/O Absolute Addressing Mode
In word-pointer mode, to access I/O space with k16 absolute I/O addressing
mode, you can use *port(#k16) in instructions using the following syntax ele-
ment:
Table 6−15 provides examples of I/O space accesses with the k16 absolute
I/O addressing mode.
Table 6−15. k16 Absolute Addressing Mode Used For I/O Space Access
Ra = Smem AR2 = *port(#0003) k16 = 0003h The CPU loads the value at I/O address
0003h into AR2.
Smem = ALLa *port(#F002h) = AR0 k16 = F002h The CPU stores the content of AR0 into
I/O address F002h.
6.10.2 Addressing xI/O Space with xI/O Absolute Addressing Modes

In word-pointer mode, to access xI/O space with the k16 (or k24) absolute xI/O
addressing mode, you can use volatile(*abs16(#k16)) or volatile(*(#k24)) in in-
structions using the following syntax elements:
Table 6−16 and Table 6−17 provide some examples of the xI/O space ac-
cesses with k16 and k24 absolute xI/O addressing modes.

Table 6−16. k16 Absolute Addressing Mode Used For xI/O Space Access
Ra = Smem AR2 = volatile(*abs16(#0003)) Assume DPH = 01h The CPU loads the value at xI/O
k16 = 0003h address 01 0003h into AR2.
Smem = ALLa volatile(*abs16(#F002h)) = Assume DPH = 01h The CPU stores the content of
AR0 k16 = F002h AR0 into xI/O address
01 F002h.
Table 6−17. k24 Absolute Addressing Mode Used For xI/O Space Access
Ra = Smem AR2 = volatile(#040003h) k24 = 040003h The CPU loads the value at xI/O
address 04 0003h into AR2.
Smem = ALLa volatile(#03F002h) = AR0 k24 = 03F002h The CPU stores the content of AR0
into xI/O address 03 F002h.
6.10.3 Addressing I/O Space with the PDP Direct Addressing Mode
In word-pointer mode, to access I/O space with the PDP direct I/O addressing
mode, you can use port(@#k7) in instructions using the following syntax ele-
ment:
Table 6−18 provides examples of using port(@#k7) to access I/O space. The
9-bit peripheral data page (PDP) value is concatenated with the 7-bit k7 offset.
Table 6−18. PDP Direct Addressing Mode Used For I/O Space Access
Generated Address
Syntax Example Instruction Example (For PDP = 511) Description
Ra = Smem T2 = port(@0h) PDP:offset = FF80h An offset of 0 indicates the top of the

current peripheral data page. The
CPU copies the value at the top of
peripheral data page 511 (address
FF80h) and loads it into T2.
Smem = ALLa port(@127) = T2 PDP:offset = FFFFh An offset of 127 indicates the bottom
of the current peripheral data page.
The CPU copies the content of T2 and
writes it to the bottom of peripheral
data page 511 (address FFFFh).

6.10.4 Addressing xI/O Space with the XDP Direct Addressing Mode
In word-pointer mode, to access xI/O space with the XDP direct xI/O address-
ing mode, you can use volatile(@Daddr) in instructions using the following
syntax elements:
Table 6−19 provides an example on the XDP direct xI/O addressing mode ac-
cessing xI/O space.
Table 6−19. @Daddr Direct Operand Used For xI/O Space Access
Generated Address
Syntax Example Instruction Example For XDP = 03 0001h = .dp = 0 Description
Ra = Smem T2 = volatile(@0004h) XDP + Doffset The CPU loads the value at

= 03 0001h + 04h = 03 0005h xI/O address 03 0005h into
T2.

6.10.5 Addressing I/O and xI/O Space With XAR Indirect Addressing Modes
In word-pointer mode, to access I/O space with the XAR indirect I/O address-
ing mode, you can use an indirect operand with the port() qualifier in instruc-
tions using the following syntax element:
In word-pointer mode, to access xI/O space with the XAR indirect xI/O ad-
dressing mode, you can use an indirect operand with the volatile() qualifier in
instructions using the following syntax elements:
Table 6−20 lists the indirect operands that support accesses to I/O space.
Table 6−21 lists the indirect operands that support accesses to xI/O space.
The sections following the tables provide details and examples for the oper-
ands.
Note:
In word-pointer mode, only the 16 LSBs of the 24-bit indirect address are
used for an I/O access, whereas only the 23 LSBs are used for an xI/O ac-
cess.
Table 6−20. Indirect Operands For I/O Space Access
Syntax Element Description Available Indirect Operands
Smem Smem indicates one word (16 bits) XAR indirect addressing mode:
of data. *ARn
*ARn+
*ARn−
*+ARn
*−ARn
*(ARn + T0/AR0)
*(ARn − T0/AR0)
*ARn(T0/AR0)
*(ARn − Tx)
*ARn(Tx)
*ARn(#K16)
*+ARn(#K16)
*ARn(short(#k4))

Table 6−21. Indirect Operands For xI/O Space Access
Smem, Smem indicates one word (16 bits) XAR indirect addressing mode:
dbl(Smem) of data. dbl(Smem) and *ARn
HI(Smem)/LO(Smem) HI(Smem)/LO(Smem) indicates *ARn+
one long word (32 bits) of data *ARn−
*+ARn
*−ARn
*(ARn + T0/AR0)
*(ARn − T0/AR0)
*ARn(T0/AR0)
*(ARn − Tx)
*ARn(Tx)
*ARn(#K16)
*+ARn(#K16)
*ARn(short(#k4))
6.10.5.1 *ARn Used For I/O and xI/O Spaces Access
Operand Description
*ARn I/O − xI/O generated address in linear mode: XARn

I/O − xI/O generated address in circular mode: (ARnH:BSAyy) + (00:ARn)
Generated Address
Ra = Smem T2 = port(*AR4) XAR4 The CPU reads the value at I/O

Assume XAR4 = 00FF80h address 00 FF80h and loads it into
T2. XAR4 is not modified.
Smem = ALLa port(*AR5) = T2 XAR5 The CPU reads the content of T2

Assume XAR5 = 00FFFFh and writes it to I/O address
00 FFFFh. XAR5 is not modified.
Ra = Smem T2 = volatile(*AR4) XAR4 The CPU reads the value at xI/O

Assume XAR4 = 01FF80h address 01 FF80h and loads it into
T2. XAR4 is not modified.
Smem = ALLa volatile(*AR5) = T2 XAR5 The CPU reads the content of T2

Assume XAR5 = 02FFFFh and writes it to xI/O address

6.10.5.2 *ARn+ Used For I/O and xI/O Spaces Access
Operand Description
*ARn+ I/O − xI/O generated address in linear mode: XARn

XARn modification: XARn = XARn + 1
XARn = XARn + 2 (For 32-bit xI/O access)
Generated Address
Ra = Smem T2 = port(*AR4+) XAR4 The CPU reads the value at I/O

Assume XAR4 = 00FF80h address 00 FF80h and loads it
into T2. After being used for the
cremented by 1.
Smem = ALLa port(*AR5+) = T2 XAR5 The CPU reads the content of T2

Assume XAR5 = 00FFFFh and writes it to I/O address
00 FFFFh. After being used for
incremented by 1.
Ra = Smem T2 = volatile(*AR4+) XAR4 The CPU reads the value at xI/O

into T2. After being used for the
cremented by 1.
dbl(Smem) = ALLa volatile(dbl(*AR5+)) = XAR5 The CPU reads the content of

AC2 Assume XAR5 = 02FFFEh AC2 and writes it to xI/O address
02 FFFEh. After being used for
incremented by 2.

6.10.5.3 *ARn– Used For I/O and xI/O Spaces Access
Operand Description
*ARn– I/O − xI/O generated address in linear mode: XARn

XARn modification: XARn = XARn − 1
XARn = XARn − 2 (for 32-bit xI/O access)
Generated Address
Ra = Smem T2 = port(*AR4–) XAR4 The CPU reads the value at I/O

Assume XAR4 = address 00 FF80h and loads it
00 FF80h into T2. After being used for
is decremented by 1.
Smem = ALLa port(*AR5−) = T2 XAR5 The CPU reads the content of

Assume XAR5 = T2 and writes it to I/O address
00 FFFFh 00 FFFFh. After being used for
is decremented by 1.
Ra = Smem T2 = volatile(*AR4−) XAR4 The CPU reads the value at

Assume XAR4 = xI/O address 01 FF80h and
01 FF80h loads it into T2. After being
used for the address, XAR4 is
decremented by 1.
dbl(Smem) = ALLa volatile(dbl(*AR5−)) = AC2 XAR5 The CPU reads the content of
Assume XAR5 = AC2 and writes it to xI/O
02 FFFEh address 02 FFFEh. After being
used for the address
generation, XAR5 is
decremented by 2.

6.10.5.4 *+ARn Used For I/O and xI/O Spaces Access
Operand Description
*+ARn I/O − xI/O generated address in linear mode: XARn + 1

Generated address in circular mode: (ARnH:BSAyy) + (00:ARn) +1
XARn modification: XARn = XARn + 1
XARn = XARn + 2 (For 32-bit xI/O access)
Generated Address
Ra = Smem T2 = port(*+AR4) XAR4 + 1 Before being used for the

Assume XAR4 = address generation, XAR4 is
00 FF7Fh incremented by 1. The CPU
reads the value at I/O address
00 FF80h and loads it into T2.
Smem = ALLa port(*+AR5) = T2 XAR5 + 1 Before being used for the

00 FFFEh incremented by 1. The CPU
reads the content of T2 and
writes it to I/O address
00 FFFFh.
Ra = Smem T2 = volatile(*+AR4) XAR4 +1 Before being used for the

01 FF7Fh incremented by 1. The CPU
reads the value at xI/O address
01 FF80h and loads it into T2.
dbl(Smem) = volatile(dbl(*+AR5)) = AC2 XAR5 +1 Before being used for the

ALLa Assume XAR5 = address generation, XAR5 is
02 FFFEh incremented by 2. The CPU
reads the content of AC2 and
writes it to xI/O address
02 FFFFh.

6.10.5.5 *–ARn Used For I/O and xI/O Spaces Access
Operand Description
*–ARn I/O − xI/O generated address in linear mode: XARn − 1

Generated address in circular mode: (ARnH:BSAyy) + (00:ARn) − 1
XARn modification: XARn = XARn − 1
XARn = XARn − 2 (for 32-bit xI/O access)
Generated Address
Ra = Smem T2 = port(*−AR4) XAR4 – 1 Before being used for the address

Assume XAR4 = 00 FF80h generation, XAR4 is decremented
I/O address 00 FF7Fh and loads it
into T2.
Smem = ALLa port(*−AR5) = T2 XAR5 – 1 Before being used for the address
Assume XAR5 = 00 FFFFh generation, XAR5 is decremented
by 1. The CPU reads the content of
T2 and writes it to I/O address 00
FFFEh.
Ra = Smem T2 = volatile(*−AR4) XAR4 − 1 Before being used for the address

Assume XAR4 = 01 FF80h generation, XAR4 is decremented
xI/O address 01 FF7Fh and loads it
into T2.
dbl(Smem) = volatile(dbl(*−AR5)) = XAR5 − 1 Before being used for the address

ALLa AC2 Assume XAR5 = 02 FFFEh generation, XAR5 is decremented
by 2. The CPU reads the content of
AC2 and writes it to xI/O address
02 FFFCh.

6.10.5.6 *(ARn + T0/AR0) Used For I/O and xI/O Spaces Access
*(ARn + T0) I/O − xI/O generated address in *(ARn + AR0) I/O − xI/O generated address in
linear mode: XARn linear mode XARn
I/O − xI/O generated address in I/O − xI/O generated address in
circular mode: circular mode:
Generated Address
Ra = Smem T2 = port(*(AR4 + T0)) XAR4 The CPU reads the value at I/O
Assume XAR4 = address 00 FF80h and loads it into
00 FF80h T2. After being used for the address
generation, XAR4 is incremented by
the number in T0.
Smem = ALLa port(*(AR5 + T0)) = T2 XAR5 The CPU reads the content of T2 and
Assume XAR5 = writes it to I/O address 00 FFFFh.
00 FFFFh After being used for the address
the number in T0.
Ra = Smem T2 = volatile(*AR4 + XAR4 The CPU reads the value at xI/O

T0) Assume XAR4 = address 01 FF80h and loads it into
the number in T0.
dbl(Smem) = ALLa volatile(dbl(*AR5 + XAR5 The CPU reads the content of AC2
T0)) = AC2 Assume XAR5 = and writes it to xI/O address
02 FFFEh 02 FFFEh. After being used for the
incremented by the number in T0.

6.10.5.7 *(ARn – T0/AR0) Used For I/O and xI/O Spaces Access
*(ARn – T0) I/O − xI/O generated address in *(ARn – AR0) I/O − xI/O generated address in
linear mode: XARn linear mode: XARn
I/O − xI/O generated address in I/O − xI/O generated address in
circular mode: circular mode:
Generated Address
Ra = Smem T2 = port(*(AR4 − T0)) XAR4 The CPU reads the value at I/O
Assume XAR4 = address 00 FF80h and loads it into
Smem = ALLa port(*(AR5 – T0)) = T2 XAR5 The CPU reads the content of T2
Assume XAR5 = and writes it to I/O address
00 FFFFh 00 FFFFh. After being used for the
decremented by the number in T0.
Ra = Smem T2 = volatile(*AR4 − T0) XAR4 The CPU reads the value at xI/O
Assume XAR4 = address generation 01 FF80h and
01 FF80h loads it into T2. After being used for
the address, XAR4 is decremented
dbl(Smem) = ALLa volatile(dbl(*AR5 − T0)) XAR5 The CPU reads the content of AC2
= AC2 Assume XAR5 = and writes it to xI/O address
02 FFFEh 02 FFFEh. After being used for the
decremented by the number in T0.

6.10.5.8 *ARn(T0/AR0) Used For I/O and xI/O Spaces Access
*ARn(T0) I/O − xI/O generated address in linear *ARn(AR0) I/O − xI/O generated address in linear
mode: XARn + T0 mode: XARn + AR0
I/O − xI/O generated address in circular I/O − xI/O generated address in circular
mode: mode:
a base pointer. T0 is a 16-bit signed a base pointer. AR0 is a 16-bit signed
value added to the base pointer. value added to the base pointer.
Generated Address
Ra = Smem T2 = port(*AR4(T0)) XAR4 + T0 The CPU reads the value at I/O

Assume XAR4 = FF7Dh address FF80h and loads it into
and T0 = 3 T2. XAR4 is not modified.
Smem = ALLa port(*(AR5(T0))) = T2 XAR5 + T0 The CPU reads the content of

Assume XAR5 = FFFAh T2 and writes it to I/O address
and T0 = 5 FFFFh. XAR5 is not modified.
Ra = Smem T2 = volatile(*AR4(T0)) XAR4 + T0 The CPU reads the value at

01FF7Dh loads it into T2. XAR4 is not
modified.
dbl(Smem) = volatile(dbl(*AR5(T0))) = XAR5 + T0 The CPU reads the content of

ALLa AC2 Assume XAR5 = AC2 and writes it to xI/O
02FFFAh and T0 = 4 address 02 FFFEh. XAR5 is not
modified.

6.10.5.9 *(ARn + Tx), (Tx = T1, T2, or T3) Used For I/O and xI/O Spaces Access
Operand Description
*(ARn + Tx) I/O − xI/O generated address in linear mode: XARn

Tx is a 16-bit signed value.
Generated Address
Ra = Smem AR3 = port(*(AR9 + T1)) XAR9 The CPU reads the value at I/O
00 FF80h into XAR3. After being used for
Smem = ALLa port(*(AR10 + T3)) = AR0 XAR10 The CPU reads the content of
Assume XAR10 = XAR0 and writes it to I/O address
00 FFFFh 00 FFFFh. After being used for
Ra = Smem AR3 = volatile(*AR9 + T1) XAR9 The CPU reads the value at xI/O
dbl(Smem) = ALLa volatile(dbl(*AR10 + T3)) = XAR10 The CPU reads the content of
XAR0 Assume XAR10 = XAR0 and writes it to xI/O
02 FFFFh address 02 FFFFh. After being
number in T3.

6.10.5.10 *(ARn – Tx), (Tx = T1, T2, or T3) Used For I/O and xI/O Spaces Access
Operand Description
*(ARn – Tx) I/O − xI/O generated address in linear mode: XARn

Tx is a 16-bit signed value.
Generated Address
Ra = Smem AR3 = port(*(AR9 – T2)) XAR9 The CPU reads the value at I/O
T2.
Smem = ALLa port(*(AR10 – T2)) = AR0 XAR10 The CPU reads the content of
Assume XAR10 = AR0 and writes it to I/O address
00 FFFFh FFFFh. After being used for the
T2.
Ra = Smem AR3 = volatile(*AR9 − T2) XAR9 The CPU reads the value at xI/O
T2.
dbl(Smem) = ALLa volatile(dbl(*AR10 − T2)) = XAR10 The CPU reads the content of
02 FFFEh address 02 FFFEh. After being
number in T2.

6.10.5.11*ARn(Tx), (Tx = T1, T2, or T3) Used For I/O and xI/O Spaces Access
Operand Description
*ARn(Tx) I/O − xI/O generated address in linear mode: XARn + Tx

I/O − xI/O generated address in circular mode: (ARnH:BSAyy) + (00:ARn) + Tx
XARn is not modified. ARn is used as a base pointer.
Tx is a 16-bit signed value added to the base pointer. Tx can be T1, T2, or T3.
Generated Address
Ra = Smem AR3 = port(*AR9(T3)) XAR9 + T3 The CPU reads the value at

Assume XAR9 = I/O address 00 FF80h and
00 FF7Dh loads it into XAR3. XAR9 is
and T3 = 3 not modified.
Smem = ALLa port(*AR10(T3)) = AR0 XAR10 + T3 The CPU reads the content of
Assume XAR10 = XAR0 and writes it to I/O
00 FFFAh address 00 FFFFh. XAR10 is
and T3 = 5 not modified.
Ra = Smem AR3 = volatile(*AR9(T3)) XAR9 + T3 The CPU reads the value at

01 FF80h loads it into XAR3. XAR9 is
not modified.
dbl(Smem) = ALLa volatile(dbl(*AR10(T3))) = XAR10 + T3 The CPU reads the content of

02 FFF0h and T3 = 0Eh address 02 FFFEh. XAR10 is
not modified.

6.10.5.12 *ARn(#K16) Used For I/O and xI/O Spaces Access
Operand Description
*ARn(#K16) I/O − xI/O generated address in linear mode: XARn + K16

I/O − xI/O generated address in circular mode: (ARnH:BSAyy) + (00:ARn) + K16
XARn is not modified. XARn is used as a base pointer. The 16-bit signed constant
(K16) is 24-bit sign extended and is used as an offset from that base pointer.
Generated Address
Ra = Smem AR3 = port(*AR12(#8)) XAR12 + 8 The CPU reads the value at I/O
address (XAR12+ 8) and loads
it into AR3. XAR12 is not
modified.
Smem = ALLa port(*AR8(#20)) = T1 XAR8 + 20 The CPU reads the content of

T1 and writes it to I/O address
XAR8 + 20. XAR8 is not
modified.
Ra = Smem AR3 = volatile(*AR12(#8)) XAR12 + 8 The CPU reads the value at

xI/O address (XAR12+ 8) and
loads it into AR3. XAR12 is not
modified.
dbl(Smem) = volatile(dbl(*AR8(#20))) = AC1 XAR8 + 20 The CPU reads the content of

ALLa AC1 and writes it to xI/O
address (XAR8 + 20). XAR8 is
not modified.

6.10.5.13 *+ARn(#K16) Used For I/O and xI/O Spaces Access
Operand Description
*+ARn(#K16) I/O − xI/O generated address in linear mode: XARn + K16

I/O − xI/O generated address in circular mode: (ARnH:BSAyy) + (00:ARn) + K16
Generated Address
Ra = Smem AR3 = port(*+AR12(#8)) XAR12 + 8 Before XAR12 is used for the I/O
address generation, the constant
is added to XAR12. The CPU
reads the value at I/O address
(XAR12 + 8) and loads it into
AR3.
Smem = ALLa port(*+AR8(#20)) = T1 XAR8 + 20 Before XAR8 is used for the I/O
address generation, the CPU
(XAR8 + 20).
Ra = Smem AR3 = volatile(*+AR12(#8)) XAR12 + 8 Before XAR12 is used for the

xI/O address generation, the
constant is added to XAR12. The
CPU reads the value at I/O
address (XAR12 + 8) and loads it
into AR3.
dbl(Smem) = ALLa volatile(dbl(*+AR8(#20))) = T1 XAR8 + 20 Before XAR8 is used for the xI/O
address generation, the CPU
(XAR8 + 20).

6.10.5.14 *ARn(short(#k4)) Used For I/O and xI/O Spaces Access
Operand Description
*ARn(short(#k4)) I/O − xI/O generated address in linear mode: XARn + k4

I/O − xI/O generated address in circular mode: (ARnH:BSAyy) + (00:ARn) + k4
Generated Address
Ra = Smem AR11 = port(*AR7(short(#3))) XAR7 + 3 The CPU reads the

Assume XAR7 = value at I/O address
00 FF70h 00 FF74h and loads it
into AR11. XAR7 is not
modified.
Smem = ALLa port(*AR14(short(#7))) = AR2 XAR14 + 7) The CPU reads the

Assume XAR14 = content of AR2 and
00 FFF0h writes it to I/O address
00 FFF7h. XAR14 is not
modified.
Ra = Smem AR11 = volatile(*AR7(short(#3))) XAR7 + 3 The CPU reads the

Assume XAR7 = value at xI/O address
01 FF70h 01 FF74h and loads it
into AR11. XAR7 is not
modified.
dbl(Smem) = ALLa volatile(dbl(*AR14(short(#6)))) = XAR14 + 6 The CPU reads the

XAR2 Assume XAR14 = content of XAR2 and
02 FFF0h writes it to xI/O address
02 FFF6h. XAR14 is not
modified.

Exceptions/Restrictions on Accesses to I/O − xI/O Spaces
6.11 Exceptions/Restrictions on Accesses to I/O − xI/O Spaces
6.11.1 Exceptions on Accesses to I/O and xI/O Spaces

In word-pointer mode, the instructions below enable data transfers between
data memory and I/O space. Either Smem or Ymem operands (but not both
at the same time) can be qualified with port(). For Ymem, you can use any of
the dual XAR indirect operands listed in Table 6−4.
Instruction Syntax that can have Smem or Ymem qualified to access I/O
space
Smem = Ymem
Ymem = Smem
In word-pointer mode, the instructions below enable data transfer between

data memory and xI/O space. Either Smem/dbl(Smem) or Ymem/dbl(Ymem)
operands (but not both at the same time) can be qualified with port(). For
Ymem/dbl(Ymem), you can use any of the dual XAR indirect operands listed
in Table 6−4.
Instruction Syntax that can have Smem/dbl(Smem) or Ymem/dbl(Ymem)

qualified to access xI/O space
Smem = Ymem
Ymem = Smem
6.11.2 Restrictions on Accesses to I/O and xI/O Spaces

It is not allowed to have any instructions executed in parallel with an in-
struction performing an I/O or an xI/O space access
The instructions below having the Smem syntax element cannot be used
for I/O or xI/O space accesses:
Instruction Syntax that Does Not Support I/O − xI/O Spaces Accesses
delay(Smem)
ACa = m40(rnd(ACa + frct(uns(Smem) * uns(Cmem))),

T3 = Smem, delay(Smem)

None of the instructions having the dbl(Smem) or HI(Smem)/LO(Smem)

operands can be used for I/O space accesses
In word-pointer mode, none of the instructions having the byte(Smem) op-

erand can be used for I/O or xI/O space accesses
Instruction Syntax that Does Not Support I/O − xI/O Spaces Access
Ra = uns(byte(Smem))
byte(Smem) = Ra
byte(Smem) = byte(Ymem)
byte(Ymem) = byte(Smem)
byte(Smem) = k8
mar(byte(Smem))
In case of an I/O address greater than FFFFh or an xI/O address greater

than 7F FFFFh, the CPU behavior is undefined
Any illegal access to I/O space generates a hardware bus-error interrupt

(BERRINT) to be handled by the CPU
Note:
Some differences apply on restrictions on accesses to I/O and xI/O space
when the CPU is in byte-pointer mode, see Section 7.11 for more details.

Circular Addressing
6.12 Circular Addressing

Circular addressing can be used with any of the indirect addressing modes.
Each of the eight extended auxiliary registers (XAR0–XAR7) and the XAR15
register can be independently configured to be linearly or circularly modified
as they act as pointers to data memory or register bits. This configuration is
performed with a bit in status register ST2_55 (see Table 6−22). To choose cir-
cular modification, set the corresponding bit.
The size of a circular buffer is defined by one of three registers—BK03, BK47,
or BKC (see Table 6−22). The buffer size register defines the number of words
in a buffer of words, or it defines the number of bits in a buffer of bits within a
register. The maximum buffer size is 2^16 elements.
Unlike the C55x DSP generations, the circular buffer on the C55x+ DSP is not
constrained to be allocated in a 64-kword main data page. The following table
illustrates how the array element i of the circular buffer A is addressed on the
C55x+ revision. Each address within the buffer has 24 bits. The start address
of the buffer (A) is composed of the 8 MSBs of the extended auxiliary register
XARn (ARnH) and the 16 bits of the appropriate buffer start address (BSAxx)
register. The value you load into the pointer ARn or AR15 acts as the index i
selecting words relative to the start address. To load ARnH you must load
XARn which is the concatenation ARnH:ARn.
Buffer Start Address Buffer Element Index
A i
ARnH:BSAyy 00:ARn
All ARnH (with n = 0−7) must be loaded via its extended auxiliary register.
Note:
For source code compatibility with C55x DSP generations, the coefficient
data pointer XCDP is mapped by the assembler tool to the XAR15 register
in the C55x+ DSP. AR15H can be loaded individually.
For a buffer of bits, the buffer start address register defines the reference bit,
and the pointer selects bits relative to the position of that reference bit. You
need only to load ARn (with n = 0−7); you do not have to load XARn.
Note:
The extended auxiliary registers XAR8−XAR14 cannot be configured for cir-
cular addressing. There are no corresponding circular configuration bits in
the ST2_55 registers for these registers.

Circular Addressing
Table 6−22. Circular Addressing
Buffer Start
Linear/Circular Address Buffer Size Computed Circular
Pointer Configuration Bit Register Register Buffer Start Address
XAR0 ST2_55(0) = AR0LC BSA01 BK03 AR0H:BSA01

XAR15 ST2_55(8) = CDPLC BSAC BKC AR15H:BSAC
6.12.1 Configuring XAR0–XAR7 for Circular Addressing
Each of the eight extended auxiliary registers XARn (XAR0−XAR7) has its own
linear/circular configuration bit in ST2_55. XAR8−XAR14 registers cannot be
used for circular addressing.
ARnLC XARn Is Used For ...
0 Linear addressing
1 Circular addressing
The CDPLC bit in status register ST2_55 configures the DSP to use the
XAR15 register for linear or circular addressing:
CDPLC XAR 15 Is Used For ...
0 Linear addressing
1 Circular addressing
You can use the circular addressing instruction qualifier if you want every
pointer used by the instruction to be modified circularly. In algebraic assembler
code, add the circular() qualifier in parallel with the instruction (instruction || cir-
cular()). The circular addressing instruction qualifier overrides the linear/circu-
lar configuration in ST2_55.

Circular Addressing
6.12.2 Circular Buffer Implementation

As an example of how to set up a circular buffer, consider this procedure for
a circular buffer of words in data memory (with this procedure, the circular buff-
er memory allocation does not have any alignment constraints).
1) Initialize the appropriate buffer size register (BK03, BK47, or BKC). For ex-
ample, for a buffer of size 8, load the BKxx register with 8.
2) Initialize the appropriate configuration bit in ST2_55 to choose circular
modification for the selected pointer.
3) Initialize the appropriate extended register XARn (n = 0−7, or 15) to define
the 8 most significant bits of the circular buffer start address in ARnH. For
example, if XAR3 is the circular pointer, then load XAR3.
4) Initialize the appropriate buffer start address register (BSA01, BSA23,
BSA45, BSA67, or BSAC) to define the 16 LSBs of the circular buffer start
address.
5) Load the selected pointer, ARn (n = 0−7, or 15), with a value from 0 to
(buffer size − 1). For example, if you are using AR15 and the buffer size
is 8, then load AR15 with a value less than or equal to 7.
If a circular buffer of size R does not use BSAxx (that is BSAxx = 0 in the above
procedure), then this circular buffer must start on an N-bit boundary, where N
is the smallest integer that satisfies the relationship, 2N > R. For example, for
a buffer size R = 8, N is 4. In this case, the top of the circular buffer is the ad-
dress generated when the 4 LSBs of the pointer (ARn) are 0s. When the ad-
dress incrementing leads beyond the buffer, the 4 LSBs of the pointer are
forced to 0s. This case can occur when the C54x source code is migrated to
the C55x(+) revisions without any modifications.
If you are using indirect addressing operands with offsets, then ensure that the
absolute value of each offset is less than or equal to (buffer size − 1). Likewise,
if the circular pointer is to be incremented or decremented by a programmed
amount (supplied by a constant or by T0, AR0, or T1, T2, T3), then ensure the
absolute value of that amount is less than or equal to (buffer size − 1).
Note:
In case of circular pointer being decremented by a signed index register (T0,
AR0, or T1, T2, T3), the step size is the twos complement of the content of
that register. There is no twos complement of the negative maximum value
8000h. This means subtracting 8000h is an illegal operation.
Figure 6−10 summarizes how the circular address is computed with the follow-
ing form:
(ARnH: BSAyy) + (00 + ARn) + Step

Circular Addressing
Unlike on the C55x DSP generations, the circular pointer modification is per-
formed on 24-bit width.
Figure 6−10. Circular Buffer Computation in 24-Bit
ARn/AR15
Pre/Post modification Step (+/− T0/1/2/3, #K, short(#k)), .. Virtual buffer computation on
16-bit
BKxx/BKC
zero extension to 24-bit “Virtual” address on 16-bit width
ARnH/AR15H BSAxx/BSAC Buffer start address

addition on 24-bit
24-bit memory address
Note:
See Section 7.11 for the differences regarding the circular buffer computa-
tion.
The following code demonstrates initializing and then accessing a circular buffer.
BK03 = #3h ; Circular buffer size is 3 words
Bit(ST2_55, @AR1LC) ; AR1 is configured to be modified circularly
mar(XAR1 = #07FFFEh) ; The 8 MSBs of the circular buffer start address
; (07FFFEh) are stored into AR1H
BSA01 = #07FFFEh ; The 16 LSBs of the circular buffer start address
; (07FFFEh) are stored into BSA01
mar(AR1 = #0000h) ; Index (in AR1) is 0000h
AC0 = *AR1+ ; AC0 loaded from 07FFFEh + (AR1) = 07FFFEh,

; and then AR1 = 0001h
AC0 = *AR1+ ; AC0 loaded from 07FFFEh + (AR1) = 07FFFFh,
AC0 = *AR1+ ; AC0 loaded from 07FFFEh + (AR1) = 080000h,
AC0 = *AR1+ ; AC0 loaded from 07FFFEh + (AR1) = 07FFFEh,

Circular Addressing
6.12.3 TMS320C54x DSP Compatibility

In the TMS320C54x DSP-compatible mode (when the C54CM bit is 1), the cir-
cular buffer size register BK03 is used with all of the auxiliary registers and
BK47 is not used. The C55x+ DSP device enables you to emulate
TMS320C54x circular buffer management by following these programming
rules:
1) Initialize BK03 with the desired buffer size.
2) Initialize the appropriate configuration bit in ST2_55 to set circular activity

for the selected pointer.
3) Initialize the appropriate extended auxiliary register (XARn) with the main
data page in the seven MSBs (ARnH).
4) Initialize the pointer (ARn ) to set the start address.
5) Initialize the appropriate buffer start address register to 0, so that it has no

effect.
Since above procedure requires setting the BSAyy register to 0, the source
code migrated from the C54x needs to comply with the rule described in Sec-
tion 6.10.2 about circular buffer memory allocation alignment.
If you are using indirect addressing operands with offsets, then ensure that the
absolute value of each offset is less than or equal to (buffer size − 1). Likewise,
if the circular pointer is to be incremented or decremented by a programmed
amount (supplied by a constant or by AR0, or T1, T2, T3), then ensure the ab-
solute value of that amount is less than or equal to (buffer size − 1).
What follows is an example code sequence that emulates a C54x DSP circular
buffer:
BK03 = #3h ; Circular buffer size is 3 words
bit(ST2_55, @AR1LC) = #1 ; AR1 is configured to be modified circularly
XAR1 = #010000h ; Circular buffer is in main data page 01
AR1 = #0A01h ; Circular buffer start address is 010A00h
BSA01 = #0h ; BSA01 is 0, so that it has no effect
AC0 = *AR1+ ; AC0 loaded from 010A01h, and then AR1 = 0A02h

Circular Addressing
This circular buffer implementation has the disadvantage that it requires the
alignment of the circular buffer on an 8-word address boundary. To remove this
constraint, you can initialize BSA01 with an offset. For example:
BK03 =#3h ; Circular buffer size is 3 words
bit(ST2_55, @AR1LC) = #1 ; AR0 is configured to be modified circularly
XAR1 = #010000h ; Circular buffer is in main data page 01
AR1 = #0A01h ; Circular buffer start address is 010A00h
BAS01 = #2h ; Add an offset of 2 to the buffer start address,
; so that the effective start address is 010A02h
AC0 = *AR1+ ; AC0 loaded from 010A01h + 2h = 010A03h,

; and then AR1 = 0A02h

Chapter 7
Byte-Pointer
Mode
This chapter introduces the two stacks located on the C55x+ DSP. It also ex-
plains how they relate to each other and how they are used by the CPU during
automatic context switching (saving register values before executing an inter-
rupt or a subroutine and restoring those values when the return from the inter-
rupt or the subroutine is executed).
Topic Page
7.1 Introduction on Byte-Pointer Addressing Mode . . . . . . . . . . . . . . . . . . 7-2

7.2 Accessing Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.3 Stack Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
7.4 Interrupt and Reset Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
7.5 Addressing Modes Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
7.6 Addressing Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26
7.7 I/O and xI/O Addressing Modes Description . . . . . . . . . . . . . . . . . . . . 7-39
7.8 Addressing I/O and xI/O Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-44
7.9 Exceptions/Restrictions on Accesses to I/O − xI/O Spaces . . . . . . 7-55
7.10 Circular Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-57
7.11 TMS320C54x Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-57
7-1
Introduction on Byte-Pointer Addressing Mode
7.1 Introduction on Byte-Pointer Addressing Mode

The C55x+ DSP features byte addressing capability to support the compilation
of the C codes written for standard microcontrollers.
The C55x+ DSP has two different execution modes in order to execute codes
using 23-bit effective word addresses (in CPU word-pointer mode) or using
24-bit effective byte addresses (in CPU byte-pointer mode).
In word-pointer mode, you can recompile and execute the C55x DSP gen-
eration source code.
In byte-pointer mode, you can benefit from byte addressing modes.
The BPTR bit (see Section 2.10.4.1) switches execution from one mode to the
other.
This chapter describes the C55x+ DSP behavior in byte-pointer mode such as
byte(Smem) syntax element and byte specific instructions. It also describes
the differences occurring between word- and byte-pointer modes for the fea-
tures below.
Features Byte-Pointer Mode Word-Pointer Mode
C54x DSP compatibility Section 7.11 Section 2.10
Data accesses and alignment rules Section 7.2 Section 3.3
Stack operations Section 7.3 Section 4.1
Interrupt and reset operations Section 7.4 Section 5.1
Addressing modes Sections 7.5 to 7.10 Section 6.2
7-2 Byte-Pointer Mode

Accessing Data Memory
7.2 Accessing Data Memory
7.2.1 Byte Addresses (24-Bit Effective Byte Addresses)

When the CPU accesses the data space in byte-pointer mode, it uses 24-bit
effective byte addresses to reference 8-, 16-, or 32-bit words. The following
figure shows a row of 32-bit-wide memory. Each byte is assigned an address.
For example, byte 0 is at address 00 0200h, byte 1 is at address 00 0201h,
byte 2 is at address 00 0202h, and byte 3 is at address 00 0203h.
Byte addresses Byte 0 Byte 1 Byte 2 Byte 3

00 0200h−00 0203h
The address buses carry 24-bit byte addresses. In byte-pointer mode, when
the CPU reads from or writes to a data space, the 24-bit effective byte address
is used as on the address buses. For example, suppose an instruction reads
a word at the 24-bit byte address 00 0204h. The appropriate data-read ad-
dress bus carries the 24-bit value 00 0204h.
Effective byte address: 0000 0000 0000 0010 0000 0100
Data-read address bus value: 0000 0000 0000 0010 0000 0100
7.2.2 Byte Accesses

The C55x+ CPU features dedicated byte instructions for the byte-pointer
mode. These instructions are using the byte(Smem) syntax element, and al-
low you to reference individual 8-bit values in data and I/O − xI/O spaces.
Table 7−1 describes these instructions. The byte(Smem) syntax element uses
the same operands as Smem and dbl(Smem) syntax elements. See Sec-
tion 7.5 for more details on the addressing modes in byte-pointer mode.
Table 7−1. Byte Access Instructions

Instructions Syntax Description
Ra = uns(byte(Smem)) byte(Smem) element is sign or zero extended to 16- or 40-bit
byte(Smem) = Ra Lower 8 bits of Ra is stored to byte(Smem)
byte(Smem) = #k8 The 8-bit constant k8 is stored to byte(Smem)
byte(Smem) = byte(Ymem) Copy an 8-bit value from one location to another (see Sections 7.5.3 through
7.5.6 for byte(Smem) and byte(Ymem) addressing operands details)
mar(byte(Smem)) Modify XARn register as if a single byte memory access is made
Byte-Pointer Mode 7-3

The instructions described in Table 3−1, cannot be used in the byte-pointer

mode. If these instructions are used, then the CPU behavior is undefined.
Note:
Only the instruction Ra=uns(low_byte(mmap(@RegisterID))) can be
used in byte-pointer mode to access a CPU register with its register ID.
Note:
If the instructions listed in Table 7−1 are used in word-pointer mode, then the
CPU generates a bus error interrupt (BERRINT).
7.2.3 Word/Long Word Memory Access Alignment

In the byte-pointer mode, all accesses made to data and I/O − xI/O spaces
must be aligned according to the size of the referenced element.
When using byte(Smem) or byte(Ymem) syntax element to access one

byte (8 bits), the generated address does not have any alignment
constraints.
When using an Smem, Xmem, or Ymem syntax element to access one

word (16 bits), the generated address must be even. The LSB of the ad-
dress must be 0.
When using dbl(Smem), dbl(Ymem), dbl(Cmem), HI(Smem), LO(Smem),

HI(Cmem), or LO(Cmem) syntax element to access one long word (32
bits), the generated address must be a multiple of 4. The 2 LSBs of the
address must be 0.
Note:
1) In the byte-pointer mode, when a word memory address (16 bits of data)
or a long word memory address (32 bits of data) is unlined, the CPU gen-
erates a bus error.
2) The C55x+ DSP always makes 16-bit accesses to the data stack; there-
fore, in the byte-pointer mode, you must ensure that the XSP content is
even. If not, then the CPU generates a bus error when executing a
push(), pop(), call(), return(), trap(), intr(), H/W interrupt, or a return from
interrupt.
3) These address alignment rules are different when the CPU is in word-
pointer mode, see Section 3.3.2 for more details.

When the CPU accesses words, the address used for the access is the ad-
dress of bits[16−8] of the 16-bit value.
Byte addresses Byte 0 Byte 1

00 0200h−00 0201h bits[16−8] bits[7−0]
When the CPU accesses long words, the address used for the access is the
address of bits[31−24] of the 32-bit value.

00 0200h−00 0203h bits[31−24] bits[23−16] bits[15−8] bits[7−0]
7.2.4 Example of Data Organization

The following table and Figure 7−1 provide a similar example as the one de-
scribed in Section 3.3.3. Seven data values of varying sizes have been stored
in 32-bit-wide memory. No data value is stored in the shaded byte at address
00 0200h. When the CPU is in the byte-pointer mode, the alignment rules de-
scribed in Section 7.2.3 must be respected:
To access a long word, you must reference its most significant byte
(bits[31−24]). C is accessed at address 0204h. D is accessed at address
00 020Ah which is an illegal long word address, resulting in a CPU bus er-
ror in the byte-pointer mode.
To access a word, you must reference its most significant byte (bits[15−8]).
B is accessed at address 0202h. E is accessed at address 00 020Dh
which is an illegal word address, resulting in a CPU bus error in the byte-
pointer mode.
Data Value Data Type Address
A Byte 00 0200h
B Word 00 0202h
C Long Word 00 0204h
D Long Word 00 020Ah (Illegal access due to unaligned address)
E Word 00 020Dh (Illegal access due to unaligned address)
F Byte 00 020Eh
G Byte 00 020Fh

Figure 7−1. Data Organization in Byte-Pointer Mode

00 0200h−00 0203h A bits[15−8] of B bits[7−0] of B
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
00 0204h−00 0207h bits[31−24] of C bits[23−16] of C bits[15−8] of C bits[7−0] of C
00 0208h−00 020Bh
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÇÇÇÇÇÇÇÇÇÇÇÇ D
00 020Ch−00 020Fh
ÇÇÇÇÇÇÇÇÇÇÇÇ E F G
7.2.5 Data Interface Requirements for Word- or Byte-Pointer Mode Switch

The 23-bit effective word addresses are used in word-pointer mode, and 24-bit
effective byte addresses are used in byte-pointer mode. Therefore, when you
switch from one pointer mode to the other, you have to make sure before reus-
ing an address, to shift it by software accordingly to the new mode before ac-
cessing the memory.
For example, if the CPU is in word-pointer mode and you want to switch to
byte-pointer mode, then a word address must be shifted to the MSBs by one
bit to convert it to a byte address before being used. Once this address has
been converted to a byte address, no scaling is applied by the CPU during the
code execution.
Note that for the stack pointers XSP and XSSP, the appropriate address shift
is performed automatically by hardware when switching from one mode to
another.
You can switch pointer modes with a function call as described in Section
2.10.4.1.

Stack Operations
7.3 Stack Operations

In byte-pointer mode, there are some differences occurring in data and system
stack operations accesses as compared to the accesses in word-pointer
mode. These differences are described in this section.
7.3.1 Stack Configurations

The C55x+ DSP provides one stack configuration in byte-pointer mode. In this
configuration:
The CPU uses only one software stack: the data stack referenced by XSP.
The system stack referenced by XSSP is not used.
The CPU uses the fast return process.
The CPU uses 24-bit linear stack addressing.
When the CPU is in the byte-pointer mode, the CPU does not use the system
stack. The only stack pointer available in byte-pointer mode is the data stack
pointer XSP.
The XSP register contains the 24-bit address of the value last pushed onto the
data stack. The CPU decrements XSP before pushing a value onto the stack,
and increments XSP after popping a value off the stack. You can allocate the
data stack anywhere in the data space. As mentioned in Section 2.6.7, the
C55x+ DSP has a 24-bit flat data addressing mechanism. This allows the stack
to span over the 64-KWord data page boundaries, and to have a size greater
than 64 KWords. The stack pointer increments or decrements happening dur-
ing stack operations are done linearly on 24-bit width.
The stack configuration can only be changed during a hardware or software

reset at the same time as the CPU default pointer mode (see Section 2.10.4.1
for more details on the default pointer mode usage). You can select a specific
stack configuration and the default pointer mode by placing the appropriate
value in the 32-bit reset vector location. See Section 4−2 for more details on
how to set up the reset vector. Table 4−2 lists all possible stack configurations
in both word- and byte-pointer modes.

Stack Operations
7.3.2 Automatic Context Switching

The CPU automatically saves the return address, the loop context bits, and the
pointer mode (BPTR), when responding to an interrupt or a called routine. See
Section 4.4 for more details. The automatic context switching is dependent on
the current processor pointer mode and on the ISR (or called) routine pointer
mode. In any case, the ISR (or called) routine pointer mode determines the
way the CPU is saving the context. Four cases have to be considered:
CPU Current Pointer ISR or Called Routine

Mode Pointer Mode See Section ...
Word Word 4.4
Byte Byte 7.3.2.1, step 1

7.3.2.2, step 1
Word Byte 7.3.2.1, step 2

7.3.2.2, step 2
Byte Word 7.3.2.1, step 3

7.3.2.2, step 3
Note:
When switching from the word- to byte-pointer mode, the C54CM bit (ST1[5])
is set to 0. See Section 7.11 for more details on the C54x DSP-compatible
mode in byte-pointer mode.
7.3.2.1 Fast-Return Context Switching for Calls
1) The current processor pointer mode and the called routine pointer mode
are both the byte-pointer mode.
Before beginning executing the called routine, the CPU automatically
saves CFCT and RETA to the data stack. The CPU decrements the data
stack pointer XSP by two before each 16-bit write to the stack. The system
stack pointer XSSP is not used.

Stack Operations
Data Stack
Byte 0 Byte 1
After Save XSP = x−4 CFCT RETA(23−16)
XSP = x−2 RETA(15−8) RETA(7−0)
Before XSP = x Previously Previously

Save saved data saved data
At the same time, the CPU saves the return address to RETA as well as the
loop context flags and the pointer mode bit in CFCT (see the following fig-
ure).
RETA PC (return address) CFCT Ctrl. bit
A return instruction at the end of a subroutine forces the CPU to restore

values in the opposite order. First, the CPU transfers the return address
from RETA to PC and restores its loop context flags as well as its pointer
mode bit from CFCT. Second, the CPU reads the CFCT and RETA values
from the data stack. The CPU increments the data stack pointer (XSP) by
two after each read from the data stack.
2) The current processor mode is the word-pointer mode. The called routine
pointer mode is the byte-pointer mode.
Before beginning executing the called routine, the CPU automatically
saves CFCT and RETA to the data stack. The CPU decrements the data
stack pointer XSP by one before each 16-bit write to the stack. The system
stack pointer XSSP is not used.
Data Stack
Byte 0 Byte 1
Before Save XSP = x Previously Previously

saved data saved data

Stack Operations
ure).
As shown on the following figure, during the completion of the call instruc-
tion, the CPU automatically shifts the data stack pointer (XSP) by one to
the MSBs for proper alignment to operate in the byte-pointer mode (see
Section 7.2.3 for alignment details).
Data Stack
Byte 0 Byte 1
After the XSP = CFCT RETA(23−16)

(x−2) << 1
Automatic RETA(15−8) RETA(7−0)
Pointer scaling Previously Previously


from the data stack. The CPU increments the data stack pointer (XSP) by
two after each read from the data stack. During the completion of the
return instruction, the CPU automatically shifts the data stack pointer
(XSP) by one to the LSBs to restore the data stack pointer address in
word-pointer mode.
3) The current processor mode is the byte-pointer mode. The called routine
pointer mode is the word-pointer mode.
The system stack pointer XSSP is used because of the called routine
pointer mode (word). Before beginning executing the called routine, the
CPU automatically saves CFCT and RETA to the system and data stacks
in parallel. Before each 16-bit write to the stacks, the CPU decrements the
data and system stack pointers by two.

Stack Operations

Byte 0 Byte 1 Byte 0 Byte 1
After
XSSP = (x − 2) CFCT RETA(23−16) XSP = (y − 2) RETA(15−8) RETA(7−0)
Save
Before Previously Previously Previously Previously
XSSP = x XSP = y
Save saved data saved data saved data saved data
ure).
As shown on the following figure, during the completion of the call instruc-
tion, the CPU automatically shifts the data stack pointer (XSP) by one to
the LSBs for proper alignment to operate in the word-pointer mode.

After XSSP = XSP =

CFCT RETA(23−16) RETA(15−8) RETA(7−0)
the automatic (x − 2) >>1 (y − 2) >>1
pointer Previously Previously Previously Previously
scaling saved data saved data saved data saved data

from the stacks. The CPU increments the data stack pointer (XSP) and the
system stack pointer (XSSP) by one after each read from the stacks. Dur-
ing the completion of the return instruction, the CPU automatically shifts
the stack pointers (XSP and XSSP) by one to the MSBs to restore the data
stack pointer address in the byte-pointer mode (see Section 7.2.3 for
alignment details).

Stack Operations
7.3.2.2 Fast-Return Context Switching for Interrupts

1) The current processor mode and the interrupt service routine (ISR) pointer
mode are both byte-pointer mode.
Before beginning executing the interrupt service routine (ISR), the CPU
automatically saves the ST2, ST0, ST1, DBSTAT, CFCT, and RETA regis-
ters to the data stack. The CPU decrements the data stack pointer XSP by
two before each 16-bit write to the stack. The system stack pointer XSSP is
not used.
Data Stack
Byte 0 Byte 1
XSP = x−10 RETA(15−8) RETA(7−0)
XSP = x−8 DBSTAT(15−8) DBSTAT(7−0)
XSP = x−6 ST1_55(15−8) ST1_55(7−0)
XSP = x−4 ST0_55(15−8) ST0_55(7−0)
XSP = x−2 ST2_55(15−8) ST2_55(7−0)

ure).
A return from interrupt instruction at the end of an ISR forces the CPU to
restore values in the opposite order. First, the CPU transfers the return ad-
dress from RETA to PC and restores its loop context flags as well as its
pointer mode bit from CFCT. Second, the CPU reads the CFCT, RETA,
DBSTAT, ST1, ST0, and ST2 values from the data stack. The CPU incre-
ments the data stack pointer (XSP) by two after each read from the data
stack.
2) The current processor mode is the word-pointer mode, and the interrupt
service routine (ISR) pointer mode is the byte-pointer mode.

Stack Operations
Before beginning executing the interrupt service routine (ISR) routine, the
CPU automatically saves the ST2, ST0, ST1, DBSTAT, CFCT, and RETA
registers to the data stack. The CPU decrements the data stack pointer
XSP by one before each 16-bit write to the stack. The system stack pointer
XSSP is not used.
Data Stack
Byte 0 Byte 1
XSP = x−4 DBSTAT(15−8) DBSTAT(7−0)
XSP = x−3 ST1_55(15−8) ST1_55(7−0)
XSP = x−2 ST0_55(15−8) ST0_55(7−0)
XSP = x−1 ST2_55(15−8) ST2_55(7−0)

ure).
As shown on the following figure, during the completion of the interrupt ac-
knowledgement, the CPU automatically shifts the data stack pointer
(XSP) by one to the MSBs for proper alignment to operate in the byte-
pointer mode (see Section 7.2.3 for alignment details).

Stack Operations
Data Stack
Byte 0 Byte 1
After the XSP = (x−6) << 1 CFCT RETA(23−16)
Automatic RETA(15−8) RETA(7−0)
DBSTAT(15−8) DBSTAT(7−0)
ST1_55(15−8) ST1_55(7−0)
ST0_55(15−8) ST0_55(7−0)
ST2_55(15−8) ST2_55(7−0)
Pointer scaling Previously Previously

A return from the interrupt instruction at the end of an ISR forces the CPU
to restore values in the opposite order. First, the CPU transfers the return
address from RETA to PC and restores its loop context flags as well as its
pointer mode bit from CFCT. Second, the CPU reads the CFCT, RETA,
DBSTAT, ST1, ST0, and ST2 values from the data stack. The CPU incre-
ments the data stack pointer (XSP) by two after each read from the data
stack. During the completion of the return from interrupt instruction, the
CPU automatically shifts the data stack pointer (XSP) by one to the LSBs
to restore the data stack pointer address in word-pointer mode.
3) The current processor mode is the byte-pointer mode, and the interrupt
service routine (ISR) pointer mode is the word-pointer mode.
The system stack pointer XSSP is used because of the interrupt service
routine (ISR) pointer mode (word). Before beginning executing interrupt
service routine (ISR), the CPU automatically saves the ST2, ST0, ST1,
DBSTAT, CFCT, and RETA registers to the system and data stacks in par-
allel. Before each 16-bit write to the stacks, the CPU decrements the data
and system stack pointers by two.

Stack Operations

After
XSSP = (x − 6) CFCT RETA(23−16) XSP = (y − 6) RETA(15−8) RETA(7−0)
Save
XSSP = (x − 4) DBSTAT(15−8) DBSTAT(7−0) XSP = (y − 4) ST1_55(15−8) ST1_55(7−0)
XSSP = (x − 2) ST0_55(15−8) ST0_55(7−0) XSP = (y − 2) ST2_55(15−8) ST2_55(7−0)
Before Previously Previously Previously Previously
XSSP = x XSP = y
Save saved data saved data saved data saved data
loop context flags and the pointer mode bit in CFCT (see below).
As shown on the following figure, during the completion of the interrupt in-
struction, the CPU automatically shifts the data stack pointer (XSP) by one
to the LSBs for proper alignment to operate in the word-pointer mode.

After XSSP = XSP =

CFCT RETA(23−16) RETA(15−8) RETA(15−0)
the automatic (x − 6) >>1 (y − 6) >>1
Pointer DBSTAT(15−8) DBSTAT(7−0) ST1_55(15−8) ST1_55(7−0)

scaling ST0_55(15−8) ST0_55(7−0) ST2_55(15−8) ST2_55(7−0)
Previously Previously Previously Previously
saved data saved data saved data saved data
A return from the interrupt instruction at the end of a subroutine forces the
CPU to restore values in the opposite order. First, the CPU transfers the
return address from RETA to PC and restores its loop context flags as well
as its pointer mode bit from CFCT. Second, the CPU reads the CFCT,
RETA, DBSTAT, ST1, ST0, and ST2 values from the stacks. The CPU in-
crements the data stack pointer (XSP) and the system stack pointer
(XSSP) by 1 after each read from the stacks. During the completion of the
return from the interrupt instruction, the CPU automatically shifts the stack
pointers (XSP and XSSP) by one to the MSBs to restore the data stack
pointer address in byte-pointer mode (see Section 7.2.3 for alignment de-
tails).

Interrupt and Reset Operations
7.4 Interrupt and Reset Operations

The CPU supports the same 32 interrupt service routines (ISR) in word- and
byte-pointer modes as described in Section 5.2.
Whether the CPU operates in word- or byte-pointer mode, the CPU services
the interrupts with the same procedure as the one described in Section 5.1.
More specifically:
The CPU starts executing all ISRs in the CPU default pointer mode as de-
fined during a hardware or software reset (see Section 4.2).
As shown in the following table, the automatic context switch occurs and
varies depending on:
The CPU pointer mode before the interrupt is acknowledged.
The CPU default pointer mode.
Table 7−2. Automatic Context Switch Procedure
Pointer Mode at Interrupt Acknowledgement Default CPU Pointer Mode See Section ...
Byte-pointer mode Byte-pointer mode 7.3.2.2
Word-pointer mode Word-pointer mode 4.4
Word-pointer mode Byte-pointer mode 7.3.2.2
Byte-pointer mode Word-pointer mode 7.3.2.2

Addressing Modes Description
7.5 Addressing Modes Description

This section describes the differences between the byte- and word-pointer
modes for the address generation and pointer modifications.
In byte-pointer mode, the C55x+ DSP supports the same addressing modes
as the ones described in Section 6.2:
Absolute addressing modes reference a location by supplying all or part

of an address as a constant in an instruction:
See Section 7.5.3 for data memory access
Direct addressing modes reference a location using an address offset:

See Section 7.5.4 for data memory, C55x+ register, and register bit ac-
cesses
Indirect addressing modes reference a location using a pointer:

See Section 7.5.5 for data memory access
Note:
In byte-pointer mode, the C55x+ DSP registers are not memory-mapped.
See Section 7.5.2 for more details.
As explained in Section 3.1, in byte-pointer mode, data memory locations are

referenced by the A unit with a 24-bit effective byte address generated by the
DAGEN with the 24-bit address registers (XARn, XDP, XSP).
Note:
During the address computation or pointer modification associated with the
addressing modes described in this section, an increment past FF FFFFh or
a decrement past 00 0000h causes the address to wrap around. Do not make
use of this behavior; it is not supported.
7.5.1 Pointer Modification Scaling

In the byte-pointer mode, before performing the address calculation, the ad-
dressing modes with an address index or an offset are scaled for alignment
purposes (see Section 7.2.3 for more details on memory access alignment).
The following sections detail all index scaling for all addressing modes in the
byte-pointer mode.

Addressing Memory-Mapped Registers (MMRs)
7.5.2 Addressing Memory-Mapped Registers (MMRs)

In the byte-pointer mode, the C55x+ DSP registers are not mapped to data
space. Therefore, when the DSP addresses the MMR region (byte address
00h−BFh), the actual memory location is read or written. Therefore, in byte
mode, you cannot use absolute, direct, or indirect addressing modes to access
MMR registers. You can use instead the C55x+ register ID symbols to address
them (see Section 6.4.4).
Note that in word-pointer mode, some C55x+ registers are memory-mapped

(see Table 2−2 for the complete list); and can be addressed using the abso-
lute, direct, or indirect addressing modes described in Chapter 6.
7.5.3 Absolute Addressing Modes

The k16 and the k24 absolute addressing modes have the same assembly
syntax in the byte- and word-pointer modes. See Section 6.3.1 for more details
on assembly syntax. The address generation is also computed the same way
in byte- or word-pointer mode. The only difference is:
In the byte-pointer mode, the 24 bits of the generated address are used
to address the memory.
In the word-pointer mode, the 23 LSBs of the generated address are used
Table 7−3. Absolute Addressing Mode Differences Between Byte- and Word-Pointer
Modes
Byte-Pointer Mode Word-Pointer Mode
dbl(Smem), dbl(Smem),
Operands byte(Smem) Smem HI(Smem)/LO(Smem) Smem HI(Smem)/LO(Smem)
abs16(#K16) DPH:K16
*(#k24) k24

7.5.4 Direct Addressing Mode
7.5.4.1 XDP Direct Addressing Mode
The assembler syntax of the XDP direct addressing mode is identical in byte-
and word-pointer modes. See Section 6.4.1 for more details on assembly syn-
tax.
In the byte-pointer mode, the generated address is the 24-bit sum of two val-
ues (see Table 7−4):
The value in the extended data page register (XDP)

A 7-bit offset (Doffset) calculated by the assembler
The calculation of Doffset by the assembler depends on the size of the refer-
enced element (see Table 7−5 for more details).
XDP identifies the start address of a local data page where 8-, 16-, or 32-bit
elements can be referenced. The size of the local data page varies depending
on the size of the referenced element:
128 bytes when 8-bit elements are referenced.

128 words when 16-bit elements are referenced.
128 long words when 32-bit elements are referenced.
Table 7−4. XDP Direct Addressing Mode Doffset Scaling Differences Between Byte- and
Word-Pointer Modes
dbl(Smem), dbl(Smem),
HI(Smem)/ HI(Smem)/
Operands byte(Smem) Smem LO(Smem) Smem LO(Smem)
@(Daddr) XDP+Doffset XDP+(Doffset <<1) XDP+(Doffset<<2) XDP+Doffset XDP+Doffset

Table 7−5. Doffset Calculation by the Assembler in Byte-Pointer Mode
Access Made To ... Doffset Calculation Description

Data memory Doffset = (Daddr – .dp) & 7Fh Daddr is the 24-bit address for the read or
byte(Smem) write operation; .dp is a value you assign
with the .dp assembler directive (.dp
generally matches XDP); the symbol &
indicates a bitwise AND operation.
Data memory, Doffset = ((Daddr – .dp) >> 1) & 7Fh Daddr is the 24-bit address for the read or
Smem write operation; .dp is a value you assign
with the .dp assembler directive (.dp
generally matches XDP); the symbol >>
indicates a logical shift to the LSBs; the
symbol & indicates a bitwise AND operation.
Data memory, Doffset = ((Daddr – .dp) >> 2) & 7Fh Daddr is the 24-bit address for the read or
dbl(Smem), write operation; .dp is a value you assign
HI(Smem)/LO(Smem) with the .dp assembler directive (.dp
generally matches XDP); the symbol >>
indicates a logical shift to the LSBs; the
symbol & indicates a bitwise AND operation.
The following three examples illustrate how in byte-pointer mode the assem-
bler automatically subtracts .dp from Daddr and scales the result down to com-
pute Doffset according to the size of the referenced memory location.
Example 1 uses XDP direct addressing to access an 8-bit data memory loca-
tion:
XDP = #07FFE0h ;For run-time, XDP is 07 FFE0h
.dp = #07FFE0h ;For assembly time, .dp is 07 FFE0h
T2 = byte(@07FFE9h) ;Load T2 with the 8-bit value at address 07 FFE9h

Doffset = (Daddr – .dp)&7Fh = (07FFE9h – 07FFE0h) & 7Fh = 09h
Doffset is encoded in the instruction: T2 = byte(@07FFE9h). At run time, the

24-bit data-space address is generated:
24-bit address = XDP + Doffset = 07 FFE0h + 0009h = 07 FFE9h
Example 2 uses XDP direct addressing to access a 16-bit data memory loca-
tion:
T2 = @07FFE2h ;Load T2 with the 16-bit value at address 07 FFE2h


Doffset = ((Daddr – .dp) >> 1) & 7Fh =
((07FFE2h – 07FFE0h) >> 1) & 7Fh = 01h
Doffset is encoded in the instruction: T2 = @07FFE2h. At run time, the 24-bit

data-space address is generated:
24-bit address = XDP + (Doffset << 1) = 07FFE0h +(0001h << 1) = 07 FFE2h
Example 3 uses XDP direct addressing to access a 32-bit data memory loca-
tion:
AC2 = dbl(@07FFE4h) ;Load AC2 with 32-bit value at address 07 FFE4h
Doffset = ((Daddr – .dp) >> 2) & 7Fh =
((07FFE4h – 07FFE0h) >> 2) & 7Fh = 01h
Doffset is encoded in the instruction: AC2 = dbl(@07FFE4h). At run time, the

24-bit data-space address is generated:
24-bit address = XDP +(Doffset << 2) = 07 FFE0h +(0001h << 2) = 07 FFE4h
7.5.4.2 XSP Direct Addressing Mode

The assembler syntax of the XSP direct addressing mode is different in byte-
and word-pointer modes. In the byte-pointer mode, the assembler syntax of
the XSP addressing mode is *SP[offset] where offset is a 7-bit unsigned
constant (see Section 6.4.2 for more details on the assembly syntax in the
word-pointer mode).
In the byte-pointer mode, the generated address is the 24-bit sum of two val-
ues:
The value in the extended data stack register (XSP).
The 7-bit offset that you specify in the instruction. This offset is scaled ac-
cording to the size of the referenced element (8-, 16-, or 32-bit values).
XSP identifies a stack frame where the 8-, 16-, or 32-bit elements can be refer-
enced. The size of the stack frame varies depending on the size of the refer-
enced element:
128 bytes when the 8-bit elements are referenced.
128 words when the 16-bit elements are referenced.
128 long words when the 32-bit elements are referenced.
Table 7−6 describes the offset scaling for the address calculation. This table
also gives the correspondence and difference between the byte- and word-
pointer modes for the operand syntax and address calculation.

Table 7−6. XSP Direct Addressing Mode Offset Scaling Differences

Between Byte- and Word-Pointer Modes
dbl(Smem) dbl(Smem)
HI(Smem) HI(Smem)
Operands byte(Smem) Smem LO(Smem) Operands Smem LO(Smem)
*SP[offset] XSP+offset XSP+(offset<<1) XSP+(offset<<2) *SP(offset) XSP+offset XSP+offset
7.5.4.3 Register ID Direct Addressing Mode

The register ID direct addressing mode is used in the same way in byte- and
word-pointer modes. See Section 6.4.4 for more details.
7.5.4.4 Register Bits Direct Addressing Mode

The register-bit direct addressing mode is used in the same way in byte- and
word-pointer modes. See Section 6.4.5 for more details.
7.5.5 Indirect Addressing Modes

The C55x+ supports the same indirect addressing modes in byte- and word-
pointer modes: XAR indirect addressing mode, dual XAR indirect addressing
mode, and the coefficient indirect addressing mode.
7.5.5.1 XAR Indirect Addressing Mode to Data Space

The XAR indirect operands for XAR indirect addressing mode to data space
are different between word- and byte-pointer modes. (See Table 6−3 for the
list of indirect operands in word-pointer mode.)
In byte-pointer mode, C54CM is always 0 (see Section 7.11 for more details):
*(ARn+AR0), *(ARn−AR0), ARn(AR0), *(ARn+AR0B), and *(ARn−AR0B) in-
direct operands are not available.
In byte-pointer mode, when an operand specifies an offset for the XAR indirect
addressing mode, this offset is scaled according to the size of the referenced
element (8-, 16-, or 32-bit). Table 7−7 lists the syntax differences for the follow-
ing indirect operands: *ARn[#K16], *+ARn[#K16], *ARn(short[#k4]),
*ARn(#K16), *+ARn(#K16), and *ARn(short(#k4)).
In byte-pointer mode, when the XAR indirect addressing mode accesses data
space, the selected 24-bit extended auxiliary register, XARn, contains a 24-bit
effective byte address.
Table 7−7 lists the address index/offset scaling for the address calculation
when these operands are used. This table also gives you the correspondence

and difference between the byte- and word-pointer modes for the operand
syntax and address calculation.
Table 7−7. XAR Indirect Addressing Mode Scaling Differences Between

Byte- and Word-Pointer Modes
dbl(Smem) dbl(Smem)
HI(Smem) HI(Smem)
*ARn 0 0 0 0 0
*ARn+ +1 +2 +4 +1 +2
*ARn− −1 −2 −4 −1 −2
*+ARn +1 +2 +4 +1 +2
*−ARn −1 −2 −4 −1 −2
*(ARn + Tx) +Tx +(Tx << 1) +(Tx << 2) +Tx +Tx
*(ARn − Tx) −Tx −(Tx <<1) −(Tx <<2) −Tx −Tx
*ARn(Tx) +Tx +(Tx << 1) +(Tx << 2) +Tx +Tx
*(ARn − T0B) −T0 −(T0<< 1) −(T0<< 2) −T0 −T0
*(ARn + T0B) +T0 +(T0 << 1) +(T0 << 2) +T0 +T0
*ARn[#K16] +k16 +(k16 << 1) +(k16 << 2) +k16 +k16
*+ARn[#K16] +k16 +(k16 << 1) +(k16 << 2) +k16 +k16
*ARn(short[#k4]) +k4 +(k4 << 1) +(k4 << 2) +k4 +k4
*ARn(XAR15[23:4]) N/A +((XAR15>> 4) <<1) N/A XAR15>> 4 N/A
Note: Tx can be the T0, T1, T2, or T3 register.
7.5.5.2 XAR Indirect Accesses to Register Bits
The XAR indirect addressing mode to register bits is used in the same way in
byte- and word-pointer modes. See Section 6.5.1.2 for more details.
7.5.5.3 Dual XAR Indirect Addressing Mode
The dual XAR indirect operands for dual XAR indirect addressing mode to data
space are different in word- and byte-pointer modes (see Table 6−4 for the list
of indirect operands in the word-pointer mode).
In the byte-pointer mode, C54CM is always 0 (see Section 7.11 for more de-
tails); *(ARn+AR0), *(ARn−AR0), and ARn(AR0) indirect operands are not
available.

In the byte-pointer mode, when an operand specifies an offset for the XAR dual
indirect addressing mode, this offset is scaled according to the size of the refer-
enced element (8-, 16-, or 32-bit).
In the byte-pointer mode, when the dual XAR indirect addressing mode ac-
cesses data space, the selected 24-bit extended auxiliary register, XARn, con-
tains a 24-bit effective byte address.
Table 7−8. Dual XAR Indirect Addressing Mode Scaling Differences

dbl(Smem) dbl(Smem)
dbl(Cmem) dbl(Cmem)
Smem HI(Smem) Smem HI(Smem)
Xmem LO(Smem) Xmem LO(Smem)
byte(Smem) Ymem HI(Cmem) Ymem HI(Cmem)
Operands byte(Ymem) Cmem LO(Cmem) Cmem LO(Cmem)
*ARn 0 0 0 0 0
*ARn+ +1 +2 +4 +1 +2
*ARn− −1 −2 −4 −1 −2
*ARn(T0) +T0 +(T0<< 1) +(T0<< 2) +T0 +T0
Note: Tx can be the T0 or T1 register.
7.5.6 (Single/Long) Coefficient Indirect Addressing Mode

The coefficient indirect operands for the coefficient indirect addressing mode
to data space are different between the word- and byte-pointer modes (see
Table 6−4 for the list of the indirect operands in the word-pointer mode).
available.
In the byte-pointer mode, when an operand specifies an offset for the coeffi-
cient indirect addressing mode, this offset is scaled according to the size of the
referenced element (16- or 32-bit).

In the byte-pointer mode, when the coefficient indirect addressing mode ac-
cesses the data space, the selected 24-bit extended auxiliary register, XARn,
contains a 24-bit effective byte address.
when these operands are used. This table also gives you the difference be-
tween byte and word modes for the address calculation.

Addressing Data Memory
7.6 Addressing Data Memory
7.6.1 Absolute Addressing Mode

In byte-pointer mode, you can use the k16 or k24 absolute addressing mode
described in Section 7.5.3 in any instruction having one of the following syntax
elements:
byte(Smem) Indicates one byte (8 bits) of data
Table 7−9 describes the absolute address computations (see Table 7−4 for
address computation).
Table 7−9. *abs(k16) Used For Data-Memory Access in Byte-Pointer Mode

Generated Address
Syntax Example Instruction Example For DPH = 03h Description
Ra = byte(Smem) T2 = byte(*abs16(#0005h)) DPH:k16 = 03 0005h The CPU loads the value at address 03 0005h
into T2.
Ra = Smem T2 = *abs16(#0004h) DPH:k16 = 03 0004h The CPU loads the value at addresses
03 0004h:03 0005h (but only the 03 0004h
address is generated) into T2.
Ra = HI(Smem), T2 = HI(*abs16(#2020h)), DPH:k16 = 03 2020h The CPU reads the values at addresses
Ra+1 = LO(Smem) ¶ T3 = LO(*abs16(#2020h)) 03 2020h:03 2021h and 03 2022h:03 2023h
(but only the 03 2020h address is generated)
and copies them into T2 and T3, respectively.
Table 7−10. *(k24) Used For Data-Memory Access in Byte-Pointer Mode

Ra = byte(Smem) T2 = byte(*(#030005h)) k24 = 03 0005h The CPU loads the value at address 03 0005h into
T2.
Ra = Smem T2 = *(#030004h) k24 = 03 0004h The CPU loads the value at addresses
03 0004h:03 0005h (but only the 03 0004h
address is generated) into T2.
Ra = HI(Smem), T2 = HI(*(#032020h)), k24 = 03 2020h The CPU reads the values at addresses
Ra+1 = LO(Smem) ¶ T3 = LO(*(#032020h)) 03 2020h:03 2021h and 03 2022h:03 2023h (but
only the 03 2020h address is generated) and
copies them into T2 and T3, respectively.

Direct Addressing Mode
7.6.2 Direct Addressing Mode

In the byte-pointer mode, you can use the direct addressing modes described
in Section 7.5.4 in any instruction having one of the following syntax elements:
Depending on which operand syntax is used, the XDP direct operand @Daddr,
the XSP direct operand *SP(offset), or the register ID direct operand
mmap(@registerID), the address computation is different. Table 7−11 through
Table 7−13 provide examples of how to use these addressing modes (see
Table 7−4 through Table 7−6 for details on index/offset scaling).
Table 7−11. @Daddr Used For Data-Memory Access in Byte-Pointer Mode

Generated Address
Syntax Example Instruction Example For XDP = 03 0010h = .dp Description
Ra = byte(Smem) T2 = byte(@030015h) XDP + Doffset The CPU loads the value at address
= 03 0010h + 05h 03 0015h into T2.
= 03 0015h
Ra = Smem T2 = @030014h XDP + (Doffset <<1) The CPU shifts Doffset 02h by 1 to the MSBs
= 03 0010h + (02h<<1) and adds it to XDP to construct an address
= 03 0014h (03 0014h) which is generated. The CPU
reads the value at addresses
03 0014h:03 0015h and loads the value into
T2.
Ra = HI(Smem), T2 = HI(@030020h), XDP + (Doffset<<2) The CPU reads the values at addresses
Ra+1 = LO(Smem) ¶ T3 = LO(@030020h) = 03 0010h + (04h<<2) 03 0020h:03 0021h and 03 0022h:03 0023h
= 03 0020h (but only 03 0020h is generated) and loads
the values into T2 and T3, respectively.

Table 7−12. *SP[offset] Used For Data-Memory Access in Byte-Pointer Mode

Generated Address
Syntax Example Instruction Example For XSP = 00 FF00h Description
Ra = byte(Smem) T2 = byte(*SP[5]) XSP + offset The CPU loads the value at address 00 FF05h
= 00 FF00h + 05h into T2.
= 00 FF05h
Ra = Smem T2 = *SP[5] XSP + (offset<<1) The CPU shifts offset 05h by 1 to the MSBs and
= 00 FF00h + (05h << 1) adds it to XSP to construct an address
= 00 FF0Ah (00 FF0Ah) which is generated. The CPU reads
the value at addresses 00 FF0Ah:00 FF0Bh and
loads the value into T2.
Ra = HI(Smem), T2 = HI(*SP[4]), XSP + (offset<<2) The CPU reads the values at addresses
Ra+1 = LO(Smem) ¶ T3 = LO(*SP[4]) = 00 FF00h + (04h << 2) 00 FF10h:00 FF11h and 00 FF12h:00 FF13h
= 00 FF10h (but only the 00 FF10h address is generated) and
loads the values into T2 and T3, respectively.
Table 7−13. @(RegisterID) Used for CPU Register Access in Byte-Pointer Mode
Ra = byte(Smem) AR8 = byte(mmap(@AC14.L)) Register ID access through The CPU loads the 8 LSBs of
6Eh Register ID address AC14 accumulator into AR8.
Ra = Smem AR8 = mmap(@AC14.L) Register ID access through The CPU loads the 16 LSBs of
6Eh Register ID address AC14 accumulator into AR8.
Ra = HI(Smem), T2 = HI(mmap(@AC14)), Register ID access through The CPU load the 16 LSBs of
Ra+1 = LO(Smem) ¶ T3 = LO(mmap(AC14)) 0Eh Register ID address AC14 accumulators into T3 and
the 16 MSBs of AC14 into T2.
7.6.3 Indirect Addressing Mode

In the byte-pointer mode, you can use the indirect addressing operand de-
scribed in Section 7.5.5 in any instruction having one of the syntax elements
described in Table 7−14.
Examples on how the addresses are generated are shown in the following sec-
tions (see Table 7−7 and Table 7−8 for more detail on index scaling).

Table 7−14. Indirect Operands for Data Memory in Byte-Pointer Mode
byte(Smem) byte(Smem) indicates one byte XAR indirect addressing mode:

Smem (8 bits) of data. *ARn
dbl(Smem) Smem indicates one word (16 bits) of *ARn+
HI(Smem)/LO(Smem) data. *ARn−
dbl(Smem) and HI(Smem)/LO(Smem) *+ARn
indicate one long word (32 bits) of *−ARn
data. *(ARn + Tx) (Tx can be T0, T1, T2, or T3)
*(ARn − Tx)
*ARn(Tx)
*(ARn + T0B)
*(ARn − T0B)
*ARn[#K16]
*+ARn[#K16]
*ARn(short[#k4])
*ARn(XAR15[23:4]) †
byte(Ymem) byte(Ymem) indicates one byte Dual XAR / Coefficient indirect addressing
Xmem, Ymem (8 bits) of data. mode:
dbl(Ymem) Xmem, Ymem indicate one word *ARn
HI(Cmem)/LO(Cmem) (16 bits) of data. *ARn+
dbl(Ymem) and HI(Cmem)/LO(Cmem) *ARn−
indicate one long word (32 bits) of *(ARn + T0)
data. *(ARn − T0)
*ARn(T0)
*(ARn + T1)
*(ARn − T1)
† It is applicable for the following instructions only:

copy(ALLa = Smem), Smem = ALLa, XDa = mar(Smem).

7.6.3.1 *ARn Used For Data-Memory Access
Operand Description
*ARn Generated address in linear mode: XARn


Ra = byte(Smem) T2 = byte(*AR4) XAR4 The CPU reads the value at address 01 FFFFh
Assume XAR4 = 01 FFFFh and loads it into T2. XAR4 is not modified.
Ra = Smem T2 = *AR4 XAR4 The CPU reads the value at addresses

Assume XAR4 = 01 FFFEh 01 FFFEh:01 FFFFh and loads it into T2. XAR4 is
not modified.
Ra = HI(Smem), T2 = HI(*AR4), XAR4 The CPU reads the values at addresses

Ra+1 = LO(Smem) ¶ T3 = LO(*AR4) Assume XAR4 = 01 FFFCh 01 FFFCh:01 FFFDh and 01 FFFEh:01 FFFFh
(but only the 01 FFFCh address is generated) and
loads them into T2 and T3, respectively. XAR4 is
not modified.

7.6.3.2 *ARn+, *ARn− Used For Data-Memory Access
Operand Description
*ARn+ Generated address in linear mode: XARn

*ARn− Generated address in linear mode: XARn


Ra = byte(Smem) T2 = byte(*AR4+) XAR4 The CPU reads the value at address 01 FFFFh
Assume XAR4 = 01 FFFFh and loads it into T2. After being used for the
address generation, XAR4 is incremented by 1.
Ra = Smem T2 = *AR4+ XAR4 The CPU reads the value at addresses

Assume XAR4 = 01 FFFEh 01 FFFEh:01 FFFFh and loads it into T2. After
being used for the address generation, XAR4 is
incremented by 2.
Ra = HI(Smem), T2 = HI(*AR4+), XAR4 The CPU reads the values at addresses

Ra+1 = LO(Smem) ¶ T3 = LO(*AR4+) Assume XAR4 = 01 FFFCh 01 FFFCh:01 FFFDh and 01 FFFEh:01 FFFFh
(but only the 01 FFFCh address is generated) and
loads them into T2 and T3, respectively. After
being used for the address generation, XAR4 is
incremented by 4.

7.6.3.3 *+ARn, *−ARn Used For Data-Memory Access
Operand Description
*+ARn Generated address in linear mode: If 8-bit access: XARn + 1

Generated address in circular mode: If 8-bit access: (ARnH:BSAyy) + (00:ARn) + 1
*−ARn Generated address in linear mode: If 8-bit access: XARn − 1

Generated address in circular mode: If 8-bit access: (ARnH:BSAyy) + (00:ARn) − 1

Ra = byte(Smem) T2 = byte(*−AR4) XAR4 − 1 Before being used for the address generation,
Assume XAR4 = 02 0000h XAR4 is decremented by 1. The CPU reads the
value at address 01 FFFFh and loads it into T2.
Ra = Smem T2 = *−AR4 XAR4 − 2 Before being used for the address generation,
Assume XAR4 = 02 0000h XAR4 is decremented by 2. The CPU reads the
value at addresses 01 FFFEh:01 FFFFh and
loads it into T2.
Ra = HI(Smem), T2 = HI(*−AR4), XAR4 − 4 Before being used for the address generation,
Ra+1 = LO(Smem) ¶ T3 = LO(*−AR4) Assume XAR4 = 02 0000h XAR4 is decremented by 4. The CPU reads the
values at addresses 01 FFFCh:01 FFFDh and
01 FFFEh:01 FFFFh (but only the 01 FFFCh
address is generated) and loads them into T2
and T3, respectively.

7.6.3.4 *(ARn + Tx), *(ARn − Tx) (Tx =T0, T1, T2, or T3) Used For Data-Memory Access
Operand Description
*(ARn + Tx) Generated address in linear mode: XARn

XARn modification: If 8-bit access: XARn = XARn + Tx
If 16-bit access: XARn = XARn + (Tx<<1)
Tx is a 16-bit signed value. Tx can be T0, T1, T2, or T3.
*(ARn − Tx) Generated address in linear mode: XARn

XARn modification: If 8-bit access: XARn = XARn − Tx
If 16-bit access: XARn = XARn − (Tx<<1)

(Linear Addressing)
Ra = byte(Smem) AR3 = byte(*(AR7 + T2)) XAR7 The CPU reads the value at address
Assume XAR7 = 01 FFFFh 01 FFFFh and loads it into AR3. After be-
ing used for the address generation, XAR7
is incremented by the number in T2.
Ra = Smem AR3 = *(AR7 + T1) XAR7 The CPU reads the value at addresses
Assume XAR7 = 01 FFFEh 01 FFFEh:01 FFFFh and loads it into AR3.
After being used for the address genera-
tion, XAR7 is incremented by (T1 << 1).
Ra = HI(Smem), AR2 = HI(*(AR5 − T3)), XAR5 The CPU reads the values at addresses
Ra+1 = LO(Smem) ¶ AR3 = LO(*(AR5 − T3)) Assume XAR7 = 01 FFFCh 01 FFFCh:01 FFFDh and
01 FFFEh:01 FFFFh (but only the
01 FFFCh address is generated) and
loads them into AR2 and AR3, respective-
ly. After being used for the address genera-
tion, XAR5 is decremented by (T3 << 2).

7.6.3.5 *ARn(Tx) (Tx =T0, T1, T2 or T3) Used For Data-Memory Access
Operand Description
*ARn(Tx) Generated address in linear mode: If 8-bit access: XARn + Tx

If 16-bit access: XARn + (Tx<<1)
Generated address in circular mode: If 8-bit access: (ARnH:BSAyy) + (00:ARn) + Tx
If 16-bit access: (ARnH:BSAyy) + (00:ARn) + (Tx<<1)
Tx is a 16-bit signed value added to the base pointer. Tx can be T0, T1, T2 or T3.

(Linear Addressing)
Ra = byte(Smem) AR3 = byte(*AR7(T3)) XAR7 + T3 The CPU reads the value at address
Assume XAR7 = 01FFFFh, 02 0000h and loads it into AR3. XAR7 is not
and T3 = 1 modified.
Ra = Smem AR3 = *AR7(T0) XAR7 +( T0<<1) The CPU reads the value at addresses
Assume XAR7 = 01FFFEh, 01 FFFCh:01 FFFDh and loads it into AR3.
and T0 = −1 XAR7 is not modified.
Ra = HI(Smem), AR2 = HI(*AR5(T1)), XAR5 + (T1<<2 ) The CPU reads the values at addresses
Ra+1 = LO(Smem) ¶ AR3 = LO(*AR5(T1)) Assume XAR5 = 01FFFCh, 02 0004h:02 0005h and 02 0006h:02 0007h
and T1 = 2 (but only the 02 0004h address is generated)
and loads them into AR2 and AR3, respective-
ly. XAR5 is not modified.

7.6.3.6 *(ARn + T0B), *(ARn − T0B) Used For Data-Memory Access
C54CM = 0 or 1 (.c54cm_off/on assembler directive has no effect in byte-pointer mode)

Operand Description
*(ARn + T0B) Generated address in linear mode: XARn

XARn modification: If 8-bit access: XARn = XARn + T0
If 16-bit access: XARn = XARn + (T0<<1)
If 32-bit access: XARn = XARn + (T0<<2)
(done with reverse carry propagation)
*(ARn – T0B) Generated address in linear mode: XARn

XARn modification: If 8-bit access: XARn = XARn − T0
If 16-bit access: XARn = XARn − (T0<<1)
If 32-bit access: XARn = XARn − (T0<<2)
(done with reverse carry propagation)
by the circular addressing computation.

(Linear Addressing)
Ra = byte(Smem) T2 = byte(*(AR10 + T0B)) XAR10 The CPU loads the value at address XAR10
into T2. After being used for the address gener-
ation, XAR10 is incremented by the number in
T0. Reverse carry propagation is used during
the addition.
Ra = Smem T2 = *(AR10 + T0B) XAR10 The CPU loads the value at address XAR10
into T2. After being used for the address gener-
ation, XAR10 is incremented by (T0<<1). Re-
verse carry propagation is used during the
addition.
Ra = HI(Smem), T2 = HI(*(AR10 + T0B)), XAR10 The CPU reads the values at address XAR10
Ra+1 = LO(Smem) ¶ T3 = LO(*(AR10 + T0B)) and the following word address (XAR10 + 2),
and loads them into T2 and T3, respectively.
After being used for the address generation,
XAR10 is incremented by (T0<<2). Reverse
carry propagation is used during the addition.

7.6.3.7 *ARn[#K16], *+ARn[#K16] Used For Data-Memory Access
Operand Description
*ARn[#K16] Generated address in linear mode: If 8-bit access: XARn + K16
If 16-bit access: XARn + (K16<<1)
Generated address in circular mode: If 8-bit access: (ARnH:BSAyy) + (00:ARn) + K16
If 16-bit access: (ARnH:BSAyy) + (00:ARn) + (K16<<1)
XARn is not modified. XARn is used as a base pointer. The 16-bit signed constant (K16) is 24-bit sign
extended before being scaled and added to the base pointer.
*+ARn[#K16] Generated address in linear mode: If 8-bit access: XARn + K16

Generated address in circular mode: If 8-bit access: (ARnH:BSAyy) + (00:ARn) + K16
XARn modification: If 8-bit access: XARn = XARn + K16
If 16-bit access: XARn = XARn + (K16<<1)
The 16-bit signed constant (K16) is 24-bit sign extended and scaled before being added.
Generated Address
Ra = byte(Smem) AR3 = byte(*AR12[#8]) XAR12 + 8 The CPU reads the value at address
Assume XAR12 = 01FF00h 01 FF08h and loads it into AR3. XAR12 is not
modified.
Ra = Smem AR3 = *AR12[#8] XAR12 + (8<<1) The CPU reads the value at addresses
Assume XAR12 = 01FF00h 01 FF10h:01 FF11h and loads it into AR3.
Ra = HI(Smem), AR2 = HI(*+AR5[#8]), XAR5 +( 8<<2) Before being used for the address generation,
Ra+1 = LO(Smem) ¶ AR3 = LO(*+AR5[#8]) Assume XAR12 = 01FF00h XAR12 is incremented by (8<<2). The CPU
reads the values at addresses
01 FF20h:01 FF21h and 01 FF22h:01 FF23h
and loads them into AR2 and AR3, respective-
ly.

7.6.3.8 *ARn(short[#k4]) Used For Data-Memory Access
Operand Description
*ARn(short[#k4]) Generated address in linear mode: If 8-bit access: XARn + k4
If 16-bit access: XARn + (k4<<1)
Generated address in circular mode: If 8-bit access: (ARnH:BSAyy) + (00:ARn) + k4
If 16-bit access: (ARnH:BSAyy) + (00:ARn) + (k4<<1)
If 32-bit access: (ARnH:BSAyy) + (00:ARn) + (k4<<2)
XARn is not modified. XARn is used as a base pointer. The 4-bit unsigned constant (k4) is zero ex-
tended to 24 bits before being scaled and added to the base pointer. k4 can be a number from 0 to
15.

(Linear Addressing)
Ra = byte(Smem) AR3 = byte(*AR7(short[#1])) XAR7 + 1 The CPU reads the value at address
Assume XAR7 = 01FF00h 01 FF01h and loads it into AR3. XAR7 is
not modified.
Ra = Smem AR3 = *AR7(short[#1]) XAR7 + (1<<1) The CPU reads the value at addresses
Assume XAR7 = 01FF00h 01 FF02h:01 FF03h and loads it into
AR3. XAR7 is not modified.
Ra = HI(Smem), AR2 = HI(*AR5(short[#1])), XAR5 + (1<<2) The CPU reads the values at addresses
Ra+1 = LO(Smem) ¶ AR3 = LO(*AR5(short[#1])) Assume XAR7 = 01FF00h 01 FF04h:01 FF05h and
01 FF06h:01 FF07h (but only the
01 FF04h address is generated) and
loads them into AR2 and AR3, respec-
tively. XAR5 is not modified.
7.6.3.9 *ARn(XAR15[23:4]) Used For Data-Memory Access in Byte Addressing Mode
Operand Description
*ARn(XAR15[23:4]) Address generated in linear mode: XARn + (XAR15[23:4] << 1)
Address generated in circular mode: (ARnH:BSAyy) + (00:ARn) + (XAR15[23:4] << 1)
XARn is not modified. XARn is used as a base pointer. XAR15 has to be a positive value for this
addressing mode. The 20 bits from bit 4 to bit 23 of the XAR15 register is 24-bit zero extended
and is used as an unsigned offset from that base pointer: the offset is shifted to the MSBs by one
bit according to the alignment rules described in Section 7.2.3. This offset addressing mode
supports the C55x+ field insert/extract instructions. This operand can be used only with 16-bit
load/store/mar() instructions. It cannot be used with any other instructions.
NOTE: byte(Smem) and dbl(Smem) addressing modes are not available with
*ARn(XAR15[23:4]) operand in byte-pointer mode.

(Linear Addressing)
Ra = Smem AC0.L = *AR1(XAR15[23:4]) XAR1 + (XAR15[23:4] << 1) The CPU reads the value at address
Assume XAR15 = 72, then XAR1 + (4 << 1) and loads it into AC0.L.
XAR15[23:4] = 4 XAR1 is not modified.

7.6.4 Addressing Register Bits (Baddr)

Direct addressing and indirect addressing can address individual or pair
register bits. See Section 6.8 for more details.
7.6.4.1 Register-Bit Direct Addressing Mode
The register-bit direct operand @bit_position accesses a register bit in

instructions having the Baddr syntax element. It is used the same way in both
byte- and word-pointer modes. See Section 6.8.1 for details.
7.6.4.2 Register-Bit Indirect Addressing Mode
With instructions having the Baddr syntax element, you can use the indirect
operands to access register bits. As Baddr indicates directly the address of
one bit of data to access, only the byte(Smem) addressing mode can be used
for the register-bit indirect addressing mode in the byte-pointer mode. See
Section 6.8.2 for details on indirect operands.

I/O and xI/O Addressing Modes Description
7.7 I/O and xI/O Addressing Modes Description

This section describes the differences for I/O and xI/O address computation
between the byte- and word-pointer modes.
In the byte-pointer mode, the C55x+ DSP supports the same xIO address-
ing modes as the ones described in Section 6.9; the absolute, direct, and
indirect addressing modes are available to access xI/O space. See Sec-
tion 7.7.1 for the description of these addressing modes.
In the byte-pointer mode, the C55x+ DSP supports the same absolute and
indirect I/O addressing modes as the ones described in Section 6.9. See
Section 7.7.1 for the description of these addressing modes. Note that
PDP direct addressing is not available in the byte-pointer mode.
In the byte-pointer mode, the same qualifiers as in the word-pointer mode

are used to access the I/O − xI/O spaces:
− The volatile() qualifier is used for the xI/O addressing modes
− The port() qualifier is used for the I/O addressing modes
Using those qualifiers with an instruction adds a one byte extension to the
instruction.
In the byte-pointer mode, the restrictions/exceptions on accesses to the

I/O and xI/O spaces are different from the ones in word-pointer mode, see
Section 7.9 for more details.
7.7.1 I/O − xI/O Absolute Addressing Modes
7.7.1.1 k24 Absolute I/O Addressing Mode
The assembler syntax of the k24 absolute I/O addressing mode is the same
for both byte- and word-pointer modes (*port(#k24)); except that in byte-point-
er mode, the I/O address is specified with a 24-bit unsigned constant k24.

Note:
When this addressing mode is used, k24 must specify a valid I/O space ad-
dress (00 0000h − 01 FFFFh); in the case it is not, the CPU behavior is unde-
fined.
The k16 absolute I/O addressing mode is not available in the byte-pointer
mode. See Section 6.9.1.1 for more details on the k16 absolute addressing
mode in word-pointer mode.

7.7.1.2 xI/O Absolute Addressing Mode

The k16 absolute xI/O addressing mode and the k24 absolute xI/O addressing
mode have the same assembly syntax in the byte- and word-pointer modes.
See Sections 6.9.1.2 and 6.9.1.3 for more details on the assembly syntax.
The address generation is also computed the same way in byte- or word-point-
er modes. The only difference is:
In the byte-pointer mode, the 24 bits of the generated address are used
In the word-pointer mode, the 23 LSBs of the generated address are used
7.7.2 I/O − xI/O Direct Addressing Modes
Note:
In the byte-pointer mode, the PDP direct I/O addressing mode is not avail-
able. See Section 6.9.2.1 for more details on this addressing mode in the
word-pointer mode.
7.7.2.1 XDP Direct xI/O Addressing Mode

The assembler syntax of the XDP xI/O direct addressing mode is identical in
the byte- and word-pointer modes. See Section 6.9.2.2 for more details on the
assembly syntax.
The computation process of the XDP xI/O address is the same as the one de-
scribed for the XDP direct addressing mode in Section 7.5.4.1. See Table 7−4
and Table 7−5 for more details.
7.7.3 XAR Indirect I/O − xI/O Addressing Modes

The C55x+ supports the same indirect addressing modes in the byte- and
word-pointer modes: the XAR indirect addressing mode, the dual XAR indirect
addressing mode, and the coefficient indirect addressing mode.
7.7.3.1 XAR Indirect Addressing Mode to I/O Space

The XAR indirect operands for the XAR indirect addressing mode to I/O space
are different between the word- and byte-pointer modes (see Table 6−20 for
the list of the indirect operands in the word-pointer mode).
available.

In the byte-pointer mode, when an operand specifies an offset for the XAR
indirect addressing mode, this offset is scaled according to the size of the
referenced element (8 or 16 bits). Table 7−15 lists the syntax differences for
the following indirect operands: *ARn[#K16], *+ARn[#K16], *ARn(short[#k4]),
In the byte-pointer mode, only the 17 LSBs of the generated XAR indirect
address are used to address the I/O space. This is different from the
word-pointer mode where only the 16 LSBs of the generated XAR indirect
address are used to address the I/O space.
Note:
Although an increment past 01 FFFFh or a decrement past 00 0000h causes
the XAR indirect I/O address to wrap around, do not make use of this behav-
ior. It is not supported. Also during circular addressing, the BSAxx addition
must not increment the address beyond 01 FFFFh (see Section 6.12 for
more details on circular addressing).
Table 7−15. XAR I/O Indirect Addressing Mode Scaling Differences

Operands byte(Smem) Smem Operands Smem

*ARn 0 0 *ARn 0
*ARn+ +1 +2 *ARn+ +1
*ARn− −1 −2 *ARn− −1
*+ARn +1 +2 *+ARn +1
*−ARn −1 −2 *−ARn −1
*(ARn + Tx) +Tx +(Tx << 1) *(ARn + Tx) +Tx
*(ARn − Tx) −Tx −(Tx <<1) *(ARn − Tx) −Tx
*ARn(Tx) +Tx +(Tx << 1) *ARn(Tx) +Tx
*ARn[#K16] +k16 +(k16 << 1) *ARn(#K16) +k16
*+ARn[#K16] +k16 +(k16 << 1) *+ARn(#K16) +k16
*ARn(short[#k4]) +k4 +(k4 << 1) *ARn(short(#k4)) +k4

7.7.3.2 XAR Indirect Access to xI/O Space
The XAR indirect operands for the XAR indirect addressing mode to xI/O
space are different in the word- and byte-pointer modes (see Table 6−21 for
the list of indirect operands in word-pointer mode).
available.
In the byte-pointer mode, when an operand specifies an offset for the XAR indi-
rect addressing mode, this offset is scaled according to the size of the refer-
enced element (8, 16, or 32 bits). Table 7−16 lists the syntax differences for
the following indirect operands: *ARn[#K16], *+ARn[#K16], *ARn(short[#k4]),
and difference between byte- and word-pointer modes for the operand syntax
and address calculation.
In the byte-pointer mode, the whole 24 bits of the generated XAR indirect ad-
dress are used to address the xI/O space. This is different from the word-point-
er mode where only the 23 LSBs of the generated XAR indirect address are
used to address the xI/O space.

Table 7−16. XAR xI/O Indirect Addressing Mode Scaling Differences

dbl(Smem) dbl(Smem)
HI(Smem) HI(Smem)
*ARn 0 0 0 0 0
*ARn+ +1 +2 +4 +1 +2
*ARn− −1 −2 −4 −1 −2
*+ARn +1 +2 +4 +1 +2
*−ARn −1 −2 −4 −1 −2
*ARn(Tx) +Tx +(Tx << 1) +(Tx << 2) +Tx +Tx
*ARn[#K16] +k16 +(k16 << 1) +(k16 << 2) +k16 +k16
*+ARn[#K16] +k16 +(k16 << 1) +(k16 << 2) +k16 +k16
*ARn(short[#k4]) +k4 +(k4 << 1) +(k4 << 2) +k4 +k4

7.8 Addressing I/O and xI/O Spaces

The absolute addressing modes (described in Section 7.7.1), direct address-
ing modes (described in Section 7.7.2), and indirect addressing mode (de-
scribed in Section 7.7.3) can address the peripheral registers in the I/O and
xI/O spaces in the byte-pointer mode. The following sections provide some ex-
amples for the I/O − xI/O addressing modes.
There are some restrictions/exceptions on accesses to the I/O and xI/O

7.8.1 Addressing I/O Space with the I/O Absolute Addressing Mode
In the byte-pointer mode, to access the I/O space with the k24 absolute I/O
addressing mode, you can use *port(#k24) in instructions having the following
syntax element:
Table 7−17 provides some examples of I/O space accesses with the absolute
addressing mode.
Table 7−17. k24 Absolute Addressing Mode Used for I/O Spaces Access
Ra = byte(Smem) AR2 = *port(byte(#000003h)) k24 = 00 0003h The CPU truncates the generated address to its
16 LSBs and loads the value at the I/O address
0003h into AR2.
Smem = ALLa *port(#00F002h) = AR0 k24 = 00 F002h The CPU truncates the generated address to its
16 LSBs and stores the content of AR0 into I/O
addresses F002h:F003h.
7.8.2 Addressing xI/O Space with xI/O Absolute Addressing Modes

In the byte-pointer mode, to access xI/O space with the k16 or k24 absolute
xI/O addressing mode, you can use volatile(*abs16(#k16)) or volatile(*(#k24))
in instructions using the following syntax elements:

Table 7−18 and Table 7−19 provide some examples of the xI/O space ac-
cesses with the k16 and k24 absolute xI/O addressing modes.
Table 7−18. k16 Absolute Addressing Mode Used For xI/O-Space Access

DPH = 03h
Ra = byte(Smem) AR2 = volatile(byte(*abs16(#0003))) DPH:k16 = 03 0003h The CPU loads the value at xI/O ad-
dress 03 0003h into AR2.
Smem = ALLa volatile(*abs16(#F002h)) = AR0 DPH:k16 = 03 F002h The CPU stores the content of AR0 into
xI/O addresses 03 F002h: F003h.
Table 7−19. k24 Absolute Addressing Mode Used For xI/O-Space Access

Ra = byte(Smem) AR2 = volatile(byte(#040003h)) k24 = 040003h The CPU loads the value at xI/O address
04 0003h into AR2.
dbl(Smem) = ALLa volatile(dbl(#03F004h)) = XAR0 k24 = 03F004h The CPU stores the content of XAR0 into xI/O
addresses 03 F004h − 03 F007h.
7.8.3 Addressing xI/O Spaces with Direct Addressing Mode
7.8.3.1 Addressing xI/O Space with XDP Direct Addressing Mode
In the byte-pointer mode, to access the xI/O space with the XDP direct xI/O
addressing mode, you can use volatile(@Daddr) operand in instructions hav-
ing the following syntax element:
Table 7−20 provides examples on the XDP direct addressing mode accessing
I/O space.

Table 7−20. @Daddr Used For xI/O Space Access

Generated Address
Syntax Example Instruction Example For XDP = 00 0010h = .dp Description
Ra = byte(Smem) T2 = volatile(byte(@000014h)) XDP + Doffset The CPU adds Doffset to XDP to

= 00 0010h + 04h construct an address (00 0014h) which
= 00 0014h is generated. The CPU reads the value
at xI/O address 00 0014h and loads it
into T2.
Smem = ALLa volatile(@000014h) = T2 XDP + (Doffset<<1) The CPU shifts Doffset by one to the
= 00 0010h + (0002h<<1) MSBs and adds it to XDP to construct
= 00 0014h an address (00 0014h) which is gener-
ated. The CPU reads the content of T2
and writes it to xI/O addresses
00 0014h:00 0015h.
Ra = HI(Smem), T2 = volatile(HI(@000020h)). XDP + (Doffset<<2) The CPU reads the values at xI/O
Ra+1 = T3 = volatile(LO(@000020h)) = 00 0010h + (0004h<<2) addresses 00 0020h:00 0021h and
LO(Smem) = 00 0020h 00 0022h:00 0023h (but only the
00 0020h address is generated) and
loads it into T2 and T3, respectively.
7.8.4 Addressing I/O − xI/O Spaces with Indirect Addressing Mode

In the byte-pointer mode, to access the I/O space with the XAR indirect I/O ad-
dressing mode, you can use an indirect operand with port() qualifier in instruc-
tions having one of the syntax element described in Table 7−21.
In the byte-pointer mode, to access the xI/O space with the XAR indirect xI/O
addressing mode, you can use an indirect operand with volatile() qualifier in
instructions having one of the syntax element described in Table 7−22.
Note:
In the byte-pointer mode, only the 17 LSBs of the 24-bit indirect address is
used for an I/O access, whereas the whole 24 bits are used for an xI/O ac-
cess.

Table 7−21. Indirect Operands For I/O Space Access in Byte-Pointer Mode
byte(Smem) byte(Smem) indicates one byte (8 bits) of XAR indirect addressing mode to I/O:
Smem data *ARn
Smem indicates one word (16 bits) of *ARn+
data. *ARn−
*+ARn
*−ARn
*(ARn + Tx) (Tx can be T0, T1, T2, or T3)
*(ARn, − Tx)
*ARn(Tx)
*ARn[#K16]
*+ARn[#K16]
*ARn(short[#k4])
Table 7−22. Indirect Operands For xI/O Space Access in Byte-Pointer Mode
byte(Smem) byte(Smem) indicates one byte (8 bits) XAR indirect addressing mode to xI/O:
Smem, of data *ARn
dbl(Smem) Smem indicates one word (16 bits) of *ARn+
HI(Smem)/LO(Smem) data. *ARn−
dbl(Smem) and HI(Smem)/LO(Smem) *+ARn
indicates one long word (32 bits) of data *−ARn
*(ARn + Tx) (Tx can be T0, T1, T2, or T3)
*(ARn − Tx)
*ARn(Tx)
*ARn[#K16]
*+ARn[#K16]
*ARn(short[#k4])

7.8.4.1 *ARn Used For I/O − xI/O Spaces Access
Operand Description
*ARn I/O − xI/O generated address in linear mode: XARn
Address Generated
Ra = byte(Smem) T2 = port(byte(*AR4)) XAR4 The CPU reads the value at I/O address
Assume XAR4 = 00FF80h FF80h and loads it into T2. XAR4 is not
modified.
Smem = ALLa port(*AR5) = T2 XAR5 The CPU reads the content of T2 and
Assume XAR5 = 00FFFEh writes it to I/O addresses FFFEh:FFFFh.
Ra = byte(Smem) T2 = volatile(byte(*AR4)) XAR4 The CPU reads the value at xI/O address
Assume XAR4 = 01FF80h 01 FF80h and loads it into T2. XAR4 is not
modified.
Ra = Smem T2 = volatile(*AR4) XAR4 The CPU reads the value at xI/O address
Assume XAR4 = 01FF80h 01 FF80h:01 FF81h and loads it into T2.
dbl(Smem) = volatile(dbl(*AR5)) = XAR2 XAR5 The CPU reads the content of XAR2 and
ALLa Assume XAR5 = 02FFFCh writes it to xI/O addresses 02 FFFCh −

7.8.4.2 *ARn+, *ARn− Used For I/O − xI/O Spaces Access
Operand Description
*ARn+ I/O − xI/O generated address in linear mode: XARn

Note: 32-bit access is only available for xI/O access.
*ARn− I/O − xI/O generated address in linear mode: XARn

Address Generated
Ra = byte(Smem) T2 = port(byte(*AR4+)) XAR4 The CPU reads the value at I/O address
Assume XAR4 = 00FF80h FF80h and loads it into T2. After being used
for the address generation, XAR4 is increm-
ented by 1.
Smem = Ra port(*AR5+) = T2 XAR5 The CPU reads the content of T2 and writes
Assume XAR5 = 00FFFEh it to I/O addresses FFFEh:FFFFh. After be-
ing used for the address generation, XAR5
is incremented by 2.
Ra = byte(Smem) T2 = volatile(byte(*AR4+)) XAR4 The CPU reads the value at xI/O address
Assume XAR4 = 01FF80h 01 FF80h and loads it into T2. After being
used for the address generation, XAR4 is in-
cremented by 1.
Ra = Smem T2 = volatile(*AR4+) XAR4 The CPU reads the value at xI/O addresses
Assume XAR4 = 01FF80h 01 FF80h:01 FF81h and loads it into T2. Af-
ter being used for the address generation,
XAR4 is incremented by 2.
dbl(Smem) = volatile(dbl(*AR5+)) = AC2 XAR5 The CPU reads the content of AC2 and
ALLa Assume XAR5 = 02FFFCh writes it to xI/O addresses 02 FFFCh −
02 FFFFh (but only the 02 FFFCh address
is generated). After being used for the ad-
dress generation, XAR5 is incremented by
4.

7.8.4.3 *+ARn, *−ARn Used For I/O − xI/O Spaces Access
Operand Description
*+ARn I/O − xI/O generated address in linear mode: If 8-bit access: XARn + 1
I/O − xI/O generated address in circular mode: If 8-bit access: (ARnH:BSAyy) + (00:ARn) + 1
*–ARn I/O − xI/O generated address in linear mode: If 8-bit access: XARn − 1
I/O − xI/O generated address in circular mode: If 8-bit access: (ARnH:BSAyy) + (00:ARn) − 1
Address Generated
Ra = byte(Smem) T2 = port(byte(+AR4)) XAR4 + 1 Before being used for the address genera-
Assume XAR4 = 00FFFFh tion, XAR4 is incremented by 1. The CPU
reads the value at I/O address 10000h and
loads it into T2.
Smem = Ra port(*−AR5) = T2 XAR5 − 2 Before being used for the address genera-
Assume XAR5 = 010000h tion, XAR5 is decremented by 2. The CPU
reads the content of T2 and writes it to I/O ad-
dresses FFFEh:FFFFh.
Ra = byte(Smem) T2 = volatile(byte(*+AR4)) XAR4 +1 Before being used for the address genera-
Assume XAR4 = 01FF7Fh tion, XAR4 is incremented by 1. The CPU
reads the value at xI/O address 01 FF80h
and loads it into T2.
Ra = Smem T2 = volatile(*+AR4) XAR4 +2 Before being used for the address genera-
Assume XAR4 = 01FF7Eh tion, XAR4 is incremented by 2. The CPU
reads the value at xI/O addresses
01 FF80h:01 FF81h and loads it into T2.
dbl(Smem) = volatile(dbl(*−AR5)) = AC2 XAR5 − 4 Before being used for the address genera-
ALLa Assume XAR5 = 030000h tion, XAR5 is decremented by 4. The CPU
reads the content of AC2 and writes it to xI/O
addresses 02 FFFCh − 02 FFFFh (but only
address 02 FFFCh is generated).

7.8.4.4 *(ARn + Tx), *(ARn − Tx), (Tx = T0, T1, T2 or T3) Used For I/O − xI/O Spaces Access
Operand Description
*(ARn + Tx) I/O − xI/O generated address in linear mode: XARn

XARn modification: If 8-bit access: XARn = XARn + Tx
*(ARn – Tx) I/O − xI/O generated address in linear mode: XARn

XARn modification: If 8-bit access: XARn = XARn − Tx
Address Generated
Ra = byte(Smem) AR3 = port(byte(*(AR7 + T1))) XAR7 The CPU reads the value at I/O ad-
Assume XAR7 = 00FF80h dress FF80h and loads it into AR3.
After being used for the address gen-
eration, XAR7 is incremented by the
number in T1.
Smem= ALLa port(*(AR5 + T2)) = AR4 XAR5 The CPU reads the content of AR4
Assume XAR5 = 00FFFEh and writes it to I/O address
FFFEh:FFFFh. After being used for
the address generation, XAR5 is in-
cremented by (T2<<1).
Ra = byte(Smem) AR3 = volatile(byte(*(AR9 − T1))) XAR9 The CPU reads the value at xI/O ad-
Assume XAR9 = 01FF81h dress 01 FF81h and loads it into
AR3. After being used for the ad-
dress, XAR9 is decremented by T1.
Ra = Smem AR3 = volatile(*(AR9 + T1)) XAR9 The CPU reads the value at xI/O ad-
Assume XAR9 = 01FF80h dresses 01 FF80h:01 FF81h and
loads it into AR3. After being used for
the address, XAR9 is incremented
by (T1<<1).
dbl(Smem) = volatile(dbl(*AR10 + T3)) = XAR0 XAR10 The CPU reads the content of XAR0
ALLa Assume XAR10 = 02FFFCh and writes it to xI/O address
02 FFFCh − 02 FFFFh (but only the
02 FFFCh address is generated). Af-
ter being used for the address gener-
ation, XAR10 is incremented by
(T3<<2).

7.8.4.5 *ARn(Tx) (Tx =T0, T1, T2, T3) Used For I/O − xI/O Spaces Access
Operand Description
*ARn(Tx) I/O − xI/O generated address in linear mode: If 8-bit access: XARn + Tx
I/O − xI/O generated address in circular mode: If 8-bit access: (ARnH:BSAyy) + (00:ARn) + Tx
Tx is a 16-bit signed value scaled and added to the base pointer. Tx can be T0, T1, T2 or T3.
Address Generated
Ra = byte(Smem) AR3 = port(byte(*AR7(T3))) XAR7 + T3 The CPU reads the value at I/O ad-
Assume XAR7 = FF7Dh dress FF80h and loads it into AR3.
and T3 = 3. XAR7 is not modified.
Smem = ALLa port(*AR5(T1)) = AR4 XAR5 + (T1<<1) The CPU reads the content of AR4 and
Assume XAR5 = FFFAh writes it to I/O addresses
and T1 = 4. 10002h:10003h. XAR5 is not modified.
Ra = byte(Smem) AR3 = volatile(byte(*AR9(T3))) XAR9 + T3 The CPU reads the value at xI/O ad-
Assume XAR4 = 01FFFEh dress 01 FFFDh and loads it into AR3.
and T3 = −1 XAR9 is not modified.
Ra = Smem AR3 = volatile(*AR9(T3)) XAR9 + (T3<<1) The CPU reads the value at xI/O ad-
Assume XAR4 = 01FFFEh dresses 01 FFFCh:01 FFFDh and
and T3 = −1 loads it into AR3. XAR9 is not modified.
dbl(Smem) = volatile(dbl(*AR10(T3))) = XAR0 XAR10 + (T3<<2) The CPU reads the content of XAR0
ALLa Assume XAR10 = 02FFFCh and writes it to xI/O addresses
and T3 = 2h 03 0004h − 03 0007h (but only the
03 0004h address is generated).

7.8.4.6 *ARn[#K16], *+ARn[#k16] Used For I/O − xI/O Space Access
Operand Description
*ARn[#K16] I/O − xI/O generated address in linear mode: If 8-bit access: XARn + K16
I/O − xI/O generated address in circular mode: If 8-bit access: (ARnH:BSAyy) + (00:ARn) + K16
XARn is not modified. XARn is used as a base pointer. The 16-bit signed constant (K16) is 24-bit sign
extended before being scaled and added to the base pointer.
*+ARn[#K16] I/O − xI/O generated address in linear mode: If 8-bit access: XARn + K16
I/O − xI/O generated address in circular mode: If 8-bit access: (ARnH:BSAyy) + (00:ARn) + K16
XARn modification: If 8-bit access: XARn = XARn + K16
The 16-bit signed constant (K16) is 24-bit sign extended before being scaled and added.

(Linear Addressing)
Ra = byte(Smem) AR3 = port(byte(*AR12[#8])) XAR12 + 8 The CPU reads the value at I/O ad-
Assume AR12 = FF08h dress FF10h and loads it into AR3.
Smem = ALLa port(*+AR8[#8]) = T1 XAR8 + (8<<1) Before being used for address gen-
Assume AR12 = FF00h eration, XAR8 is incremented by
(8<<1). The CPU reads the content
of T1 and writes it to I/O addresses
FF10h:FF11h.
Ra = byte(Smem) AR3 = volatile(byte(*AR12[#8])) XAR12 The CPU reads the value at xI/O ad-
Assume XAR12 = 02FF00h dress 02 FF08h and loads it into
Ra = Smem AR3 = volatile(*AR12[#8]) XAR12 + (8<<1) The CPU reads the value at xI/O ad-
Assume XAR12 = 02FF00h dresses 02 FF10h:02 FF11h and
loads it into AR3. XAR12 is not modi-
fied.
dbl(Smem) = volatile(dbl(*+AR8[#8])) = AC1 XAR8 + (8<<2) The CPU reads the content of AC1
ALLa Assume XAR8 = 02FF00h and writes it to xI/O addresses
02 FF20h − 02 FF23h (but only the
02 FF20h address is generated).

7.8.4.7 *ARn(short[#k4]) Used For I/O − xI/O Spaces Access
Operand Description
*ARn(short[#k4]) I/O − xI/O generated address in linear mode: If 8-bit access: XARn + k4
I/O − xI/O generated address in circular mode: If 8-bit access: (ARnH:BSAyy) + (00:ARn) + k4
If 16-bit access: (ARnH:BSAyy) + (00:ARn) +
(k4<<1)
If 32-bit access: (ARnH:BSAyy) + (00:ARn) +
(k4<<2)
XARn is not modified. XARn is used as a base pointer. The 4-bit unsigned constant (k4) is zero ex-
tended to 24-bits before being scaled and added to the base pointer. k4 can be a number from 0 to 15.
Address Generated
Ra = byte(Smem) AR3 = port(byte(*AR7(short[#4])) XAR7 + 4 The CPU reads the value at I/O
Assume XAR7 = FF70h address FF74h and loads it into
Smem= ALLa port(*AR5(short[#7])) = AR4 XAR5 + (7<<1) The CPU reads the content of
Assume XAR5 = FFF0h AR4 and writes it to I/O address-
es FFFEh:FFFFh. XAR5 is not
modified.
Ra = byte(Smem) AR11 = volatile(byte(*AR7(short[#1]))) XAR7 + 1 The CPU reads the value at xI/O
into AR11. XAR7 is not modified.
Ra = Smem AR11 = volatile(*AR7(short[#1])) XAR7 + (1<<1) The CPU reads the value at xI/O
Assume XAR7 = 02FF00h addresses 02 FF02h:02 FF03h
and loads it into AR11. XAR7 is
not modified.
dbl(Smem) = volatile(dbl(*AR14(short[#1]))) = XAR14 + (1<<2) The CPU reads the content of
ALLa XAR2 Assume XAR14 = 02FF00h AR2 and writes it to xI/O ad-
dresses 02 FF04h − 02 FF07h
(but only address 02 FF04h is
generated). XAR14 is not modi-
fied.

7.9 Exceptions/Restrictions on Accesses to I/O − xI/O Spaces
7.9.1 Exceptions on Accesses to I/O and xI/O Spaces

In the byte-pointer mode, the instructions below enable data transfers be-
tween the data memory and I/O space. Either byte(Smem)/Smem or
byte(Ymem)/Ymem operands (but not both at the same time) can be qualified
with port(). For byte(Ymem)/Ymem, you can use any of the XAR indirect oper-
ands listed in Table 7−15.
Instruction Syntax that can have Smem or Ymem qualified to access I/O
space
Smem = Ymem
Ymem = Smem
In the byte-pointer mode, the instructions below enable data transfers be-
tween the data memory and xI/O space. Either the byte(Smem)/Smem/
dbl(Smem) or byte(Smem)/Ymem/dbl(Ymem) operand (but not both at the
same time) can be qualified with port(). For byte(Smem)/Ymem/dbl(Ymem),
you can use any of the XAR indirect operands listed in Table 7−16.
Instruction Syntax that can have Smem/dbl(Smem) or Ymem/dbl(Ymem)

qualified to access xI/O space
Smem = Ymem
Ymem = Smem
7.9.2 Restrictions on Accesses to I/O and xI/O Spaces

It is not allowed to have any instructions executed in parallel with an in-
struction performing an I/O or an xI/O space access
The two instructions below having the Smem syntax element cannot be
used for I/O or xI/O space accesses:

delay(Smem)
ACa = m40(rnd(ACa + frct(uns(Smem) * uns(Cmem))),

T3 = Smem, delay(Smem)
None of the instructions having dbl(Smem) or HI(Smem)/LO(Smem) op-

erands can be used for I/O space accesses
In byte-pointer mode, none of the instructions having high_byte(Smem)/

low_byte(Smem) operands can be used for I/O and xI/O space accesses
Ra = uns(high_byte(Smem))
Ra = uns(low_byte(Smem))
ACa = high_byte(Smem) << S6
ACa = low_byte(Smem) << S6
high_byte(Smem) = Ra
low_byte(Smem) = Ra
In case of an I/O address greater than FFFFh or an xI/O address greater

than 7F FFFFh, the CPU behavior is undefined
Any illegal access to I/O space generates a hardware bus-error interrupt

(BERRINT) to be handled by the CPU
Note:
Some differences apply on restrictions on accesses to I/O and xI/O space
when the CPU is in the word-pointer mode, see Section 6.11 for more details.

Circular Addressing
7.10 Circular Addressing

The circular addressing mode is used in the same way in byte- and word-point-
er modes; in particular, the configuration of the registers is performed the same
way. See Section 6.9.2 for more details.
Note that in the byte-pointer mode, BK03, BK47, and BKC define the number
of bytes (8-bit data) in the circular buffer that you want to reference. Whereas
in the word-pointer mode, these three BKxx registers define a number of words
(16-bit data) in the circular buffers.
7.11 TMS320C54x Compatibility

The TMS320C54x DSP-compatible mode is not supported in the byte-pointer
mode.
The C54CM bit (bit 5 of the ST1_55 register) is reserved.
Any action to set the C54CM bit to 1 has no effect on that bit, it will stay
at 0.
The default pointer mode value determines the C54CM bit value at H/W and
S/W reset :
If the default pointer mode is the byte-pointer mode, then the C54CM reset
value is 0.
If the default pointer mode is the word-pointer mode, then the C54CM re-
set value is 1.
If the CPU is in the word-pointer mode with the C54CM bit set to1, a switch to
the byte-pointer mode will automatically clear the C54CM bit.
If the switch occurred at interrupt acknowledgment, then the C54CM value

will be automatically restored during the return from interrupt.
If the switch occurred at function call, then you will need to restore the
C54CM bit if needed.

Chapter 8
Index
addressing modes, 6-2, 6-4, 6-7, 6-13

Symbols absolute, 6-4
*(#k23), 6-35, 6-58 direct, 6-7
*abs16(#k16), 6-35, 6-58 indirect, 6-13
alignment of fetches from program space, 3-4
Numbers alignment of long-word accesses, 3-5
16-bit versus 32-bit operations in D-unit ALU

(C16 bit), 2-44
32-bit mode of computation, 2-49
40-bit mode of computation, 2-49
54-compatible mode bit, 2-45
54CM, 2-45
A
A unit diagram, 1-10
A-unit arithmetic logic unit (A-unit ALU), 1-11
A-unit registers, 1-11
absolute addressing modes, 6-4
AC0−AC3, 2-9
accumulator overflow flags, 2-38
accumulator saturated before storage (SST), 2-62
accumulator shift mode bit, 2-40
accumulators, 2-9
ACOV0−ACOV3, 2-38
address buses, 1-16
address maps, 3-2, 3-8
I/O space, 3-8
address-data flow unit (A unit) diagram, 1-10
addresses for data-space accesses, 3-5
addresses for instruction fetching
(byte addresses), 3-3
addresses for memory-mapped registers, 2-4
Index-1
ALU, 1-11, 1-13 BRAF, 2-41, 2-42, 2-43, 2-44

address-data flow unit (A unit), 1-11 BRC0 and BRC1, 2-33
data computation unit (D unit), 1-13 BRS1 (BRC1 save register), 2-33
AR indirect accesses, 6-14, 6-15, 6-16 BSA01, 2-15
to data space, 6-14
BSA23, 2-15
to I/O space, 6-16
BSA45, 2-15
to register bits, 6-15
BSA67, 2-15, 2-16
AR indirect addressing mode, 6-14
control mode operands, 6-16 BSAC, 2-15
DSP mode operands, 6-16 buffer size registers, 2-16
AR mode switch, 2-53 buffer start address registers, 2-16
AR0−AR7, 2-13 bus error detected (CBERR bit), 2-57
AR0−AR7 linear/circular configuration bits, 2-52 bus error interrupt (BERRINT), 2-25, 2-28, 2-31
debug enable bit (BERRINTD), 2-31
AR0H−AR7H, 2-12
enable bit (BERRINTE), 2-28
AR0LC−AR7LC, 2-52 flag bit (BERRINTF), 2-25
arithmetic logic unit (ALU), 1-11, 1-13 buses, 1-16
address-data flow unit (A unit), 1-11 data-read address buses, 1-3
data computation unit (D unit), 1-13 data-read data buses, 1-3
ARMS, 2-53 data-write address buses, 1-4
ASM, 2-40 data-write data buses, 1-3
auxiliary registers, 2-12, 2-13 overview, 1-16
program-read address bus, 1-3
program-read data bus, 1-3
B usage by access type, 1-16
byte (definition), 3-5
BAB, 1-3, 1-16 byte addresses (24 bits), 3-3
Baddr, 6-3 byte-load/store operations, 3-5
BB, 1-3, 1-16
BERRINTD, 2-31
BERRINTE, 2-28
C
BERRINTF, 2-25 C, 2-39
BK03, 2-16 C16, 2-44, 2-45
BK47, 2-16 C54x-compatible mode bit, 2-45
BKC, 2-16 CAB, 1-3, 1-16
block access to emulation registers cache clear bit, 2-56
(EALLOW bit), 2-54 cache enable bit, 2-57
block debug events (DBGM bit), 2-54 cache freeze bit, 2-57
block interrupts, 2-26, 2-29 CACLR, 2-56
with DBIER0 and DBIER1, 2-29 CAEN, 2-57
with IER0 and IER1, 2-26 CAFRZ, 2-57
block maskable interrupts globally (INTM bit), 2-47 carry bit, 2-38
block time-critical interrupts (DBGM bit), 2-54 carry bit position (M40 bit), 2-49
block-repeat active flag, 2-41 carry/borrow detection (C bit), 2-38
block-repeat activity status in CFCT, 2-20 CB, 1-3, 1-16
block-repeat registers, 2-33 CBERR, 2-57, 2-58
borrow/carry detection (C bit), 2-38 CDP, 2-14, 2-15
Index-2
CDP indirect accesses, 6-28, 6-29 context bits stored in CFCT, 2-20
to data space, 6-28 control bits in status registers, 2-36
to I/O space, 6-29 control mode operands, 6-16
to register bits, 6-29
control mode versus DSP mode (ARMS bits), 2-53
CDP indirect addressing mode, 6-28
counter, 2-33, 2-35
operands, 6-30
for block-repeat operation, 2-33
CDP linear/circular configuration bit, 2-53 for single-repeat operation, 2-33
CDPH, 2-14 CPL, 2-46
CDPLC, 2-53 CPU bus error flag, 2-57
CFCT, 2-20, 4-5 CPU diagram, 1-2
CFCT and LCRPC example, 4-5 CSR, 2-33
CFCT contents, 2-20
circular addressing/circular buffer creation, 6-105
circular buffer size registers, 2-16
D
circular buffer start address registers, 2-15 D unit diagram, 1-12
circular/linear configuration, 2-52, 2-53 D-unit arithmetic logic unit (D-unit ALU), 1-13
for AR0−AR7, 2-52 D-unit registers, 1-15
for CDP, 2-53 DAB, 1-3, 1-16
CLKOFF (CLKOUT disable bit), 2-58 DAGEN, 1-11
Cmem, 6-3 data buses, 1-16
coefficient data pointer, 2-14 data computation unit (D unit) diagram, 1-12
coefficient indirect addressing mode, 6-31 data log interrupt (DLOGINT), 2-25, 2-27, 2-31
operands, 6-33 debug enable bit (DLOGINTD), 2-31
compatibility with TMS320C54x DSPs (54CM bit), enable bit (DLOGINTE), 2-27
2-45 flag bit (DLOGINTF), 2-25
compiler mode bit, 2-46 data organization, 3-7
computation mode bit, 2-49 data page register, 2-17, 2-39, 2-40
computed single-repeat register, 2-33 copy of 9 MSBs in ST0, 2-40
Index-3
data space, 3-2, 3-5, 3-7 with IER0 and IER1, 2-26
memory map, 3-2 disable/enable maskable interrupts globally
organization of data in, 3-7 (INTM bit), 2-47
word addresses (23 bits), 3-5 disable/enable on-chip ROM (MP/NMC bit), 2-59
data stack pointer, 2-18, 2-19, 4-3 disable/enable time-critical interrupts
data types, 3-5 (DBGM bit), 2-54
data-address generation unit (DAGEN), 1-11 DLOGINTD, 2-31
data-read address buses, 1-3 DLOGINTE, 2-27
data-read data buses, 1-3 DLOGINTF, 2-25
data-write address buses, 1-4 Doffset calculated for DP direct addressing
data-write data buses, 1-3, 1-16 mode, 6-9
DB, 1-3, 1-16 DP, 2-17, 2-39, 2-40
DBGM, 2-54 copy of 9 MSBs in ST0, 2-40
DBIE16−DBIE23, 2-31 DP direct addressing mode, 2-46, 6-8
select with CPL bit, 2-46
DBIE2−DBIE15, 2-32
DP status bits, 2-39, 2-40
DBIER0 and DBIER1, 2-29
DPH, 2-17
debug events enabled/disabled by DBGM bit, 2-54
DSP hardware reset, 5-22
debug interrupt enable bit, 2-30, 2-31, 2-32
DSP interrupt vector pointer (IVPD), 2-22, 5-4
for bus error interrupt (BERRINT), 2-31
for data log interrupt (DLOGINT), 2-31 DSP mode operands, 6-16
for each interrupt vector 16−23, 2-31 DSP mode versus control mode (ARMS bits), 2-53
for each interrupt vector 2−15, 2-32 dual 16-bit arithmetic mode bit, 2-44
for real-time operating system interrupt dual AR indirect addressing mode, 6-25
(RTOSINT), 2-30 operands, 6-25
debug interrupt enable registers, 2-29
debug mode bit, 2-54
diagrams, 1-2, 1-6, 1-8, 1-10, 1-12, 3-2, 3-8, 5-9,
E
5-12, 5-15 EAB, 1-4, 1-16
address-data flow unit (A unit), 1-10 EALLOW, 2-54, 2-55
CPU, 1-2 EB, 1-3, 1-16
data computation unit (D unit), 1-12
emulation access enable bit, 2-54
I/O map, 3-8
instruction buffer unit (I unit), 1-6 emulation registers protected from accesses
memory map, 3-2 (EALLOW bit), 2-54
process flow for time-critical interrupts, 5-12 enable/disable access to emulation registers
program flow unit (P unit), 1-8 (EALLOW bit), 2-54
standard process flow for maskable enable/disable cache (CAEN bit), 2-57
interrupts, 5-9 enable/disable debug events (DBGM bit), 2-54
standard process flow for nonmaskable enable/disable interrupts, 2-26, 2-29
interrupts, 5-15 with DBIER0 and DBIER1, 2-29
direct addressing modes, 6-7 with IER0 and IER1, 2-26
disable/enable access to emulation registers enable/disable maskable interrupts globally
(EALLOW bit), 2-54 (INTM bit), 2-47
disable/enable cache (CAEN bit), 2-57 enable/disable on-chip ROM (MP/NMC bit), 2-59
disable/enable debug events (DBGM bit), 2-54 enable/disable time-critical interrupts
disable/enable interrupts, 2-26, 2-29 (DBGM bit), 2-54
with DBIER0 and DBIER1, 2-29 end address for block-repeat operation, 2-33
Index-4
example of how CPU uses LCRPC and CFCT, 4-5

examples, 6-9
H
DP direct access to memory-mapped register, 6-9 hardware reset, 5-22
extended auxiliary registers, 2-12 high part of XCDP, 2-14
extended coefficient data pointer, 2-14 high part of XDP, 2-17
extended data page register, 2-17 high part of XSP and XSSP, 2-18
extended data stack pointer, 2-19, 4-3 high parts of XAR0−XAR7, 2-12
extended system stack pointer, 2-19, 4-3 HINT, 2-58
external flag, 2-52 HM, 2-47
hold mode bit, 2-47
host interrupt bit, 2-58
F host interrupt vector pointer (IVPH), 2-22, 5-4
FAB, 1-4, 1-16
FB, 1-3, 1-16 I
figures, 1-2, 1-6, 1-8, 1-10, 1-12, 3-2, 3-8, 5-10,
I unit diagram, 1-6
5-12, 5-15
address-data flow unit (A unit), 1-10 I/O absolute addressing mode, 6-6
CPU, 1-2 I/O space, 3-8, 6-104
data computation unit (D unit), 1-12 restrictions on accesses to, 6-104
I/O map, 3-8 IE16−IE23, 2-28
instruction buffer unit (I unit), 1-6 IE2−IE15, 2-29
process flow for time-critical interrupts, 5-12 IER0 and IER1, 2-26
program flow unit (P-unit), 1-8
IF16−IF23, 2-25
standard process flow for maskable
interrupts, 5-10 IF2−IF15, 2-26
standard process flow for nonmaskable IFR0 and IFR1, 2-23
interrupts, 5-15 illustrations, 1-2, 1-6, 1-8, 1-10, 1-12, 3-2, 3-8, 5-10,
flag bit(s), 2-24, 2-25, 2-26, 2-36 5-12, 5-15
for bus error interrupt (BERRINT), 2-25 address-data flow unit (A unit), 1-10
for data log interrupt (DLOGINT), 2-25 CPU, 1-2
for interrupt vectors 16−23, 2-25 data computation unit (D unit), 1-12
for interrupt vectors 2−15, 2-26 I/O map, 3-8
for real-time operating system interrupt instruction buffer unit (I unit), 1-6
(RTOSINT), 2-24 memory map, 3-2
in status registers, 2-36 process flow for time-critical interrupts, 5-12
program flow unit (P unit), 1-8
flow charts, 5-9, 5-12, 5-15
maskable interrupts, 5-9
nonmaskable interrupts, 5-15 interrupts, 5-10
standard process flow for nonmaskable
time-critical interrupts, 5-12
interrupts, 5-15
fractional mode bit, 2-46
indirect addressing modes, 6-13
FRCT, 2-46
instruction buffer queue, 1-6
freeze cache (CAFRZ bit), 2-57
instruction buffer unit (I unit) diagram, 1-6
instruction decoder, 1-7
G instruction organization in program space, 3-3
interrupt enable bit, 2-27, 2-28, 2-29, 2-30,
general-purpose output bit (XF), 2-52 2-31, 2-32
Index-5
for bus error interrupt (BERRINT), 2-28, 2-31

for data log interrupt (DLOGINT), 2-27, 2-31 L
for each interrupt vector 16−23, 2-28, 2-31 last-called routine control−flow context register, 2-20
for each interrupt vector 2−15, 2-29, 2-32
last-called routine PC, 2-20
for real−time operating system interrupt
LCRPC, 2-20, 4-5
(RTOSINT), 2-27, 2-30
LCRPC and CFCT example, 4-5
interrupt enable registers, 2-26, 2-29
DBIER0 and DBIER1, 2-29 level 0 and level 1 loops, 2-33
IER0 and IER1, 2-26 linear/circular configuration, 2-52, 2-53
interrupt flag bit, 2-24, 2-25, 2-26 for AR0−AR7, 2-52
for bus error interrupt (BERRINT), 2-25 for CDP, 2-53
for data log interrupt (DLOGINT), 2-25 Lmem, 6-3
for each interrupt vector 16−23, 2-25 lock (freeze) cache (CAFRZ bit), 2-57
for each interrupt vector 2−15, 2-26 long word (definition and alignment discussion), 3-5
for real-time operating system interrupt loop levels (0 and 1), 2-33
(RTOSINT), 2-24
interrupt flag registers, 2-23
interrupt host processor (HINT bit), 2-58
M
interrupt mode bit, 2-47 M40, 2-49, 2-50
interrupt vector address formation, 2-22, 5-4 MACs, 1-14
interrupt vector pointers, 2-22, 5-4 maskable interrupts, 5-8
bits and registers used to enable, 5-9
interrupt vectors 16−23, 2-25, 2-28, 2-31
process flow for time-critical interrupts, 5-12
debug enable bits, 2-31
standard process flow, 5-9
enable bits, 2-28
flag bits, 2-25 memory map, 3-2
interrupt vectors 2−15, 2-26, 2-29, 2-32 memory-mapped registers, 2-4, 6-79
debug enable bits, 2-32 restrictions on accesses to, 6-79
enable bits, 2-29 microprocessor/microcomputer mode bit, 2-59
flag bits, 2-26 modes for addressing data space and register
interrupts, 2-23, 2-24, 5-2, 5-4, 5-8, 5-9, 5-12, bits, 6-2
5-14, 5-15 MP/NMC, 2-59
introduction, 5-2 multiplication results saturated (SMUL bit), 2-61
maskable, 5-8 multiplication results shifted automatically
nonmaskable, 5-14 (FRCT bit), 2-46
pending (reflected in IFRs), 2-23 multiply-and-accumulate units (MACs), 1-14
interrupts, 5-10 N
standard process flow for nonmaskable
nonmaskable interrupts, 5-14
interrupts, 5-15
standard process flow, 5-15
vectors and priorities, 5-4
INTM, 2-47, 2-48
IVPD and IVPH, 2-22 O
outer (level 0) loop, 2-33
K output bit (XF), 2-52
output of CLKOUT pin disabled (CLKOFF), 2-58
k16 absolute addressing mode, 6-4 overflow detected at bit position 31 or 39
k23 absolute addressing mode, 6-5 (M40 bit), 2-49
Index-6
overflow flags for accumulators, 2-38 address-data flow unit (A unit), 1-10
overflows (not) saturated in A unit (SATA bit), 2-61 CPU, 1-2
overflows (not) saturated in D unit (SATD), 2-50 data computation unit (D unit), 1-12
I/O map, 3-8
instruction buffer unit (I unit), 1-6
P memory map, 3-2
P unit diagram, 1-8 program flow unit (P unit), 1-8
P-unit registers, 1-9 standard process flow for maskable
PAB, 1-3, 1-16 interrupts, 5-9
parallel 16-bit operations in D-unit ALU standard process flow for nonmaskable
(C16 bit), 2-44 interrupts, 5-15
PB, 1-3, 1-16 priorities of hardware interrupts, 5-4
PC, 2-20 program control logic, 1-8
PDP, 2-18 program counter, 2-20, 4-5
PDP direct addressing mode, 6-11 program flow registers, 2-20
pending interrupts reflected in IFRs, 2-23 program flow unit (P unit) diagram, 1-8
peripheral data page register, 2-18 program space, 3-2, 3-3, 3-4
pictures, 1-2, 1-6, 1-8, 1-10, 1-12, 3-2, 3-8, 5-9, alignment of fetches from, 3-4
5-12, 5-15 byte addresses (24 bits), 3-3
Index-7
instruction organization in, 3-3

memory map, 3-2 S
program-address generation logic, 1-8 SATA, 2-61
program-read address bus, 1-3, 1-16 SATD, 2-50
program-read data bus, 1-3, 1-16
saturate-on-store mode bit, 2-62
R
RDM, 2-55, 2-56
REA0 and REA1, 2-33
real-time operating system interrupt
(RTOSINT), 2-24, 2-27, 2-30
debug enable bit (RTOSINTD), 2-30
enable bit (RTOSINTE), 2-27
flag bit (RTOSINTF), 2-24
register reset values, 2-2
register summary, 2-2
register-bit direct addressing mode, 6-11
registers in CPU, 1-9, 1-11, 1-15
address-data flow unit (A unit), 1-11
data computation unit (D unit), 1-15
program flow unit (P unit), 1-9
registers in memory map, 2-4, 6-79
repeat loop levels (0 and 1), 2-33
repeat registers, 2-33
for block-repeat operations, 2-33
for single-repeat operation, 2-33
repeat-operation status in CFCT, 2-20
reset, 2-37, 5-17, 5-18, 5-19, 5-20, 5-21, 5-22
hardware, 5-22
software, 5-17, 5-22
reset instruction (software reset), 5-22
reset values of registers, 2-2
restrictions on accesses to I/O space, 6-104
restrictions on accesses to memory-mapped
registers, 6-79
ROM enabled/disabled (MP/NMC bit), 2-59
rounding mode bit, 2-55
RPTC, 2-33
RSA0 and RSA1, 2-33
RTOSINTD, 2-30
RTOSINTE, 2-27
RTOSINTF, 2-24
Index-8
saturation mode bit, 2-50, 2-61 TC1 and TC2, 2-40

for A unit, 2-61 temporary registers, 2-11
for D unit, 2-50
test/control flags, 2-40
saturation to 32 or 40 bits (M40 bit), 2-49
time-critical interrupts, 2-29, 5-12
saturation-on-multiplication mode bit, 2-61 process flow, 5-12
shift value for ’54x accumulator shifts (ASM bit), 2-40 TMS320C54x−compatible mode bit, 2-45
shifter, 1-13
transition registers, 2-10
sign bit extracted from bit position 31 or 39
TRN0 and TRN1, 2-10
(M40 bit), 2-49
sign-extension mode bit, 2-51
single-repeat activity status in CFCT, 2-20 V
single-repeat registers, 2-33
size registers for circular buffers, 2-16 vector address formation, 2-22, 5-4
Smem, 6-3 vectors for interrupts, 5-4
SMUL, 2-61, 2-62
software reset, 5-22
SP, 2-18, 2-19, 4-3 W
SP direct addressing mode, 2-46, 6-10
word (definition), 3-5
select with CPL bit, 2-46
word addresses (23 bits), 3-5
SPH, 2-18, 2-19, 4-2, 4-3
SSP, 2-18, 2-19, 4-2, 4-3
SST, 2-62 X
ST0−ST3, 2-36
start address registers, 2-15, 2-33 XAR0−XAR7, 2-13
for block-repeat operations, 2-33 XCDP, 2-14, 2-15
for circular buffers, 2-15 XDP, 2-17
status registers, 2-36
XF, 2-52
stop internal program execution (HM bit), 2-47
Xmem and Ymem, 6-3
summary of registers, 2-2
XSP, 2-18, 2-19, 4-2, 4-3
SXMD, 2-51, 2-52
XSSP, 2-18, 2-19, 4-2, 4-3
system stack pointer, 2-18, 2-19, 4-3
T Y
T0−T3, 2-11 Ymem and Xmem, 6-3
Index-9
Index-10

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TMS320C55x ’C55x+’ CPU

Technical Reference Manual

PRODUCTION DAT A information is current as of publication date.

Printed on Recycled Paper

Mailing Address: Texas Instruments

Copyright  2006, Texas Instruments Incorporated

Read This First

About This Manual

About This Manual Release

CPU architecture: new pipeline structure, program bus extension to 64−bit

CPU registers: 16 accumulators available, 15 auxiliary registers available,

Addressing modes: new addressing modes are available. All information

Byte−pointer mode: the revision ’Ryujin’ introduces a byte addressing

How to Use This Manual

Read This First iii

Chapter 3 Memory and I/O Space

This chapter introduces the two stacks located on each TMS320C55x

This chapter describes the available interrupts of the TMS320C55x

This chapter describes the byte−pointer mode of the TMS320C55x

This document uses the following conventions.

The device number TMS320C55x is often abbreviated as C55x.

Active-low signals are indicated with an overbar (for example, RESET).

Program listings, program examples, and interactive displays are shown

Notation Description Example

Register(n−m) Bits n through m of Register AC0(15−0) represents the 16

Bus[n:m] Signals n through m of Bus A[21:1] represents signals 21

The following terms are used to name portions of data:

Term Description Example

LSB Least significant bit In AC0(15−0), bit 0 is the LSB.

MSB Most significant bit In AC0(15−0), bit 15 is the MSB.

Related Documentation From Texas Instruments

TMS320C55x DSP Algebraic Instruction Set Reference Guide (literature

TMS320C54x, C54x, TMS320C55x, and C55x are trademarks of Texas In-

Read This First v

1 CPU Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

2 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.6.2 Coefficient Data Pointer (XAR15 / AR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

3 Memory and I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

4 Stack Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.4.2 Fast-Return Context Switching for Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11

5 Interrupt and Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

6 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.9 Circular Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-78

6−6 Register-Bit Direct Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12

6−10 *SP(offset) Used For Data-Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32

This chapter describes the CPU architecture of the TMS320C55x+

1.1 Overview of the CPU Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.1 Overview of the CPU Architecture

Figure 1−1. CPU Diagram

Data-Read Address Buses BAB, CAB, DAB (Each 24 Bits)

Program-Read Data Bus PB (64 Bits)

Program-Read Address Bus PAB (24 Bits)

Data-Write Data Buses EB, FB (Each 16 Bits)

Data-Write Address Buses EAB, FAB (Each 24 Bits)

1-2 CPU Architecture

1.1.1 Internal Data and Address Buses

CPU Architecture 1-3

1.1.2 Memory Interface Unit

1.1.3 Instruction Buffer Unit

1-4 CPU Architecture

1.1.4 Program Flow Unit

1.1.5 Address-Data Flow Unit