Expedition PCB User's Guide PDF

Expedition™ PCB User’s Guide
Software Release EE2007.1
© 1998-2007 Mentor Graphics Corporation

All rights reserved.
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MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL
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FITNESS FOR A PARTICULAR PURPOSE.
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RESTRICTED RIGHTS LEGEND 03/97
U.S. Government Restricted Rights. The SOFTWARE and documentation have been developed entirely
at private expense and are commercial computer software provided with restricted rights. Use,
duplication or disclosure by the U.S. Government or a U.S. Government subcontractor is subject to the
restrictions set forth in the license agreement provided with the software pursuant to DFARS 227.7202-
3(a) or as set forth in subparagraph (c)(1) and (2) of the Commercial Computer Software - Restricted
Rights clause at FAR 52.227-19, as applicable.
Contractor/manufacturer is:
Mentor Graphics Corporation
8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.
Telephone: 503.685.7000
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Table of Contents
Chapter 1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Mouse Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Default Mouse Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Alternate Mouse Mappings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Middle Button Strokes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Mouse Strokes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Keyins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Moving Parts by File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
File Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Moving Parts with the Arrow Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Snap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Measure > Minimum Distance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Tab Key. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Measure Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Dialog Boxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Modeless Dialogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Keyboard Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Accelerators / Shortcut Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Function Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Customizing the Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Getting the Most from Graphics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Object Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Graphics Zoom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Graphics Pan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Finding Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Display Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Net. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Hazards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Groups Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Saving Your Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Docking a Dataset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Not Opening an Undocked Dataset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Undock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Printing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Windows Printing - Print Setup Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Sun Solaris, HP-UX and Linux Printing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Using the Visual MainWin Control Panel to Configure Printers . . . . . . . . . . . . . . . . . . . . 49
Expedition PCB User’s Guide, EE2007.1 3

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Setting up printers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Time Zone Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Mentor Graphics Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Product Licensing Assistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Chapter 2
Library Manager and the Central Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
What is a Central Library. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Production Flows Supported by Library Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Recommended Central Library Permissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
User Access to a Central Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Partitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Library Manager Workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Library Navigation Tree Viewer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Project Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Menu Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Library Manager Utilities and Editors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Library Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Modify Cells and Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Visual IBIS Editor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Import Symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Property Definition Editor (Common Properties). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Part Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
DX Designer Packaging Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Mapping Expedition Device Data to DxDesigner Device Data . . . . . . . . . . . . . . . . . . . . . 65
Symbol Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Cell Editor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Rules within the Cell Editor for Nested Cells. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Material / Process Editor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Parts Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Reusable Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
IBIS Model Editor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Padstack Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Layout Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Library PDF Documenter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
File Viewer Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Property Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Partition Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Partition Search Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Unreserve Partitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Setup Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Units Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Chapter 3
Expedition PCB Design Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Verifying Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Setup Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
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General Tab in Setup Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Remap Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Via Definitions Tab in Setup Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Via Clearances Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Layer Stackup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Buried Resistors and Rise Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Reserved Layer Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Editor Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
General Setup Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Parts Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Cells Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Clusters and Rooms Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Routes Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Gloss Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Pad Entry Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Grids Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Filter Tab. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Tuning Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Jumpers Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Net Classes and Clearances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Clearances Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Contour & Mounting Hole to Mounting Hole . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Contour & Mounting Hole to Non-Plane Conductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Contour & Mounting Hole to Plane Conductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Placement Outline to Placement Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Placement Outline to Placement Obstruct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Placement Outline to Board Edge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Plane to Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Testpoint Center to Testpoint Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Toggle Plane Clearance Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Toggle Embedded Passives Clearance Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Net Properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Draw. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Plane Shapes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Place an Actual Plane Shape. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Dynamic Area Fills . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Plane Obstructs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Route and Via Obstructs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Reserved Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Display Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Place Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Board Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Manufacturing Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Board Origin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Mounting and Tooling Holes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Route Border. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Contour Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Part Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table of Contents
Nested Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Use Place Parts to place the remaining parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Placing Etch Text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Netline Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Chained Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Virtual Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Guide Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Placement Improvement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Fixing Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Editing Selected Cells and Spare Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Move Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Move Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Snap to Grid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Rotate Part. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Push Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Copy Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Swap Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Swap Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Swap Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Automatic Placement Modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Automatic Swap/Rotate by Cell Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Automatic Swap by Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Polar Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Placement Verification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
DRC - Verifying Part Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Mechanical Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Routing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Route Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Saving Your Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Routing Costs using the Editor Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Placement Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Routing Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Router Tuning Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Tuning Meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Design Grid. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Net Selection Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Routing Interactively . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Moving Traces and Vias in Route Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Multiple Via Objects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Hug Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Glossing Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Gloss Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Guiding Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Glossing Possibilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Semi-Automatic Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Curved Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Example for routing curved traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Curve trace end point rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Forced Plow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Table of Contents
Dyna-Plow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Route Plow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Angle Plow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Multi-Plow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Via Patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
<Alt> Auto-Finish Preview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Planes Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Fanout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Changing the Active Layers and Adding Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Blind and Buried Vias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Interconnect Modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Working with Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Recalculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Bus Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Bus Routing Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Routing Steps for Bus Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Bus Tune . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Target Area Placement and Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Supported Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Unsupported Functionality for Target Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Target Areas in the PCB Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Target Area Route and Auto Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Straight Line Interconnects Auto Route Pass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
All other Auto Route Passes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Removing Unwanted SLI Route Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Interactive Moving of Routed/Partially Routed Target Areas . . . . . . . . . . . . . . . . . . . . . . 172
Input and Formula Parameters for Automatic Calculation of Target Areas. . . . . . . . . . . . 173
Automatic Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Copy Trace / Fanout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Changing a Trace Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Reroute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Remove Hanger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Replace Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Using the Auto Router . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Layer Stackup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Technology Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Routing Process Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Fanout Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Routing Critical Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Auto Routing Critical Nets Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Auto Routing Specific Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Routing with Fences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Hard Fences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Soft Fences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Move Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Run the Auto Router . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Dynamic Teardrops and Breakout Traces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Table of Contents
Finish Remaining Opens. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Review Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Clean-Up for Manufacturing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Modify Corners. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Reviewing the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Design Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Signal Integrity Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Hazards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Generating Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
High Speed and Critical Nets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
General Comments on High Speed Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Pin Ordering Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Impedance Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Length / Delay Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Group Length Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Pin Package Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Hazards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Routines affected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Format of PinPkgLengths.txt file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Differential Pair Routing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Crosstalk Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Post Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Test Points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Place Test Points from File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Delete Unused Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Padstack Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Plane Classes and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Split Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Discard Plane Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Delete Plane Data or Actual Plane Shapes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Migrating Existing Plane Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Plane Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Design Verification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Running Batch DRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Review DRC Hazards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Running Batch DFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Renumbering Reference Designators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Text Modification using Draw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Generating Silkscreens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Drill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Drill Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Drill File Naming Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Drill Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Drill Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Gerber (274X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Gerber (274D). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Custom Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Gerber Machine Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
General Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Table of Contents
Hyperlynx Thermal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Detailed Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Annotation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Modification Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Plotting - Archive Plots. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Chapter 4
Circuit Move and Copy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
General Methodology for Copy & Paste . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Moving Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Copying and Pasting Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Deleting Objects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Differences between Copy Circuit and Circuit Move and Copy . . . . . . . . . . . . . . . . . . . . . . 218
Objects that are not allowed to copy in Circuit Move & Copy . . . . . . . . . . . . . . . . . . . . . 218
Alternate Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Cell Name Mismatches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Part Placement Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Multiple Equivalent Circuit Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Via Span Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Multiple Via Objects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Plane Shapes and Net Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Rule Area Scheme Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Rooms and Clusters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Mounting Holes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Virtual Pins and Guide Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Test Points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Using Find with Circuit Move and Copy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Circuit Clipboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Retrieving a Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Selection List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table Associations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Multiple Via Objects Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Selection Filter Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Selection Filter Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Design Reference Objects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Part Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Dimension Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Selection Filter Outside RF Toolkit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Multiple Selected Objects Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Copy to Layout Clipboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Instantation Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Instantiation Wizard Ref Des . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Instantiation Wizard Physical Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Circuit Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Allowing Mapping more than one circuit layer to one host layer . . . . . . . . . . . . . . . . . . . 233
Instantiation Wizard Physical Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

Table of Contents
Instantiation Wizard User Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

Change Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Incompatible Via Spans . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Save Schemes in Push and Change Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
To Select a Pre-Defined Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
To Create and Save a New Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
To Delete a Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
To Use an Existing Scheme as a Template. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Mirror. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Dynamic Mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Static Mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
DRC Violations after Mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Examples of cells with an axis of symmetry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Push . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
RF Shapes and Groups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Move and Rotate Selection (Including Mirror and Push). . . . . . . . . . . . . . . . . . . . . . . . . . 242
Copy Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
RF Elements in the Instantiation Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Instantiating RF Shapes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Embedded Passives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Instantiating Embedded Passive Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Team PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Move / Rotate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Paste and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Chapter 5
Product Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
IDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
DXF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
IFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
ICX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Schematic Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Project Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Project Indicator Light in Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Schematic Connectivity and Constraint Status Section . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Library Extraction Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Back Annotation to the Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
CES Integration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Netlist Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Schematic iCDB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Foreign iCDB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Keyin Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
CAE Netlist. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
DXDesigner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Design Architect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
DXDesigner Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Design Architect Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

Table of Contents
Steps to translate a DA schematic to Expedition PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

Cross Probe Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Enabling Cross Probing Between Design Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
DXDesigner (Cross Probe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Using Cross Probing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Xplore (Cross Probe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Invoking from Expedition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Connect Tool Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Invoking from Design Architect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Design Architect Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Xplore Cross Probe Server . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Variant Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
OBDG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
OBD++. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
ODBG ++ DRC Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Creating Special Properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Enterprise 3000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Scepter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
OrCAD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
HyperLynx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
XTK/QE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Chapter 6
Microvia Routing Strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Fanout with Micro and Blind/Buried Vias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Laminate Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Laminate Rule 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Laminate Rule 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Laminate Rule 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Buildup Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Buildup Rule 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Buildup Rule 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Buildup Rule 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Examples of Laminate and Buildup Fanouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Example 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Chapter 7
Rule Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Master Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Minimum Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Overlapping Areas - Same Layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Overlapping Areas - Adjacent Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Remap Rule Area Schemes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

Table of Contents
Chapter 8
Reusable Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Central Library Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Reusable Block Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Reusable Block Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Schematic Adjustments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Layout Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Saving the Reusable Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Becoming Unverified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Using a Reusable Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Reusable Blocks used within Design Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Reusable Blocks within Expedition PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Forward Annotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Placing Reusable Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Reusable Block Clearances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Reusable Block Net Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Reusable Block Manipulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Flatten Reusable Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Making an ECO to an Reusable Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Chapter 9
Embedded Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Setting up Embedded Passives Support in a DxDesigner and Design Capture Flow. . . . . 319
Schematic Parametric Symbol Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Schematic Parameter Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Layout Template Cell Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Parametric Cell Creation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Parametric Pad Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Additional parametric parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Embedded Passives Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Integration in FabLink XE and Expedition PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
File Command Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Save (Exp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Save (FLXE Pro). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Save Copy (Exp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
File Viewer (Exp and FLXE Pro) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Export . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Edit Command Modifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Review > Minimum Distance… (Exp and FLXE Pro). . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Properties (Place Mode - Exp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Setup Command Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Material/Process Editor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
Place Command Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Route Command Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
ECO Command Enhancements (Exp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Analysis Command Enhancements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

Table of Contents
Appendix A
Draw and Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Draw Toolbars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Select Toggle Button. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Polygon Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Snap Grid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Angle Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Snap to Grid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Join . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Create Polyline / Polygon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Dissolve Polyline / Polygon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Delete End Point Handle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Trim. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
Flip Horizontal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
Flip Vertical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
Rotate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Bring Forward. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Send Backward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
Merge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Extend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
Draw Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Arc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Circle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Polyline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
Polygon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
Rectangle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
Text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Appendix B
FabLink XE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Licensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Acquiring FabLink XE Pro and FabLink XE licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Standalone. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Through the Expedition PCB License Splash Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Through Setup Licensing in Expedition PCB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
Invoking FabLink XE and FabLink XE Pro from within Expedition . . . . . . . . . . . . . . . . . . 395
Independent of the FabLink XE license . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
After acquiring a FabLink XE/FabLink XE Pro license. . . . . . . . . . . . . . . . . . . . . . . . . . . 396
Panel Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
Design Placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
Import Gerber. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

Table of Contents
Rendered Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399

Import Drill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Rendered Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
GDSII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
Embedded Passive Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
IPC-D-356B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
FabMaster Panelization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
Detail Views. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
Modification and Annotation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
Copper Balancing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
Display Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Place Copper Balancing Shapes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Adding User-defined Copper Balancing to the Board/Panel design . . . . . . . . . . . . . . . . . 407
Copper balancing rectangles exception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
Copper Balancing Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
Delete Copper Balance Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
Copper Balancing DRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
Mask Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
PDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Current Limitations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
XE Neutral File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
Manufacturing Output Validation (MOV). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
Pre-Validation Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
Package Creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
Validation Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
Error Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
Panel DRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
Setup Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
Library Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Layout Templates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Padstack Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Cell Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Panel Cell Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
Test identifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
Assembly fixtures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
Solder palette . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
Sky-hook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Panel stiffeners . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Board obstructs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Pin fixtures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Test coupons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Trace elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Pad elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Place via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Draw elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Nested panel cell elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Break Away Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Creating a Panel Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

Table of Contents
Panel Cell Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425

Manufacturing Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
Export IDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
Appendix C
ICX Pro HSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
License Scenario 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
License Scenario 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
DxDesigner to Expedition Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
Enabling CES in Expedition PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
Cross Project Enabling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
Forward Annotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
Back Annotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
Design Architect / Board Architect > Expedition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
Expedition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
Target Length / TOF Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
Current Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
Routing Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
Hazard Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
Changes to the User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
Appendix D
Split and Join a PCB Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
License Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
Converting between Team PCB Reserved Areas and Xtreme PCB Protected Areas . . . . . . 438
Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
Creating Reserved Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
Using guide pins on the edge of reserved areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
Polygons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
CES with Team PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
Other Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
Net Classes and Net Properties with Team PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
Net Properties Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
Split Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
Join Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
Usability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
Partitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
Routing in a Partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
Save Function in Partitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
Update from Other Partitions (Split / Join Design) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
Command List for Partitioned Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
Appendix E

Table of Contents
Xtreme PCB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455

Read This Before You Begin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
Xtreme Design Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
Xtreme Design Client . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
Editor Control Dialog Warnings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
Overview of Xtreme PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
Xtreme PCB Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
Using CES with Xtreme PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
User Analysis of Xtreme PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
Session and /or Client Design Crash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
Undo and Redo Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
Undo and Redo Can Fail. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
Undo and Redo availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
Rejecting Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
Xtreme Design Session Interrupt Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
Rejecting an Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
Accepting the Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
Client Saves in the Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
Starting an Xtreme Design Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
Client Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
Joining an Xtreme Design Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
Expedition PCB Editor Centric Joining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
Expedition PCB, Data Centric Joining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
Ending an Xtreme Client Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
Adding Clients to the XDS dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
Stopping an Xtreme Design Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
Force Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
Force Field Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
Display Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
Force Field Shape and Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
Force Field Priority calculations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
Force Field Effects and Conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
Xtreme Protected Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
Rules of Protected Areas. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
Behavior of Protected Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
To Display Protected Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
Manipulating Protected Areas. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
To Create Protected Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
Converting between Team PCB Reserved Area and Xtreme PCB Protected Areas . . . . . . . 478
Command Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
Appendix F
Xtreme Auto Router . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
Environment Variables (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
Xtreme Design Session License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
Xtreme Design Clients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
XtremeAR Editor Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488

Table of Contents
XtremeSvc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
Xtreme Design Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
Setting up the System Service on Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
XAR Batch File Start Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
To uninstall system service. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
XtremeAR Command Line Invocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
Basic Client Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
XAR Recording & Playback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
Server . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
Client. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
Process Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
Selecting Client Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
Starting the Xtreme Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
Accessing the Xtreme Design Session License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
Starting XtremeAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
Dual and Hyperthreaded Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
Re-displaying XtremeAR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
Controlling the XtremeAR Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
Adding Clients during a Route Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
Stopping Clients during a Route Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
Killing Clients during a Route Session. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
Completing XtremeAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
Pausing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
Interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
XtremeAR Host or XtremeAR Client Crashes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
Using Xtreme Design Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
Steps To Participate in XtremeAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
Xtreme Logging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
Logging Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
Starting Xtreme Design Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
Run Time Report. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
Summary Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
Third Party Integration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
Glossary
Index
End-User License Agreement

Table of Contents

Chapter 1
Overview
This chapter provides an overview on using the different mouse mappings, zoom and pan
functionality, time zone constraints and a list of the various keyins available. The Customer
Support section gives information on whom to contact with any questions or problems related to
the use of any of our software.
If you want to:

Learn about Time Zone Constraints Information on page 55
Learn how to contact Mentor Graphics for Support Information on page 56
Learn about Mouse Mappings Information on page 19
Learn how to use the Zoom commands Information on page 31
Learn about the Pan command Information on page 32
Learn how to use the Keyins Information on page 23
Learn about the Snap command Information on page 24
Learn about the Measure command Information on page 25
Learn how to move parts with Arrow Keys Information on page 24
Learn about Customizing the Interface Information on page 29
Learn about the Display Control dialog Information on page 33
Learn how to get the most from graphics Information on page 29
Learn how to select an object Information on page 29
Learn how to Dock/Undoc a Dataset Information on page 46
Learn how to Save your work Information on page 45
Mouse Mappings
Expedition™ PCB makes extensive use of the mouse. Many common tasks like object selection,
zooming, windowing, and panning are mapped to each mouse button. To make best use of
Expedition PCB, we suggest that a three-button mouse be used. Also, if your mouse has a
wheel, you can use it to zoom in (rolled forward) or zoom out (rolled back).

Overview
Mouse Mappings
Default Mouse Mappings

Table 1-1. Default Mouse Mappings
Action Left Button Middle Button Right Button
Single-click Deselects all objects, then selects a Zooms in Context-sensitive
single object under the cursor. popup
<Shift> plus Adds a single object under the cursor Zooms out Place Tentative
single-click to select set. Snap point
<Ctrl> plus Toggles the select state of a single Toggle between Fit Deletes Tentative
single-click object under the cursor. View and Previous Snap point
View
Press and drag In Place Mode: If over an object, Pan Strokes
moves the object.
If in open space, deselects all objects,
then selects all objects in the rectangle
(or selects all objects partially in the
rectangle).
<Shift> plus If in open space, selects all objects in Zoom area - zooms Zoom area - zooms
press and drag the rectangle (or selects all objects out by dragging out by dragging
partially in the rectangle). right to left and right to left and
zooms in by zooms in by
dragging left to dragging left to
right. right.
Alternate Mouse Mappings

The alternate mouse mapping is intended for users of pre-Expedition PCB software.
Table 1-2. Alternate Mouse Mappings
Single-click Deselects all objects, then selects Zoom out Context-sensitive
single object under the cursor. popup menu
<Shift> plus Adds single object under the cursor Zoom in Place Tentative
single-click to select set. Snap point
<Ctrl> plus Toggles the select state of a single Zoom out Deletes Tentative
single-click object under the cursor. Snap point
Press and drag Unselects all objects, then selects all Zoom Area - zoom Window pan
objects in the rectangle (or selects in by dragging left
all objects partially in the rectangle). to right and zoom
out by dragging
right to left.

Overview
Middle Button Strokes
Table 1-2. Alternate Mouse Mappings

<Shift> + press Adds all objects in the rectangle to Zoom Area - zoom Zoom Area - zoom
and drag the select set in by dragging left in by dragging left
to right and zoom to right and zoom
out by dragging out by dragging
right to left. right to left.
Middle Button Strokes

The middle button strokes command allows you to make use of the middle mouse button to
generate stroke patterns within your design.
Table 1-3. Middle Button Strokes
Single-click Deselects all objects, then selects Zooms in Context-sensitive
a single object under the cursor. popup
<Shift> plus Adds a single object under the Zooms out Place Tentative
single-click cursor to select set. Snap point
<Ctrl> plus Toggles the select state of a single Toggle between Fit Deletes Tentative
single-click object under the cursor. View and Previous Snap point
View
Press and drag Deselects all objects, then selects Strokes Pan
all objects in the rectangle (or
selects all objects partially in the
rectangle).
<Shift> + press Adds all objects in the rectangle Zoom area - zooms Zoom area - zooms
and drag to the select set out by dragging out by dragging
right to left and right to left and
zooms in by zooms in by
dragging left to dragging left to
right. right.
Mouse Strokes
Strokes are pre-defined patterns of mouse movements that execute or initiate functions. To use a
mouse stroke to enter a function, press and hold the Stroke mouse button, move the mouse in the
predefined stroke pattern for the function, and release the mouse button. As you move the
mouse to draw the pattern, a red line follows the mouse pointer to show you the created pattern.

Overview
Mouse Strokes
Table 1-4. Stroke Recognition Grid

1 2 3
4 5 6
7 8 9
Strokes are recognized by fitting the stroke path onto a 3 x 3 grid creating a numerical sequence
in the display area, the 456 stroke toggles the display area from framed mode to window mode.
Stroke Action Grid

Displays help on strokes 78952
Undo 7412369
Report Selected 1474123
View Area 159
View All 951
Zoom In 357
Zoom Out 753
Delete 74123698
Copy Trace / Segment 3214789
Turns On / Off Netlines 321478965

Tentative Snap 729
Static snap 927
(PC) ALT key + Route Mode 123
(UNIX) Meta Key
(PC) ALT key + Place Mode 321
(UNIX) Meta Key
(PC) ALT key + Draw Mode 147
(UNIX) Meta Key
Layout Strokes
Route Interactive (Plow) 852

Overview
Keyins
Stroke Action Grid

Route Switch Ends 9632147
Display Control 1478
Editor Control 14569
Auto Finish (Plow) 258

Unselect All 1478963
Move (Place Mode) 74159
Rotate 3698741
OK 654
Cancel 456
Keyins
Keyins are two-character mnemonics of the action-object form. To use the keyin, click in the
main window to set the focus and type. The characters are echoed in the keyin field. It is not
necessary to set the focus to the keyin field.
You may choose a previous keyin if you wish as the last 10 keyins are saved between sessions.
The online help menu offers help on keyins, and gives extensive examples of the various
available mnemonics.
Moving Parts by File

Using the following keyin command, you can specify a file which has locations for those parts
you want to move or place in a design.
pr -file=<dir>/<filename>{-x}
The '-x' argument (if supplied) exports the current placement information into the named file
and the overwrites the file contents. The default filename is xyplace.dat. The default directory is
the one where the .pcb file is located. The created log file is logfiles\xyplace.log. You may
specify a full path and different filename. The defaults are used if none are specified.

Overview
Moving Parts with the Arrow Keys
If you are importing the file from the main directory, no directory needs to be specified,
however, if you are importing a file that resides in the config directory, you must specify that
directory. For example: default file is config\xyplace.dat. Created log file is logfiles\xyplace.log.
File Syntax
Syntax of the file is:
{.units <in> | <mm> | <th> |<um> }
The .units line is optional. If omitted, the current units settings are used. The line may be
specified more than once to change the units on a part by part basis. Optional statement to set
units in the file.
.ref <ref_des> {cellname=<cellname>} <xy> <rot> <top|bottom> { fix |

lock }
One line for each part to be placed is a requirement. The comment lines are prefixed with an
exclamation point (!). The cellname need only be supplied if it's different than the default part
entry for that part. The alternate cellname and the fix and lock flags are optional, the coordinates
are specified as 'x,y' (100,-400) and the rotation is in degrees. Not all the parts need to be in the
list, only those which you want to move or place.
Moving Parts with the Arrow Keys

There are three ways you can move selected parts using the keyboard arrow keys. Each of these
methods requires the parts are selected and not in dynamics:
1. Using the four arrow keys moves the part(s) by one grid or one pixel, if no grid is
defined in the direction of the selected arrow key.
2. Using the arrow key with the Shift key moves the part(s) by 10 grids or 10 pixels; if no
grid is defined in the direction of the selected arrow key.
3. The arrow keys, used in conjunction with the Ctrl key moves the selected part(s) as close
as possible to existing parts in the direction of the arrow key without violating the Pad to
Pad or Part to Part Net Class general clearances, while still maintaining its placement
grid.
Snap
Snap functions can be accessed from the View - Toolbars - Snap option or from the popup menu
that displays when you click the right mouse button in the graphics display. The following
methods are available when using snap:
• Select a point and start a drawing element

Overview
Measure > Minimum Distance
• Align two elements

• Move an element(s) by delta or absolute coordinates.
There are two different snap modes: Tentative and Static. Tentative snap works as a
temporary snap point and allows you to briefly use a snap point for moving or aligning
parts. Static snap leaves the snap point in the design until you remove it, and as an example
would allow you to draw a number of radial lines from a single point.
Tentative snap points can be used in conjunction with a static snap points resident in the design;
however, tentative snap points take precedence over static snap points when the “Use Snap
Point” option is selected.
Snap placement in space (no element attached)
With grid lock on the snap point is placed on the grid.

With grid lock off the snap point can be placed on the nearest design unit.
Snap to element
Select Place Tentative or Static snap.

With Hover Snap enabled, the snap point attaches to the nearest keypoint of the nearest
element.
As the cursor is dragged, the snap point moves from one keypoint to the next.
If multiple radial lines are needed, enter the next line length and angle and the system
uses the same snap point.
The Next Snap Keypoint and Previous Snap Keypoint options on the Snap toolbar
allow you to toggle from keypoint to keypoint forward or backward respectively.
The Remove Snap option allows you to delete snap points from the design.
Hover snap is turned on and off through the icon located on the Snap toolbar. While on, the
icon stays depressed. When hover snap is enabled, as the cursor moves across the graphics
display, the snap point tracks to the nearest keypoint of the nearest element. As the cursor
moves down an element, the snap point tracks from keypoint to keypoint. If the left mouse
button is clicked while a hover snap graphic is displayed on a keypoint, the location of this
keypoint is used instead of the cursor’s location.
Measure > Minimum Distance

Measure is available in any mode; Place, Route, or Draw. There are three different modes which
can be utilized, Edge (default mode), Center, and Centerline. The distance attaches to the cursor
and as the cursor is moved, the dimension changes based on the distance from the selected point
to the cursor position. If a placement or routing grid is specified within Editor Control, the grid

Overview
Dialog Boxes
points are used and a measurement off-grid is not allowed. Within Place mode, primary or
secondary part grid can be used. Within Draw mode the use of grid can be turned on/off using
the icon on the toolbar.
You can use the Display Control > Layer tab settings to display the defined grid. If a point or
grid is selected in the design and an element falls within the cursor array, the measure point
would select the element. The Tab key can then be used to move from one element to the next
within the array.
The right mouse popup provides the ability to change the type measurement while in the
command, allows you to cancel the Measure command and use the Snap commands. If you use
Hover snap the end point of the measure line snaps to the nearest object and calculates the
distance between the two objects.
Tab Key
Once an element is selected, the Tab key can be pressed to move from one element to another
within the selected element. In a congested area, multiple elements can be in the general area of
a selected point and when zoomed out it could be difficult to select the exact, required element.
To help solve this when an element is selected you can use the Tab key, which cycles through
the types of the element. The type, distance and dx/dy location of each element displays within
the status bar and the distance and dx/dy location also displays in the field in the Measure
toolbar. As an example, this provides the option to select a padstack and switch from a layer 1
pad to the soldermask pad.
Measure Usage
The initial measure point is mode locked. For example, if you select the Measure command
while in Edge mode, the initial point will always be in Edge mode and cannot be changed to a
different mode. The only way to change the initial point mode is to exit the command, select a
different mode, then reselect the element.
Once the first point is selected the mode can be changed prior to selection of the second point.
For example, the first point is selected in Edge mode, this point is locked in Edge mode. You
can then change the mode to Center and tag a pad, essentially measuring from the edge of the
first element to the center of the second.
Dialog Boxes
Commands within Expedition PCB often require information that cannot be provided when a
command is issued. These commands require additional input before they can execute
successfully. In these situations, a dialog box containing data entry devices such as choice lists,
check boxes and editable text fields collects the additional information.

Overview
Keyboard Entry
Several of the commands in the Expedition PCB's pulldown menus and action keys are followed
by an ellipsis (...) . This indicates the presence of a dialog box. Occasionally,
ellipses also signify the presence of a secondary pulldown menu.
Modeless Dialogs
Modeless dialogs, dialogs that can be left open and do not force you to respond, are used
throughout Expedition PCB. For example, Review Hazards and Display Control, can
dynamically display information related to the current status of your design and provide easy
access to frequently used commands. This is true regardless of the application's focus.
Keyboard Entry
If you use keyboard entry, make sure that the dialog box is active and that the correct option
within the dialog is selected. To select a different option within the dialog, use the Tab key.
Once the appropriate option is selected, press Enter or the spacebar to execute.
Note
When the graphics dialog is active and you are in Route mode, the spacebar allows you to
move between the active and secondary layers within your design (see Display Control
Layers). However, once you change focus to a dialog, pressing the spacebar no longer
changes your active layer; instead, it activates the selected option within the active dialog.
Mnemonics
Mnemonics are single characters of a menu selection. The mnemonics are the letters underlined
on the menu bar and pulldown menus. Abbreviations are used for the most common keys (for
example, the Escape key is shown as Esc; the Control key is shown as Ctrl).
Keys can be used in combinations or sequences. Shift + F1 means hold down the Shift key and
the F1 key, at the same time. If you press the Alt key, then the r key, then the a key (Alt - r - a),
the Auto Route dialog appears.
When the pulldown menu displays and the character is keyed in, the command is invoked. For
example, to access the Save Settings command using a mnemonic, if the File pulldown is
displayed, key in s. If the mnemonics are not underlined within the application, press the Alt
key to display them.
To use a mnemonic when the pulldown is not displayed, you must press the Alt key and the first
letter of a selection on the menu bar to select the pulldown. For example, to access the Save
Settings command when the File pulldown is not displayed, press the Alt key, followed by the f
key which displays the File pulldown, then press the s key.

Overview
Keyboard Entry
Arrow keys are the collective name for the Up, Down, Right, and Left arrow keys. Arrow keys
can move the cursor through fields in a dialog box. The arrow keys can also be used to move the
cursor within a data field: however, they cannot be used to move to the next data entry field.
The Tab key moves the cursor to the next field in a dialog box. For example, after you enter
information into a data entry field, use the Tab key to go to the next field.
The Ctrl key can be used, in conjunction with the left mouse button, to select multiple items
within the design. If you hold the Ctrl key down and then click the left mouse button, you can
select multiple items.
Accelerators / Shortcut Keys

Accelerators, also known as shortcut keys, provide a quicker method of keyboard access than
mnemonics. Shortcut keys can select a menu item even when the menu is not active, whereas a
menu must have focus before mnemonics can be used.
Shortcut keys require a unique keyboard sequence, while mnemonics must only be unique
within the menu that has focus. For example, the Editor Control command has been assigned
Ctrl - E as the shortcut key.
Function Keys
When the command window is active, the keyboard function keys map to the Action Keys
across the bottom of your screen, but when the focus changes to a dialog, the function keys no
longer map to the Action Keys. These function keys allow the quick selection of common
commands, for example, if a part is selected, the function keys allow the part to be pushed,
rotated, and moved.
The F1 key always displays online help. The function keys change to reflect the mode of
operation, Place, Route or Draw.
Figure 1-1. Place Action Keys
Figure 1-2. Route Action Keys
Figure 1-3. Draw Action Keys

Overview
Customizing the Interface
Customizing the Interface

The interface can be customized to meet your design needs. For the purpose of this manual, it is
assumed that the default interface is being used. Dockable toolbars that can be undocked,
moved, resized and redocked are available. Also, the View >Toolbars > Customize dialog can
be used to add or remove toolbars, add or remove toolbar icons and customize the toolbar look
and feel.
To move a toolbar, click the edge of it and drag it to the required position. When you move a
toolbar it is called a "floating toolbar"; it can be resized or moved anywhere on the screen.
Moving the toolbar to one of the window edges will dock that toolbar to that edge. Moving the
toolbar back to the top of the application window docks it back into its original position.
By default, the buttons shown are small. To display larger buttons, select the Large Buttons
check box on the Customize dialog. Large buttons contain more detail and may be easier to
read. Small buttons contain less detail, but more of them can be placed on the toolbar because of
their smaller size. If it becomes necessary to contact Mentor Graphics Customer response
center, please return the interface to the system default. Customize the interface only after
becoming fully familiar with the Expedition PCB interface.
Getting the Most from Graphics

The mouse activates a variety of the basic graphical commands and actions used throughout the
design process. You can use the mouse to change the relative position of your design, zoom into
or out of the design or pan across the design. Since Expedition PCB does not respond to two or
more buttons being pressed simultaneously, any command that requires the depression of a
mouse button automatically pans as you get closer to the edge of the design. This process is
known as Dynamic Panning (Dyna-Pan).
If, at any time, you become lost in your design, select the Fit Board icon or one of the
pulldown menu commands, Fit Board or Fit Selected, to display either the entire design or
selected items. Additional commands such as Previous View or Next View allow you
to re-display previous board displays. The Previous View command returns you to the previous
display. The Next View command allows you to return to the board display where the Previous
View command was issued.
Object Selection
In Expedition PCB, two methodologies are used in the command structure: action-object and
object-action. To execute an action-object command, select the command and then select the
item to be affected. To execute an object-action command, select the item(s) and then execute
an action or command against the item(s). It is important that you understand the selection and
de-selection process.

Overview
Getting the Most from Graphics
There are several commands available from the Edit > Add to Select Set pulldown menu that
allow you to select groups of objects. These action-object commands allow you to quickly
select groups such as fixed traces, unfixed traces, fixed vias or unfixed vias within your design.
The Edit > Find command, when used with its graphics options, functions as an action-
object command. The Find command not only finds items in the database but also allows you to
select, highlight and fit those items into your display.
To use the object-action commands, you must first select an item or group of items. Using the
mouse, point to an item and click the left mouse button. This selects that item, and de-selects
any previously selected items.
All items that are electrically connected to the selected item are also selected (called net-
selected) and are changed to include black diagonal hashes. Net-selection is used as a visual
reference to an item’s electrical associations; any netlines attached to the selected item are
displayed. If you select a pin any netlines attached to the pin are selected rather than the
electrical traces of the net.
Figure 1-4. Net and Pin Selected Items
If the netline display is turned off, the selected netlines (and only those netlines) and net-
selected items display. When you select a trace or a surface mounted device (SMD), their layer
becomes the active layer. Selecting netlines, through pins and/or vias does not change the active
layer.
Clicking the left mouse button not only selects an item, it creates a select group. This group
contains all items in that position for all layers of the design, but within that select group, only
one item is selected at a time. Once a select group is created, use the Tab key to step through the
items within the group.
Using the left mouse button, you can control how much of the net is selected. Single-click a
trace to select just that net segment. Double-click a segment to select those segments in a path.
A path can be composed of a series of vias and their trace segments with either a component
pad, trace T junction or via that is active as a T junction at the ends. Triple-click a net element to
select the entire net.

Overview
Graphics Zoom
To add to the selected item(s), hold down the Shift key while you are selecting, this adds items
to those already selected. To subtract an item from the select group, hold down the Shift key and
click the left mouse button on a previously selected item, this de-selects that item.
Use the left mouse button if you want to select just a portion of a trace segment. A single left
click, then another single left click in a different location on the trace will select only the
segment between the clicks. You can then press and hold the left mouse button to move just the
selected segment. This is extremely useful for modifying and cleaning up traces and adding
notches in traces.
During the design process it may be necessary to select an area or group of items within your
design. The click and drag function of the left mouse button allows you to select an area within
your design. Using the mouse, point to a corner of the area you intend to select then press and
hold the left mouse button. Drag the cursor to the opposite corner of the area. Two boxes are
created:
• Select Area box - A box indicating the area to be selected will follow the cursor. All
items that fall within, end within, or touch this rectangle will be selected once the left
mouse button is released. Area select must be initiated in an open area and not on an
object within graphics.
• Cancel box - A small box indicating the point of origin for the selected operation is also
created. Its position remains static at the point of origin. To cancel the selected
operation, return the cursor to the Cancel box and release the left mouse button.
All items in the select area are selected except netlines. Netlines are selected only if one or both
ends of the netline are within the select area. Whenever a padstack is selected, netlines ending at
the pin are selected even if the netline display is turned off.
Graphics Zoom
Graphics zoom can be done using the mouse buttons and/or mouse wheel. You must hold down
the Shift key when moving the mouse to execute a Zoom. If you do not, you will execute a Pan
command. The following methods can be used to change zoom levels within the default mouse
mappings:

Overview
Graphics Pan
• Click Zoom - A single-click with the middle mouse button zooms in while a Shift-
middle-mouse-click zooms out.
• Drag Zoom - A Shift-middle-mouse-click and drag to the left zooms out while a Shift-
middle-mouse-click drag down to the right zooms in.
• Wheel Zoom - If your mouse has a mouse wheel (NT Only) rolling the wheel down;
zooms out while rolling the wheel up zooms in.
Graphics Pan
Graphics pan allows you to shift the view within the design without changing the zoom level. A
pan is done by pressing and holding the middle mouse button while dragging the cursor slowly
in the direction you want to shift the view.
Start the pan operation by placing the cursor away from the edge that you want to pan toward.
(If you begin the pan too near the edge you're moving toward, the velocity vector will be short,
and the pan will be slow.)
If you become lost in the process of panning a display, use either the Previous View
command or the Fit command to return to the last screen of information. Because the
application saves the screen information, it is possible to jump back to a previous screen.
In the View > Display Control > General dialog, the Pan Sensitivity line item within the
Options field can be selected to gain access to the dropdown list which contains a selectable list
of pan settings. These settings can be used to change the speed of the pan. To slow the pan
operation reduces the setting. To quicken the pan operation increases the setting. Select the Fit
Board icon to return the whole design to the workspace.
Finding Objects
If at any point in your design process you need to display specific items within your design use
either the Edit > Find command and/or the View > Display Control dialog box options. These
options can be used to show only selected or highlighted objects and also allow you to display
individual nets, net classes or groups. This process turns the rest of the display off, and allows
you to fully inspect those displayed items without the clutter of a fully or partially routed
design.
The Find command is a multi-purpose command that not only finds items in your design
but also allows you to select / highlight and/or fit those items. This command is accessed
through the Edit pulldown menu.
The Edit > Find Next Open Netline command can be used to display any open netlines.
The display changes to fit the open netline and information about that netline is shown in the
status bar.

Overview
Display Control
An item may be selected and highlighted at the same time, but any item which is highlighted
continues to be highlighted until all highlighting is turned off using Edit > Unhighlight All
.
When an item is selected, you can run Expedition PCB commands on it and use the Display
Control dialog to display just that item. If the item is only highlighted, you cannot run
Expedition PCB commands on it, but you can use the Display Control dialog to display just that
item. The screen refreshes to display just those items. You can also select all highlighted items
through the use of the Select All command within the Select sub-menu.
Display Control
The Display Control dialog defines how design graphics are displayed. Each graphic object, or
set of objects, can be turned on/off and have their color and or graphic pattern changed. The tabs
within this dialog group graphic objects based on route layers, general graphics, part graphics,
color by net and color by hazard. Each of these tabs contains the same basic controls: color
boxes, radio buttons, item check boxes and group check boxes.
Figure 1-5. Display Control Layer Tab
In addition to controlling the display in the design, the Display Control dialog allows you to
define the colors used for each item type. The color boxes to the left and right of the item names

Overview
Display Control
show the color used in the display for the item. The color boxes to the left of the item names
refer to the top of the design. Those on the right refer to the bottom of the design. When the item
has no relationship to either top or bottom, the color box is only shown to the left. For the
physical routing layers, the boxes to the left of the item names refer to traces; the boxes on the
right refer to pads.
By clicking your left mouse button on a color box, you gain access to the Colors dialog - a
palette that can be used to assign colors and/or graphic patterns to item types in your design.
The editable graphic patterns are in the file GraphicsPatterns.txt which is in the application's
../standard/config/pcb directory. If a pattern was chosen, select either the Outline or Transparent
check box. The Outline check allows the pattern to display with defined outline borders. The
Transparent check allows the pattern to display as translucent (not filled solid). The Force
Outline and Force Solid options on the General tab can override the Outline and Transparent
selection on this dialog.
The View/Collapse icons can be used to expand or collapse the list of items associated with any
of the dialogs' sub-headings.
Check boxes are used throughout to represent a single choice in a set of mutually exclusive
choices. You can only select one radio button in a group. The item check boxes allow you to
turn an item on or off in the display. If an “X” appears in an item’s check box, that item is
displayed.
There are times when it becomes necessary to turn all items of a particular type either on or off.
As shown in the above figure, there are two group check boxes for just this purpose: Trace and
Pad. These group check boxes override the item check boxes by turning on or off all items
within a group whether they are individually selected or not. This allows you to fully inspect
those items without the clutter of a fully or partially routed design. Within the Layer tab, there is
an option to turn all displayed elements to gray (Shadow mode).
Options within the General tab allow you to further control the display of items within the
design by allowing you to only display elements on the active layer, change the Background
Color of your design, mirror the contents of a view about the vertical axis, change settings
within the Display Control dialog, and have the graphics update only when the Apply button is
selected and only display text which is above a certain font size.
Display schemes can be defined to aid in the display of graphics during the layout process.
These schemes can be design-specific or used by all designs. The default schemes delivered
with the application cannot be changed or deleted, but they can be used as templates for new
schemes. User-generated schemes can be edited, saved and deleted. The use of these schemes
gives you faster access to changing your display of graphics.
If you want to:

Learn about the Layer Tab Information on page 35
Learn about the General Tab Information on page 38

Overview
Display Control
If you want to:

Learn about the Part Tab Information on page 40
Learn about the Net Tab Information on page 41
Learn about the Hazard Tab Information on page 42
Learn about the GroupTab Information on page 43
Layers
The settings within this dialog allow you to define the color, visibility of netlines and classlines,
grids, pads, planes and define the selection and highlighting options.
The Enabled Placement Layer check boxes, Top and Bottom, allow you to define your design's
placement layer. Once a placement layer is selected, it appears as the active layer in the Layer
Table within this dialog, and the Move Part command is the default action, allowing you to
select and move parts within your design.
The first column in the Layer/Type Table displays the layer numbers and the second shows
whether a layer is Signal or Plane. Enabled layers appear with either a V (for vertical directional
bias) or H (for horizontal directional bias).
Figure 1-6. Display Control Layer Tab Layer Type
The directional bias and enabled layers are defined in the Editor Control's General tab. Every
layer can have a user-defined paired layer. Both the active and paired layer are shown. The
Layer/Type table also shows which is the active layer and which is the paired layer:
Active Layer - Both the layer number and the layer type (Signal) are highlighted.
Paired Layer - Only the layer number is highlighted.
The Top and Bottom check boxes can be selected alone or together, but neither can be set in
combination with Internal. When the Command Window is active, you can toggle between the
active and secondary layers within your design by using the spacebar. When the Command
Window is not active and the application focus is in a dialog, pressing the spacebar no longer

Overview
Display Control
changes your active layer. Instead, it activates the selected option within the active dialog. The
Items section of the Layers tab allows you to select various objects within the design.
Figure 1-7. Display Control Layer Tab Items
Netlines & Classlines - You can control options regarding netlines and classlines display. To
view the netlines, you must have Classlines, All Open MST Netlines and Netlines of Classlines
displayed.
Buses - Bus Paths assume the same color as the trace layer, but with a transparent pattern
applied and the symbol of “P” or “U” to indicate Bus Packing. Bus paths display on top of
routed traces. Netlines span if bus paths is selected and the editor is in Place Mode.
MST span from component pins or bus path to a bus path if it is closer than a component pin.
Separated bus path segments can span netlines, if they are closer than component pins.
If forced order nets exist for a bus, then they span at forced order nets until a bus path segment
of the related bus is placed. In Route Mode, netlines span to component pins.
Grids - This section is limited to the radio button selection of the Place, Route or Drawing grid.
The Place, Route and Draw mode determines the grid selection. If you are in Route mode, only
the Route Grid can be selected, if you change to Place mode, the Place grid is selected, etc.
Pads - You can specifically assign a color and pattern to through, via and test point pads. This
specific color or pattern overrides the general pad layers assigned color and pattern.
Planes - You can display plane data, shapes and obstructs.
The Plane Shapes & Obstructs option enables the display of the plane shapes and obstructs
placed on routing layers.
The Plane Editing Sketches option enables the display of plane editing sketches, which are
boundaries used to define merge/subtract areas in input and generated plane shapes.

Overview
Display Control
The Plane Data option enables the display of outlines and tie legs generated by the Planes
Processor. However, these are only displayed if the main traces option is enabled and the
specific trace layer that the plane metal is generated on is also enabled. This checkbox is
unchecked by default the first time a design is loaded.
The Fill Hatch option controls the display of stipple fill and Hatch fill. It does not control
outlines or tie legs. The Plane Classes Parameters Dialog controls whether stipple fill or hatch is
generated by disabling or enabling the net for the plane shape.
The Plane Data behind Traces option allows the plane metal to be displayed graphically under
all traces and pads. When not selected, the plane metal displays with the active layer’s traces
and pads.
Copper Balancing - This option is only available if you have a FabLink XE license.
The Copper Balancing Data option displays metal generated by the Copper Balancing
Processor. This includes physical copper patterns that are added to either a signal or plane layer
and have no net name assigned.
The Copper Balancing Shapes option displays the Copper Balancing shapes placed on
signal/plane layers. The shape is not output to manufacturing, as its purpose is to define the area
where copper balancing data is generated. A copper balancing shape is placed using the Draw
functionality.
Materials - Displays any material shapes. The material shapes are only visible if both the route
layer of the shape and material is enabled. The production mask and overglaze controls are
under the Fabrication Layer section of the Display Control > General Tab.
Spacers - This section allows you to display any spacers within your design. Shadow mode
turns all displayed elements to gray, except for the spacers. The spacer color is the same color as
the associated trace segment.
Restriction: This option is not available within FabLink XE.
Selection & Highlights - Only selected and highlighted items can be viewed as well as
displaying the design in "Shadow mode". You can view the entire net within the design and/or
the starting pair of differential pair pins.
The selection of any physical net highlights all other physical nets that make up an electrical net
with the selected physical net. This option highlights all traces, vias and pads of the associated
physical net.

Overview
Display Control
General
The fields in this dialog: Fabrication Layer, User Draft Layers, Detailed Views, Board Items,
(Panel Items (if in FabLink XE)), Multiple Designers, Display Patterns, and Options, provide
access to the control elements that allow you to define their color and visibility. Each of the
fields in this dialog can be collapsed.
Figure 1-8. Display Control General Tab
Detailed Views
With a FabLink license detailed views can be placed and manipulated within an Expedition
design. See Detailed Views.
Board/Panel Items
All the board (PCB) and panel (FabLink XE) items in your design display allowing you to turn
them on or off.
Multiple Designers
Note
The Multiple Designers and XDS Force Fields options are only available if you have
TeamPCB™ or XtremePCB™ licenses.
TeamPCB Reserved Areas option displays all the reserved areas within the design created
using the Team PCB Split/Join Design commands.
Shadow Mode option turns all displayed elements to gray.
Xtreme Protected Areas option allow handles associated with the protected areas to enter and
move traces, vias and place components within the boundaries.

Overview
Display Control
These options are only available if you have an XtremePCB license.
This XDC Handle - This allows you to set the color and display for your force fields.
Other XDCs - This allows you to set the color and display for other client’s force fields.
Force Field Conflicts - If force fields are enabled, this is selected by default and any conflicts
are displayed as they appear. Force field conflicts are displayed when the client without priority
in an area has their commands and selections prevented.
Display Patterns
The line items within the Display Patterns section of this tab allow outlines to be displayed for
any object’s defined with a pattern that has the outline option turned off, and select to display all
objects with a solid fill if the assigned objects fill pattern was not defined as solid.
Options
The line items within the Options section of this tab allow you to:
Use the Auto Pan command. This is a toggle option that allows you to select a part, and by
holding the mouse button down, drag that part using the Pan command. If this option is not
checked, parts cannot be selected and moved using the Pan command.
Modify your cursor display to meet your needs. By default, the cursor is set to full screen.
Display a graphical display on your cursor for the max length/delay, matched length/delay, and
formula restrictions using a Tuning Meter. This displays values indicating if you are within
approaching tolerance, within tolerance or over tolerance.

Overview
Display Control
Change settings within the Display Control dialog, and have the graphics update only when the
Apply button is selected. When this option is checked, the Apply button is inactive until a
graphics setting is changed within the dialog. After the change(s) are applied, the Apply button
again becomes inactive until another change has been detected. If you select the Close
command after changes have been made but have not been Applied, a warning prompt displays.
Only display elements on the active layer. For example, if you have implemented teardrops or
breakout traces using the "Selected active layer pads" option and you turn via pads off, the
teardrops/breakouts attached to these via pads still display on non-active layers, which could be
confusing.
Only display text which is above a certain font size. If you use the Zoom in option on the design,
this small text becomes visible.
Control the speed of the Pan operation. To slow the pan operation reduce the setting.
Change the Background Color of your design using the Colors dialog.
Mirror the contents of a view about the vertical axis. This allows the board to display as if it
were seen from the bottom.
Part
The fields in this tab provide access to the control elements that allow you to define color, and
visibility of graphic objects built within parts and cells.
The display of virtual pins is controlled by the Pin Numbers and Pin Types options on the Part
tab of Display Control.
Figure 1-9. Display Control Part Tab

Overview
Display Control
The virtual pin, pin number is identical to the virtual pin reference designator. The Pin Type for
virtual pins is a “V”. An example of a displayed Pin Number, Pin Type combination, would be
VP1:V. Once the virtual pins are placed, they can be used as targets for netlines.
The Group Check boxes Top and Bottom can be used to limit or expand the range of the items
to be affected by the settings. For example, to apply the Item Check box settings to only those
parts on the top layer of the design ensure that the Top group box is selected. To apply the
settings to both the top and bottom layers in the design, ensure that both group boxes are
selected.
Net
The Nets tab allows colors or graphic patterns to be assigned to either net classes (groups of
nets), constraint classes (requires CES to have been used on the design) or to individual nets.
These colors override the default layer colors defined on the General tab.
Figure 1-10. Display Control Nets Tab
If the Net, Net Class and Constraint Class - Color By options are all enabled, then the net color
overrides the other colors. Likewise, Net Class color overrides the Constraint Class color if both
are enabled.

Overview
Display Control
If you have a Topology license, all nets within a bus are selected have their color applied to the
elements checked within the "Apply color to:" section of the dialog. This option overrides the
general layer color and pattern defined on the Layers tab. Once colors have been defined, you
can determine if you want to display these colors by net and/or class.
If you want to display only the netlines of the net class Diff_Pair (without seeing the net class,
Default), use the Apply Filter to netlines option in the Editor Control Filter dialog. All netlines
visible that are excluded in the filter become invisible.
Pads, Traces, Netlines, Vias and Planes can be selected allowing the color assigned to the Class
Names or Net Name to override the layer colors and color rules set in other tabs of this dialog. If
an “Apply color to” option is not selected, the layer colors and color rules set elsewhere in the
Display Control dialog are used.
Hazards
The Hazards tab allows you to define the color or graphic pattern of objects in hazard. If the
Display Hazard Symbols check box is set, markers are displayed where the hazard is located.
Selecting one of these markers and then selecting the Review Hazards option displays the
Review Hazards dialog with information on that specific hazard.
These options can be defined individually for every Online, Batch and Simulation hazard type.
The Shadow mode option turns all graphics, except the objects in hazard, gray.
Caution
Having multiple Color by Hazard options selected can cause a performance decrease in
the system, therefore only select the Hazard options in which you are specifically
interested.
DFF hazards have an additional severity attribute and you can display DFF hazards either by
their severity, or by their type (default). In FabLink XE, the DFF hazards only display if you are
working on a single design (*.pcb), and not a panel (*.pnl).
Additional DFF Information

All DFF Sliver Analysis options will invoke the Select a Color Fill Pattern dialog box when you
need to change its present color and pattern. All other non-sliver options will invoke the Select a
Color dialog box when you want to change its present color.
Regardless of the present state (selected/unselected) of the Display Control > General > Options
> Display Active Layer Only option, all analysis hazard symbols found on every enabled layer
of the last analysis run are displayed.
For this release, if you run the DFF analysis for both the Top and Bottom sides of the design,
you do not have the ability to only display the top side DFF analyses results (Top Silkscreen and

Overview
Display Control
Layer 1 turned on) while having the bottom side DFF analyses turned off (Bottom Silkscreen
and Layer 4), or the bottom side DFF analyses results (Bottom Silkscreen and Layer 4 turned
on) while having the top side DFF analyses turned off (Top Silkscreen and Layer 1).
It is recommended that you run the Soldermask, Silkscreen and/or Solder Paste analyses with
everything on for the first DFF analysis pass, just to establish the total number of DFF
violations found, and then run additional passes that have only the Top-side related layers or the
Bottom-side related layers enabled.
Hazards Display
Non-sliver hazards that are found are designated at the location of the problem with an “X”.
These hazards only have the “Select a Color” dialog box.
Sliver hazards that are found are designated by unique polygon shapes. All sliver hazards have
the “Select a Color Fill Pattern” dialog box. You can also select to fill the sliver symbol.
If two or more different hazards are found at the same location, the priority of the which layer is
displayed instead of the other layers is based on:
• Severe hazards (starting from Signal Proximity having the greatest layer priority down
to Silkscreen Sizes having the lowest layer priority).
• Moderate hazards, (starting from Signal Proximity having the greatest layer priority
down to Silkscreen Sizes having the lowest layer priority).
• Warning hazards (starting from Signal Proximity having the greatest layer priority down
to Silkscreen Sizes having the lowest layer priority).
Groups Tab
The Groups tab control the display of group bounding borders. As there may be a large number
of group bonding borders a filter is provided allowing you to narrow the number of groups that
display in the design. The filter field accepts standard wildcards; for example, typing stitch
would list all groups that start with "stitch", typing *contour would list all groups with contour
in their name.
Groups
A group can contain a single object but can also be a mix of other design objects and other
groups available in the design. For example, two RF shapes, one cell and a group that contains
two other RF shapes and a cell. Groups can be created in the design or be transferred from the
schematic. Groups are not automatically locked outside the toolkit.
Note
Netlines cannot be grouped.

Overview
Display Control
A default group is available and cannot be deleted. It is created when the RF toolkit is accessed
and is empty until an instance from the RF Library is added to the design and no other group is
set to be the active group. This group has a reference point of the board origin. Groups created
in the RF toolkit are protected and cannot be accessed outside the toolkit.
Creating and editing groups can only be done in the RF toolkit and is limited to the objects
available within the toolkit.
Special Conditions for Objects in Groups

Information about the group is displayed in the Status bar at the bottom of the design window.
When a single group is selected, the following information is displayed:
• Group name
• Location (X and Y position of the reference point).
• Layer and rotation
When multiple groups are selected, all names of the groups are displayed in a comma separated
list in the first field of the status bar.
Moving Groups or objects in a group

A group bounding border (closed polygon) is created for the group and is used in motion
graphics when a group is moved. This border hugs as close as possible to the distributed
elements belonging to the same group.
When moving a group, the group bounding border must be selected in Display Control and the
selection filter must have "RF Group" active.
When a group contains sub-groups, you can move around the groups using the Tab key. Moving
an object within a group does not affect the membership of the object. It still belongs to the
group after a move even if it is not physically connected to any other object within the group.
Lock/Unlock
To protect the group, you should select the group and then use the Lock function. When a group
is locked in the RF toolkit, the group or individual objects within the group cannot be
manipulated or moved. To manipulate a locked group or objects within a group, you should
select the group and then use the Unlock function. Unlocked groups or individual objects within
a group can be moved.

Overview
Saving Your Work
Add / Remove a single object

You can add or remove single objects from a group without using the Group/Ungroup dialog.
RMB popup > Group/Ungroup > Adds the selected shape in the design to the active group
Add to active group listed in the RF Control Pane.
RMB popup > Group/Ungroup > The selected object in the design is deleted from its
Remove group. RF shapes must belong to a group. If they are
removed they are automatically assigned to the default
group. RF Shapes and parts cannot be deleted from the
default group.
Objects available for grouping
• Conductive shape
• Groups
• Pad obstructs
• Parts
• Plane shapes
• Plane obstructs
• RF shapes
• Route obstructs
• Traces
• Vias
Saving Your Work

Use the File > Save command periodically, especially after performing major tasks.
Saving your data protects against data loss in the event of a system crash or power outage.
Use the File > Save Copy command to save a copy of the top-level layout directory (with
the option to save only the essential files) to the specified name and location. This command is
useful, for example, after completing part placement or critical routes. You could then return to
a previous version of the design. When the File > Save Copy command is invoked, A private
local copy of the current design /database can be saved to disk. You can save the current version
of the design before proceeding with the copy. If the PCB design file is not in the same directory
as the source project file or in a sub-directory under the source project file, an error message
appears and the copy is not performed.

Overview
Docking a Dataset
The Setup > Editor Control - Auto Save Options checkbox on the General tab, allows you
to automatically save your design databases to the job’s temporary work subdirectory at regular
intervals (default is 60 minutes). The Autosave interval range is from 0 (zero) to 1440 minutes.
Entering zero turns the Autosave interval off.
Auto Save places your data in a temporary location so that at any time, you can exit without
having the auto saved data permanently saved. However, in the event of a system crash, when
the design is re-entered, a dialog appears stating that Auto Saved data exists. This allows you to
open the design on the auto saved temporary data. The Auto Save data must be permanently
saved manually by selecting the Save option. Once you exit a design, the Auto Save data is
deleted. This option does not execute during an Auto Route session
The Auto Router can also Auto Save your current design at the time interval designated in the
Route > Auto Route dialog. If the Auto Router exits abnormally for any reason, and Auto
Save files exist, you are prompted with an option to update your design from the last Auto Save
databases the next time the application is initialized. The Auto Save files are written to disk, but
setting this option does not permanently save the PCB database.
Docking a Dataset
When a master dataset with one or more undocked backend datasets is opened, a message
appears asking if you want to dock the dataset before opening the design. If you select Yes, the
dock takes place and the design opens.
Dock - To take an isolated application dataset and pull the changes within the dataset into the
main design project. Any conflicts with the merged data have to be manually managed.
Undock - To isolate an application dataset from the main design project so it can be edited
regardless of the network or the physical location of the dataset. The isolated dataset will have
no dependence on the main design project.
Main Design Project - The master dataset from which the application specific design data is
isolated during the Undock process.
Undocked Design - The design that was created by the Undock process.
Caution
Any information that was changed in the master design prior to the undock is lost. If you
chose to leave the design project with read/write access, you are warned prior to the dock.
If after opening the design, you want to dock a dataset, the design should be closed and
reopened; this initiates the docking process. If there are multiple undocked datasets from the
main master design, a warning message displays informing you that it is your responsibility to
reconcile any differences between the undocked datasets before they dock them back into the
master design.

Overview
Undock
You can select the undocked dataset by selecting the down arrow; this displays a drop down of
all the undocked datasets. If an undocked dataset does not display in this list, you may use the
browse button to navigate to the correct location.
Once selected, verification is performed to check that the undocked dataset came from the
design. Datasets from other designs are not allowed to dock into a design from which they were
not created. If that happens an error message appears and you are requested to select another
dataset. You can also reset all undocks; this disassociates any undocked datasets and resets the
main design to have no undocked datasets. When the dock operation is completed the
information in the undocked dataset is now included in the master design.
Not Opening an Undocked Dataset

If you select not to dock the dataset when opening the master design, the layout tool needs to
determine which mode into which to open the design. If the main design project has an
undocked layout dataset, the tool checks if the source dataset was marked as read/write. If yes, a
warning message displays that Forward and Backward Annotation is disabled. If the dataset is
not read/write, the design opens read only. If the schematic is undocked, a message displays
stating that Back Annotation is disabled.
The titlebar of the application displays "undocked", to visually remind you that you are working
on an undocked dataset. For example:
<Tool> <c:\designs\motherboard\pcb\board.pcb> (Undocked)
The ability to browse for a new project file is disabled within the layout tool for undocked
datasets. Cross probing with CES is not affected by the undocked dataset.
Undock
Note
This option is only available when the layout tool is opened on an iCDB based master
design. Designs that contain netlist based design are not supported.
Undocking is also not available when opening a design that was previously undocked from a
master design; this prevents undocking from an undocked dataset. The undock operation
performs a complete save.
You can select the location to place the undocked dataset by clicking the browse button. If you
select a location that already contains an undocked dataset, you are informed and prompted to
choose another location. You can also check to include data that may be needed for cross
probing.
Information regarding the undock process displays in the message window at the bottom of the
application. If the message window is not visible; select View > Message Window. If the
undock process fails or is cancelled, the layout application continues to operate as usual.

Overview
Printing
Printing
When the design is complete and has been approved, it is time to prepare the files for archive.
For most companies, this means preparing some type of archive prints or plots. The
documentation is created and signed by the appropriate people, usually the design engineer,
CAD manager, CAD designer and the Checking department.
Windows Printing - Print Setup Dialog

Expedition PCB printing supports all print queues and drivers configured with the Windows
Print Setup dialog. The Print Setup dialog supports all user-defined print driver properties and
also supports other application-specific print options:
Print entire design - All design data is used in print area output.
Print view - Viewed window boundaries is used in print area output.
Scale - User defined percent scale.
Fit paper - Fits print area to selected paper size.
Mirror - Generates the plot about its horizontal axis.
Note
On the HP 2100 Series PLC-6 Windows Print driver, reference designator text is not
mirrored correctly.
No Footer - The footer note (filename and page number) is not included on the plot.
Black and white only - Produces black output when selected otherwise, it performs color
output.
Sun Solaris, HP-UX and Linux Printing

Printer configuration processes for Unix are different from Windows. The print setup/print
dialogs are identical to a PC with the exception of the properties menu options. Solaris, HP-UX,
and LINUX require the configuration utility "MWCONTROL" for new printer configuration.
Only Postscript printers are supported. When printing to some printers that support Adobe
Postscript Emulation, the printer may output an error that reads:
"Offending Command = ~Error = nametype : undefined".

To correct this problem, set an environment variable of:
MWPOSTSCRIPT_LEVEL1=true

Overview
Printing
The printing environment on UNIX is accomplished by a "default" setup, or may require user-
definitions within the application-specific mwcontrol utility. Registry information that is similar
to the Windows Registry is supported. The Add Printer Wizard has been improved.
The user MUST use the Visual MainWin Control Panel to configure printers for this release.
mwcontrol is the utility behind the Visual MainWin Control Panel. The interface contains
applets used to configure the application and the required system settings. This document is
only concerned with the Printers applet.
The Printer settings are stored in the current user and machine settings portions of the Registry,
depending on the parameters affected.
Note
If only one system printer is configured with Admintools, the File > Print dialog printer
specification "Generic Postscript" will print to the system "Default" Printer. The Generic
Postscript Printer options within the mwcontrol interface may require the editing of the
print command line "lpr; rm %s" as documented below.
Using the Visual MainWin Control Panel to Configure

Printers
To access the Visual MainWin Control Panel
1. Change directory to $SDD_HOME/common/<platform>/bin/.

2. Type the following command at the Unix command line:
sddmwcontrol
sddmwcontrol is a wrapper script used to setup the environment and then launch mwcontrol.
The Visual MainWin Control Panel appears.
Figure 1-11. MainWin Control Panel

Overview
Printing
Setting up printers
The Visual MainWin Control Panel Printers applet is similar to the Windows Printers applet.
However, unlike Windows, when setting up a printer you do not map an actual printer for use
with your application. Instead, you map a print request to a proper print command on your Unix
host. Thus, the procedure for adding new print capabilities differs slightly from that on
Windows.
Note
PostScript Printer Description (PPD) files describe how to use the special features for a
specific PostScript printer. To take advantage of your printer's specific features, for
example; duplex printing or paper tray selection, you need the PPD file. Most printer
vendors provide PPD files for their printers. For your convenience, Visual Mainwin
Control Panel supplies a large subset of the PPD files that are included with Windows. In
addition, a PPD file for generic PostScript printers, which should allow you to print on
any PostScript printer, is also provided.
The Visual MainWin Printers applet includes an Add Printer wizard, as described below.
1. Launch the Visual MainWin Control Panel.

2. Double-click Printers to open the MainWin Printers applet.
Figure 1-12. MainWin Printers Dialog
3. Double-click Add New Printer to start the Add New Printer wizard.

Overview
Printing
Figure 1-13. Add New Printer Dialog
4. Click Next.
Figure 1-14. Identify your UNIX Printer Dialog
5. Specify the Unix printer to which you want to print. A list of the printers defined on the
Unix host appears at the bottom of this page. If the printer you want to add is on the list,
select it. To add a printer that does not appear on the list, type the Unix name of the
printer in the Unix printer text box. The printer name should be keyed using the same
printer name as used in the System Print Manager or Admintools Interface.

Overview
Printing
Note
The list of printers is extracted from the /etc/printcap file, which contains a list of all
printers on the network to which your Unix host has access. The printcap file is used on
Unix platforms as the central location for specifying printers. It is configured and
maintained by the system administrator. In case your system does not have this printcap
file, and there are no printers listed, then you should add the Unix name of the printer,
manually.
Some Unix Operating Systems do not support /etc/printcap files. Solaris and HP-UX
support /etc/printers.conf. Mentor Graphics is working with MainSoft on changing the
MWCONTROL Utility to read the /etc/printers.conf. Until then, the user should
manually configure printers.
6. Click Next.
Figure 1-15. Print Command Dialog
The default print command for the selected printer appears in the Print Command text
box. Usually, the default command is the one you should use. You may need to modify
the command depending on the UNIX OS the system is running. The "lpr -P
printername; rm %s" may need to be modified to "lp -d printername; rm %s". The "lp"
and "lpr" Unix print commands sometimes reside in directory other than /bin and the
<path> may need to be add to the command line; ex: "/usr/ucb/lpr -P printername; rm
%s". The Unix Print command "lp" should work with all Unix OS Systems.
Tip: If you manually added a Unix name of a printer in the previous step, the print
command will automatically use that name.
7. Click Next.

Overview
Printing
Figure 1-16. Choose PPD File Dialog
8. Select the manufacturer and model of your printer. If, however, you have your own PPD
file, then click Choose File to locate your PPD file. After entering the file's full
pathname, click OK.
Note
If you use your own PPD file, you must either have write permission to the directory
"/MentorGraphics/2004/common/<OS Type>/mw502/system/ppd".
If you do not select anything in the Choose PPD File page, then a default generic PPD file
is automatically selected.
9. Click Next.
Figure 1-17. Printer Name Dialog

Overview
Printing
The Add Printer wizard provides a default printer name, which may be modified in the
Printer Name text box. The Printer Description text box has the same functionality as on
Microsoft Windows.
10. Click Next.
Figure 1-18. Default Printer Dialog
Decide whether you want this printer to be your default printer.
Note
This Default Printer page will not appear in the wizard if this is the first printer you are
setting up. When you add another printer, then you will choose your default printer.
11. Click Next.
Figure 1-19. Print Test Page Dialog
Printing a test page (similar as in Windows) supplies you with various information, such
as the features of the added printer.
12. Click Next.

Overview
Time Zone Constraints
Figure 1-20. Finishing Add New Printer Dialog
Verify the information you specified in the Add Printer wizard is correct. If you are
satisfied with the settings, click Finish. Otherwise, click Back to change the settings.
The printer you added now appears in the list of printers and these printers will now
show in the File > Print Setup and File > Print dialogs.
Time Zone Constraints

The date stamp stored internally in files uses the time zone of the system. Therefore, if you have
two systems with different time zones, you may have problems opening the files. If so, an error
message is generated stating that the files were created in the future.
If you experience problems with differences in timestamps when you move your designs across
the network, make sure that the time zones on all platforms are consistent. If the time zones on
all systems are not in sync, there may be a difference of one or two hours between the
timestamp and the clock time of the computer on which you are trying to edit the file. If this
occurs, you must synchronize the systems for this application to operate properly.
Some networking systems (such as Novell) have the capability to override the setting in the
autoexec.bat file and reset the time zone variable back to Greenwich Mean Time thus creating a
time zone inconsistency. Consult your networking software documentation for information on
how to set the correct time zone on your system.

Overview
Mentor Graphics Support
Mentor Graphics Support

Mentor Graphics software support includes software enhancements, technical support, access to
comprehensive online services with SupportNet, and the optional On-Site Mentoring service.
For details, see:
http://www.mentor.com/supportnet/options
If you have questions about this software release, please log in to SupportNet. You may search
thousands of technical solutions, view documentation, or open a Service Request online at:
http://www.mentor.com/supportnet
If your site is under current support and you do not have a SupportNet login, you may easily
register for SupportNet by filling out the short form at:
http://www.mentor.com/supportnet/quickaccess/SelfReg.do
All customer support contact information can be found on our web site at:
http://www.mentor.com/supportnet/support_offices.html
Product Licensing Assistance

Contact the Mentor Graphics Customer Response Center at 1-800-547-4303 or your regional
sales office to obtain new product licenses or to address questions or issues related to product
licensing. Please include the following information with your request:
• Your name
• Company name, address, telephone number and email address
• List of products you would like to license or upgrade
• Name of server(s) that you plan to use (if different from your current server) including
any new licensing server configurations
• The host ID numbers of client and licensing server workstations for node-locked
licenses
• The host ID number of the licensing server workstation for all floating licenses
International customers should contact their local Mentor Graphics sales office for product
licensing assistance.

Chapter 2
Library Manager and the Central Library
Before getting started, you should review the Library Manager Process Guide that describes the
recommended procedures for creating and maintaining your company libraries. This process
guide also walks you through a simple integrated design flow using the tools launched directly
from the Library Manager interface. While your company’s process may vary, these procedures
illustrate the basics of how to use the Library Manager™ and its tools.
Brief information about the DxDesigner™ - Expedition™ Library Manager Interface is also
included in this Chapter. In depth information about the DXDesigner Interface is documented in
the Library Manager Process Guide.
Note
We strongly encourage you to perform a nightly backup of your central library and all
associated directories to another machine. This ensures that all data is preserved in the
event of a disk drive failure or if the data becomes corrupted.
What is a Central Library

A central library is a collection of interrelated libraries with an improved level of data integrity
and consistency checking. A central library contains a library management and control file
(.lmc) that maintains an inventory of the contents in the central library.
An individual library (one of the sub-folders in the central library) is a collection of partitions.
Libraries are the storage locations for parts, cells, symbols, IBIS model software, padstacks,
reusable blocks, and parametric data (from Parts Manager in the DC/DV-Expedition flow and
DxDatabook Data Editor in the DxD-Expedition flow).
A partition is a user-defined grouping of data objects. For example, the Cell (footprint) library
might be separated into partitions for SMD Cells, Through Cells, Mechanical Cells, Panel Cells,
and Drafting Cells.
The Library Manager interface controls central library creation, partition editing, and invocation
of library editors. Designs then reference a central library as a whole rather than inter-mixing
library files from various locations.

Production Flows Supported by Library Manager

Library Manager features three product flows that include all the software tools needed to create
symbols, cells, and parts. These distinct design flows are based on the type of central library you
use:
• Design Capture/DesignView - Expedition PCB: Using Design Capture or

DesignView to create and manage parts, cells, symbols, and padstacks, Parts Manager to
manage parametric data (Windows only), and IBIS Librarian. Use Expedition PCB to
link to a schematic project, compiling a PCB design, placing cells, performing gate
swapping, pushing a cell, and replacing a cell.
• DxDesigner - Expedition PCB: Using Dx Symbol Editor to create and manage
symbols (or import symbols from DxDesigner), DxDatabook Data Editor to manage
parametric data, and IBIS Librarian or Visual IBIS Editor. Use Expedition PCB to link
to a schematic project, compiling a PCB design, placing cells, performing gate
swapping, pushing a cell, and replacing a cell.
• Expedition only flow - using Design Architect to create symbols.
Recommended Central Library Permissions

The company librarian controls access to partitions in a central library and sets the access
privileges for numerous purposes. For example, symbols or cells (footprints) which have not
been checked and certified for use may be placed into a partition that is inaccessible to
designers, and production partitions may be read-only to designers.
To disallow individuals from making changes to a central library but still allow Read access for
viewing library data, the central library must be loaded on a Windows NTFS, Linux, or UNIX
operating system disk. All files, whether they are on Windows, UNIX, or Linux, should have
Write permission except for individual library files, which can be write-protected as desired to
control access.
Note
Windows users can use the Properties/Security dialog box and Linux and UNIX users can
use the chmod command to adjust central library permissions to corporate guidelines.
Files that can be permission-controlled are:
• Common property (CentLib.prp) file

• Padstack library (padstackDB.psk) file
• Layout template files (Templates directory in a central library)
• Files in the CellDBLibs, IBISModels, PartDBLibs, and SymbolLibs subdirectories.

• Parts Manager database (partsmanager.mdb) file (DC/DV-Expedition flow only)

• All other files in the central library should remain Everyone = Change (read-write) to
ensure proper operation of the library.
The Windows share that allows access to the central library directory from remote machines
must have permissions set to Everyone = Full Control. The share permissions are superseded
User Access to a Central Library

More than one user can access a single central library (.lmc) file at a time with different
machines. When multiple users access a central library, the partition opened first by a user for
editing is write-protected. Other users can access information in that central library partition in
read only mode. Once the user editing an entity in a partition has written information to disk and
closed that partition, then Library Manager software grants access to another user. Multiple
users can edit different partitions in the same central library simultaneously.
While not recommended, Library Manager allows multiple central libraries. A central library
cannot be created in a directory that contains a central library file (.lmc), a project file (.prj),
and/or an Expedition PCB file (.pcb). Only one central library is associated with one design.
Designs reference one central library as a whole.
Note
In EE2007, certain types of objects in pre-EE2007 central libraries must be migrated to
the current release because the EE2007 software looks for library data objects (such as
reusable blocks, layout templates, and symbol data) in their new central library
directories. See Opening a Pre-EE2007 Central Library File to Convert to EE2007 on
Page 51 of the Library Manager Process Guide.
Partitions
Partitions provide the following advantages:
• Access Privileges - Each partition may have settings that control its access. The library
administrator may setup the access privileges for numerous purposes. For example, cells
or symbols that have not been checked may be put into a partition that is inaccessible to
a designer.
• Simultaneous Access to a Library - When editing a library, the active partition is
reserved until the editing is complete; the other partitions are available for editing by
others. In this way, multiple users can be editing different partitions in the same library
at the same time.
• Search Paths - The library administrator can set search path schemes allowing searches
to focus on partitions containing frequently used parts.

Library Manager Workspace
Library Manager Workspace

Library Manager delivers a library-centric environment that illustrates the entire library
contents and data. Users access interactive library management tools and data (design) editing
software from the menu bar, tool bar, and Library Navigation tree. The Library Navigation tree
identifies the active central library and the contents within partitions (symbols, cells, parts,
padstacks) associated with a selected central library. Library Manager is a launching area for
library/project management, design management, and editing tools.
Figure 2-1. Library Manager Workspace
Library Navigation Tree Viewer

The Library Navigation Tree is located by default to the left of the design space. This displays
the active central library and all contents within the Parts, Cells, Symbols, and Padstack
partitions within that central library. This allows you to view associations between entities
within the central library without opening several different editors in the workspace.
Project Tab
Use the Project tab to open, view, edit, and save symbols, cells, parts, and padstacks within
partitions in the selected central library (*.lmc). When you select an entity in the Project tab, the
software invokes the appropriate editor and displays the entity in the display area. For example,
if you select a symbol from the Library Navigation tree, the software displays the selected
symbol. You can also invoke the appropriate software tool from the toolbar or menu bar and

Library Manager Utilities and Editors
then open the symbol within the application. Files are recognizable by the associated icon and
file extension.
Menu Bar
Library Manager commands are listed on pulldowns available from the menu bar. Click the
topic to display a cascading list of library management, design creation and manipulation, and
user interface control tools. Many of these same commands are accessible via the toolbar.
Toolbar
The toolbar provides one click access to most tools and utilities associated with Library
Manager. To determine what tool or utility is associated with a toolbar icon, position your
cursor over an icon and a tooltip (label associated with the icon) appears and identifies the
associated tool or utility. The status bar (bottom of the Library Manager interface) also displays
the tool or utility associated with an icon.
Toolbars can be repositioned in the interface by dragging the toolbar to the desired location on
the interface (called docking).

Library Manager provides tools to manipulate data and manage access to Central Library files.
When Library Manager is invoked within a point tool, DXDesigner, Design Capture or
Expedition PCB, only editors that apply to the specific point tool are available.
If you want to:

Learn about Library Services Information on page 62
Learn about Setup Parameters Information on page 73
Learn about the Property Definition Editor Information on page 64
Learn about Property Verification Information on page 71
Learn about the Partition Editor Information on page 72
Learn about Partition Search Paths Information on page 72
Learn about Unreserving Partitions Information on page 72
Learn about the Part Editor Information on page 64
Learn about the Material / Process Editor Information on page 68
Learn about the Symbol Editor Information on page 66
Learn about the Cell Editor Information on page 67
Learn about Reusable Blocks Information on page 69

If you want to:

Learn about the Parts Manager Editor Information on page 69
Learn about Units Display Editor Information on page 73
Learn about the IBIS Model Editor Information on page 69
Learn about the Visual IBIS Editor Information on page 63
Learn about Import Symbols Information on page 63
Learn about Modify Cells & Symbol Pins Information on page 63
Learn about the Padstack Editor Information on page 70
Learn about Layout Templates Information on page 70
Learn about the Output PDF Information on page 70
Learn about the File Viewer Information on page 71
Library Services
Library Services allows you to manipulate data within your Central Library file. Tools available
from this dialog provide a means to import and export parts, cells, symbols, padstacks,
materials, processes and IBIS Models between the following. Tools are also available, from this
dialog, to delete parts, cells, symbols, padstacks and IBIS Models from a library.
• From a central library (.lmc) file to another central library (.lmc) file
• Between partitions in a central library file
• From PCB (on a designer's workstation) to a central library (.lmc) file
• To and from ASCII (.txt or .hkp)
Library Services is accessible from either within the Library Manager environment or from the
Setup pulldown in Expedition PCB. Library Services allows you to copy, move, and delete
parts, cells, symbols, materials, processes, padstacks, and IBIS Models from partitions in the
Central Library.
When invoked from within a PCB job’s local design library, extractions are only allowed from
the attached Central Library. When invoked on a Central Library, local design databases and
other central libraries can be used as the source library during extraction. However, when
exporting library data, you cannot export to a local design's library. You can use the Export
feature only between central libraries.
When importing parts and cells from a library, all referenced objects are automatically
imported. For example, importing a part automatically imports the cells and symbols called by
the part's entries, and the padstacks called by the cells. The same applies when exporting parts
and cells to a library. If you import or export parts and cells from/to ASCII, the software only

processes the selected part or cell. Referenced objects are not copied to or from ASCII. For
example, if cells are exported to ASCII, only the cell data is exported; the associated padstacks
need to be exported separately.
Use Design Capture and Expedition PCB to create templates that have schematic parts placed.
Library Services will not allow parts to be added to a job without Forward Annotation being run
because the schematic data is directly associated to the part data.
Modify Cells and Symbols

Use this dialog box to rename and renumber cell and symbol pins. Pin changes cannot be
completed if any cell or symbol partitions are reserved. If any partitions are reserved, a message
dialog displays that provides information on which partitions are reserved. If none of the cell or
symbol partitions are reserved, then a confirmation dialog appears detailing all the part entries
that are affected by the change. You can accept the changes or cancel.
Visual IBIS Editor

When accessing Library Manager in standalone mode, you may not know which flow is being
used in Expedition PCB, therefore access to both IBIS editors is available. When using a CES
flow, the Visual IBIS Editor must be used. The Visual IBIS Editor allows you to use the IBIS
Model specification (Version 3.2) and should be used in a CES flow.
The Visual IBIS Editor supports multiple modeling languages VHDL and IBIS and when the
Visual IBIS Editor is selected, an additional dialog appears asking you to select either an:
• ICX Pro Visual IBIS Editor

• ICX Pro Visual VHDL Editor
Import Symbols
Use the Import Symbols command to copy symbols into a symbol partition in an active Central
Library. You must have a valid symbol partition in your active Central Library to import
symbols from another Central Library or an external symbol file. The software copies all
representations for a symbol (example: Sym.1, Sym.2,..., Sym.n). The software also copies any
associated WIR and SCH files for each symbol, if they exist.
When you invoke the Import Symbols command, the Select Symbols to Import dialog box only
displays version *.1 symbol files. Even though version *.2, *.3, (and so forth) symbols are not
displayed in the browser, the software also copies these symbols. You can copy more than one
symbol via the dialog box, by holding the Shift key and highlighting the symbols you want to
import.

Property Definition Editor (Common Properties)

The Property Definition Editor allows you to define the available properties and their format in
a Central Library. You can define new properties and define property types and their associated
syntax. You can also change certain attributes of pre-defined system properties. The values of
the properties themselves are stored on the data objects and are not defined in the Property
Definition Editor.
When a Central Library is created, the software automatically places a default property file
(centlib.prp) into the directory.
Part Editor
The Part Editor provides tools to create and modify the part entries. Parts provide a link between
the physical design cells and schematic symbols through packaging information, such as gate,
pin, and device definitions.
Electrical Board Description (EBD) files are assigned in the Part Editor and EBD models or
IBIS models can be assigned by adding an IBIS property to the part entry and then browsing for
the desired model. When an EBD model is assigned to a part entry, the pin mapping is
automatically verified and if there is a mismatch between the part pins and the model pins, an
error dialog displays.
If the Part Editor is invoked from the Setup pulldown in Expedition PCB , changes are
made to the LocalPartsDB.pdb and not the Central Library part databases. The
LocalPartsDB.pdb is the localized parts database, which is created from the Central Library part
databases.
All the partitions in the central library are displayed using the Partition dropdown list.
DX Designer Packaging Parts

The DxDesigner packager translates logical components into physical parts. Using the central
library with the part enables you to:
• Process the symbol and map the data to a logical symbol.

• Annotate pin numbers in the part to new components as you place them, or to existing
components.
• Pass data forward to Expedition and back annotate changes to the schematic.
Before you assign pin numbers from a central library part, you must:
• Import DxDesigner legacy libraries into the central library using the Library Migration
Wizard. The resulting symbol graphics and part file containing pin number assignments
can then be accessed from the central library.

• Specify the path to the central library in the project’s design configuration.
Mapping Expedition Device Data to DxDesigner Device

Data
Expedition device data is extracted from the part in DxDesigner. The following table maps
DxDesigner device data to the part.
Table 2-1. Mapping Expedition Device Data to DxDesigner Device Data

Expedition Device DxDesigner Data Expedition Part Expedition Part
Data (ASCII Editor field
Representation)
Device Name DEVICE/Symbol Part Number Part Number (key
component attribute field)
value
Part Number P/D_NUM component Name Part Name (optional,
attribute value (optional, name of the part)
defaults to DEVICE
value)
Reference REFDES symbol RefPrefix Reference
Designator Prefix attribute value designator prefix
(used as a character
prefix for reference
designators)
Default Footprint PKG_TYPE component TopCell Top Cell Name
Name attribute value
Bottom Footprint N/A BottomCell (not Bottom Cell Name
Name included in part file) (not used)
Alternate Footprint ALT_PKG_LIST AltCell [one entry per Alternates
Name component attribute alternate package]
value
Symbol Names All symbols in the design Symbol [one entry per Symbol Name
sharing a common device symbol]
DEVICE attribute value
Symbol Pin Names Symbol Pin Labels Symbol_SwapGroup Logical pins: Pin
[unique value per Name
device symbol]...
PinName [list of
symbol pin labels, in
symbol pin order]

Table 2-1. Mapping Expedition Device Data to DxDesigner Device Data

Expedition Device DxDesigner Data Expedition Part Expedition Part
Data (ASCII Editor field
Representation)
Pin Swappability PINSWAP symbol SwapGroup…SwapI Selection of the
attribute D [unique SwapID Swap icon
value for each
swappable pin group,
in symbol pin order]
Device Pin Types PINTYPE Symbol pin SwapGroupProperties Pin Type Property
attributes ....Prop "Pin Type and Value
Slot Swappability Determined by matching Slots [one entry per Selection of the
symbol names. device slot]… Swap icon
Heterogeneous devices Slot_SwapGroup
can have multiple [One Slot_Swapgroup
symbol names per device per device slot, listing
each pin number per
slot in symbol pin
order. Each
swappable slot has a
unique
Slot_SwapGroup
name]
The DEVICE attribute is required for a DxDesigner symbol to be mapped into a part number in
a part. It identifies the corresponding parts in the part and associates the schematic symbols with
the physical cells using the part number property. The part enables you to map the same symbol
to different parts. It also enables you to map different cells/symbols to a single part and enables
you to map the same symbol/cell to different parts.
Symbol Editor
When Library Manager is invoked within Expedition PCB, Symbol Editor and Parts Manager
Administrator are not available from the Library Manager interface.
The Symbol Editor is a separate editing environment where you create and edit symbols.
Symbol Editor allows you to open multiple libraries and edit multiple symbols during a single
session. Each symbol window contains tabs along the bottom that represent the composite view
of the symbol and the eight available rotations to build for a symbol (0˚, 90˚, 180˚, 270˚ and the
mirrors for each). Place all graphics, pins, and text in Composite view and (if desired) modify
the position and rotation of text properties in the eight rotation views. If you make modifications
in the rotation views (views other than the Composite view), the Composite view reflects the
text position and rotation in the 0˚ view.

Symbols are stored in library files (also referred to as partitions). The filename extension of a
symbol library is ".slb." The library files are binary compatible across all supported hardware
platforms and operating systems. Within a library, symbols are identified by symbol name and
internal time stamp. Each library can contain multiple versions of each symbol: however, only
the latest version is editable in the Symbol Editor. A new version is created each time the
symbol is saved.
Cell Editor
The Cell Editor allows you to create Package, Mechanical, Drawing and Panel cells in the
partition you created within your .lmc file.
Note
Panel Cells are only available through FabLink XE or Library Manager stand-alone and
are elements that are added to a manufacturing panel to aid in the manufacturing process.
Package cells are associated with a part in the Parts Database. Mechanical cells are objects such
as nuts, bolts, card ejectors, heatsinks, washers, and plastic mounting devices, which may or
may not be referenced in the Parts Database. Drawing cells are composed of drawing objects
and text. Within a given library (Central or Design), the names for mechanical and drawing cells
must be unique regardless of their partition.
The Cell Editor can also be accessed through the Setup pulldown in Expedition PCB . Cell
Editor allows all three modes (Place, Route and Draw) with functionality restricted in each
mode to commands necessary for editing a cell.
All the partitions contained within the Central Library are available from the dropdown list.
Your ability to view and edit these partitions is limited by the protection settings defined by the
Library Administrator. Partitions that do not have Read or Write access are insensitive and the
partition name is greyed. Partitions which have Read access only have (Read Only) added and if
selected, the OK button on the Cell Editor dialog is inactive.
Note
When cells are edited the text locations are not modified on the board if the ECO >
Replace Cell > Keep text attributes during replace option within Expedition PCB or
FabLink XE is selected. You must unselect this option before editing a cell's text location.
When making changes to any of the fields in this dialog, you must first reset the focus of the
mouse by either selecting another row or by selecting another operation such as Delete, Copy.
before the OK and Apply buttons become enabled.
All parts are required to be built as if they were viewed from the top side. If you intended on
creating top and bottom cells for a part, the bottom cell should be built as viewed from the top.
Normally, it is not necessary to create a bottom side cell. Top cells can be pushed or mounted

directly on the bottom of the board and the pads revert the bottom side pads as defined in the
Padstack Editor. In this case, the reference designators automatically mirrors and cell graphics
revert to bottom side entities.
All the partitions contained within the central library are available from the drop down list.
Your ability to view and edit these partitions is limited by the protection settings defined by the
Library Administrator. Partitions which do not have Read or Write access are insensitive and
the partition name is grayed. Partitions that have only Read access have (Read Only) added and,
if selected, the OK button on the Cell Editor dialog is grayed.
Rules within the Cell Editor for Nested Cells

Nesting associations can only be made with the Cell Editor . The nested mechanical and
drawing cells are referenced in the package cell so that any modifications to the original cell are
automatically reflected in the package cell. A mechanical or drawing cell that is referenced by a
package cell cannot be deleted. If a nested mechanical or drawing cell is renamed, it is
automatically renamed within the referenced package cells.
Allowed
• Mechanical and / or drawing cells may only be placed in a package cell
• One or more mechanical cells may be placed in a package cell
• One or more drawing cells may be placed in a package cell
Not Allowed
• A package cell in a package cell
• A package cell in a mechanical cell or a drawing cell
• A drawing cell in a mechanical cell
• A mechanical cell in a drawing cell
• A mechanical or drawing cell in a Jumper or Test Point
The mechanical cell may be placed on the top or bottom layer. A mechanical cell may be
pushed to the bottom layer if required. The drawing cell data is placed on the layers
defined in the drawing cell. If you want to mirror the drawing cell, the mirror commands
within Draw should be used.
Material / Process Editor

In order to design with embedded passives a number of material properties must be defined. An
embedded passive is built into the product and is a device that does not add energy to the signal
it passes, for example: resistors, capacitors, inductors.

The materials are stored in a material library and all editing of material and process properties is
done in the Material/Process Editor. To limit the number of materials and processes within the
Cell or Layout Editor, Library Services is used to create and modify the local libraries as well as
the importation of material and process information from external sources.
Since embedded components are part of the fabrication processes and not an assembly process,
the Bill of Materials (BOM) does not reflect the components as physical components.
Parts Manager
If you do not purchase Parts Manager, the Parts Manager icon on the Library Manager interface
becomes non-selectable.
Parts Manager is an electronic component management tool that provides access to parametric
data and part data stored in a relational database. Users of electronics design applications, such
as Design Capture, can access this data from nodes on the network.
Parts Manager stores and retrieves parametric data from a database. Parametric data in the Parts
Manager database works in tandem with the Library Manager software which stores
information on symbols, parts, and cells in partitions in the Central Library.
Reusable Blocks
Reusable blocks are sections of circuitry that are reused in multiple designs. The Reusable
Block functionality within the Library Manager interface allows the creation and modification
of Reusable Block circuity. These reusable blocks are stored within the Central Library so they
can be used by all designs that reference this same library. See “Reusable Blocks” on page 309
for more information.
IBIS Model Editor

IBIS is an industry standard format used to describe the behavior of inputs and outputs of active
devices. IBIS Librarian organizes and verifies device models for use in transmission line
simulation by Signal Vision and Signal Analyzer. IBIS Librarian facilitates organization of
models by device vendor, technology, function. The models are then verified for compliance
with the IBIS format prior to simulation. Models may also be edited within the Librarian.
Multi-board simulation is available in support of IBIS ver. 3.2 for EBD models. Models may be
created from the existing design for instant use and saved using the Save Electrical Board
Description command. Any errors found during the creation of the EBD file generates a log file.
The log file is placed in the <design name>/PCB/LogFiles directory and is named
EBDGenerationLogFile.txt.
EBD files are assigned in the Part Editor and EBD models or IBIS models can be assigned by
adding an IBIS property to the part entry and then browsing for the desired model. When an

EBD model is assigned to a part entry, the pin mapping is automatically verified. If there is a
mismatch between the part pins and the model pins, an error dialog displays.
A graphical viewer displays I/V curves for pulldown/pull up states and power / ground clamps
as well as V/T curves for rising and falling edges.
Padstack Editor
The Padstack Editor can also be accessed through the Setup pulldown in Expedition PCB .
The Padstack Editor allows you to create padstacks that are one of five types:
• Fiducial
• Mounting Hole
• Pin-SMD
• Pin-Through
• Via
When defining a padstack you first need to assign one of the above types. Once defined and
named, you can assign different pads to each layer, specify pad filters, define holes, and define
any custom pads or drill symbols. From the Custom Pads & Drill Symbols tab, you can import
DXF data to be used as either a custom pad, an obstruct, or drill symbol graphics objects.
If you change the name of a padstack that is referenced in the design, and then want to delete the
original, you must Save and Exit the Padstack Editor before these changes are seen.
Layout Templates
Layout Templates allows you to select the template for a design or create a template using
Expedition PCB to start the job then set the attributes of the job as needed. The Available
Templates list displays all the available templates in the Central Library.
Two templates are delivered (4 Layer Template and 8 Layer Template) that contain layer
settings and spacing.
You need to use Design Capture and Expedition PCB to create templates that have schematic
parts placed. Library Services will not allow parts to be added to a job without Forward
Annotation being run because the schematic data is directly associated to the part data.
Library PDF Documenter

The Library PDF Documenter option allows you to generate a customized PDF document
containing a listing of selected layers (system, user) with cell items, part and symbol
information and graphics that are present within the Central Library partitions.

File Viewer Utility

The File Viewer is a utility, available from the File pulldown menu on the Library Manager
interface and from the File pulldown menu within Expedition PCB , which allows you to
view the contents of ASCII files with the .txt extension, such as process log files.
These .txt files are located in the job's LogFiles directory. Options are also provided from the
pulldowns to delete; rename; print; send; copy; find; list with or without details, and arrange by
Name, Size or Date.
Property Verification
The Property Verification Settings dialog, available from the Setup > Library Manager >
Setup > Property Verification, provides a list of our products that can be used in your design
process. Placing a check next to the tools you use ensures that your library entries will be
verified to meet your design needs and comply with our other down-stream tools. By default, all
tools are selected.
This verification is available for part entries and performed via the Parts Database Editor. You
can designate which product is used so that required data sets for data objects is known. For
example, the Part Editor would be sensitive to which properties need values based on the
downstream tools that use the part information.
If your company does not use any of our products listed on this dialog, you can de-select those
options. This reduces the amount of error checking performed by the software. If you de-select
our tools on this dialog but purchase/use them at a later date, be sure to enable these options to
ensure proper verification.
When establishing property verification settings for your Central Library file, any of our tools
that you are not using can be turned off.
For example, if you create a new part in the Part Editor, the Part Name/Number/Label displays
in red text that notifies you that certain properties required by downstream tools have yet to be
added.
If you selected any tools other than Design Capture and Expedition PCB, then red text may
appear indicating that you have additional properties associated with your part.
The PCB Thermal and SI options are only accessible if you select the PCB checkbox. If the
Signal Analyzer / Signal Vision option is not selected, you will not be able to create an error
report from the Part Editor - Output pulldown which details any IBIS model errors for part
entries.

Partition Editor
The Partition Editor (Setup > Library Manager > Setup > Partition Editor) allows you to
create new symbol, cell, part and IBIS model partitions, rename existing partitions, and remove
partitions from the central library if you have the correct permission. You cannot remove a
partition that is in use (reserved) by another user or which contains parts. Partitions are library
files that allow you to store data within your .lmc file.
Information about the number of existing entries in the partition and whether that partition is
reserved (in use) displays on this panel. If the library partition is reserved, other users can access
the partition in Read Only mode (no changes are permitted) until it is unreserved (not in use).
Partition Search Paths

The Partition Search Paths dialog is available from, Setup > Library Manager > Setup >
Partition Editor. Partition search paths can be unique for each library. During actual use, we
recommend you use the default search path scheme as a template to create custom search path
schemes that increase the speed and efficiency of searches. For example, if you have separate
domestic and international facilities that use different parts, you can create a customized search
order scheme for each facility.
By putting a frequently used partition at the top of the search path scheme, the software
automatically searches that partition first during a part search.
Once you create a search path scheme, you can add, remove, or reorder the search paths for each
library by placing a check in the appropriate boxes and using the arrow buttons.
You can grant users permission to alter the search path scheme at the design level by selecting
the check box in the Scheme List. A search scheme includes all partitions in a Central Library.
At the design level, when a Central Library is selected for use in a design, the software applies
the default search path scheme to the design.
For example, Expedition PCB stores the default scheme within the project file for the design.
Within Expedition PCB's Project Integration option, you can review the search path scheme and
make changes if (the Librarian) provided the option to do so within the Central Library (using
the check box in the Scheme List box).
Unreserve Partitions
Use the Unreserve Partitions dialog, available from Setup > Library Manager > Setup >
Unreserve Partitions to view partitions that are being edited within a central library (.lmc) file
and remove READ/WRITE access to those partitions. Upon completion, the software removes
the partition from the list allowing another user to perform editing operations within that
partition.

If a network disruption, power outage, workstation crash, or similar unexpected anomaly occurs
while nodes access partitions in the central library, the software may not automatically
unreserve partitions being edited when the anomaly occurred. Use the Unreserve Partitions
dialog to view these partitions, ensure that no editing operations are in progress, and unreserve
them. If you attempt to unreserve a partition that is in use, the following message displays:
“Warning: If a partition is reserved because it is currently being edited,

this action will prevent those edits from being saved to the database. Are
you sure you want to unreserve the selected partitions?”
Partitions in a central library file are considered "reserved" when a node accesses and performs
operations within that partition. Other nodes can connect to that partition with READ access
only. When the editing node disconnects from a partition, that partition becomes "unreserved"
and another node can access and perform editing operations within that partition.
Setup Parameters
The Setup Parameters dialog is available from the Setup pulldown on the Library Manager
interface. It displays the user layers, default fanout via and via clearances that are used when
cells are built.
Units Display
The Units Display dialog allows you to set the precision for electrical and physical properties as
well as time and percentages you use for all entities in your Central Library files. You can
specify the active electrical units display format and other general options using this dialog. The
precision and the format of the various types of numbers likely to be seen across our product
line are considered global notation settings.
The working units are restricted to English (in and th) or Metric (mm and um). The default is
English. The precision in all of the categories describes the number of decimal places. An
example is displayed to the right of the precision.


Chapter 3
Expedition PCB Design Process
Expedition PCB gives you exceptional placement manipulation, dynamic Online DRC,
extensive Batch DRC, Rules by Area, dynamic area fills, and powerful routing by high-speed
rules. The Automatic Routing commands provide you with access to the most powerful shape-
based automatic routing tools available. These commands allow you to automatically
manipulate individual traces or groups of traces, or to automatically route the entire design
based on a user-defined routing scheme. The ability to define routing schemes allows you to
make adjustments in how the automatic router tackles your toughest designs.
The Placement manipulation routines allow parts to be moved, rotated and pushed using
automatic part shove and shove-back along with automatic re-route. Parts can be moved
individually or as groups. If you would like to retain the routing within a group of parts, the
move circuit option will automatically make adjustments to the design with minimal effect to
the connectivity within the circuit.
If you have groups of like circuitry or reusable blocks in your design, copy circuit will
automatically scan your design for equivalent parts and connectivity and allow you to
automatically build new circuits based on an existing master circuit.
Expedition PCB has a built-in dynamic Online DRC engine. This keeps track of any existing
hazards created within your design. Hazards such as Open nets, pad entry, layer restriction,
trace length and delay are shown based on the current state of the design. As you make changes
to your design, these and other online hazards are added and removed from the Review Hazards
dialog.
By default, Expedition PCB does not allow clearance violations to be created. However if
clearances or rules are changed while the design is in progress, these changes could create
hazards for the existing objects placed in your design. Batch DRC allows for the checking of
Proximity, Connectivity and manufacturing rule hazards.
Batch DRC can have sets of verification settings defined as a scheme that can be used to check
for hazards during the design process. Schemes allow you to define which verification options
you would like to run grouped as a scheme name. So you can define specific verification
routines to be run after placement, routing, planes and a final routine that can be selected by a
single name. Any hazards, found by Batch DRC, are listed in the Review hazards dialog in the
Batch pulldown.
Expedition PCB has the ability to define areas within your design that have different clearance
rules. These rule areas give you the ability to define areas within your design where the
clearance must be smaller in order to complete routing to BGAs, large QFPs, or other more
difficult parts. Dynamic Area fills are areas of plane metal that dynamically change when

Verifying Parameters
objects are placed within or when traces are routed through the area. This gives visualization of
the impact of changes made within plane areas.
Expedition PCB has extensive high-speed rules that can be defined to aid in routing correctly by
construction. These rules, like pin order, maximum length, minimum length, delay formulas,
differential pairs, routing trace groups to tolerance, parallelism, and cross-talk, aid in the
construction of your design.
The ability to split a PCB design into multiple partitions and have different designers working
on those simultaneously is available in Expedition PCB. After the work on the partitions is
complete, the partitions may be joined back into the original design.
Verifying Parameters
Prior to editing your design file, you must verify the parameters that determine how you want
Expedition PCB to work. Some general utilities are available with Expedition PCB to make
working in graphics easier:
If you want to:

Learn about Setup Parameters Information on page 76
Learn about Editor Control Information on page 89
Learn about Net Class and Clearances Information on page 101
Learn about Net Properties Information on page 104
Learn about Plane Shapes Information on page 109
Learn about Actual Plane Shapes Information on page 110
Learn about Plane Obstructs Information on page 111
Learn about Rule Areas Information on page 303
Learn about Fixing Parts Information on page 125
Setup Parameters
Setup Parameters defines the layers, planes, vias, clearances, layer stackup and graphic levels
that are used in the design. It also specifies whether or not options such as buried parts are
utilized in the design process. Due to the significance of the information in Setup Parameters, it
should be defined at the beginning of the design process.
General Tab in Setup Parameters

Defines the number of physical layers, user-defined layers, padstack technology, display units
and test point settings.

Setup Parameters
To set general parameters

1. Define the number of physical layers; the maximum number of physical route layers is
120. The number for the design displays in this entry, and is editable. If you change the
number, you must select the Remap Layers button.
2. Set the user-defined layers; all the user-defined layers found in the design and Cell
Editor display in this field. The maximum number of user-layers is 250. You can add,
delete, undo deletions and rename user-defined layers.
Caution
Renaming user-defined layers in Setup Parameters does not automatically rename the
layers used in cells or designs. Some layer names are reserved and cannot be used.
3. Define the padstack technology name to be used in the design process. Use the drop-
down to view all the defined padstack technology names. New padstack technology files
are created in the File > New Technology dialog within the Padstack Editor.
4. Select the Design Units. The options are: Inches, Millimeters, Microns or Thousands.
5. Select the Velocity of Propagation units. The options are: Inches/ns,Meters/s or %C.
6. Select a Test Point Cell Name from the drop-down list. This list contains all the cell
names for the test points prefixed by Local: for cell names in the local central library and
Central: for cell names in the Central Libraries database. (None) is the default.
7. Select the placement grid for test points. This is a user-defined number displayed in (th)
units.
8. Select the test side for test points. Options are: Top, Bottom or Both.
9. Define the prefix to be used by the reference designator.
10. Check to use closed polygon assembly outlines as test point obstructs.
Remap Layers
This dialog allows you to remap current net class layer assignments to new layers. The
maximum number of physical route layers is 120. This command should be used when the net
class information is setup with a number of layers that differ from the current number of layers.
This situation arises when:
1. Net classes and the number of layers used during the setup differ from the actual number
of layers used to design the board using PCB.
2. Net classes and the number of layers used during the initial setup must be changed.

Setup Parameters
3. Within PCB the number of layers in Setup Parameters changes. This happens when a
seed job with net class data is assigned a number of layers and more or less layers are
required for the actual design.
Note
You cannot remap the top and bottom layers.
The Current Layer column displays the number of layers assigned in Setup Parameters and for
each current layer (apart from the top and bottom) you can use the drop-down list to select the
layer to which the Net Class Layer Assignments are to be mapped.
Caution
A layer can appear in this column only once, therefore, when a new layer is selected,
make sure that any existing entries for that layer are also remapped.
Via Definitions Tab in Setup Parameters

The vias that are defined in Setup Parameters are the defaults for use by Interactive Routing or
Autorouting. When the router needs a via, it uses a via defined in Setup Parameters based on the
span that is needed. However, if a net class is defined for the net being processed, the vias are
based off the net class definition which, by default, is the same as is defined in Setup
Parameters.
If the design uses through vias, then only one via that spans all layers needs to be defined. If the
design uses multiple via spans, Blind or Buried, each span must also be defined with a default
via padstack.
Although through vias and blind/buried vias have a different span when placed in a design, a
through via and blind/buried via can use the same via padstack because the span is a property of
each via. For each via span defined, a default via padstack must also be assigned. A net class
assigned to specific nets, in the Via Assignment section of the Net Classes and Clearances, can
override this via padstack. The vias that are defined in Setup Parameters are the defaults for use
by Interactive Routing or Autorouting. When the router needs a via, it uses a via defined in
Setup Parameters based on the span that is needed.
If a net class is defined for the net being processed, the vias are based off the net class definition
that, by default, is the same as is defined in Setup Parameters. Certain padstack / via range
combinations can be created that cannot be manufactured. The Allowed Via Padstacks dialog
accessed by clicking in the Padstacks field (in the diagram above marked by a red rectangle)
contains a list of padstacks with a check box beside each one that lets you define the padstacks
that will be allowed for the selected layer range.

Setup Parameters
Figure 3-1. Allowed Via Padstacks
Only checked padstacks are allowed. Check the appropriate padstacks and click OK to display
only these selected padstacks in the dropdown list in the Padstack dropdown. The Allowed Via
Padstacks dialog affects the contents of the net class via list, found in the Via Assignments
section of the Net Classes and Clearances dialog, and the contents of the via padstacks, found in
the right-mouse click popup menu during Plow.
To create and define via definitions

1. Select the New icon if you want to add a new via span definition. A new column appears
with the "Undefined Range" heading. If one of the layer ranges is highlighted, the new
column appears to the right; if no layer ranges are selected, the new column appears at
the end of the layer ranges.
2. Define the layer range that represents the span of a via. Via spans are created by clicking
on the green column between the layers where you want to place a via span. If you press
and hold the right mouse button and move over each row in the stack, its selection state
toggles. A via span may only be defined once for a job. If a duplicate span is defined, the
Layer Range field displays "Duplicate Range".
For example, if the span 1-2 already has a via assigned to it, you cannot assign a
different via to the same layer span in another column. If multiple via sizes are to be
defined for a single span, these must be defined by net class. The Padstack entry
displays (Not Defined), the Capacitance and Delay Entry fields display 0, the Grid entry
displays (Default) and the via span accepts the defined layer type for those layers.
3. Select the Padstack by clicking (Not Defined). A drop-down displays that contains all
the via padstacks that are defined in either of the libraries. The via name appears as
L:<via name> or C:<via name> to distinguish between Central and Local libraries. The
Allowed option displays the Allowed Padstack dialog where you can define the
padstacks that are allowed for the selected layer range.
4. Enter a capacitance value for the selected via; by default, the capacitance values are set
to 0pF. If Signal Vision cannot determine the correct via span for the transmission line

Setup Parameters
symbols that transition between layers, the via capacitance for that layer transition,
defaults to the through-hole span capacitance value.
5. Enter an Inductance value for the selected via; by default, the inductance values are set
to 0pF.
6. Enter a delay; by default, the capacitance values are set to 0ns. PCB routes to a value
less then the maximum specified. If a delay is not entered into this files, the delay
entered in Net Properties is used.
7. Define the grid setting by either entering a new value in this field or selecting form the
drop-down list. The Grid allows you to change the via grid for each span overriding the
Editor Control default via grid setting. If [Default] is selected, the via grid value in the
Editor Control Grids tab is used. If [None] is selected for a via span, no grid is used
when this span is placed in the design.
8. Check the Skip via box for each via layer span if you want to only allow trace
connections to the top and bottom of the via span. If checked, all pads on internal layers
will be removed and will not exist in any of the output files.
9. You can define the layer type between routing layers as either Buildup (Blue) or
Laminate (Red). This layer type is used to aid in defining the via spans correctly for your
design. In Buildup areas only standard technology vias can be used. Photo -vias or
internal vias (cutouts in dielectric switches) are allowed.
10. Select the Sort Via Spans icon, if you have added new via spans that are out of sequence.
11. Select the Use mount and opposite side pads for start and end layers of blind and buried
vias checkbox.
Skip Vias
A skip via is a via (hole) with pads only on the top/start and bottom/stop layers of its rule, span
and/or layer. This method minimizes the amount of metal to produce a board and increases the
routable area through adherence to hole clearances rather than pad clearances on the
unconnected inner layers. All layers between these top and bottom layers have the pads
removed. For example; for a rule span of 1-3 layers, 1 and 3 have pads, layer 2 does not.
Note
You can only select the Skip Via check box if more than two layers are in the span. You
cannot mix skip vias and non-skip vias on a specific via layer range, for example, if you
have a via range of 1-4, the vias are either all normal vias or all skip vias based on the
settings on the current settings in Setup Parameters.
If the rules have been violated, design rule checking is available and highlights any errors.

Setup Parameters
Routing
If you had previously routed a net with a via that is marked as a skip via and then disable the
skip via (uncheck the option in Setup Parameters) all existing vias of that range lose the skip via
setting and are no longer classed as skip vias.
It is quite possible to change your skip via settings after some or all of the design has been
routed. After the changes are done, the design is reloaded. The result of this reload could be
numerous skip via violations as the reload does not automatically remove any illegal
connections. In this case, a warning displays stating:
Skip Via design rule changes have resulted in numerous skip via
violations. Please run Batch DRC to highlight these violations.
Plow
Plow will only allow traces to exit or enter a skip via on the top or bottom layer of the via's span.
Push
When traces are pushed, illegal skip via connections will be prevented. The illegal connections
are prevented during Push Trace and Push Part commands.
Re-Route
When traces are re-routed with the Re-Route command or during Push & Shove the skip via
rules are respected.
• When the via/range being shoved is a skip via, push and shove re-uses the skip via's hole
and does not re-connect to an inner layer of the skip via's span.
• Via optimization/minimization/merge routines do not merge a skip via with a samenet
via having a different range.
Drag - Move Function

When a skip via is moved by dragging the via, the hole range is retained. If the range cannot be
maintained, Move fails and a warning message is displayed.
Batch DRC
If skip vias are present in the design, Batch DRC always checks for any illegal skip via
connections:
• Trace connected on an internal range layer

• Connection to a plane on an internal range layer

Setup Parameters
Hazards
Illegal Skip Via Connections are reported as Proximity Hazards.
Display Control
The Internal Skip Via Pads option on the Pads Section in the Layer Tab of the Display Control
Dialog allows to easily distinguish skip via pads from other via pads. Visibility is always on but
you can change the color and fill pattern of the skip vias.
Plane Engine
The plane engine follows the same connection rules as the router:
1. No connections are allowed to a skip via unless the connection occurs on the start or end
layer of the via range.
2. If a skip via on a plane net passes through that plane net, the plane net uses the
appropriate clearances for that plane net to clear out the plane to ensure that no
connection exists on the plane on that layer. The clearance used in this case is the pad to
plane clearance that is normally used on this layer.
Until the pads are removed from the layer with the Padstack Processor, the clearance on
the layer is based on the pad size.
Once the pads are removed from the layer, the clearance is calculated based on the hole
size.
3. Conversely, if the skip via range ends or begins on the plane net matching the net of the
skip via, the proper thermal connection must be made.
With the Unified Plane Generation enabled, the positive plane clearances automatically are
regenerated when the pads are removed with the Padstack Processor. When negative planes are
used, the planes are processed after removing the skip via pads to allow the correct clearance
around the skip holes in the Gerber files.
Padstack Processor
In order to prepare a design for artwork generation, the Padstack Processor allows for easy
removal of internal skip via pads. On the Pads tab, the Skip Vias Only checkbox is only enabled
when the Action is set to Delete and when checked only the skip vias are processed from the
chosen selection parameter:
• If the Apply to: option is set to All Padstacks, all the Skip Vias in the design are
processed.
• Ιf the Apply to: option is set to Selected Padstacks, only the skip vias in the selected set
of padstacks are processed.
• Ιf the Skip Vias Only option is unchecked, then no skip vias will be processed.

Setup Parameters
By removing the pads in the Padstack Processor, no changes are necessary when generating the
various PCB fabrication outputs.
Via Clearances Tab

The Via Clearances tab allows you to define via clearances used in the design process. The
default this clearance is set to [Net Class] which means; use the electrical rules defined in the
Net Classes and Clearances dialog for the Trace to Via clearance. If one of these options is not
checked, then the Net Class rules are applied for all via clearances. If stacked vias are desired,
you must use the Same Net Clearances option.
When accessed from Library Manager, this tab allows you to define via clearances that can be
used when adding vias within the Cell Editor.
The Trace to Via clearance should be defined as the smallest clearance between all traces and
this specific via span. This clearance can be over-ridden by larger clearances defined as
electrical rules in the Net Classes and Clearances dialog. If the trace or via have no other
electrical rules that are larger than this clearance, this Setup Parameters clearance is used. Via to
via clearances can also be defined in this matrix.
By default, this clearance is set to [Net Class] which means use the electrical rules defined in the
Net Classes and Clearances dialog for the via to via clearance. The via to via clearance defines
the smallest clearance between spans that is allowed and can be over-ridden by larger electrical
rules defined in the Net Classes and Clearances dialog. If the via's nets have no other electrical
rules, this Setup Parameters clearance is used.
Via Clearance Definitions

Selecting this check box implies that the general trace-via and via-via rules may be set in such a
way that they override the Net Classes and Clearances trace-via and via-via clearances. When
this checkbox is selected, the via names are put in the same row to make them more visible. The
default for each field is {Net Class}.
Figure 3-2. Net Class General Clearances

Setup Parameters
The Plane to Via clearance should be defined as the smallest clearance between all traces and
this specific via span. This clearance can be overridden by larger clearances defined in the
Clearances tab of the Net Class dialog. If the trace or via have no other electrical rules larger
than this clearance, then the Setup Parameters clearance is used.
The Via to Via clearance defines the smallest clearance between spans that is allowed and can
be overridden by larger clearances defined in the Net Class dialog. If the vias’ nets have no
other electrical rules, then the Setup Parameters clearance is used. Set the Net Class via to via
clearance value to be equal to the minimum clearance you want for the microvias. Then, for
these general clearances in the via span dialog, specify {Net Class} for these microvias, and
enter a value larger than the Net Class clearance for all the other via-via clearances.
Used if > Net Class - In the case of different net clearances for vias, both trace to trace and via to
via, the value entered into the matrix is only applied if it is greater than the Net Classes and
Clearances rule.
We recommend that you set the Net Class via to via clearance value to be equal to the minimum
clearance you want for the microvias. Then, for these general clearances in the via span dialog,
specify {Net Class} for these microvias, and enter a value larger than the Net Class clearance
for all the other via-via clearances.
(Not Applicable) - If the vias do not share layers, this field is not selectable and the clearance
rule does not apply.
Use the Same Net Via Span to Via Span Clearances

This matrix refers to via spans that are connected together by a single trace path on the same net.
The default for each field is {Net Class}. The values entered in the matrix are used only if they
are less than (<) the values in the Net Classes and Clearances dialog.
Figure 3-3. Same Net Clearances in Setup Parameters
Online DRC supports and enforces the Same Net Via Clearance and Coincident Vias, if the
variable is set. If Coincident Vias are not indicated, then online DRC do not allow Coincident
Vias.
• P (Pitch (padstack origin to padstack origin)) = The router and DRC uses the value from
the via to via clearance found in default Net Class Clearances.

Setup Parameters
• PE (Pad Edge to Pad Edge (Default)) = Pad edge to pad edge.

• HE (Hole Edge to Hole Edge (Default)) = This is used for clearances of vias with the
same layer range (Row; Via-Via 1-2 and Column; Layer 1-2). All clearance options are
legal except Coincident or any combination that includes Coincident in this match of
layer ranges.
• C (Coincident (Exact center over center stack)) = If this is selected, the option to enter a
value is disallowed through a grayed-out Distance field. Coincident or any combination
that includes Coincident is not allowed if the via layer ranges share two or more of the
same layers. For example if there is a layer range 1 - 2 and another 1 - 3, then Types; C,
PC, PEC nor HEC are not valid and do not display in the pulldown.
• PC (Padstack Origin and Coincident), PEC (Pad Edge + Coincident), HEC (Hole edge +
Coincident) - are combinations of via to via clearances and coincident.
If you check General or Same Net, the dialog expands, allowing you to specify the clearances.
By default this clearance is set to [Net Class] which means use the electrical rules defined in the
Net Class dialog for the Trace to Via and Via to Via clearances. If one of these options is not
checked, then the Net Class rules are applied for all via clearances. You must use the Same Net
Clearances option if stacked vias are desired.
Multiple Via Objects

The creation of multiple via objects are dependent on the Same Net, Via to Via clearance for
their layer range. This value is used to locate single vias in relationship to each other within the
multiple via object pattern.
For staggering multiple via objects through different layer ranges, the Same Net values are used
to stagger multiple via objects to other multiple via objects or single vias on different layer
ranges. Via patterns supporting buildup layers and microvias use the efficient pattern to span
several layer sets.
To define vias so they can be stacked

1. Define your vias in Setup Parameters.
2. Use the same net selection in the bottom of the same page.
3. Select via center to via center and set all the layers that have a layer in the table in
common to clearance of 0. When you route you will now get stacked vias.
(Net Class) - Choosing this option means that there are no Same Net via-via clearance rules
between those via spans and the General clearances are applied.
(Not Applicable) - If the vias do not share layers, this field is not selectable and the clearance
rule does not apply. (Not Applicable) is also used when the matrix references the same via span.

Setup Parameters
Layer Stackup
This dialog defines the conductive and dielectric materials that make up the design's layer
structure. The Layer Stackup is only used by signal integrity tools. The Conductive Layer
Number displays the number of signal/plane layer numbers corresponding to the dielectric layer
stack in the design.
Note
This tab is not available if Setup Parameters is accessed through Library Manager.
Layer Type The type of each material in the stack. The Dielectric Material is used for
signal or plane layers.
The Metal material is used for signal flooded layers.
Thickness The thickness of each material layer in the stack in the units of the design.
Resistivity The resistivity (in ohm-meters) of each material layer in the stack. The trace
resistance is calculated using the following formula and it retrieves the
resistivity and the thickness of the trace from the field solver:
Resistance=resistivity x Length of trace / cross section Area of trace.
Dielectric Constant The dielectric constant (er) of each dielectric material layer in the stack. This
value can only be defined for a dielectric and solder mask material type. If
you do not want a dielectric layer to have any effect, set its dielectric
constant to 1 (dielectric between conductive layers must have a dielectric
constant greater than 1).
Description A user-defined description for each material layer
Keep Layer When checked, the signal and plane layer definitions in the Planes tab are
Stackup in Sync maintained. If any of the definitions have changed and this option is
with Layer checked, a warning message appears informing you that this action will
Definitions in change one or more of the material types defined in the layer stackup and
Planes tab asks if you want to continue.
Restriction: The previous option is not available if the Layer Stackup dialog
is accessed from within Signal Vision.
Options Displays a dialog allowing you to calculate or define a trace’s characteristic
impedance (Z0) and velocity of propagation (Vp)
OK Updates the other databases so that signal integrity checks can be performed
on the design using the new data and then exits the dialog.
Apply Updates the other databases so that signal integrity checks can be performed
on the design using the new data and leaves the dialog open.
Cancel Rejects the changes and exits the dialog. Any database changes enacted by
the Apply button are undone. If OK or Apply were selected in the Layer
Stackup Options dialog, the changes are also undone.

Setup Parameters
Buried Resistors and Rise Time

This dialog allows you to define buried resistors, and also to define new technology rise times.
Buried Resistors
When the Allow buried resistors checkbox is selected, SMD parts built with a resistor shape can
be placed on, or pushed to, internal board layers with the Place Part and Push commands. The
pads of the SMD part must overlap the resistor shape area. If the Allow Buried Resistors
checkbox is not selected, SMD parts can only be placed on the top or bottom of the board or be
pushed between the top and bottom.
The graphic displays the number of layers for the design. The word Plane appears next to any
layers that allow plane shapes and do not allow routing.
The Layer Stack Center determines the layer at which parts are mirrored and placed in a
different display class with the Push or Place Part commands.
Example
If the center of the layer stack is between layers 4 and 5 on an 8 layer design, parts placed on
layer 1 through 4 are considered topside parts and on layers 5 through 8 are considered bottom
side parts.
Rise time by Technology

A new technology is added by defining the "tech" field in the Part Editor. If the technology is
not in the default list, that entry is added to the list of available technologies and is assigned the
Default Tech values. These values can be edited by clicking on the appropriate field in the table.
The system is delivered with the set of technologies shown in the System Set of Technologies
table.
Use the Rise Time text field to edit the rise time values for the corresponding device
technology. If there are multiple drivers in a net, the smallest rise time is used for crosstalk
estimations.
Use the Voltage Swing text field to edit the voltage swing for the corresponding device
technology. If there are multiple drivers in a net, the largest voltage swing is used for crosstalk
estimations.
Default Values
The entered values for Rise Time and Voltage Swing are applied to all new technologies in your
design (through the Part Editor "tech" entry). The initial values are set to 0.6 nanosecond for
Rise Time and 5 volts for Voltage Swing. These values are used for crosstalk estimations on all
nets containing at lease one source pin. For example:

Setup Parameters
• Nets with I/O's and loads

• Nets with only I/O's
• Analog nets that have no drivers or loads
• Nets that have incomplete or no part information on their pins.
Reserved Layer Names

When opening a cell for edit, you may receive the following error:
Cannot open Cell lib. Unable to create scratch jobprefs.
One cause for this error is that the Central Library contains a reserved layer name. The layer
names must be renamed and any cells containing these layer names can then be changed.
Reserved User Layer Names

• (All)
• Assembly, Top and Bottom
• Drill Drawing (Through)
• Redline
• Silkscreen Top, Bottom, Mount and Opposite
• Soldermask Top, Bottom, Mount and Opposite
• Solderpaste Top and Bottom
• Documentation
The workarounds use the Documentation reserved layer. The same procedures may be followed
for all the other Reserved layers.
Workaround 1
1. Run the FixCellLayers utility to rename the conflicting user-defined layer and update
the cells in the Central Library
<$SDD_HOME>\wg\win32\bin>FixCellLayers.exe -CentralLibrary=<specify_full
_path_to_CL>.lmc
This renames the user layer and moves all draw data that was on the Documentation
layer to Documentation Temp for all cells in the Central Library.
If the Documentation Temp name is not acceptable for the new user layer name, then
use the following workaround.

Setup Parameters
Workaround 2
1. Open the Central Library, invoke Setup > Setup Parameters and rename the
Documentation user layer.
2. Use Library Services > Export ASCII to export all cells that contain draw data on the
Documentation layer to HKP.
3. Edit the HKP file(s) to replace all instances of USER_LYR Documentation to the new
user layer name. Text and Graphics definition in the HKP file is slightly different (text
has 4 dots preceding USER_LYR and graphics has 3 dots).
4. Remove or update the ..TIMESTAMP entry in the HKP file to ensure that the cell(s)
overwrite correctly when re-imported.
5. Use Library Services > Import ASCII to replace the affected cell(s) in the Central
Library.
6. Verify the LibraryServices.txt log file to ensure the operation completed successfully.
The Verification Status of cells imported from ASCII defaults back to Unverified;
therefore, cells that were previously Verified should be re-Verified as required.
Editor Control
The Setup - Editor Control dialog defines the parameters for interactive routing as well as some
of the parameters used by the Auto Router. This dialog allows you to customize which layers
routing can be on, layer bias, pad entry, grids, tuning, etc.
It also allows you to turn rules on or off when trying to route a complex design. Each of the tabs
of this dialog are discussed below.
Note
Within FabLink XE, Xtreme PCB and ICX Pro HSR, some of the tabs and options in
Editor Control may not be available.
General Setup Rules

The General tab of the Editor Control dialog allows you to define the database and checkpoint
automatic save intervals. You can also define the algorithmic expense or "cost", associated with
placing a via, or whether to go against the layer bias, when using the interactive routing tools.
In this tab, you can define which routing layers are enabled for interactive or automatic routing,
what the preferred layer bias is for each layer, and which layers are paired together when vias
are placed. Be careful about changing this control from its default setting, High. If you select
Medium or Low too early in the routing process, routing channels may quickly become
blocked, making routing very difficult.

Setup Parameters
The radius of any curved traces can be defined. Any radius can be defined and the value is based
on the units defined for the design. New entries are added to the list and are selectable from
either the drop-down or the pop-up menu. If you want to override the selected default curve
radius (Variable) you can choose a new radius from the list.
The value entered for the minimum arc radius of a curved trace affects the Modify Corners
command. If a value for the minimum radius is set in the General tab of Editor Control, the
value entered in Modify corners must be larger. If not, an error dialog appears stating the
allowed smallest minimum radius.
Figure 3-4. Editor Control General Tab
Differential pairs are composed of two nets, carrying a signal and its inverse, generally derived
from the outputs of a single gate. These nets are active at the same time, and have the same
number of inputs and terminators. Differential pairs are defined in this tab so that the signal and
its inverse arrive at the differential inputs with identical characteristics. To achieve this, these
nets are routed with adjacent traces and paired vias. If no adjacent layer pairs are defined, then
differential pairs are routed on the same layer.
Options are available, during interactive routing, to allow trace and via shoving of existing
traces and vias, to add vias using the mouse and to allow pad and via jumping over traces and
vias during interactive routing.

Setup Parameters
Curve trace radius provides the ability to create concentric arc's using curved traces. Values
entered into this field can be selected when using the command from the popup that displays
with a mouse right-click when in the route environment while in Forced or Angle Plow. If
"Variable" is selected, the methodology reverts back to a defined curve using the cursor. Values
are only stored for the current design session. When the design is exited the input values are
discarded.
The Interactive DRC option allows you to turn DRC off while in the layout environment. This
option is not available in Team PCB or Cell Editor and Backward and Forward Annotation
remain enabled. If you use DRC OFF to circumvent system limitations, any resulting hazards
will persist through to generation of manufacturing data. Certain commands are affected by
turning Interactive DRC off:
Teardrop Dialog - The following "Process" options of the "Pad Teardrops" tab of the Teardrop
generator dialog are disabled:
• All Pads
• Pads Without Teardrops
The following "Process" options of the "Trace Teardrops" tab of the Teardrop generator dialog
are disabled:
• All Traces
• Traces Without Teardrops
Breakout Traces Dialog - The following options in the "Items to process" options list of the
Breakout Traces dialog are disabled:
• All Traces
• Pads Without Breakout Traces
Auto Route - All Auto Route functions and entry points to the Auto Router are disabled.
Closing and Saving Commands - Before Closing or Saving a design (and after opening), you
are warned and advised to run Batch DRC if the session or previous sessions had turned off
Interactive DRC and not yet run Batch DRC.
The current state of Interactive DRC is saved and applied to next invocation.
Modify Corners - The following option in the "Action" options list is disabled:
• All Corners
Team PCB Reserved Areas - When DRC OFF is active on a TeamPCB split design, it only
applies to actions taken within the split design's reserved area. The remaining areas of the
design (outside of the reserved area) always maintain DRC ON.

Setup Parameters
Xtreme PCB - DRC Off is disabled within Xtreme PCB. If a design is opened in Xtreme PCB
that had not had Batch DRC run, a dialog prompting you to run Batch DRC is presented.
Reusable Blocks - If DRC OFF is enabled in a design containing placed Reusable Blocks, the
current limitations (DRCs) imposed on all un-flattened reuse blocks are maintained (Reuse
Block property is still assigned) as defined below.
• Modification to the block's elements, move, edit, etc. is not permitted.

• Reference designators are placed with the reusable block and are edited by Forward
Annotate.
• Part entries are locked.
• Plane shape information is locked. Plane data is created on demand.
• Gate and pin swap is not permitted.
• Existing routing is not editable.
• The rules as set by each un-flattened reusable block's DRC Region are maintained.
• When a reusable block is flattened, Interactive DRC is allowed.
Automatic and Interactive Tuning - On the Tuning Tab of Editor Control, automatic and
interactive Tuning are turned off and all command access, including key-ins is disabled.
Gloss - All Gloss functions and entry points are disabled.
Auto Swap/Rotate By Cell Name and Part Number - All Auto Swap/Rotate By Cell Name
and Part Number functions and entry points are disabled.
Copper Balancing - All Copper Balancing functions and entry points are disabled.
Parts Tab
The Parts tab allows you to define whether the Online Design Rules Checker (DRC) provides a
warning when part violations are created, or prevents you from creating these violations.

Setup Parameters
Figure 3-5. Editor Control Parts Tab
The preferred rotation and placement of reference designators, how netlines are to be displayed
while parts are moving, the snap anchor and the alignment method to be used for parts are also
defined on this tab.
The Display local netlines only option limits the display to those netlines directly attached to the
part. This option is to be used when the netlines have been turned off within Display Control.
The default setting for this option, Dynamic netline ordering, orders the netlines while the part
is moving. If the option to Apply filter to Netlines is selected on the Editor Control Filter tab,
these nets do not have their netlines displayed when a part is being moved.
You can set the maximum number of pins to display netlines when moving parts or groups of
parts attached to the cursor by adding a number into the text entry field. If you entered 500, any
part that has greater than 500 pins would not generate dynamic netlines during part movement.
The default is empty; this means that all netlines are shown during part movement

Setup Parameters
Cells Tab
The Cells tab contains general information about selecting parts and defining valid placement
layers and rotation angles. These defined placement layers and rotation angles are used by
Online DRC. The Online DRC options; Off, Warning or Preventative are controlled on the Parts
tab. If the Online DRC option is set to warning, placement layers and rotation angles hazards
are listed as Review Hazards Online Component hazards.
Figure 3-6. Editor Control Cells Tab
Clusters and Rooms Tab

Cluster and room configurations can be defined for your design. These are optional part
attributes used to aid in placing parts that should be clustered together (bypass capacitors or
parts that should be grouped together in a specific location on the board). A cluster has no
physical representation on the board while a room is defined using a shape. A room shape must
be defined as a polygon, circle or rectangle.
Place Part allows you to list parts based on Cluster and Room names. Once Rooms are defined,
parts that are not placed in the defined room will become an Online DRC hazard that can be
reviewed using Review Hazards component hazards.

Setup Parameters
Figure 3-7. Editor Control Clusters and Rooms Tab
Clusters and Rooms can also be defined in the Design Capture schematic using the Cluster and
Room symbol properties. Forward Annotation reads these properties and populates the Editor
Control tab with changes made in the schematic.
Any changes made to the Cluster and Room definitions must be Back Annotated so the data is
not lost during the next Forward Annotation. Back Annotation will be run when save is done.
Routes Tab
The Routes tab contains general information about routing preferences.
Options are available to allow 45 degree angles to be used in routing and to prevent loops. Via
options allow you to put restrictions on whether vias can be placed under components or how
many vias should be used when fanning out pins. Optional net rules restrictions that should be
respected during interactive routing commands and differential pair routing parameters.

Setup Parameters
Figure 3-8. Editor Control Routes Tab
The redlined options are not displayed if CES has been used on the design as these values are
entered on a net basis within the CES interface.
Convergence and separation values can be entered into this dialog if you have not used CES.
The convergence distance is calculated from the pad edge and not the pad origin. The tolerance
value entered into this field is used to ensure that the legs of the convergence point are matched
to the user-defined tolerance. A convergence point is where the traces of a differential pair come
together from the component pins.
The separation distance is measured from the pad origin. If you set the max separation distance
to a very small value, you will see numerous hazards at the pad entry points. A maximum
separation distance keyin (xmsd value) is available. However, if this keyin is used, the entered
value is set for every net on the board.
Differential Pair Convergence, Convergence Tolerance and Separation hazards are listed under
the Online pulldown in Review Hazards.
Gloss Tab
The Gloss tab contains options that allow you to improve glossing performance and applies
only to the interactive routing tools and for the Auto Route Smooth pass for Efforts 2 and 3.

Setup Parameters
You can select to move a trace over the obstacle to remove excessive vertices, remove excessive
meanders, gloss around deleted traces or vias and move vias to reduce trace segments. Dyna-
move continues to jump over pads/vias regardless of the Advanced Glossing Options being
enabled or disabled. Advanced Glossing only affects Gloss and the Push/Shove of traces and if
you dynamove a trace, the segments being dragged will hop across pads/vias.
Figure 3-9. Editor Control Gloss Tab
Pad Entry Tab

The Pad Entry tab allows you to define the preferred route entry for a particular shaped pad(s).
You can also define if vias are allowed under the pad, where they are allowed, and which via
spans are allowed. These design rules can be defined based on the selection of rectangular,
oblong/octagon, round/octagonal, square and custom pad geometries.
Figure 3-10. Editor Control Pad Entry Tab

Setup Parameters
Round / octagonal and custom pads only allow via under pad rules to be defined within Editor
Control. Trace entry for custom pads can be controlled by defining trace obstructs when the
custom pad is being created within the Padstack Editor. Round pads have system-defined pad
entry rules (a trace may enter round pads at 45 degrees increments) and this can not be adjusted.
Expedition PCB uses the pad entry as preferred rules. These rules do not stop the router from
making a connection within a pad. Pad entry hazards can be reviewed and fixed using Review
Hazards. If a Route grid is set in the Grids tab, you can select the Gridless pad entry for all pads
option to allow traces to follow the set grid to the pad and then "jump" off the grid to connect to
the pad regardless of the grid setting.
Grids Tab
The Grids tab contains parameters that define the placement, route, via and drawing grid for the
design. The dropdown list accompanying all of the grid fields can be used to select either a
previously entered setting, or none. New grid values can be entered by selecting the field and
keying in the desired value. Once a grid value is set in any of the fields, all work from then on is
done using that value.
Figure 3-11. Editor Control GridsTab
You can define two placement grids. These allow you to easily align your through parts on a
coarse grid and make the grid for SMD parts less restrictive; however, a route grid is not
required in Expedition PCB and typically, the router works best when not restricted to a route or
via grid.

Setup Parameters
If you want to use the Gridless pad entry for all pads option on the Pad Entry tab to route traces
gridless into pads as well as around pads that are off the route grid, you must select a Route
Grid. Gridless pad entry for all pads allows better pad entry as well as being able to route
between pads when the clearances are precise.
Filter Tab
The Filter tab allows you to include or exclude nets from access by the Auto Route, Item Select,
Area Select, Select All, Net Inquire, Netline Order, Hazard Review and all interactive routing
commands. This allows you to restrict the selection of objects based on the net name and can be
very useful in dense designs where you are working on critical nets.
The Display class type pulldown option is set to Net Class and is inactive and read-only if CES
has not been used in the design. The Constraint Class option only appears if you have used CES
in the design.
Figure 3-12. Editor Control Filter Tab
The Find Net option can be used to search for the net name in the Include or Exclude list.
Selecting the Apply filter to netlines option allows Excluded netlines to become invisible.
Tuning Tab
The Tuning tab allows you to set the rules defining how the tuning algorithms work. (A tuned
net is considered to be any net whose length is constrained by any of the following Net

Setup Parameters
Properties: maximum length/delay, matched length/delay or if a delay formula has been

defined.).
For the minimum spacing distance or factor option, you can also add an entry as a factor of the
trace width by entering the number followed by an x. The default value is 0x. If you enter a
factor, the design units are ignored. For example: If you enter 2x and the trace width is 10, the
spacing would be 20.
Figure 3-13. Editor Control Tuning Tab
Less restrictive tuning rules allow the router to easily add trace length to routes in order to meet
the rules defined in Net Properties. However, if your manufacturing process requires specific
distances or clearances on tuning, these can be defined here.
Jumpers Tab
This tab allows you to set the jumper grid, determine jumper placement angle and configure the
space bar to add jumpers instead of a via (the default action in Plow). A jumper part is defined
in the Parts Database (with a part type of jumper) referencing a jumper cell. This tab is not
selectable if there are no jumper parts defined for the design.

Net Classes and Clearances
Figure 3-14. Editor Control Jumpers Tab

The Setup > Net Classes and Clearances dialog allows you to group and assign properties to
the nets used in your design. These groups are called Net Classes.
Note
If your design/ database has used CES for physical rules, the Net Classes and Clearances
dialog is unavailable.
The following attributes on the first tab within the Net Class dialog can be defined per net class:
• Vias to be used by span

• Allowed routing layers
• Minimum, typical and expansion trace widths per layer
• Width defined by impedance based on layer stackup
• Differential pair spacing per layer
A net class can contain an unlimited number of nets, but the number of physical rules applied to
the net classes (width, cross-class clearances, via cells and via pad stack) is constrained to 250
design rule classes. Even if you have more than 250 net classes, you can avoid hitting this
limitation by limiting the number of classes that have cross-class clearances and using the

common clearance rules, widths and via padstacks for net classes that do not have cross-class
clearances.
In the Net Class Via drop-down, there are two special vias that can be selected, (Default Via)
and (None). (Default Via) allows you to default to the via defined in Setup Parameters for the
selected Net Class name. (None) allows you to disable a via from being used for specific via
spans for the selected Net Class name. If you change a net class via to (None) in a net class in
the Master scheme, all user-defined schemes change automatically to (None) for that netclass.
If, for example, you change the Master scheme from (None) to "VIA010", the user-defined
schemes net class via changes to "Default Via".
You can define multiple Net Class schemes that allow you to define alternate clearances for
specific areas of your design. The Net Class schemes can then be applied to user-defined areas
on the board called Rule Areas.
During Auto Route sessions, the expansion width is only enabled for finishing passes, but the
maximum width is used for all of the interactive routing methods (Plow, Route...) when
enabled. Because Expansion Width allows for the routing of many sections of differing widths
causing impedance inconsistencies, Expansion Widths are not used when tuning high-speed
nets.
If you have defined a Width/Impedance table in the Layer Stack dialog (in the Setup
Parameters), that data is used instead of calculating a new typical width. The Impedance value
is only used to determine the Typical Width. It is not used by other calculations. If a plane layer
is not defined, the following error message appears: Unable to calculate impedance with current
layer stackup. Default value used. The default value is 50 ohms.
Clearances Tab
On the Clearances tab of the Net Classes dialog, you can define clearance rule sets. These rule
sets can then be applied to define the clearances between the nets defined within two Net
Classes. General Clearance Rules are not specific to objects that have net names. General Rule
Sets are editable and allow you to define the from / to clearance for a variety of PCB elements.
Contour & Mounting Hole to Mounting Hole

The clearance between holes. Mounting hole to mounting hole clearances are used during Batch
DRC verification only as a manufacturing check. The Net Class pad to pad clearance between
mounting hole pads is used during net class verification as an electrical verification.
Contour & Mounting Hole to Non-Plane Conductor

This is used as the clearance between the contour holes/mounting holes and traces/pads/resistor
shapes.

Contour & Mounting Hole to Plane Conductor

This is used as the default clearance for contours to plane conductors. This clearance can be
changed in the Planes Processor dialog for each net and layer. Mounting holes will use the
larger of this clearance and the Other Object Minimum (on the Planes Processor dialog) when
generating plane data for mounting holes. Contours will use the larger of this clearance and the
Other Object Minimum (on the Planes Processor dialog) when generating plane data for
contours.
Placement Outline to Placement Outline

This clearance is used for clearance checking between placement outlines of one cell to
placement outlines of another.
Placement Outline to Placement Obstruct

This is used for clearance checking between placement outlines and placement obstructs.
Placement Outline to Board Edge

This is used for clearance checking between placement outlines and the board outline.
Plane to Resistor
This is used for clearance checking between resistor shapes and traces/planes.
Pad to Resistor
This is used for clearance checking between resistor shapes and all pads.
Testpoint Center to Testpoint Center

This is the minimum clearance that must be maintained between the centers of all test pads
ensuring the test probes have enough room between them.
Clearance Rule Sets are the Plane to Trace, Plane to Pad, Plane to Via, Via to Via, Via to Pad,
and Pad to Pad clearances by layer. These rule sets are independent of nets or net classes.
The Pad to Pad clearance is the one used for checking between part pads, fiducial pads, test
pads, edge connector pads, mounting hole pads and part holes. Mounting hole to mounting hole
clearances are used during Batch DRC verification only as a manufacturing check. The Net
Class pad to pad clearance between mounting hole pads is used during net class verification as
an electrical verification.

Net Properties
On negative planes, clearance distances become the sum of the clearances used by the annular
rings. For example, if a via to component clearance is set to 10th and the via to pad clearance is
set to 10th, the clearances in these instances will be maintained at 20th on negative planes.
Net Class to Net Class rules are groups of net classes which have been defined to have a specific
rule set used for specific layers. These cross-class clearances sets are used based on specific
groupings to general groups. The clearance within a specific grouping is used before the
clearance within a more general grouping.
Toggle Plane Clearance Rules

When you select the toggle plane clearance rules icon, the table adds the following
clearances; plane to trace, plane to pad, plane to via and plane to plane. If you select this icon
and change the clearances for the additional fields, those clearances are used. If you toggle this
option off, even though the values are no longer seen, they are still used.
Toggle Embedded Passives Clearance Rules

When you select the toggle passives clearance rules icon (only available if you have the
correct license), the table adds the following clearances; mask to trace, mask to pad, mask to
via, mask to resistor, resistor to trace, resistor to pad, resistor to via and resistor to resistor. If
you select this icon and change the clearances for the additional fields, those clearances are
used. If you toggle this option off, even though the values are no longer seen, they are still used.
Net Properties
The Setup - Net Properties dialog allows you to define individual net based routing rules; Net
Class assigned to nets, custom topology for specific nets, timing parameters, crosstalk
parameters, maximum number of vias, matched length groups, differential pairs and delay
formulas.
Note
If your design/ database has used CES for physical rules, the Net Properties dialog is
unavailable.
The Find Net field allows you to enter a net name, a partial net name or use an asterisk as a wild
card character to locate and select the entered net name in the Net Name column.
The Net Order tab displays all the nets in the design. Each net may be assigned to a net class,
assigned a netline order and have pin order defined. Any net not assigned to a specific net class
is included in the (Default) Net Class.

Net Properties
Figure 3-15. Net Properties Net Order Tab
The Net Order tab can be used at any time during the design process to order nets. Typically, it
would be used to order nets prior to placing components. If the nets are to be chained, a pin type
(source, driver, load, terminator, test point, connector) should be assigned to each pin to allow
proper ordering. Plane nets can only be defined as MST.
The Timing and Differential Pairs tab allows you to define nets that have a maximum length or
delay, matched net groups based on their length or delay tolerance, and define the differential
pairs in your design. The differential pair tolerance allows you to set up a matched group of
differential pairs that have to be within a matched group tolerance and at the same time maintain
a tolerance between the nets of the individual pairs. Any violations are reported in the Review
Hazards - Differential Pair - Delay or Length Tolerances sections.
Figure 3-16. Net Properties Timing and Differential Pairs
A maximum length assigned to a net can either be specified as a distance, a delay, or as a

percentage over the Manhattan length of a net. If the Maximum length or delay value is set,

Net Properties
Expedition PCB routes the net within the length. If a trace cannot be completed within the
maximum values, it appears as a Length or Delay Hazard in the Review Hazards dialog. While
interactively routing, tuning rings appear for nets that have a maximum length or delay. This
ring defines the length that is left before the maximum is exceeded. Care should be taken when
assigning these values, as it is possible to assign values that will make routing impossible.
Differential pairs are composed of two nets (carrying a signal and its inverse), generally derived
from the outputs of a single gate. These nets are active at the same time and have the same
number of inputs and terminators. Differential pairs are defined in this dialog so that the signal
and its inverse arrive at the differential inputs with identical characteristics. To achieve this,
these nets are routed with adjacent traces and paired vias.
Differential pair tolerances may also be set in this dialog. The differential pair tolerance is a
length or delay tolerance that is applied between the two nets of the differential pair. The
differential pair tolerance allows you to set up a matched group of differential pairs that have to
be within a matched group tolerance and at the same time maintain a tolerance between the nets
of the individual pairs.
For example, a group of differential pairs have to be within 250(th) of each other, but the nets
within each diff pair must match within 25(th). You would enter 25 in the Diff Pair Tol. column.
Any violations are reported in the Review Hazards - Differential Pair - Delay or Length
Tolerances sections.
The Crosstalk tab allows you to assign values for the maximum crosstalk or the maximum
parallelism allowed on individual nets. A net can have Maximum Crosstalk or Parallelism Rules
Factor rules defined, but not both. The values entered in this tab are used to determine the
existence of these hazards within your design. Crosstalk estimation is based on the layer stackup
and the timing parameters displayed in Setup Parameters.

Net Properties
Figure 3-17. Net Properties Crosstalk Tab
The Other tab settings define the maximum stub length, the maximum number of vias, and the
nets supply voltage. The Maximum Stub Length value is used during routing of chained or
custom topology nets. If the stub length has been exceeded by a net, Review Hazards displays
this as an Online Stub Length hazard. Ideally all netline connections for chained and custom
topology nets should be made with independent paths between the device pins at the end of the
netlines. This can often be difficult or impossible. In some instances, a trace must be shared by
two or more netline connections. This shared interconnect is called a stub.
Figure 3-18. Net Properties
The Delay Formulas tab allows you to enter the formulas for pin to pin delays on custom nets.
These formulas can be used to constrain pin to pin delays, match delays between a set of pins,
and define relationships between a set of pins.

Draw
Figure 3-19. Net Properties Format Variables
All custom topology nets in your design are organized into a spreadsheet format allowing you to
enter a delay defined in terms of electrical length.
Figure 3-20. Net Properties Custom Topology
Draw
For more information on the functionality of the Expedition PCB drawing module called Draw,
refer to Appendix A - Draw. The drawing module is for creating and editing lines, arcs,
polylines, polygons, rectangles, circles and text. Graphic objects such as plane shapes, reserved
areas, rule areas and route obstructs must be created and/or modified by you while in Draw
mode.

Draw
Plane Shapes
At the beginning of the design process and/or after placement, define the areas and layers on the
board that will be used for plane signals. Plane shapes can be placed with the Place Plane Shape
command. The plane shape can be defined using a Polygon, Rectangle or Circle.
Plane shapes are used by the Planes Processor command to determine the extents of
positive and negative plane data.
These areas are critical in determining if a net can simply be fanned out into a plane or if it has
to be fully routed. Plane shapes can be placed on any signal layer of the board.
Plane shapes may be placed on signal layers or the plane could encompass the entire layer.
If an entire layer consists of a single plane signal, a plane shape does not have to be defined. The
option of defining the route border to be used for a signal plane signal on a layer can be set
within Setup Parameters.
Each positive plane shape can override the Area Fill Parameters; Hatch Option Width and
Hatch Distance. These attributes are only used for positive planes. If one of these attributes is
defined for the shape, they all must be defined. Also, a route attribute allows you to define
whether traces other than the plane net are allowed to pass within the plane shape.

Draw
Place an Actual Plane Shape

You can place actual plane shape outlines in the design. You can only allow place actual plane
shape outlines on valid routing layers. You can select the layer and the traces and the
corresponding nets display. When placing actual plane shapes, you can use the options in the
Draw Properties dialog.
It is possible to scale an actual plane shape outside of the board outline. In this case, when
Planes Processor is generated, the plane data is generated outside of the route border and plane
data that outlines the shape follows the shape outside of the board outline. Either resize the
actual plane shape or use the Subtract option while in Draw mode.
Actual plane shapes outline and represent the true plane data including obstructs or holes,
islands and tie legs as they would be plotted. These shapes are always enclosed shapes and
adhere to the clearance rules and connection types defined within the parameters of each tab of
the Planes Parameters and Processor dialog.
Dynamic Area Fills

This option on the Display Control Layers Tab enables the display of area fill data inside user-
defined plane shapes placed on trace layers.
The Dynamic Area Fill command is only active when no Planes Processor generated plane data
is present on any layer of the board. You can use the Delete Plane Data command to remove all
previously generated plane data.
Dynamic area fills are only generated for positive layers which have routing enabled in Editor
Control. Dynamic area fills are not generated for negative and positive layers which do not
have routing enabled in Editor Control.
Dynamic Area Fill can be used as a tool to help visualize what positive plane data will look like
once it is generated. It is not physical data and therefore the command must be activated each
time you enter the design. When Dynamic Area Fills is enabled, a status bar appears at the
bottom of the PCB window and any positive plane net that is checked to be processed within the
Planes Processor dialog and that exists on a routing layer enabled in the Editor Control dialog is
filled.
Options for area fill hatching are defined within Draw mode using the Properties dialog.
Note
If Dynamic Area fill is turned on and you modify a plane shape in Draw mode, the
Dynamic Area Fill data will still display using the original shape and will only regenerate
when you have exited Draw mode.

Draw
In order to generate real plane data on the board before Gerber is created, you must run the
Planes Processor.
Plane Obstructs
Plane Obstructs are user-defined areas where plane data is not allowed. A Plane Obstruct may
be any of the standard closed draw objects: Polygon , Rectangle and Circle . Arcs
are allowed in the polygons. Plane Obstructs can be placed on any routing layer of the design.
As an example, planes can be generated inside plane obstructs as long as the plane shape is fully
included within the obstruct. This allows you to use the plane obstruct to isolate planes from
each other. You could have a GND net which is composed of two shapes; the inner shape is
used for GND for a power supply, the outer shape is used for GND for a digital circuit. In order
to isolate the power supply GND from the digital GND (same net), place the plane obstruct so it
totally encloses the inner shape.
Route and Via Obstructs

Trace route and via route obstructs are used to prohibit the routing commands from placing
conductive material in areas that might cause interference problems. Route obstructs are also
used as plane obstructs by the Planes Processor.
When placing a route obstruct, the shapes do not have to be orthogonal. Trace route obstructs
and via route obstructs are respected by the automatic router and interactive routing commands.
If for some reason a trace or via violates a route obstruct, it is flagged by Batch DRC as a
proximity violation.
Route trace obstructs prohibit placing routes within the area, but allow vias. Via route obstructs
prohibit vias, but traces are allowed. “Both” route/via obstructs allow neither traces nor vias
within their outlines.
Traces cannot cross over a line obstruct or be inside an area obstruct. Line obstructs are used
most often to direct the routing escape from pins.
Area obstructs keep traces or vias, or both, from a particular area. When a piece of hardware,
such as a heatsink or a bracket, is touching the surface of the design, a trace/via “Both” obstruct
should be placed on the outside layer. This prevents any traces from being routed in the area on
the outside and prohibits any vias that may be placed by internal traces.
Reserved Areas
Reserved areas are created in the Properties dialog of Draw, as closed polygons with the
Reserved Area attribute. They are used to define the reserved areas that are used to split the
design. These reserved areas will represent the split area for all layers.

Setup
Setup
This section gives you information on how to define the physical attributes of the board. If you
design a large number of boards of one or more standard sizes, it is recommended that the board
outline, mounting holes, etc., be defined in a layout template.
If you want to:

Learn about the Display Control dialog Information on page 112
Learn about placement mode Information on page 113
Learn about the Board Outline Information on page 113
Learn about the Manufacturing Outline Information on page 114
Learn about the Board Origin Information on page 114
Learn about the Mounting and Tooling Holes Information on page 114
Learn about the Route Border Information on page 114
Learn about Contour Placement Information on page 115
Learn about Part Placement Information on page 115
Learn about Placing Etch Text Information on page 118
Learn about using netline manipulation Information on page 118
Display Control
The Display Control dialog defines how design graphics are displayed. Each graphic object, or
set of objects, can be turned on/off and have their color and or graphic pattern changed. The tabs
within this dialog group graphic objects based on route layers, general graphics, part graphics,
color by net and color by hazard. In addition to controlling the display in the design, The
Display Control dialog allows you to define the colors used for each item type.
There are times when it becomes necessary to turn all items of a particular type (Trace and Pad)
either on or off. This allows you to fully inspect those items without the clutter of a fully or
partially routed design.
Options within Display Control allow you to further control the display of items within the
design. You can select to only display elements on the active layer, change the background
color of your design, turn all displayed elements to gray, and only display text which is above a
certain font size and mirror the contents of a view about the vertical axis. When changes occur
within the Display Control dialog you can select to have the graphics update only when the
Apply button is selected.

Display Control
Place Mode
Place Mode allows the selection or manipulation of parts. Package, Mechanical and Drawing
cells can be manipulated while in this mode. While in Place Mode, there are two states that can
be entered, Select and Move.
The Select state is used to select parts without moving them. These parts can be pushed or
rotated without the part entering dynamics. The Move state is used to move a part or groups of
parts. Move operates on individual parts, multiple parts, grouped parts and reusable blocks. You
can activate the Move state by double-clicking on a part or by selecting the Move command
either before or after the part is selected. While in the move state, you can move, rotate and push
parts. The parts will appear dynamically attached to the cursor.
• If parts within the design have been assigned to a group, selection and movement of any
of the parts within the group cause the entire group to move together.
• If a selected part is nested within a reusable block, movement of this part, or any parts,
within a reusable block cause the entire block to move.
Many commands can be active while in the Select or Move states. The Part Properties dialog
can be active while in either state and displays information about the selected part. Existing
parts can be manipulated to make room for parts that have not yet been placed.
Board Outline
The board outline defines the physical shape and size of the board and cannot be deleted. Only
one board outline can be in a design file; therefore, if a new board outline is placed in the design
file, the old board outline is removed. Use the Edit > Place > Board Outline command to define
the board area. The board outline consists of a polygon that produces a single, closed shape. The
board outline may be placed using the grid points as a reference, or the outline may be placed
using precision keyins, using the Draw properties dialog.
Manufacturing Outline
The Manufacturing Outline is only a required object within FabLink XE Pro or FabLink XE and
can be DRC'd against other designs placed within a panel. The manufacturing outline within
Expedition PCB will not be DRC'd. Use the Edit > Place > Manufacturing Outline command to
define the manufacturing area. Only one manufacturing outline can be in a design file;
therefore, if a new manufacturing outline is placed in the design file, the old manufacturing
outline is removed. The manufacturing outline consists of a polygon that produces a single,
closed shape. The outline may be placed using the grid points as a reference, or the outline may
be placed using precision keyins, using the Draw properties dialog.
Manufacturing outlines are not saved within a reusable block.

Display Control
Board Origin
The board origin defines the (0,0) point in the design file, and the location of all design elements
are referenced from it. The lower left corner of the board makes a good location for the board
origin, as it puts all parts in positive coordinate design space and provides an easy reference
point to measure from. Use the Edit > Place > Origin command to define the board origin.
Optionally a Drill Origin can be placed. This allows you to define a specific location as the 0,0
point of your NC Drill output. Board and Drill origins can be moved using the X-Y option on
the dialog.
Mounting and Tooling Holes

Mounting holes are holes drilled in the board for purposes of securing hardware to the board or
for securing the board to a fixture, and are typically non-plated holes. Mounting holes
associated with specific parts, such as connectors, are typically built into those parts. Mounting
holes placed as part of the board setup would be those used to mount the board to a fixture or to
mount hardware, such as card ejectors or stiffeners, to the board.
Figure 3-21. Place Mounting Hole
Tooling holes are holes used to register and/or secure the board during the manufacturing
process. Tooling holes are often placed outside the board outline and are cut off during the final
routing of the panel. All mounting hole padstack types found in the Local and Central Library
padstack databases are displayed. The padstack name is prefixed by Local, for padstack in the
local Padstack database, and Central, for padstacks in the Central Libraries padstack database.
Use the Edit - Place - Mounting Hole command to place any needed mounting holes and tooling
holes. Mounting holes and tooling holes may be placed using the grid points as a reference, or
they may be placed by precision keyins using the Properties dialog.
Route Border
The route border defines the area within the board that contains trace and plane data. The route
border is used by the Auto Router and Batch DRC and must lie entirely within the board outline.
The route border can be used as a plane shape by selecting this option within Setup Parameters.

Display Control
Use the Edit > Place > Route Border command to place the route border. The route border
may be placed using the grid points as a reference, or by using precision keyins on the
Properties dialog.
Contour Placement
Contours are placed on the board to define slots or cutout areas to be cut into the board. A
contour can also be placed that defines how the board is to be cut from the panel. Use the Edit >
Place > Contour command to place any contours needed in the board.
Part Placement
Placing critical parts first ensures that the location does not get congested before a critical part is
placed. Critical parts typically have mechanical constraints to their location that cannot be
changed. Connectors, card ejectors, and stiffeners fall into this category.
Figure 3-22. Place Parts and Cells

Display Control
To aid in placing parts with critical routing constraints, the parts can be sorted by Net Classes
and Clearances. This allows parts to be grouped and placed based on the nets or net classes
assigned to its pins.
The parts should be fixed or locked after placement so that they are not inadvertently moved or
shoved when other non-critical parts are placed. This ensures that interactive routines do not
move, rotate or delete the part.
Place Part respects the DRC options defined in Editor Control. These options control how a part
will be placed, if DRC is enabled, and if existing parts are allowed to be shoved out of the way
of a part being placed.
If Online DRC is set to Off or Warning while placing parts, Review Hazards lists any
Component hazards that are created.
You can push back parts during placement by pressing and holding the CTRL key while you
place the part. If this option is enabled, when a part is placed in violation, the part is
automatically placed at minimum spacing (applying the normal part to part clearance rules),
from the violated part.
If the pushback fails (not enough room to place it in an error free location), the part returns to
dynamics.
After parts are placed, the Part Properties dialog is used to change the properties. If the rotation
or location fields are changed, the cell reflects these changes based on the Absolute or Delta
selection.
Absolute data is given in absolute coordinates (that is, coordinates that are taken relative to the
0,0 point) while Delta data is based on the current cell’s location and rotation. For example, a
part is at 180 degrees and Absolute is selected. If -15 is entered into the Rotations text entry
field, the result is 345 degrees. If a part is at 180 degrees, Delta is selected and -15 is entered
into the Rotations text entry field, the result is 165 degrees.
Nested Cells
When the properties for a nested mechanical cell are displayed or reported, the height of the
mechanical cell is adjusted by the height of the package cell, (if required, this is adjusted by the
underside space of the mechanical cell).
Only the reference designator for the package cell appears in the Place Parts and Cells list;
nested cells do not appear in this list. Nesting associations can only be made within the Cell
Editor . Batch DRC and Online DRC ignore the placement and insertion outline rules
violations between package cells and their nested cells.
Within a given library (central or design), the names for mechanical and drawing cells must be
unique regardless of their partition.

Display Control
Rules within IDF Import and Export

Nested mechanical cells are exported to IDF and are merged into the package cell; however,
nested drawing cells are not exported to IDF, they are ignored. During Import IDF, any package
cells that have been moved or otherwise manipulated are relocated as before and the nested cells
maintain their original location and orientation relative to the package cell.
Rules within PCB for Nested Cells

Nested Cells "flattened" - A mechanical or drawing cell nested within a package cell behaves
just like any other mechanical or drawing cells. When in Expedition PCB, individual instances
are added.
Move - When you move the package cell, the mechanical and drawing cells move with it. You
cannot ungroup nested cells in Expedition PCB.
Rotate - When rotating a package cell with nested cells, the nested cells maintain their relative
locations and rotations with the package cell.
Push - When pushing a package cell with nested cells, the nested cells maintain their relative
locations and rotations with the package cell.
Replace Cell - When a package cell with nested cells is replaced, it is modified to match the
data in the Cell Library.
Since the package cell has references to the nested cell, it always reflects the current state of the
mechanical or drawing cells that are nested. If you replace or reset the package cell, the nested
cells are also updated in the PCB Editor.
• If you modify a nested mechanical or drawing cell, it is automatically updated in the

package cell and in the PCB Editor.
• You cannot replace a nested mechanical or drawing cell in the PCB Editor; you must
make the change in the package cell in the Cell Editor.
Forward Annotation - If a package cell is added or updated from the Central Library and it has
nested cells, these are also forward annotated as well as any updated mechanical and drawing
cells.
Use Place Parts to place the remaining parts

Once the critical parts are placed, the rest of your parts can be placed. There are many ways to
place parts within Expedition PCB. Parts can be sorted by reference designator, part number,
package cell, room, cluster.
Some parts such as connectors and LEDs, must be placed at precise locations. This can be
accomplished by using keyins.

Display Control
Many times the best way of interactively placing parts is using the Connected to Placed option.
This sorts the parts based on the number of connections to parts that are already placed. While
parts are being placed, Review Hazards Online DRC reports any part of the maximum net
length hazards that are created. Part hazards can be controlled using the Editor Control Parts tab
which allows you to define if Online Placement Outline hazards are Off, Warning or in
Preventative mode.
Placing Etch Text

While the part placement area is populated mainly by parts, there are various types of text that
may be etched into the board. As some companies are avoiding the use of silkscreens, many
times all board identification must be done via etch text.
Figure 3-23. Example on how to place text
On most designs, at least a board identification number and layer numbers are required to be
etched onto the board. The text can be placed using the Place Text option in the Draw
module. More complex board identification can be built into a mechanical cell. This allows you
to build the documentation once and use it for multiple boards.
Netline Manipulation
Netline manipulation enables an interactive method for manipulating the ordering of nets. With
this command you can change the topology of a net from MST to Chained or Custom ordering
and you can specify the order in which pins of Custom nets are connected by interactively
modifying, adding or deleting netlines. You can also interactively place virtual pins and guide
pins. All changes made while in this command are reflected in the Net Properties menu.
Note
If your design has used CES, you have more flexibility when defining high-speed
topologies such as T -shape, Star and H-Tree topologies.

Display Control
If a plane shape is added to an existing net that is chained or custom, the net will then change to
MST.
When you initiate the Netline Manipulation command, all net objects on the board display in
Shadow Mode - all net objects appear grey except for the selected net. When you select a net by
selecting a pin or netline, all items in the net are displayed in the select color and the view is
fitted to include all component pins and netlines associated with the selected net.
Target Pin Selected by Mouse Position

The system seeks out a new target pin for a net based on the present location of the cursor
within the display window. The following are the required steps:
Note
If an "MST" topology netline becomes selected and is dragged in the display window,
that netline will automatically become a "Custom" topology netline.
1. Pre-select a location point on the netline closer to the pin that you want to be the anchor
pin.
2. A red "+" will be placed on this pin. The entire net and objects associated with the net
will be selected.
3. Hold down the Shift key, and then select the netline you want to re-assign by selecting
and holding down the left mouse button on that netline.
4. Once the netline is selected, release the Shift key.
5. Move the cursor within a very close proximity (but not exactly over) the target pin, and
the netline is tentatively "snapped" (be redrawn) between the anchor pin and the "new"
target pin.
6. As the cursor is moved in the display window within the proximity of other pins of the
selected net, the tentative netline "snaps" from the anchor pin to these other "new" target
pins.
7. To finalize the new netline between the anchor pin and the new target pin, release the
left mouse button, and the new netline, between these pins, is created and the previous
netline between the anchor pin and the original target pin is deleted. The red "+" will
disappear after the new netline to the target pin is created.
To change the net ordering back to the original target pin select either the Edit >Undo
command or the F6 Undo action key.
Terminology
Custom - This method looks for a user-defined netline order. If netlines are not found, or if the
definition is invalid (is incomplete or has loops), the chaining algorithm is used. Only pins are

Display Control
considered as valid connection points. If a net has more than 100 pins (or a plane net) and it is
marked Custom Order, the netlines cannot be ordered, and are then generated using the
Minimum Spanning Tree (MST) algorithm.
Guide Pin - Guide Pins cannot be shoved, as they are suggestion points of where a trace should
be routed.
Anchor Pin - The pin determined as the fixed end of a change of an existing netline connection
between two pins.
Target Pin - The pin determined as the new destination end of a replacement net connection
between two pins of an existing net.
MST - The Minimum Spanning Tree (MST) algorithm is used to generate the basic connection
order. However, netlines are dynamically generated to the closest connection point during
routing. A pin may be 'starred' to more than two pins in this configuration. If a net is a plane net
(because it is on a plane layer or it has a shape on a plane shape layer) it is always MST. When
a net is MST-ordered, the net lines are purely advisory. That is, you can make a connection to
any pin, via or trace regardless of the net lines.
If you choose a netline for a MST ordered net, and if there are multiple pins of the same net, you
can use the Tab key to change the target pin of the current plow.
Chained Order
The Chain algorithm is used to generate netlines. This algorithm connects the pins in a series to
create a daisy chain. A pin can be connected to a maximum of two other pins in this
configuration. The chain's pins are ordered according to their type, as defined in the following
table. Only single pin test points defined in the schematic are included in chained and custom
ordered nets. If a net has more than 100 pins, it cannot be chained.
Only pins are considered as valid connection points.
Parts Database Attributes

This maps the part pin type definitions accordingly:
• Input and Schmitt become loads.
• Bi-directional, output, tristate, open collector, open drain, and open emitter become
drivers.
• Test points and connectors are a direct map.
• Discrete part definitions for series/parallel resistor, capacitor, RC resistor, and Thevenin
resistor become terminators.

Display Control
Cell Types
Connectors and test points are identified.
Design Capture Properties and Symbols

This is a direct map to the necessary pin types.
All remaining unrecognizable pins become loads

The pin type assigned to a pin in the part can be displayed by clicking the Pin Types
button in the Display Control dialog. Plane nets can only be defined as MST Order.
Table 3-1. Chained Order

No. of No. of No. of No. of Algorithm
Drives Loads Connectors Terminators
0 >1 0 0 Chain the loads together
>0 >=0 0 0 Chain the drives, then the loads
0 >0 1 0 Chain the connector, then the loads
>0 >=0 1 0 Chain the drives, then loads, then
connectors
>=0 >=0 2 0 Chain with the connectors on the
ends
>=0 >=0 >2 0 Chain in any order
0 >0 0 1 Chain the loads, then the terminator
>0 >=0 0 1 Chain the drives, then loads
>=0 >=0 1 1 Chain the connector, then the drives
and loads, then the terminator
>=0 >=0 >1 1 Chain in any order
>=0 >=0 >=0 2 Chain with a terminator at both ends
- unless both terminators are within
.5”. In this case, both
terminators are treated as one
terminator. See the previous
references for one terminator.
>=0 >=0 >=0 >2 Chain in any order
Virtual Pins
Virtual pins should not be placed on existing pins, vias or traces as they would violate these
existing objects. The ms and xy keyins allow virtual pins to move within Netline Manipulation.

Display Control
Note
If traces have been routed to the virtual pins, Netline Manipulation move mode will
delete the traces connected to the virtual pin.
It is recommended to use Virtual Pin dyna-move to maintain connection of the traces to the
virtual pin. This can be done anytime in the design session without Netline Manipulation being
active.
1. Locate the virtual pin in the design.

2. Using the Shift key + the left mouse button on a virtual pin, drag the virtual pin to the
desired location.
3. During the drag, the netlines to the virtual pin will adjust accordingly. If the virtual pin
is routed, the traces connected to the virtual pin adjust accordingly.
Once the virtual pins are placed, the netlines can be connected to them in the same way they are
connected to the other pins on the net.
Characteristics
• The virtual pin has no padstacks and can reside on any particular layer.
• The virtual pin uses trace clearances instead of pad clearances.
• Vias are allowed under virtual pins.
• Virtual pins have unique reference designators. These unique reference designators
make it easier to find individual virtual pins.
• Virtual pin manipulation is not available in the Net Properties dialog. They are displayed
and can be moved, but new virtual pins can only be added while in Netline
Manipulation.
• Virtual pins do not allow stubs. Therefore any stub rules associated with a net are
ignored with virtual pins.
• Virtual pins can only be deleted from the design using the Delete key or the Delete icon
within Netline Manipulation.
Router Interaction With Virtual Pins

The automatic and autoactive router interacts with virtual pins as specified below.
• Vias and T-junctions will only be placed at the exact location of the virtual pin point.
• The router will not push or shove virtual pins.
• Fanouts do not work with virtual pins. The router may place a via at that point during
auto route if it needs to change layers.

Display Control
• If manually routing on a layer other than where the virtual pin resides, a via must be
dropped onto that layer, or the virtual pin must be moved to the active routing layer
before connecting the virtual pin.
• Automatic clean-up routines for vias and virtual pins are applied upon net completions
to minimize routing challenges.
Guide Pins
Guide pins are horizontal bowties and each has its own reference designator and is numbered
sequentially in the design for the active session. Guide pins and their associated netlines may be
selected and printed, but they cannot be photoplotted.
Guide pins are placed within the route outline and cannot be DRC’d against existing pads,
planes, traces or vias. When DRC checks are run, guide pins are identified as opens on nets (if
the routing between two pins are incomplete).
Adding Guide Pins on user-defined layers

The following explains the methodology on how to change the layer associated to each guide
pin.
1. Select a netline.
2. Select the Place Guide Pin command (F4 key). All guide pins automatically default to
being placed on All Layers.
3. While adding guide pins, if you want to assign a guide pin to a single layer, PRIOR to
placing it with the left mouse button, access the popup by clicking the right mouse
button, and select the layer that the next guide pin is to be placed on. All guide pins
placed after this layer has been selected default to being placed on All Layers.
4. Add (place) as many guide pins to the net as desired between the two pins and use the
popup’s "Accept Guide Pins" command to finish.
5. If you select the Cancel Place command from the popup, the guide pins being placed
between the pins of the highlighted net are discarded. Selecting the Esc key also cancels
the placement of guide pins.
6. When creating a netline with guide pins, the Undo command removes the last placed
guide pin, subsequent selection of the Undo command removes all placed guide pins on
the active net.
To edit / delete guide pins

A single guide pin may be selected either by using the left mouse button or by using the Ctrl-left
mouse button combination to toggle selecting/unselecting a guide pin. The Ctrl-left mouse

Placement Improvement
button may be used to drag select an area with guide pins within the Netline Manipulation
mode.
1. With the Guide pin(s) selected, click the right mouse button and from the popup decide
whether to assign the guide pin(s) to a single signal layer, a single plane layer or to all
layers of the design.
2. If a guide pin's layer is set to All Layers, the guide pin changes to the layer selections
you make by using the computer keyboard up and down arrows.
3. If a guide pin is deleted within the connections between its anchor and target pins, all
remaining pins are reconnected (but not renumbered) to a serial sequence.
Using guide pins on the edge of reserved areas

Every split design could potentially route to a different layer of the guide pins on the edge of the
reserved areas as these connections to the guide pins do not connect through the layers.
Therefore, the routes in each split design meet at the guide pins on different layers. These
connections must be manually controlled to ensure they are made on the same layer. Layer
restricted guide pins will force the connection between the splits to a specific layer.
Once the design has been either fully or partially placed, there may be a need to refine the part
locations. Parts can be moved, swapped or rotated. To help reduce the connection lengths, gates
and pins may also be swapped. When all the part, gate and pin refinements have been made, all
the changes can be automatically backannotated to the schematic.
If you want to:

Learn about fixing parts Information on page 125
Learn about moving parts Information on page 125
Learn about editing cells and part numbers Information on page 125
Learn about moving circuits Information on page 127
Learn about rotating parts Information on page 128
Learn about pushing parts Information on page 128
Learn about swapping parts Information on page 130
Learn about swapping pins Information on page 131
Learn about swapping gates Information on page 130
Learn about automatically swapping by cell name Information on page 131
Learn about automatically swapping by part number Information on page 132

Fixing Parts
The Fix Part command is selected while in Place Mode and is useful for temporarily fixing
or locking cells into place. The pads of a fixed cell will appear hatched instead of solid. Some
parts, such as LEDs and connectors, have pre-defined locations in the design. Once these parts
are placed, they should be fixed into their positions to prevent their accidentally being moved.
Expedition PCB provides two methods of preventing a part from being moved or deleted. The
two commands, Fix and Lock , provide slightly different protection schemes. The most
common method is the Fix Part command. The Fix command is used to temporarily fix a part in
location but may be unfixed later in the design process. The Lock command is used to lock a
part to a location permanently throughout the design process.
Once a part has been fixed or locked, they must be unlocked using the Unfix or Unlock
commands. Mounting Holes and Fiducials may also be fixed and/or locked. These objects may
also require specific locations in which you want the objects to be permanently placed.
You must be in Route Mode to Fix/Lock mounting holes, fiducials and test points.
In Place Mode, the Fix command fixes selected cells in position. Once a cell is fixed, it cannot
be moved, pushed, deleted or rotated. Fixed cells pads are drawn as filled (hatched) outlines.
This command is useful when working with cells that must be placed in critical positions.
Editing Selected Cells and Spare Part Numbers

You can use the Cell Editor to change the selected cells local library definition wile you are in
Place mode. When you choose Edit Selected Cell, the Cell Editor opens into graphics with that
cell active. You may then edit, save and exit Cell Editor and all the parts that reference this cell
are updated within the design.
If you have the Cell Editor open and you choose Edit Selected Cell on a different cell, you are
asked to save the first one opened.
There are two modes of changing a part number for a selected cell. The first method is to assign
a new part number based on the valid part numbers which are defined for the selected cell in the
Central Library. The second method allows the assignment of a new part number based on
existing unplaced parts referenced by the schematic which are valid for the selected cell.
Move Part
Use the Move Part command when moving individual parts. This command adjusts the
locations of all package, mechanical and drawing cells. Mounting holes and fiducials must be
moved using the Edit > Properties command, while in Route Mode.
Move operates on individual parts, multiple parts, grouped parts and reusable blocks.

• If parts within the design have been assigned to a group, selection and movement of any
of the parts within the group causes the entire group to move together.
• If a selected part is nested within a reusable block, movement of this part, or any parts,
within a reusable block causes the entire block to move.
While a part is attached to the cursor, the following commands can be selected from the action
keys: Rotate 90, Rotate 180, Push, and Snap to Grid. Parts can also be moved using the arrow
keys or by file.
Rotate 90 Rotates the selected part counter-clockwise in 90-degree segments.
Rotate 180 Rotates the selected part counter-clockwise in 180-degree

segments.
Push Moves a selected part and its local interconnects from one side of
the board to the other.
Rip-Up Segment Un-routes the first segment on non-local traces attached to the part
or parts being moved.
Rip-Up Junction Un-routes all non-local traces back to junction.
Rip-Up All Un-routes all non-local traces back to junction and all local
interconnects (except cosmetic traces in a cell).
Snap to Grid Snaps the selected part's origin to the nearest placement grid point.
While the parts are in dynamics click the left mouse button to place the parts at the selected
location. If this location causes DRC hazards to occur, either a warning is generated, the part is
not placed, other parts are moved out of the way or the placed part is moved out of the way
based upon the following four options. These options, except Pushback, are selected within the
Editor Control > Parts tab.
• Warning allows the placement outlines of the part being placed or moved to overlap the
placement outlines of existing parts. Pads are never allowed to break the defined
clearance rules.
• Preventative does not allow placement outlines or pads of the part being placed or
moved to violate the placement outlines or pads of existing parts based on the Net Class
General Part to Part and Pad to Pad clearances.
• Shove Part shoves any existing parts out of the way if Pad to Pad or Placement Outline
hazards will be created.
• Pushback Part pushes back the part being placed or moved out of the way of existing
parts in order to prevent Pad to Pad or Placement Outline to Placement Outline hazards
from occurring. Pushback occurs when the Ctrl key is held down during placement or
movement of a cell. Pushback will place the part using the minimum defined clearances.

Your may choose to select a group of parts. If a group of parts is selected individually, using the
Shift or Ctrl key, or by fence while in this move state, you will be required to select an anchor
point for the group. The parts and any routing fully contained within the selected area, enter
dynamics, allowing these circuits to be moved.
If parts are selected, prior to the Move command being selected, parts will enter dynamics as
soon as the command is invoked and the anchor point will be the center of the selected parts.
When moving a group of parts that you consider to be a circuit, select the Move Circuit option
in order to maintain the location of existing traces and vias.
Move Circuit
Use the Move Circuit command when a group of parts is moved and you want to maintain all
routing between the parts. This command requires you to place a fence around all the parts that
are to be moved. Traces that are fully contained within the circuit are maintained and any traces
that connect outside the circuit being moved may be re-routed or adjusted as needed.
When the circuit is attached to the cursor in dynamics, choose one of the following action keys:
Rotate 90, Rotate 180, Push, or Snap to Grid.
When using Move Circuit, the following are automatically selected:
• All the interconnects (traces and vias, no plane data) between the selected parts.
• All plane net fanouts, (multiple vias included), within a half inch of the pin. Non-plane
nets only select out to the first via.
• All the traces and vias which are locked (and connected to the traces or vias in the first
two categories) regardless of their length.
The above methodology gives you the ability to add any other traces and vias to the set of
objects moved during Move Circuit. Fixed traces are ignored if they do not fall into the first two
categories.
Any interconnect which is selected with Move Circuit is placed exactly as it was originally;
however, if it were to create a short, it is ripped up.
Snap to Grid
The selected part's origin snaps to the nearest placement grid point if that option was selected in
the Editor Control - Parts tab. If the Centroid of Pins button was selected in the Editor Control -
Parts tab, the geometric center of a part's pins is snapped to the placement grid. Multiple parts
can be snapped to grid at a time.

Rotate Part
Selected parts can be rotated, counter-clockwise, in 90- and/or 180-degree increments. The part
rotates around the grid nearest the centroid of the part. An attempt is made to preserve all
existing connections.
Multiple parts that are selected can be rotated. Each part rotates about its own centroid. To
rotate the parts as a group, you must have the parts selected in dynamics. Use the Move
command and then select rotate. This rotates the parts based on the centroid of the group.
If your Editor Control - Parts option is set to Warning you should conduct a hazard analysis,
anytime you move a part, using the Online - Component Hazard dialog. Even though no metal
to metal conflicts are allowed, it is possible to violate placement outline clearances.
Push Part
This command allows you to move a selected part and its local interconnects from one side of
the board to the other. If the selected part is currently on the top placement layer, Push moves
the part to the bottom placement layer. The part mirrors about the grid nearest the centroid of
the part and the X axis. Text within the cells will follow the Editor Control text orientation rules
when a part is pushed.
Note
RF circuits cannot be pushed.
Care should be taken when pushing parts with existing traces. If the traces connect to other pins
of the same part, they are pushed to the new side with the part. If an existing trace goes to
another part, then the trace will be rerouted. When a trace goes from the part being pushed to a
via, the trace is pushed with the part and whenever possible the via is deleted.
If the part is in dynamics and the push command is selected, the part is pushed to the opposite
side of the board. To release the part once it has been pushed, click the left mouse button on the
part. If the part cannot be released without conflict, the part remains in Click Move mode, and
you can either push the part back to its original position or press Esc to return the part to its
original board side. The active placement layer returns to the original placement layer.
If the application is set to the Editor Control - Parts tab - Warning option, anytime you move a
part, you should conduct a hazard analysis using the Component Hazard dialog. Even though no
metal to metal conflicts are allowed, it is possible to violate placement outlines.
If an SMD part is pushed from the top to the bottom layer or vice versa, the padstack attached to
the part is not pushed. Instead, one from the padstack database is used. The Padstack definition
is layer-specific. Any changes made to a part's pads using the Padstack Processor are replaced
by the Padstack Editor's default pad definition during a push between layers.

Copy Circuit
Use this command to make a copy of a group of parts with completed inter-connections.
Connecting traces with both end points inside the selected area are copied with the selected
parts. The software looks for unplaced parts and distributed parts (parts outside the board
outline) that are equivalent to the selected parts within the master circuit. Equivalency is based
on the master circuit’s part numbers and interconnections within the master circuit.
To help Copy Circuit find an equivalent circuit, order the Reference Designators between the
circuits. Therefore, your master circuit might have Reference Designators U1, R1, D1 etc. Each
circuit to be copied from the master would have Reference Designators U1X, R1X and D1X
where X is unique between the circuits. This causes the circuits to have their Reference
Designators sorted. X in the example could be A, B, C or _1, _2, _3 with each being consistent
within the circuits. After the circuit is placed, the Reference Designators can be renumbered.
Once the circuit is copied to its new location it becomes individual traces and parts. The copied
circuit is not maintained as a group and has no relationship to the master circuit from which it
was copied.
Process of designing your schematic

In order to make optimal use of the Copy Circuit command, the schematic must be defined with
each circuit as a block and the References Designators between each block packaged so they are
sorted alphabetically ascending. By designing your schematic in this way, it will aid the Copy
Circuit equivalency algorithm in finding the next equivalent circuit as fast as possible.
1. Create a new schematic for each circuit you intend to copy using Copy Circuit. Make
sure to use hierarchical connectors for any signals that enter or exit the circuit.
2. Within your main schematic, select Place->Block to place a schematic block,
referencing the schematic circuit you just created. This will be your master circuit. The
block will contain any pins for signals that enter or exit the circuit.
3. Save and Compile the iCDB.
4. Run Tools->Packager to create the packaging for your master circuit and any other
symbols placed in your project. Check the log file to verify no parts or cells were
missing.
5. Open your master circuit, this will automatically absorb the packaging that was just
done. Placed the Frozen Package property with Block as its value on all symbols in the
master circuit.
6. Open your main schematic and copy, or place, this block as many times as the circuit is
needed.
7. Run the iCDB Compiler to create iCDB instances for each block that was placed.

8. Run the Packager to package all of the circuits. The packager will base the packaging of
the copied circuits on the master circuit and by using the Frozen Package property, will
append the block number to each Reference Designator. This generates the Reference
Designators, sorted alphabetically, between each circuit.
9. Enter the Expedition PCB job and run Forward Annotation. Check the log file to verify
no parts or cells were missing.
10. Place the master circuit in Expedition PCB. This can be done easily by using Place Part
with schematic cross probe. Open the master circuit that has the original packaging on
each symbol (the Reference Designators without _XX appended). Then with Place Part
displayed and in “By schematic mode”, select each symbol and place it on the board.
The option of adding to the list can be used to group select all of the symbols within the
master circuit.
11. Once you place the master circuit, use Expedition PCB routing functionality to route the
connections that are within the circuit. Do not route any connections that exit or enter
the circuit.
12. Now that the master circuit is fully placed and routed, use the Copy Circuit command in
Expedition PCB to copy this master circuit for each instance that was defined in the
schematic.
Swap Parts
Use the Swap Parts command to swap the physical location of two parts. This command is
useful when the parts are placed in a pattern that should be maintained, but parts within the
pattern still require netline optimization. Part Swapping with grouped components is not a
supported function.
Swap parts determines the location of the parts to be swapped based on the part origin. This
allows parts of different package types to be swapped. Each part is moved to the other’s XY
origin location using each other’s rotation and side.
Swap Parts respects the Fixed and Lock settings and will not allow part swapping to occur on
fixed or locked cells.
Swap Gates
Swap Gates allows gates to be exchanged within a part and external to a part, as long as the
parts share the same part number. You can swap individual gates, gates with common pins and
symbol gate groups. The latter two are supported through the Gate Swap dialog. If you do not
choose to display the Gate Swap dialog, only individual gates may be selected and swapped. To

Automatic Placement Modification
swap gates with common pins or symbol gate groups, you must use the Gate Swap dialog. Gates
are only allowed to be swapped if a DRC violation does not get created and gate swapping is not
allowed for gate pins that have routed connections.
Swap Pins
Swap Pins allows pins within gates to be exchanged based on the swap definition defined for
the part. The purpose of pin swapping is to reduce the crossing of netlines at the package. In
many cases, just swapping two pins of a gate make the difference in successful routing.
Equivalent pins are swapped if they are within the same gate. Pins are only allowed to be
swapped if a DRC violation does not get created.
Automatic Placement Modification

In addition to the Interactive Placement Improvement process discussed in the previous section,
Expedition PCB provides automatic swapping by cell name, automatic part swapping and polar
place commands. Proper use of these commands greatly decreases the time required to take a
design from the placement phase to the routing phase.
Automatic Swap/Rotate by Cell Name

Like the semi-automatic Part swapping commands, the Automatic Swapping process provides
an automatic way to exchange parts to reduce netline length. However, unlike its interactive
counterpart, Automatic Swap/Rotate by Cell Name only swaps parts of the same package type.
This is done to prevent the introduction of placement errors in the design resulting from
swapping with a part of a larger part outline. This command swaps and/or rotates parts in an
effort to reduce the netline lengths.
If parts are placed in rows and columns and this orientation is to be maintained, only the Swap
option of the command should be used. Using the Rotate or Flip option may change a part to an
undesired rotation. Rotate and flip should be used on parts whose orientation is not critical.
The difference between Rotate and Flip is that Flip always moves in increments of 180 degrees.
The Rotate option rotates the part in 90 degree increments if the part outline is basically square,
as in quad-packs and PGAs. If the part outline is a shape other than square, the part is rotated in
180 degree increments to prevent overlap of the part with the design edge, mounting hole, or
other part. Therefore, the Flip and Rotate options are basically the same for parts with non-
square outlines.
Parts with traces cannot be moved or rotated by this command. Parts that are fixed or locked
will not be swapped. If two parts to be swapped have traces attached, the traces must be
attached to the same pin and must be of the same net, or the parts cannot be swapped. If a part is
completely routed, it will also not be considered for swapping.

Placement Verification
Automatic Swap by Part Number

Like the semi-automatic Part, Gates and Pin swapping commands, the Automatic Swapping
process provides an automatic way to exchange parts, gates and pins to reduce netline length.
Automatic Swap by Part Number swaps parts, gates and pins based on the part swap definition
for each part number in order to minimize the length of the netlines that facilitates optimum
routing. When swapping is complete, the Back Annotation process is run when the design is
saved. Back Annotation maintains consistency between the board design and its CAE input.
Automatic Swap by Part Number respects the Fix and Lock settings. Parts that are fixed or
locked are not swapped. If two parts to be swapped have traces attached, the traces must be
attached to the same pin and must be of the same net, else the parts cannot be swapped. If a part
is completely routed, it is also not considered for swapping.
Polar Placement
Parts may be moved into a defined polar (circular) array using the Polar Place command. Parts
may be rotated, placed on the top or bottom of the design, or by pin 1, part origin or part
centroid.
You cannot use polar placement on fixed parts. They must be unfixed before they can be
defined as part of the array. Parts that are already placed and are defined as being part of the
array will be moved from their current position to the array location.
Placement Verification
Before starting the routing phase of a design, verification checks should be made to validate the
placement of the design. Making checks at this point ensures that the design is error free prior to
connections being routed. Routing a design with placement errors may invalidate large
percentages of routing and may not be repairable after traces have been added to the design.
If you want to:

Learn about verifying part placement in DRC Information on page 132
Learn about mechanical verification Information on page 133
DRC - Verifying Part Placement
Batch DRC should be executed to verify that the parts in the design have been placed and/or
moved without creating spacing violations. Batch DRC is used again later in the design phase to
verify routing.
At this point in the design process, many of the Connectivity and Manufacturing checks are of
little or no use. Only the options that check for proximity violations should be selected. To

Routing
ensure consistency between which validation checks are done during Batch DRC, a DRC
scheme can be created with the options selected to verify placement, then this scheme can be
used for multiple designs. The following are suggested checks that can be run to verify
placement:
• In the DRC Settings Tab:

o Area - Within the board outline
o Rules to Check - Net Class Clearances
o General Element to Element Rules
Note
If there is no check mark in the Connectivity and Special Rules and/or General Element
to Element Rules check boxes, none of the options in the Connectivity and Special Rules
or Advanced Element to Element Rules are active.
Upon completion of Batch DRC, a message displays indicating the number of DRC hazards
found in the design, dependent upon your selections. The breakdown of these hazards can be
reviewed in the created DRC.txt file through File Viewer. If errors exist, they should be
corrected and the Design Rules Checks run again. Continue this process until DRC is run with
no errors or with errors deemed to be acceptable. For example, you may want to place some
parts underneath other parts.
Caution
It is important to check the drc.txt file after each run of Batch DRC. This file can be
viewed through File Viewer. The Batch DRC hazards limit is 10,000 for proximity
checks and 10,000 for connectivity checks. If this limit is passed, Batch DRC stops
before completing verification.
Mechanical Verification
Expedition PCB provides the capability to transfer two-dimensional electronics placement data
to mechanical verification tools and back again using IDF Export and Import. This provides you
with the ability to verify that no mechanical interference exists between the parts in the design
and any related mechanical hardware. If conflicts are found, the parts can be moved in the
mechanical design software and those changes can be translated back to Expedition PCB. The
actual capabilities of the mechanical verification depend on the mechanical design package
used.
Routing
Expedition PCB provides you with both semi-automatic and automatic routing and route editing
commands.

Routing
The Automatic Routing commands provide you with access to the most powerful shape-based
automatic routing tools available. These commands allow you to work with automatic functions
on individual traces or groups of traces or to automatically route the entire design.
Prior to using either of the two sets of routing commands, there are steps that must be completed
and verified. Many of these steps can be set up and placed in your Central Libraries layout
templates. However, before starting the routing phase of a design, always make sure the items
are correct for your design configuration and rules.
You should enter Setup Parameters and verify that the correct number of layers are being used,
the plane layers have been defined, and the correct default vias have been assigned.
• Enter Net Classes and Clearances and verify that the trace widths assigned to each Net
class and the clearances have been defined correctly.
• Enter Net Properties and verify that each net has the correct net class defined and all
high-speed rules needed for the design have been added.
• Enter Editor Control and verify that the correct layers are defined to be used for routing,
the layer pairs are defined correctly, and any other routing rule has been defined to meet
the needs of your design.
If you want to:

Learn about saving your work Information on page 134
Learn about route modes Information on page 134
Learn about route and via obstructs Information on page 111
Learn about net classes and clearances Information on page 101
Learn about net properties Information on page 104
Learn about routing costs using the Editor Control dialog Information on page 135
Route Mode
Route Mode enables all semi-automatic and automatic routing functions. Route mode is also
used for placing and manipulating traces, vias, mounting holes and fiducials. All traces and vias
are manipulated within this mode.
Saving Your Work
Use the Save command periodically and especially after performing major tasks. Saving your
data protects against data loss in the event of a system crash or power outage. You should

Routing
always save your work at the completion of major steps. The Save Copy command saves a copy
of the top level layout directory (with the option to save only the essential files) to the specified
name and location.
At various stages in the design process, for example, after completing component placement or
critical routes, we suggest saving a copy of your job. You could then return to a previous
version of the design if desired. The Editor Control AutoSave interval allows you to save your
design database at regular intervals during interactive commands and during Auto Routing.
If the Auto Router exits abnormally for any reason, and an AutoSave file exists, you are
prompted to update your design from the last AutoSave the next time the application is
initialized on that job.
Routing Costs using the Editor Control
The relative cost or expense of routing a design is defined in the Editor Control - General
dialog. These parameters define the behavior during semi-automatic routing sessions: routing
effort, enabled routing layers, directional bias settings and the layer pairings for the design.
The effort setting for semi-automatic routing defines the amount of effort a command expends
on any given connection. The more effort you specify, the more time will be spent trying to
complete a connection.
The routing and directional bias settings control whether routing layers are enabled and the
directional bias for the routing layers. All layers are candidates for routing unless overridden by
this command or are layer restricted in the Net Classes and Clearances dialog. By default, plane
layers are disabled in Editor Control.
The layer bias setting for interactive routing determines the relative difficulty of routing against
the layer bias versus placing a via. The higher the direction bias the more difficult it is to place
the trace against the bias. If you select medium or low too early in the routing process, routing
channels may quickly become blocked, making routing very difficult.
The via cost and maximum vias added settings for semi-automatic routing control the maximum
number of vias allowed during routing and tuning operations and the relative cost of adding a
via to a path. The default setting, medium, works best for most designs. These settings do not
override the maximum vias per net option under Net Properties.
Layer pairs are designed to aid the interactive routing of designs. For example, if you want to
switch to a layer, you can use the space bar to add a via and because of the layer pairings you
always know which layer you are going to. If you need to go to a different layer, you can select
that layer in the Display Control menu.
You can also define which adjacent layers of the design, differential pairs should be routed on.
If no adjacent layer pairs are defined, then differential pairs are routed on the same layer.

Routing
Placement Checking
The Editor Control - Parts dialog allows you to define how the Design Rules Checker (DRC)
handles part hazards as you move and push parts. When moving parts you can limit the display
to only those netlines directly attached to the part. DRC can be set to warn you or to prevent part
hazards. If the warning option is set, part hazards are allowed, and a warning is issued when
they occur. This option does not allow metal to metal conflicts. If the preventative option is set,
no part hazards are allowed. All hazards, including metal to metal conflicts must be resolved
before placement is allowed.
Routing Rules
The Editor Control - Routes dialog contains the general design rules governing your design as
well as the controls that override settings from the Net Classes and Clearances and Net
Properties menus. These should not be confused with design clearances. In those instances
where a design becomes impossible to finish, you can use this dialog to turn off rules and finish
routing your design. Even though you have overridden a rule on a temporary basis, Expedition
PCB always reports the override as a hazard allowing you to address it at a later date, as space
becomes available.
Note
You can control the fanout of unused single pin nets by using the "Enable fanout of single
pin nets" option on this tab. By default, this option is enabled.
Router Tuning Patterns

Any high speed net that requires modification to satisfy formula or net delay constraints can be
tuned. The settings in the Editor Control’s - Tuning dialog defines the topology requirements
for these modifications.
Tuning Meter
When dyna-moving or interactively plowing nets with high speed length or delay constraints,
you can display the tuning meter on your cursor to view length statistics. The Tuning Meter
displays the current length or delay in relation to the user-defined target length/delay
constraints.
The tuning meter displays yellow when the length or delay is less than the target tolerance. The
meter turns green when the routed trace is within tolerance and is red when the range has
exceeded the tolerance. When the Display Tuning Meter option is enabled, the tuning ellipses
will not be displayed.
When the active constraint is applied to a Net, the cursor has an "N" next to the starting line. If
the constraint is on a Pin Pair, there is no additional graphic.

Routing Interactively
Design Grid
If the via, placement, route, draw and/or jumper grids are set, all traces, vias and parts are placed
on their respective grids. If the Gridless pad entry for all pads option (on the Pad Entry tab) is
selected (only active if a Route Grid is defined), traces will route gridless into pads as well as
around pads that are off the route grid. This allows better pad entry as well as being able to
route between pads when the clearances are precise.
Even though the Auto Router is a gridless router, some designs may require grid setting. The
grid origins are defined by the Board Origin command. If you are unsure where the origin is,
position the cursor at the X, Y location 0, 0. If this is incorrect, reselect the origin using the
Place Origin command.
The route grid must be a multiple of the via grid or vice versa. If the router grid is greater than
the via grid, the via grid is ignored.
The Move and Push Part commands place the selected part onto the chosen grid, but if the part
was initially placed off-grid it remains off-grid.
If you plan on using the semi-automatic editor to route traces, you may want the same grid to
make sure that traces are on-grid. This limits the capabilities of the Auto Router. Remember, the
Auto Router is a shape-based-gridless router. It works best with no grid settings.
Net Selection Filter

The Filter allows you to work with specific groups of nets or net classes by activating specific
nets and or net classes within your design.
All nets by default are in the Included field. Nets listed here are those nets that are available for
routing by the Item Select, Area Select, Plow and Auto Route commands. This listing contains
both net classes and net names for the nets. When you select a net class, all rows in that list
having the same net class name are selected. When you select a net name, the entire row,
including net class, is selected. When you need to exclude nets, move them into the Excluded
field.
The Enable Filter allows you to turn the filter on or off without changing the contents of the list.
The semi-automatic routing tools use the same rules and clearances as the automatic router, and
they offer a wide variety of features to make interactive routing easier.
Note
Before you start routing, check the Review Hazards dialog to review and fix and
placement hazards that were created during placement manipulation.

These tools are discussed in the following sections:
If you want to:

Learn about moving traces and vias Information on page 138
Learn about Hug Trace Information on page 148
Learn about Gloss Information on page 149
Learn about curved traces Information on page 153
Learn about force plow Information on page 155
Learn about route plow Information on page 156
Learn about angle plow Information on page 156
Learn about dyna-plow Information on page 156
Learn about multi-plow Information on page 157
Learn about the route command Information on page 161
Learn about interconnect modification Information on page 164
If the Shove Trace option has been selected within Editor Control, these commands route a trace
through an area by pushing and shoving existing traces and vias out of the way. Force Plow,
Route Plow, Angle Plow, Dyna-Plow and Multi-Plow are also used for placing any pre-routes
into the design. Typically on high-speed designs, there are many signals that must be pre-routed
and tuned before routing the normal signals. Once routed these traces should be fixed to prevent
accidental modifications. If a part pin has more than one netline attached to it, these commands
always choose the shortest netline to route. They automatically change the target netline if an
anchor point is placed closer to the end of one of the other netlines.
Moving Traces and Vias in Route Mode

The Move command allows you to reposition and adjust trace segments and vias. It pushes and
shoves other traces in your path. To move an item, ensure that no other command is active,
position the cursor on the item you wish to move and drag the left-mouse button.
Selecting a horizontal or vertical trace segment moves that segment horizontally or vertically,
but selecting a trace vertex allows you to move the two line segments comprising the vertex
horizontally, vertically or diagonally. A selected via, and its connected traces, can be moved in
any direction.
Trace segments containing 45 degree angles can convert to 90 degree angles, but segments
containing 90 degree angles can only convert to 45 degree angles when the Editor Control -
Routes option allowing 45 degree corner is turned on.

Note
AutoTune attempts to retune all nets that haven't been tuned optimally when the
following functions are performed: exiting plow commands, Fit View, opening either the
Editor Control or Hazards dialogs.
If you want to work interactively with any of the above functions, minimize the dialogs
so they stay open but do not activate AutoTune, or you may stay in the Plow command.
The Plow command does not start Auto Tuning. The Fit View command, used many
times while plowing, should be also used while in the Plow command.

For purposes of current carrying capacity, there is a need to use multiple vias when a route path
changes layers, connecting to another trace, an area fill or plane area. In general the number of
vias to be used will be relative to the trace width and via span.
The interactive and automatic router routines respect the multiple via objects.
Multiple via objects can be manipulated like single vias in Expedition. They can be moved with
the traces and limited support of push and shove. They can push traces and default vias,
however, they cannot be shoved.
The creation of multiple via objects occur while automatic or interactive routing is taking place.
They are created from several constraints found in the Setup Parameters > Via Clearances
dialog and while routing with or selecting a multiple via object, the action keys and popup menu
allow you to change the pattern, rotation or single via count.
Single Via Object (SVO) This is a single hole via. Before the need for multiple via objects
(MVO), single via objects were known as vias.
Completely defined SVO padstacks are used to create multiple via
objects. The term via may be exchanged with the acronym SVO.
Multiple Via Object An object that represents a pattern of single via object. The
(MVO) relation is that of the master via created with a collection of two or
more single vias.
Multiple via objects use the complete padstack of a single via,
including: Pads per layer, Thermal Relief and Anti-Pads and
Holes.
A solid copper (Conductive Shape) is used on each layer to
provide interconnect between each single via object (SVO) that
make up the multiple via object (MVO).

Principles of Multiple Via Objects

1. Multiple via objects are created from multiple copies of a single via. All single via
objects within a multiple via object are identical.
2. Legal pad shapes within a single via are square, round and octagon.
3. Multiple via objects consist of two to twenty-one single vias:
Via Count Pattern (Row X Column)

2 1x2
3 1x3
4 1 x 4, 2 x 2
5 1x5
6 1 x 6, 2 x 3
8 2x4
9 3x3
10 2x5
12 2 x 6, 3 x 4
15 3x5
16 4x4
18 3x6
20 4x5
21 3x7
4. All automatically created multiple via objects patterns are symmetrical.

5. Multiple via objects are treated as a single entity by automatic and interactive routing
manipulations.
6. The connectivity point for multiple via objects is the center of the multiple via object.
7. Multiple via objects are created at 0 degree rotation.
8. The center point of the lower left single via at zero degree rotation will snap to the via
grid. This will not apply to a multiple via under pad and special multiple via objects used
for BGA fanouts.
9. Multiple via objects rotation will orbit about the connectivity origin.
10. Multiple via objects can be rotated interactively or automatically in 45 degree
increments.

11. Pad entry rules apply to multiple via objects, avoiding acute angles where possible.
12. Hazards are updated to show acute angle trace entry into multiple via objects.
13. All same net, via to via clearance options apply between multiple via objects and other
vias.
14. Same net, via to via clearances are used to create multiple via objects.
15. Before placement of a multiple via object the interactive override exists for via count,
size, pattern and rotation.
16. Multiple via objects can have their rotation, pattern or single via count changed
interactively; after they have been placed.
17. Multiple via objects offer coupling with other multiple via objects and single vias
through the Same Net, via to via clearances.
18. Via in pad options are provided for the multiple via objects in rectangular, oblong and
square pads. This requirement applies only to Automatic Routing
19. Via in pad options are provide for BGA and CSP packages using two count multiple via
objects.
20. Same net, multiple via objects to multiple via objects, multiple via objects to via and
multiple via objects to SMD pin pad fillets occur when the multiple via object's
clearance is less than the user-defined input clearance established with the option to
modify the clearance.
21. For outputs, a multiple via object is represented as the individual vias and large pad that
creates the multiple via objects.
22. Multiple via objects' hole sizes, layers and locations is available in Expedition drill
outputs.
Affected Commands
The following table represents the pulldown commands that are affected by multiple via
objects. The Remap Layers functionality automatically creates multiple via object pads on new
layers added by the command.
File > Save Any designs that are saved containing multiple via objects
cannot be opened in earlier versions of the 2005.2
software.
File > Export Treats multiple via objects as single vias and planes.

File Export > ASCII The LayoutDB.hkp file has changes reflecting multiple via
objects. Exported databases cannot be imported in earlier
versions of the 2005.2 software.
File > Split Design TeamPCB is updated to support multiple via obstructs.
File > Join Design
Edit > Undo / Redo Complete support for Undo and Redo.
Edit > Add to Select Set > Multiple via object teardrops are created only between
Teardrops multiple via objects and other object pads that are directly
connected by a trace. When a teardrop is added for a
multiple via object pad the trace attached to the multiple
via object trace is modified to ensure that the out of pad
portion of the trace is completely covered with the teardrop
shape.
Edit > Add to Select Set > Fix For Fixed and Unfixed Vias commands, multiple via
Vias / Unfix Vias objects are included with vias and these commands also
address multiple via objects.
Edit > Add to Select Set > For Locked and Unlocked Vias commands, multiple via
Lock Vias / Unlock Vias objects are included with vias and these commands also
address multiple via objects.
Edit > Find Supports the same level of select and highlight as
associated with vias.
Edit > Review > Design Status Design Status includes the single via count in the via count
section.
Edit > Review > Hazards The Multiple Via Pad Entry hazard is created for problems
with multiple via objects
Edit > Review > Minimum Multiple via objects are supported.
Distance
Edit > Review > Padstack Opens the Multiple Via Objects dialog for the selected
multiple via objects.
Edit > Place > Via Uses multiple via objects when multiple via objects are
required instead of single vias.
Edit > Modify > Padstack The Padstack Processing option is enhanced to support
Processor multiple via objects; the single via placement does not
change. The support includes the identification of multiple
via objects for padstack replacements of single vias. The
multiple via object pad is resized to accommodate the
modified single vias.
Edit > Fix and Lock Supported.
Commands

Edit > Highlight commands Supported.

Edit > Delete Commands Delete and Delete All Traces and Vias support multiple via
objects.
Edit > Properties Properties of the multiple via object display in the Padstack
Properties dialog.
Setup > Cell Editor Multiple via objects are not allowed in cells and multiple
via objects functionality is not supported in Cell Editor.
Setup > Setup Parameters Settings in Setup Parameters influence the placement of
single vias and the size of multiple via objects.
The creation of multiple via objects are dependent on the
Same Net, Via to Via clearance for their layer range. This
value is used to locate single vias in relationship to each
other within the multiple via object pattern.
For staggering multiple via objects through different layer
ranges, the Same Net values are used to stagger multiple
via objects to other multiple via objects or single vias on
different layer ranges. Via patterns supporting buildup
layers and microvias use the efficient pattern to span
several layer sets.
Setup > Editor Control The Editor Control > General tab has several influences
over the routing of multiple via objects.
Setup > Net Classes and Via and pad clearances set in Net Classes and Clearances
Clearances are applied to multiple via objects.
Setup > Net Properties The Net Properties > Other tab references Max Vias. This
value, if used, represents a multiple via object as a single
count.
Place > Move Circuit / Copy Multiple via objects are not supported for Copy Circuit or
Circuit Move Circuit with any angle rotations; only multiple via
objects with rotations at 45 and 90 degree increments are
supported.
Route> Interactive and Auto Both Interactive and Auto Route commands support
Active Routing multiple via objects.
Copy Trace - Handles multiple via objects as regular vias.
Push Trace - Allows multiple via objects insertion when
via or multiple via objects insertion is required to move a
portion of a trace to another layer.
Gloss - Multiple via objects can be rotated.

Route > Teardrops and Multiple via object teardrops are created only between
Breakout Traces > Teardrops/ multiple via objects and other object pads that are directly
Dynamic Teardrops connected by a trace. When a teardrop is added for a
multiple via object pad the trace attached to the multiple
via object trace is modified to ensure that the out of pad
portion of the trace is completely covered with the teardrop
shape.
Route > Change Width This command will not change existing multiple via
objects. However, a hazard that addresses this difference if
there should be a new or different multiple via object is
available.
Route > Remove Hanger Multiple via objects are treated as regular vias.
Route > Delete all Traces and Multiple via objects are supported.
Vias
Planes > Plane Classes Multiple via objects connect to planes by multiple via
Parameters object pads represented by conductive shapes with no tie
legs or thermal reliefs.
Internally, the multiple via object in a pad is a conductive
shape and is automatically generated on each electrical
layer where the single vias have pads. Even though it is
represented as a conductive shape it acts as a pad in terms
of pad entry rules. The multiple via object pad corners are
always chamfered (45 degrees) for round single via pads. If
a square single via is used, the multiple via object pad
displays 90 degree corners.
Analysis > DRC Window and For Design Rule Checking (DRC) of non-same net objects,
Batch DRC the following applies to multiple via objects. Interactive
DRC for multiple via objects use the Via clearances found
in Net Classes and Clearances.
A conductive shape covers all the single vias in an multiple
via object and is the metal shape used for DRC.
Individual single via pads are also used for DRC and these
use the clearances applied per netclass, which include:
• Via to Via
• Via to Trace
• Via to Pad
• Trace to Trace
• Trace to Pad
Batch DRC uses the same clearance definitions as
Interactive DRC.

Analysis > Review Hazards The Multiple Via Pad Entry hazard is created for problems
with multiple via objects.
Output > Design Status Includes the single via count in the via count section of the
file.
Output > Gerber Multiple via objects Gerber out the same as vias and plane
conductive shapes.
The Padstack Processing option is enhanced to support
multiple via objects; the single via placement does not
change. The support includes the identification of multiple
via objects for padstack replacements of single vias. The
multiple via object pad is resized to accommodate the
modified single vias.
Output > NC Drill NC Drill outputs each single via. The Padstack Processing
option is enhanced to support multiple via objects; the
single via placement does not change. The support includes
the identification of multiple via objects for padstack
replacements of single vias. The multiple via object pad is
resized to accommodate the modified single vias.
Unsupported Items with Multiple Via Objects

The following are not supported in this first release.
• Multiple via objects are not supported for Copy Circuit or Move Circuit with any angle
rotations; only 45 or 90 degree increments are supported.
• Multiple via objects are not supported in CES. An ASCII file format is used to specify
multiple via object assignment rules.
• Expedition PCB (DFL Mode) (Destination PCB) does not support multiple via objects.
• MultiPlow does not support multiple via objects.
• Differential Pairs does not support multiple via objects.
• Multiple via objects capability is not supported in the Cell Editor.
• Reusable Blocks does not support multiple via objects.
• Editing multiple via objects. A multiple via object is always selected as an entire object.
There is no way to select or query an individual single via while it is part of the multiple
via object unless you use the Dissolve MVO command that converts multiple via object
into a collection of individual vias and conductive shapes.

ASCII File Format

The following is an example of the ASCII file format used to specify multiple via object
assignment rules. Once this file has been defined the rules are loaded into AutoActive upon
launch. The file is located in the job's ../xe/config directory.
MVO Rules file name: MultiViaRules.txt

MVO Rules file location: ../xe/config
MVO Rules file format: mimics the NetClassDB.hkp format
.FILETYPE MULTIVIA_RULES
.VERSION "03.02"
.CREATOR "Mentor Graphics Corporation"
.DATE <date and time file was created>
.UNITS TH
.PHYSICAL_LAYERS <n>
The value must match the physical layer count defined in the design.
.MVO_RULE_SET "(Default)"
The value can be "(Default)" or a user-defined rule set name; example "My_MVO_Rule".
..VIASPAN
Via span definition for this MVO rule set.
...LAYER_NUM_RANGE (<n>,<n>)
The value is the via-span range i.e. “(1,8)” that the MVO is based upon as defined in
Setup
Parameters>Via Definitions tab.
...PADSTACK "(Default Via)"
Via padstack for this span; “(Default Via)” means use via span defined in Job Preferences
...MVO_RULE
MVOrule defined for the via span.
....WIDTH_EQUAL_OR_GREATER <n>
The value is a trace width as per the defined units. The MVO rule applies to the trace
widths equal or greater than the defined value.
....VIA_COUNT <n>
The value is the number of vias required to build the MVO for the given trace width
range.
.NET_CLASS_SCHEME "(Master)"
The value is “(Master)”, “(Minimum)” net class scheme or user rule scheme name as
defined in CES.
..NET_CLASS "(Default)"
The value is “(Default)”, or available net class name that uses the following MVO rule set.
...USE_MVO_RULE_SET "(Default)"
The value is “(Default)” for default MVO definition or user defined MVO rule set name,
example; “My_MVO_Rule”.

Example File
.FILETYPE MULTIVIA_RULES
.VERSION "03.02"
.CREATOR "Mentor Graphics Corporation"
.DATE "Wednesday, April 27, 2005 04:33 PM"
.UNITS TH
.PHYSICAL_LAYERS 4
.MVO_RULE_SET "MyMvoRuleSet"
..VIASPAN
...LAYER_NUM_RANGE (1,2)
...MVO_RULE
....WIDTH_EQUAL_OR_GREATER 0.150
....VIA_COUNT 2
...MVO_RULE
....VIA_COUNT 3
..VIASPAN
...MVO_RULE
....VIA_COUNT 2
...MVO_RULE
....VIA_COUNT 3
...MVO_RULE
....VIA_COUNT 4
.MVO_RULE_SET "MvoRulesForPowerGroundNets"
..VIASPAN
...MVO_RULE
....VIA_COUNT 3
...MVO_RULE
....VIA_COUNT 4
...MVO_RULE
....VIA_COUNT 6

.NET_CLASS_SCHEME "(Master)"
..NET_CLASS "(Default)"
...USE_MVO_RULE_SET "MyMvoRuleSet"
.NET_CLASS_SCHEME "MyScheme"
..NET_CLASS "FREEsym402-3"
...USE_MVO_RULE_SET "MvoRulesForPowerGroundNets"
..NET_CLASS "TRUEsym1634"
Hug Traces
This command provides you with the ability to select an un-routed net and have it hug an
existing routed trace or specified draw objects in the design. The net to be hugged can be an
entire net routed between two pins or a portion of a routed net. The un-routed net will route
adjacent using the Trace to Trace clearance and typical trace widths defined in Net Classes and
Clearances to the routed net, including curves, bends, angles and other trace anomalies.
Specifying a Hug clearance

When hugging draw items you can specify a hug clearance other than is defined for the net by
using the htc keyin and specifying a clearance. All htc entries are listed in the right mouse click
pop-up menu for quick selection.
Note
The htc keyin and the hugging of draw objects are only available with a valid Flex
license.
Hug trace will only operate on continuous trace segments, which have no junctions, vias or pins
within the segments being hugged. The following criteria prevents traces from routing using the
hug trace command:
• Traces which include vias in the selected span.

• Traces which include T-junctions in the selected span.
• Trace segments that include pins, testpoints, or any other objects making connections
within the selected span.
Hug trace will automatically push and shove vias/traces of nets which are in the way of the trace
being hugged. However hug trace will not alter the trace that is being hugged. If a segment is
selected with this criteria, an error message appears in the far right message field.

When in the command you can change the clearance by selecting them from the popup that
displays when you right-mouse click. The default clearance is named Variable. Values are only
stored for the current design session. When the design is exited the input values will be
discarded.
Hug trace portions

In the event a portion of a trace is selected to hug based on a selection of a start or end point on
the trace itself, a netline will appear from the hug trace endpoints to the un-routed pin locations.
This will only occur only if the "Netlines from Traces" checkbox is selected within the Display
Control dialog. If this option is not checked, the trace will hang in space with no netline. When
trace hangers are placed by Hug Trace, these traces will be automatically semi-fixed to ensure
that when they are connected using plow they are not glossed, causing the hugged trace to no
longer hug the target trace.
Glossing Principles
The focus of these glossing principles is to clearly define the behavior while Gloss is off and the
behavior of semi-fixed traces. The original purpose of Gloss was to automatically clean-up
traces so they were the shortest possible length and to eliminate undesirable geometries such as
acute angles, undesirable pad entries, extra segments and self-net oddities. Over time we found
that modifications were needed so designers could add and edit traces in specific user-
determined locations without Gloss (or Push & Shove) affecting them. This is especially
desirable when crafting RF circuits or adding or editing meanders to control the delay of a path.
There are multiple Gloss modes and multiple Fix states for traces. The combination of the
modes and states allow for a very flexible environment where the designer can control every
vertex or rely completely on automatic glossing.
Gloss Modes
• Gloss On – A full Gloss is applied to any trace (and net) added, edited or shoved.
• Gloss Partial – A mild glossing is applied to the currently added trace.
• Gloss Off – The currently edited or added trace is not glossed.
• Fix States (Via behavior is not mentioned here but it is the same as traces)
• Unfixed – Trace may be modified by any interactive or automatic means.
• Semi-Fixed – Trace may be modified interactively, but not by any automatic routines.
• Fixed – Trace may not be modified by any interactive or automatic means. Fixed traces
may become unfixed by using Unfixed.
• Locked – Trace may not be modified by any interactive or automatic means, not even
Unfix. Locked traces may become unfixed by using Unlock.

Note
Some routines have options to “Apply to Fixed and Locked Traces” but you must choose
that option.
Guiding Principles
1. If Gloss mode is off, nothing is glossed or shoved.
This does not count for Auto Route because it ignores Gloss modes.
2. If a trace segment is semi-fixed, automatic modifications are not applied.
Includes all Gloss modes.
Includes Auto Route.
3. If a trace is semi-fixed, any editing, in all Gloss modes, keeps the trace semi-fixed.
If while modifying the semi-fixed trace, a new segment is added, it is added as semi-
fixed in all gloss modes.
If a path has an unfixed trace segment attached to a semi-fixed trace, any modification to
the unfixed trace does not change the state of the semi-fixed trace.
4. If Gloss mode is partial, only the trace segments added from the previous click are to be
partially glossed.
There are some situations where rules 3 and 4 may not apply, but for the majority of scenarios,
the functionality works as stated.
Glossing Possibilities
This table defines what is allowed and not allowed during the different glossing modes.
Table 3-2. Glossing Possibilities

Gloss On Gloss Partial Gloss Off
Move Trace Possible?
Unfixed Segment Yes Yes Yes
Semi-Fixed Segment Yes Yes Yes
Fixed Segment No No No
Locked Segment No No No
Shove Trace Possible?
Unfixed Segment Yes Yes No
Semi-Fixed Segment No No No


Trace Added Becomes…
AutoActive Unfixed Unfixed Semi-Fixed
Interactive Unfixed Unfixed Semi-Fixed
Trace Added to Semi-Fixed Trace Becomes…
AutoActive Unfixed Unfixed Semi-Fixed
Interactive Unfixed Unfixed Semi-Fixed
Join Traces Segments Possible?
Unfixed & Unfixed Yes Yes Yes
Unfixed & Semi-Fixed No No No
Unfixed & Fixed No No No
Unfixed & Locked No No No
Delete Trace Possible?
Gloss Trace Possible?
Tune Possible?
Copy Trace Possible?

Semi-Automatic Routing

Fixed Segment Yes Yes Yes
ReRoute Possible?
Push Trace Possible?
Copy Circuit Possible?
Locked Segment Yes Yes Yes
Move Circuit Possible?
Locked Segment Yes Yes Yes
Semi-Automatic routing is made up of commands that allow you to fanout pins, route individual
traces, and multiple traces. The routing of individual traces is done using the plow command.
The plow command is broken up into Forced Plow, Route Plow and Angle Plow.
By default, the Plow commands use Gloss on all of its completed traces. Gloss changes the
entry into rectangular and round pads and gets rid of excessive bends in traces. The idea behind
this algorithm is to allow the router more room for routing. If a channel can be left open by a
slightly different exit, the push and shove routing algorithm has less work to do and the system
works faster. If you need to put a trace into the design, using a special pattern or a user-defined

trace, the Gloss mode must be toggled off. Gloss does have different settings that define how far
back on a trace gloss will operate.
If you are leaving hangers intentionally, do not use the Remove Hanger command. Use the right
mouse button to exit the Plow command and leave the hanger. The Plow command can delete
hangers on other nets. If you intend to keep the hangers, they must be fixed before re-entering
the Plow command.
You can now select anywhere on the netline in order to start plowing as opposed to only being
able to select on the pin.
You can use the Tab key to change the destination pin of the current plow if you choose a
netline for a MST ordered net and there are multiple pins of the same net.
The F8 action key (Switch End) allows you to switch to the other end of the selected netline
when plowing.
Clicking the right mouse button in graphics displays a popup menu which allows you to change
widths and via sizes.
If you are routing a trace and you want to rip up existing trace segments and try again, this can
be accomplished in the following ways:
• Use the Undo command to remove the last trace segment or via.
• Use the Delete command to remove the whole trace path.
• Select a point on the path to remove everything between the current point and the
selected point.
These methods work for all plow modes.
Curved Traces
The ability to create concentric arc's using curved traces is only available within the route
environment while in Angle or Forced Plow. Within Multi-Plow curved traces only have
variable or flexible radius’. The F10 action key allows you to toggle the traces around a
common center point while in Plow mode.
You can set the radius of the curves in the Editor Control General Tab for Angle or Forced
Plow. Any defined radius specified in Editor Control is overridden while in Multi-Plow.
The radius of the curves can then be selected when using the command from the popup that
displays with a mouse right-click. If "Variable" is selected, the methodology reverts back to a
defined curve using the cursor. Values are only stored for the current design session. When the
design is exited the input values are discarded.

Once placed, curved traces can be modified. By selecting and holding the center of the arc, you
can dynamove the arc, which changes the radius.
As the cursor is moved, the dynamic curve exactly represents the actual trace, as if the current
cursor point location was the selected anchor point. If an anchor point is selected in a location
where clearance violations will occur, the push and shove algorithm is called to relocate the
violating elements.
You can also use the Route - Modify Corners command and convert the selected (or all) curved
traces to orthogonal corners.
Example for routing curved traces

1. Select Multi-Plow, Angle Plow or Forced Plow and start routing a trace.
2. Place an anchor point (optional, curved traces can start from a pad or via).
3. Select the F10 action key to curve the trace.
4. Stretch the trace to the desired location and select another anchor point.
Upon placing an anchor point the curved trace is placed and the route remains in curve
trace mode until you either select Toggle Curve (F10) or terminate the route.
Moving Trace Segments with Arcs

Single trace segments connected to arcs on both ends may be moved. The arcs remain the same
and the vertical traces extend to compensate for the movement of the trace segment.
Curve trace end point rules

Curve traces can end on:
• Pins/pads (Avoid creating acute angles)

• Trace endpoints
• Via
• In space (creating a hanger)
When the second point is selected (creating the arc) you can either continue placing curved
traces or toggle back to regular plow mode. Selecting cancel from the right mouse button pop-
up menu, or selecting the ESC key will cancel the curve trace command. Selecting ESC will
deselect the net being routed and return you to Plow mode.

Curve center point modification

The center of the curved trace can be selected for modification. The center modification point
works as arc modification does in Draw mode. The radius changes force the trace connection
points to adjust while the arc is being modified.
Cases and exceptions

• Curve traces may be started from any trace point, pad or via, and at any angle including
existing curved traces.
• Curve trace is only selectable from a trace endpoint or pad (sensitized / desensitized)
• T-junctions or virtual pins are not legitimate sites for curved trace.
• Curved traces stay tangent (while in dynamics) to the selected trace.
• In order to maintain pad entry rules, the arc is not allowed to intersect the pad geometry.
If it is not avoidable, a corner rather than an arc is produced.
• The minimum radius for a selected trace is radius > 2X the trace width. If a specified
radius is to small to allow proper placement of a curved trace an error message displays
in the Status bar.
Forced Plow
This is the default state when you select the Plow command. When in Forced Plow mode, the
prospective trace displays as a hockey stick and flows around any obstacles or pads as anchor
points are placed. As the trace flows around obstacles, Gloss will automatically cleanup any
jags that are created.
As you move the cursor over a pad or an existing trace or via, you will notice that a temporary
netline has appeared from the cursor position to the closest point on that net. There is one
exception: if you have defined the netlines as being custom or chained, you are only able to
route in the order defined by the netlines.
As you move the cursor around the screen, you will notice the hockey stick dynamically
changing shape and following the cursor. If you now click the mouse button, Expedition PCB
attempts to place a trace that corresponds to the hockey stick from the starting point to this new
location called the anchor point. An anchor point is the transitioning point between a trace
segment(s) that has been plowed and the next trace segment(s) to be plowed. This point is
typically a vertex on the trace.
This operation does not use vias to make the connection, but if the hockey stick goes over pads
or mounting holes you will notice that the trace added to the design has gone around those
items. You can now continue to the next anchor point or finishing point. If desired, the trace can
be left as a hanger.

Dyna-Plow
The Dyna-Plow command is similar to Forced-Plow except that you are continually laying
traces into your design when using Dyna-Plow. To use the Dyna-Plow command, activate the
Plow command and drag the left mouse button. You will notice that the hockey stick has now
turned from a ghost trace to a solid trace. As you move the cursor, the trace is automatically
added to the design. Once the mouse button is released, that position becomes the new anchor
point.
As you route over obstacles, the trace attempts to bend around them. If the trace cannot route
around these obstacles, the Plow command restores to the last known good position. If an
existing trace or via becomes an obstacle, Expedition PCB attempts to push that trace or via out
of the way. Remember the Plow command cannot move fixed items. As with any PCB design,
the level of pushing that can be accomplished depends on the amount of free space in the
design.
Route Plow
You can change from the default mode, Forced Plow, by activating the Toggle Plow Mode
action key. This puts you in Route Plow mode. The system tries to automatically route from the
starting point (or last anchor point) to the new anchor point (or finishing point on a pad, via or
trace). This command is governed by the settings in the Editor Control menus. This method of
routing traces is the only Plow command that automatically uses vias during the Plow
procedure.
After you have plowed the trace and are close to the target pad, or are through a difficult area,
you can finish the trace by adding the last anchor point on a part pad, trace or via. The trace
being plowed automatically attaches to that point and you are now ready to begin the next plow
trace. You can also use the Auto Finish action key. The Plow command automatically routes to
the closest point on the net being routed. This can be a trace segment, via or another part pad.
Angle Plow
You can change from the default mode, Forced Plow, by activating the Toggle Plow Mode
action key. This puts you in Angle Plow mode.
When in Angle-Plow mode, the prospective trace displays as a Route-Plow netline and is routed
from the last anchor point or start point to the target location.
If you click in the target point, the Angle-Plow command tries to route to that point (called the
plow-anchor point). If there are any violations or it is unable to reach that target point, the trace
is not displayed.
In Angle-Plow mode, a via is added to the last anchor point or near the last anchor point if it
does not match the via grid. If you accidentally added a via, use the Undo command to delete it
and change back to the old layer.

Multi-Plow
Multi-Plow is the default Plow command and allows you to select multiple interconnects and
route them simultaneously. The display in Plow is very similar to the display in Forced Plow
and Dyna-Plow. The prospective traces display as “ghost traces” in these commands, but since
the Multi-Plow command is dealing with multiple traces, a reference line accompanies the
prospective traces.
The reference line operates as a guide or baseline for the Plow command. As you route using
Plow, it changes position to that area within your group that is driving placement. Occasionally
the Plow command is unable to place the reference line, because it cannot determine the drive
position. In this situation, the prospective traces disappear and a box surrounds this area of
ambiguity.
If you have a valid Flex license, you can use the curved traces functionality within Multi-Plow.
Curved traces are variable or flexible radius only. The defined trace clearance, or selected
convergence affects the radius for each trace selected. Any defined radius specified in Editor
Control is overridden while in Plow. See Curved Traces for further information.
Plow curved traces only have variable or flexible radius’. The defined trace clearance, or
selected convergence affects the radius for each trace selected.
• Any defined radius specified in Editor Control is overridden while in multi-plow

• All traces start at the same bisector (start point across a horizontal line for instance) and
end at the same bisector (vertical line for instance)
• Each trace has a different radius but start and stop along the same line
• Traces start and stop around a common center point
• Selection is the same as with single curve trace selection
Once placed, curved traces can be modified. By selecting and holding the center of the arc, you
can dynamove the arc, which changes the radius. As the cursor is moved, the dynamic curve
exactly represents the actual trace, as if the current cursor point location was the selected anchor
point. If an anchor point is selected in a location where clearance violations will occur, the push
and shove algorithm is called to relocate the violating elements.
You can also use the Route - Modify Corners command and convert the selected (or all) curved
traces to orthogonal corners.
1. Select Plow and start routing.

2. Select curved traces (F10).
3. Traces curve from the last point placed and curve around a common center point.

4. Select an end point.
Figure 3-24. Curved Trace in Multi-Plow
Upon placing an anchor point the curved trace is placed and the route remains in curve trace
mode until you either select Toggle Curve (F10) or terminate the route. The following example
shows a curved trace extending from an existing curved trace.
Figure 3-25. Curved Trace Extending from a Curved Trace
Since the Plow command works with multiple traces, via patterns are used to add vias to your
design. As with all other Plow commands vias are added at the last anchor point and the vias are
dropped through to the paired layer, but instead of a single via, multiple vias are placed in the
design in either a parallel, staggered or diagonal pattern. Click the right mouse button in
graphics to display a popup menu that allows you to change via sizes.
Via Patterns
The actual via pattern varies as you move your cursor. One dynamic pattern is illustrated in the
following sequence:
1. Display the via pattern, then drag the cursor to the right; the pattern changes.
2. Continue dragging. The resulting pattern is a flipped version of the starting pattern.

Figure 3-26. Via Patterns Examples
Press the Toggle Via function key to access other patterns that can also be dynamically
modified by cursor movement. An example of one pattern is shown below:
<Alt> Auto-Finish Preview

When you are getting close to your target pins while in Plow, you can hold down the Alt key to
get a ghosted image of what the Plow path would be if you completed the path. The following
pictures show the normal Plow graphic.
Figure 3-27. Auto Finish Examples

Leaving the cursor in the same position and pressing the Alt key results in:
Hold the Alt key down while you move your cursor. This gives you control of the pattern that
Alt Auto-Finish will create. Notice in the following picture that the pattern has changed as the
cursor has been moved to the left.
When you see the pattern you want, click the left mouse button. The connection will be made in
the pattern seen in Preview mode.
New via patterns and modification commands are available to help you quickly determine the
via placement option that best fits the design situation. The use of quick keys enables you to
quickly preview and determine what effect the different via pattern will have on the design. The
Alt - Auto Shift feature gives you greater control over the final topology of a multi-plowed
connector.

Route
Route
Route allows you to automatically route selected connection(s) using the parameters set up in
the Editor Control > General tab. The route command should not be confused with the Auto
Router. It is intended to be used for semi-automatic routing of critical nets. Typically this
command can be used to route easy, straightforward connections between pins or to create
routing, that can be adjusted manually.
If you want to:

Learn about handling planes Information on page 161
Learn about changing layers and adding vias Information on page 162
Planes Handling
Traces may be routed on layers reserved for planes. To route a net on a plane layer, disable any
net class restrictions for that layer and enable the layer, for routing, in Editor Control. Plane
shapes on a signal layer can be placed as obstruct areas and cannot be routed through. This is an
option when placing the shape.
Netlines are generated between pins and plane shapes to remind you of the connection. If there
are no plane shapes, unconnected pins in plane nets are signified by a large 'X' through the pin.
Nets with plane layers or plane shapes defined can only be designated as Free ordered.
When a plane net pin is fanned out, a via is dropped to the plane's layer using the shortest
possible via. If the layer is defined as a plane, the connection is considered complete. If the
target is a plane shape and the via does not land within the shape, the fanout via is left for a
routing pass to complete.
To perform calculations of the velocity of propagation (Vp) and characteristic impedance (Z0)
of a trace, at least one plane layer must be defined. Calculations may be performed on traces on
plane layers. Violations created by trace and via intersections with different-net planes can be
cleared upon exit.
Fanout
For SMD parts, fanouts with vias need to be created to allow connections to other layers. While
the router can place vias to complete connections, it is best to place all fanouts initially to assure
that preceding routes don't block future fanouts. Fanouts can be completed by this command, by
Auto Route, or by purely interactive routing of a trace and via.
By adjusting the via grid, you will get different fanout result. Start with the via grid
recommended by your manufacturing vendor and if this causes poor route completion, due to
blocked channels, consider the acceptability of a larger via grid or routing without a via grid.

Route
For signal nets, the fanout command uses the shortest via possible to reach the closest valid
signal layer (as defined in Net Classes and Clearances and Editor Control > Pad Entry).
For plane nets, Fanout uses the shortest via possible to reach the plane layer. Since planes do not
always cover the entire layer, a connection is complete only if a via is placed inside the plane. In
those instances where the via is left dangling, it must be connected to the plane during the
routing process. If an SMD pad is inside a plane shape of the same net, it is considered
connected.
Even when the connection is made during the fanout operation, you can later push the via and/or
trace, either manually or automatically, and maintain the connection.
Interactively, BGAs may be fanned out in a user-defined pattern, however, using the Fanout
command as well as Auto Route, BGAs are fanned out using the courtyard pattern.
Changing the Active Layers and Adding Vias

As you route using any of the Plow commands, a circle surrounds the trace at its last anchor
point if it is a valid via site. The following methods can be used to add a via and change layers
and are identical for the Forced Plow, Multi-Plow, Route Plow, Dyna-Plow and Angle Plow
commands. Exceptions regarding Multi-Plow are noted. Only those vias defined in the Setup
Parameters - Via Spans Definitions section are used. The active layer changes to its paired
(alternate) layer, and the graphics package automatically brings the new active layer to the top
of the display. (The active layer’s paired layer is defined in the Editor Control menu.)
Vias can be dropped under SMD pads based on the Editor Control via under pad settings. As
you plow out of an SMD pad, you can plow within the pad itself to a location where you want to
place the via and at this location, you can use any of the methods of changing layers to place the
via.
Adding Vias with the Add Via Action Key (Multi-Plow only)
Once you have completed a trace to an anchor point, you can add a via with the Add Via action
key, this will display the vias in a ghost image, allowing you to change the toggle via mode or
place another anchor point.
You can use the popup menu (accessed by clicking the right mouse button) to change the width
and name of the next via to be used on selected layers.
Adding Vias With the Space Bar

Once you have completed a trace to an anchor point, you can add a via by pressing the space
bar.
You can use the popup menu (accessed by clicking the right mouse button) to change the width,
layer and name of the next via.

Route
Adding Vias Using the Display Control Menu

If the Display Control menu is active, note that the active layer is always highlighted, when you
add a via it automatically changes to the active layer’s paired layer. This way you can track your
location in the design layer stack.
Activate the Display Control − Layers dialog (if it is not already active), and after plowing to the
desired location in your design you can add a via by clicking on the destination layer in the
Display Control − Layers dialog. You can also use the Up and Down arrow keys to select the
destination layer.
The layer highlights, and a via is added to the current anchor point. If the system can not add a
via, the active layer resorts back to the last used layer. If you are in a very complex area, it is not
always possible to add vias because of blockages by traces or other vias. Using this method
proves more successful when finishing a complex design.
Adding Vias with the arrow keys

Once you have completed a trace to an anchor point, you can add a via by pressing the up or
down arrow keys. The arrow keys scroll you through the available routing layers.
Adding Vias by Double-Clicking (All Plow commands except

Multi-Plow)
Once you have completed a trace to an anchor point, you can add a via by double-clicking.
Note
In order to add vias by double-clicking, you must have the double-click to add via option
in Editor Control's General menu turned on.
Blind and Buried Vias

If you are working with blind and buried vias, the shortest via that reaches from the current
layer to the target layer is used.
Note
To move a blind or buried via: select the via and any routing layer within the via span
except the part pad's layer and drag your cursor to activate the Move command. Once the
selected via is positioned correctly, release your mouse button.

Interconnect Modification
In all cases, the via is added at the closest via grid point to the current anchor point.
Staggered Vias (Forced Plow commands only)

Within Plow, after you have placed an anchor point, pressing the Shift key and right mouse
button, displays a popup menu listing target layers. This popup allows you to pick the layer on
which to place the staggered via. If a layer has "Restricted" next to it but is selectable, this is
because routing has been not allowed in the Net Classes and Clearances dialog for that net class.
Figure 3-28. Plow Popup
If a layer is selected as disabled for routing in Editor Control, that layer is grayed out on the
staggered via dialog and shows “Restricted”.
If a plane layer is defined on a layer and you select that layer from the popup, staggered vias are
only added to the nearest layer and you are automatically cancelled out of plow.
Expedition PCB offers a variety of editing commands to aid you in those situations where you
must complete a complex board that does not route to 100% or attempt an engineering change
order.
If you want to:

Learn about buses Information on page 165
Learn about target areas Information on page 168
Learn about copying traces Information on page 174
Learn about changing a trace width Information on page 175
Learn about the reroute command Information on page 175
Learn about removing hangers Information on page 175

Working with Buses

In the context of PCB layout, a bus is a grouping of nets (not pin pairs because they are grouped
by net name) with a bus name as defined in CES or the schematic. Typically the nets in a bus
have a common net name prefix and a sequentially numbered suffix, although you may choose
to combine a set of nets in a bus simply because they are to be routed using the bus path and bus
router methodology.
The bus path physically represents the width of the traces and their clearances and any shielding
traces and their clearances. You can change the bus packing to be different from the setting for
the overall bus per bus segment. While the bus path dialog is open, you can select the
Recalculation (F4) button to change the bus path segments widths to represent the actual
number of netlines associated to the bus path segment.
The bus path is the designated locations for a bus’ traces to be routed. Bus path supports
branching and splitting of the bus. Depending on the setting for bus packing, the path is
followed with packed or unpacked trace packing. Graphically, the line displays P for packed
bus path segments and U for unpacked path segments. Bus paths also include the identification
of a shielding net and the number of shielding traces.
As a bus is selected, the component pins and netlines (if displayed) of that bus are highlighted
for the placed components. You can then select the desired layer and draw horizontal, vertical
or 45 degree increment lines.
The bus router routes groups of nets together without layer bias with the intent of emulating
manual routing techniques.
The packing density of traces and vias in a bus path segment up to component pin convergence
points. There are two levels of packing:
• Packed (1): Bus traces stay together as much as possible and the minimum trace to trace
and trace to vias clearance is used throughout the bus.
• Unpacked (2): Ignore bus packing, minimum trace to trace clearances between bus
traces are not preferred, however, layer assignments (non-bias routing) are followed
along with bus path. This applies to all defined buses which do not have a defined bus
path.
These values are assigned to specific bus path segments with a default value of Packed per bus
path segment. In the bus path dialog, the value can be changed from packed to unpacked as
segments are placed or selected. Additionally, through a design setup variable, the default value
can be changed to unpacked.
Two hazards are generated if required; Review Hazards > Online > Bus Netline Span and Bus
Spacing.

Recalculation
Recalculation can be run when the Bus Path dialog is displayed by selecting the Recalculation
(F4) action key. If a bus path segment is selected, recalculation adjusts the width of all the
selected segments. If no bus paths are selected and the Bus Path dialog is displayed,
recalculation occurs on all buses.
Tip: The Recalculation button on the Review Hazards > Online Bus Hazards dialogs,
works exactly the same as the Recalculation (F4) action key.
There are other actions in the design process, beside bus path placement that may require
recalculation to run against all bus path segments in order to present accurate bus path segment
widths.
• Pin/Gate Swaps
• Netlist Changes
• Components moved or rotated
Bus Routing and Bus Online Hazards are dependent on accurate bus path segment widths.
Therefore, as netlines are calculated, bus width recalculation will run if bus path segments are
present in the database and the Bus Path dialog is not displayed.
Bus Routing
The Auto Route Bus pass takes the bus path and turns them into flowing bus traces. Buses
without bus paths are routed with existing route passes like Route. Apart from Tune, other route
passes ignore buses with defined bus paths.
The Bus Route will follow any defined bus paths with the following capabilities:
• Maintaining the notion of a bus so that interactive and automatic modification of the
nets in a bus have knowledge of the bus rules.
• Routing with the defined rules for the bus, such as clearance and width rules, via rules,
layer rules, and appropriate rules related to signal integrity.
• Routing without layer bias.
• Intelligent fanout with or without vias which untwists netlines and fanout from
component pins in the direction of the bus in order to minimize via usage and length of
traces connecting to the bus.
Warning: Due to the complexity of PCB buses, we cannot guarantee 100% completion of bus
routing all the time: sometimes the bus path will go through areas that are too confined; there
may be conflicting bus paths or there will be insufficient room for the vias to be added.

Bus Routing Rules

1. Bus route pass only applies to nets associated to a bus through CES.
2. Bus route pass only applies to buses with defined bus paths.
3. Bus route supports partial and fragmented bus paths.
4. Buses without bus paths are routed with other Auto Route passes.
5. Bus route pass follows a defined bus path where possible.
6. Bus route pass follows the layers indicated by the bus path.
7. Bus route pass follows bus packing option specified per bus and bus path segment.
8. If specified, bus shielding traces are routed with packed bus path segments. The
shielding traces are not routed to component pins with the same net or planes.
9. Shielding traces will be positioned with markers and not removed as hangers.
10. Shielding trace widths and clearances can be different than bus trace widths and
clearances.
11. If the bus path pass cannot follow the layers indicated by the bus path, it will use layer
rules defined for the net.
12. Bus route uses the same routing algorithm for packed and unpacked bus path segments.
13. Packed bus path segments can only be Auto Routed with the Bus Route pass.
14. Unpacked bus path segments can only be Auto Routed with the pass Bus Route and
Tune.
15. Glossing for packed bus path segments is always Mild.
16. All glossing levels are available for unpacked bus path segments.
17. Bus route pass ignores layer bias.
18. Bus route supports bus via preferences input during bus path creation.
19. Bus route will NOT support routing to end points of pre-routed bus traces.
20. For Push and Shove performed from other Auto Route passes, individual bus and bus
path segment with a packed setting will treat the related traces as a unit. Nets of the bus
are moved together, this includes any associated bus shielding.
Routing Steps for Bus Route

Without dictating which order of steps to follow, the Auto Route Bus Route pass performs the
following steps:

Target Area Placement and Routing
1. Optimized fanout/pin escape is in direction of the bus to untwist netlines to the bus paths
segments. This synchronizes the order of the bus path.
2. Transform bus paths to routed traces on layers specified by the bus path and occurs for
the entire bus path. The bus packing options are used and applied per bus path segment.
At this point, nets are assigned to the traces. If bus shielding traces are specified, they
are also transformed, however, they have a net assigned to the trace.
3. Followed by the connection of component pins to the bus path traces. Shielding traces
are not routed to component pins, nor planes.
4. Next, buses are routed without layer bias and between component pin to component pin
for each identified bus.
During the route, existing, unlocked/unfixed traces may exist. The bus route respects the bus
packing per bus path segment and will apply push and shove capabilities to achieve its desired
routing.
Bus Tune
The bus tuning occurs after bus setup, bus planning (optional), and the Auto Route Bus Route
pass (optional) or interactive bus routes. The routing of buses can occur with or without defined
bus paths and if the bus was routed with Auto Route, Bus Route pass or interactively routed.

There are two ways of working with route targets; at the macro-level, with target areas or the
micro-level with individual or groups of route targets. The Display Control dialog > Layer Tab
options are used to control the display of route targets and target areas.
Four hazards are available; Review Hazards > Online > Target Area > Route Targets, Target
Areas and Straight Line Interconnects. Review Hazards > Summary > Straight Line
Interconnects Summary.
Note
Target Areas and Route Targets can only be used on regular nets defined as MST
topology. Any topology change can cause loss of target areas and route targets.
As not all signals are buses, there will be a percentage of signals known as general nets that are
routed after the bus route and must fit with the bus routes. Therefore, target area planning and
routing from component pins to route targets should be applied after bus planning is done on a
PCB design. General nets are those remaining nets when buses, critical nets and power and
ground nets are excluded.

The level of required detail varies with the designer’s experience with AutoActive and the level
of control the designer wishes to implement with the placement of route targets. While placing
or manipulating target areas, the designer can reveal the level of display and control.
The display characteristics of target areas and route targets are the same as pad layers. The
required connection from a component pin to route target is a Straight Line Interconnect (SLI)
that shares the display characteristics of its associated target area. Meanwhile the netline has the
global option of spanning from the route target.
With the Auto Route pass Straight Line Interconnects within the Items to Route option to
include Target Areas, the router connects component pins to route targets. The router considers
the route target for each individual via/route and attempts to use the minimal vias to get from
component pin to route target. If this is not possible, then it attempts to get as close as possible,
yet stay within the target area. If a via is inserted for the route target it reaches the specified
target layer. Otherwise, the endpoint of a trace is routed to the target layer for the route target.
Route targets are automatically re-located to match the route results.
Guidelines
The relationship of the following objects: component pin, SLI, route target, target areas and
netlines are as follows:
• A component pin can support zero to n route targets providing it has an associated
netname.
• The connectivity between a component pin and route target is shown as an SLI.
• A route target is always associated to a target area.
• A target area is associated to a single trace layer.
• A target area can be associated with one to many route targets.
• The area of the target area is where trace endpoints or vias are placed for associated
route targets.
• Target Area size can be created in one of three ways:
• Automatically sized to fit all route targets (default).
• Input of maximum deviation distance.
• Grab side and extend or contract.
• Target areas can have stacked route targets (before auto routing), either
automatically optimized or interactively arranged.
• The Display Control option > Netlines From Route Targets shows the netlines span
from the route targets, instead of from the component pads.

Supported Functionality
There are five sets of functionality required to support Target Areas:
• Component pin(s) selection.

• Specify target layer selection.
• Optionally, specify maximum deviation distance for target area.
• Target area/route target placement.
• Auto Route pass > Straight Line Interconnects within the Items to Route includes target
areas: routing from component pins to route targets.
Unsupported Functionality for Target Areas

The following are unsupported for target areas:
• Target Areas are not stored or placed with Reusable Blocks, however, they are stored in
the main PCB database.
• Move Circuit does not include the Target Areas.
• The Route (F2) action key in route mode.
Target Areas in the PCB Design Flow

• Component placement should be complete.
• Bus planning should be complete before target areas are placed for general nets.
• Critical nets may be complete.
• Power and ground signals may be complete.
• Bus routing may be completed before route targets are placed.
• Place target areas or individual route targets with Target Layer.
• With Auto Route pass > Bus Route complete, run the Auto Route pass Straight Line
Interconnects within the Items to Route option to include target areas to connect
component pins to route targets.
• For route targets to route targets (same net) connections, the existing Route pass is used.

Target Area Route and Auto Routing

While in Route Mode and without the Target Area dialog displayed, you can create a select set
of target areas or select an individual target area. You can also use the Edit > Select > Target
Areas, to select all target areas. The selection set is only useful for Auto Routing.
Unless the Route > Target Areas dialog is displayed, the Delete option or any other command
will not apply to target areas. In Route mode, you can select one or more target areas and click
the right mouse button to display a popup. When you select Route Targets from this popup, the
Target Areas dialog displays.
Straight Line Interconnects Auto Route Pass

The Straight Line Interconnect pass offers at least two options for the Items to Route; All Nets
option: Nets will be SLIs (default) and Selected Target Areas. The only way to Auto Route
SLIs, is by using this pass.
For the lower efforts, the priority is to insert vias into target areas, higher efforts allow trace
endpoints. In all cases, the object is to represent a via or trace endpoint at the target layer within
the constraints of the target area.
Note
Routing within the Target Area is an absolute rule.
The Straight Line Interconnect pass embraces layer specific routing by incorporate the Enable
Layer options and the Editor Control > Routes > Vias > Max length on restricted layers >
External/Internal specifics.
When SLIs are routed, they assume a non-layer bias and use few vias and minimize trace length
to route from component pins to route target. They insert a via or trace endpoint on the target
layer within the area of the associated target area. The lower efforts use vias, the higher efforts
accept trace end-points.
The first effort of the pass attempts to route from component pin, your placed route target or
optimized route target placement. Once the route target connection is located with a via or trace
endpoint, the route target is relocated to show that point.
If layer restrictions are applied and do not include the target layer, a via is dropped from the
enabled layer (with minimum via span applied) to the target area. If the netclass and via span
require a staggered via pattern from enabled layer to target layer, the Auto Route Straight Line
Interconnect pass inserts that pattern to the target area.

All other Auto Route Passes

All other Auto Route passes target the route target, if their SLI is routed. It can be routed by the
Auto Route or interactively, but it must be completed from component pin to target area before
other Auto Route passes can connect from other component pins or other Target Areas to the
route target.
Example
The SLI connection has the highest priority, if this is not connected, then the other side of the
route target should not be completed. When it is connected, any Route pass option may work on
the Netline from Route Target to other component pins or other Route Target.
Also, advance passes and effort that employ Rip-up and Retry avoid target areas. While passes
that employ Push and Shove may have access to trace and vias in target areas, providing the
route target vias are not pushed outside of the target area.
Removing Unwanted SLI Route Results

1. Display the Target Area dialog.
2. Select a Route Target (or selection set for several) and click the right mouse button. The
pop-up displays the option of Select SLI traces and vias.
3. Select the option. All associated traces and vias from component pin to Target Area
become selected.
4. Select Delete. Using this methodology it is easy to apply other functions to the selected
set; such as Lock or Fix.
Interactive Moving of Routed/Partially Routed Target

Areas
There may be cases where a fully or partially routed target area needs to be moved.
1. Display the Target Area dialog.

2. Select the Target Area.
3. Select the Move (F2) action key. Similar to moving a routed component, the SLIs that
were connected when the Move started are Re-Routed as the target area is placed in its
new location.
Unrouted Route Targets respect the setting in the Route Target Placement option of the
Target Area dialog which determines whether their placement is optimized.

Input and Formula Parameters for Automatic Calculation

of Target Areas
The following formula details are provided to calculate the size of target areas and placement of
route targets:
Most used netclass The net class associated with the majority of the route
targets of a target area.
Via2Via Clearance The Most used netclass maximum default via to via
clearance on the layer of a target area.
ViaTraceFat The maximum of the Via2Via Clearance and the space
required to place a single trace of typical width for the
Most used netclass between the two vias.
Via2xTraceFat The maximum of the Via2Via Clearance and the space
required to place two traces of typical width for the Most
used netclass between the two vias.
Via3xTraceFat The maximum of the Via2Via Clearance and the space
required to place three traces of typical width for the
Most used netclass between the two vias.
PadDiameter The Most used netclass maximum default pad diameter
on the layer of a target area .
NumOfRouteTargets The number of route targets, which equals the number of
SLIs associated with a target area.
RouteTargetGridSize The distance between the centers of two route targets.
ViaTraceFatThreshold The threshold of the number of route targets, defining if
ViaTraceFat is included in RouteTargetGridSize
calculation. The environment variable
MGC_TARGETAREA_MIN_THRESHOLD provides
such input. If it is not set, 4 is used as the default value.
Via2xTraceFatThreshold The threshold of the number of route targets, defining if
Via2xTraceFat is included in RouteTargetGridSize
calculation. The environment variable
MGC_TARGETAREA_MAX_THRESHOLD provides
such input. If it is not set, 16 is used as the default value.
Automatic Placement
The placement of route targets is determined by the number of route targets and their associated
target area. Target area is displayed as an octagon.
If NumOfRouteTargets <= ViaTraceFatThreshold,

RouteTargetGridSize =PadDiameter + Via2Via Clearance;

If NumOfRouteTargets > ViaTraceFatThreshold and NumOfRouteTargets <=
Via2xTraceFatThreshold,
RouteTargetGridSize = PadDiameter + ViaTraceFat ;
If NumOfRouteTargets > Via2xTraceFatThreshold,
RouteTargetGridSize = PadDiameter + Via2xTraceFat.
The maximum space between the octagon of target area and route targets area is Via3xTraceFat.
SLI crossovers are reduced to the minimum under a given time constraint; under which
condition each route target is placed to be close to its associated component pin.
Route targets are placed to match the via grid.
Copy Trace / Fanout
The Copy Trace command allows you to route sections of the design that contain similar
patterns. You can select a trace and copy it to complete another connection. This requires the
new trace to be placed so its endpoints are on pins of the same net. This command is useful for
routing memory nets that have the same pattern.
The copied trace can also be pushed to any layer by using the F5 action key. This command is
useful for routing memory nets which have the same pattern.
Copy Trace does not take net class rules into account. If a copied net has default, netclass rules
that are different from the destination pins, the copied net's rules are used. Vias are
added/removed where necessary.
Using Copy Trace to fanout microvias

We recommend using a combination of manual fanout and Copy Trace to accomplish any
specialized fanout patterns. The same rules are followed to determine if the traces and vias can
be added legally and the snap to center feature is applied.
1. Add the required vias and traces. They can be any valid combination of vias, traces and
layers.
2. Use Frame Select to select the traces and vias which define the fanout and choose Copy
Trace. The ghosted fanout pattern is attached to the cursor.
3. Frame select the pads where you want the fanouts applied. When you release the left
mouse button, the fanouts appear attached properly to the pins. Once in Copy Trace
mode, you can rotate the fanout patterns by typing them into the keyin field.

r90 or r180, etc.
After the rotation is applied, you can then frame select and add to pins which are at a different
orientation.
Changing a Trace Width

The Change width and “cw <width>” keyin can be used to change the width of selected traces,
either single segments or multiple segments. You can change the width of one or more trace
segments, but only if that change does not create a design-rule violation. If the new width
creates a violation for any segment, the change is not applied to that segment. However, other
segment widths can change. If selected segments cannot be changed a warning dialog is
displayed.
Any violations of the Net Classes and Clearances dialog’s default width settings are flagged.
These settings are used to automatically and interactively route your traces. Minimum /
maximum width violations are not checked.
Reroute
The Reroute command allows you to reroute selected connections when they do not meet your
standards. It can be very useful when working in tight areas and you need to reduce the number
of bends and vias.
Instead of deleting the traces and vias that define the interconnect and routing the netline a
second time, select the existing connection and reroute. The connection is routed; using the
algorithm and effort you specify in the Editor Control and glossed.
Note
Reroute removes tuned nets and differential pair routing. Once nets are tuned and or
routed differentially, they should be fixed to preserve their placement.
Remove Hanger
The Remove Hanger command allows you to remove traces and vias that do not terminate at
pins.
Fanout traces and vias, if not connected to a plane, are considered a hanger, and this command
deletes them if they are part of the selected items. A fixed hanger is not removed until it has
been unfixed. Fanouts for plane nets are also unaffected.

Using the Auto Router
Replace Cell
Replace Cell allows you to choose whether the selected parts are Replaced (default) or Reset in
the design. After planes have been generated any changes that may move pins or vias may result
in the plane data not aligning with the pins. In this case the planes must be regenerated. Changes
include: moving a part, via or mounting hole and replacing or resetting a cell.
If a reference designator was inadvertently removed, the Silkscreen Generator will not generate
data for them; therefore they will be missing in Gerber. Using this command in Reset Mode,
you can add the missing reference designator text.
Using the Auto Router

The Auto Router is a shape-based router and interconnect editor, providing both semi-automatic
and batch routing capabilities. It can push aside routed traces and vias and work in a gridded or
gridless environment. The clearances, high-speed rules and design rules that you define control
the routing process.
Even though no clearance violations are created, you can determine the relative health of your
design by tracking hazards created during manual and automatic routing. The graphical
commands allow you to zoom into and scroll through these problem areas and assess if a change
in placement is in order.
If you want to:

Learn about layer stackup Information on page 176
Learn about the technology setup Information on page 177
Layer Stackup
The properties of the materials used for a board must be defined to enable calculation of signal
integrity attributes such as characteristic impedance, trace delay and crosstalk. The stackup
consists of conductive and dielectric materials used to make up the design's layer structure. A
stackup is initially constructed using the defined signal and plane layers. A layer of dielectric is
placed above and below every conductive layer (the outer dielectrics serve as solder masks). If
there are no solder masks on the design, set the dielectric constant of the outer dielectrics to one.
The thickness and dielectric constant may be defined for dielectric layers. The thickness and
resistivity may be defined for conductive layers.
The velocity of propagation (Vp) and characteristic impedance (Z0) may be calculated for a
defined trace width on any layer of the board. Future calculations of Vp and Z0 for other signal
integrity attributes may be overridden by constructing a table of Vp and Z0 values for layer /
width combinations.

Routing Process Flow
Technology Setup
To calculate crosstalk, the rise time and voltage swing of the aggressor net's driver must be
defined. A core set of technologies is supplied with the product, giving common values for rise
time and voltage swing. A driver's technology is determined using the 'tech' field in the part.
Technologies not found in the existing list are added automatically. If a net does not have a
driver, the Default Technology values are used.
When calculating crosstalk, if there is more than one driver on a net, the smallest rise time and
largest voltage swing are used.

While the routing of a design can proceed in any order, there are common steps that are
typically followed.
If you want to:

Learn about fanout vias Information on page 177
Learn about routing critical nets Information on page 178
Learn about moving parts Information on page 182
Learn about running the Auto Router Information on page 182
Learn about dynamic teardrops and breakout traces Information on page 183
Learn about the finishing remaining opens Information on page 183
Learn about reviewing the design Information on page 183
Learn about clean-up for manufacturing Information on page 184
Learn about modifying corners Information on page 184
Fanout Vias
For SMD parts, fanouts with vias need to be created to allow connections to other layers. While
the router can place vias to complete connections, it is best to place all fanouts initially to assure
that preceding routes don't block future fanouts. Fanouts can be completed by the Auto Router,
by the Fanout command, or by purely interactive routing of a trace and via. Different fanout
results, can be achieved by adjusting the via grid. Start with the via grid recommended by your
manufacturing vendor. If this causes poor route completion due to blocked channels, consider
the acceptability of a larger via grid or routing without a via grid.
Attempts to route pin to pin connections on a single layer without additional vias being added
by planning during Effort 1, which determines how the connections can be distributed between
routing layers. The No Via/Bias pass does all of it's distribution calculations during Effort 1.

Without Effort 1 being run, the router will not plan the distribution of connections resulting in a
drop in the number of connections that are made.
Because a bias will not be used, both horizontal and vertical route channels can be easily
blocked by this pass. This pass should be used in circumstances where vias are not required for
critical nets like differential pairs which need to be routed on a specific layer and back plane
designs which have a lot of routing room and layers to route on.
The No Via/Bias pass replaces the normal Route pass in the situations described above. When
used to route critical nets, it should be limited to the layers you on which you want the bias rules
to be ignored. Any nets routed using this pass should be fully fanned out before the pass is run.
Fanout Cover Layers

By using the Editor Control dialog in conjunction with the Auto Router, you can quickly fanout
the cover layer of your design.
1. Open the Editor Control - Costs dialog and enable routing only on your design’s cover
layers.
2. Open the Auto Route dialog.
3. Turn off all routing options except Fanout.
4. Select All Nets from the Route choice box.
5. Set Fanout to start effort 1 and end effort 3 and select Route.
Routing Critical Nets

After fanout, route your critical nets. Critical nets are defined as any net whose performance
must be managed to achieve a working design. These nets should be routed first, while space is
available to achieve the optimum tuning. If you have defined rules for these nets, they can be
auto routed and the rules are adhered to. You can also manually route them using the Plow
command.
If exact vertex placement is important, you should turn glossing off to avoid unwanted topology
modifications. Net groups can be interactively tuned using Tune after the nets are completely
routed. See Auto Routing Critical Nets Example for further information.
At this stage the ordering of pins can be changed (using Netline Order) without worrying about
existing route blockages. If exact route locations are critical, the routes should be fixed to avoid
minor modifications while routing other signals. See the Auto Routing Critical Nets Example
for further information.
Prior to initializing the Auto Router, all of your parts should be placed, but if you are
experimenting with a critical or complex layout problem it is possible to place and route only

those parts. Change the route border to surround these parts to constrain stray routes (remember
to return the border to its correct position after placing the rest of the parts).
Using this procedure, a design can be partially placed and routed by sections, and after the last
part is placed the Auto Router can be used to connect the remaining connections. Traces can be
left as dangling traces and used to route sections to sections.
Auto Routing Critical Nets Example

There are two types of critical nets; those handled in the Tuning pass and those handled in the
Route pass. Tuned nets include matched net groups and nets with pin to pin delay formulas.
Critical nets handled in the routing pass include nets with maximum length / delay constraints.
To route tuned nets:
1. Display the Auto Route dialog.

2. Add three passes
3. Set the route types to Fanout, Route and Tune, and set the appropriate start and end
efforts.
4. Turn off all other options.
5. Select Route.
The Auto Router automatically fixes those nets that are routed in accordance with their delay
formula. If any segment of the net does not meet the constraints of the nets delay formula; the
Auto Router does not fix the net.
To route nets with maximum length / delay constraints, you must first use a selection method
that is recognized by the Auto Router.
To route nets with maximum length / delay constraints:
1. Use the Net Class dialog to define your nets with maximum length / delay constraints as
members of a specific net class.
2. Use the Editor Control - Filter dialog to move this net class to the Included list and all
other nets to the Excluded list.
4. Select the Filter option from the Route choice box.
5. Turn on the Route option and set the appropriate start and end efforts. Fanouts for all
nets should be completed prior to routing nets with maximum length / delay constraints
to avoid cutting off pad exits.

7. Select Route.
Auto Routing Specific Nets

If there are nets in your design that have specific routing requirements and you need to route
them separately, the following strategy allows you to define and auto route these nets.
1. Use the Net Class dialog to define these specific nets as members of a selected net class.
2. Use the Editor Control - Filter dialog to move the critical net class to the Included list
and all other nets to the Excluded list.
4. Select the Filtered Nets option from the items to Route choice box.
5. Turn on the Fanout and Route options, and set the appropriate start and end efforts.
7. Select Route.
Routing with Fences

The Auto Route Fences pass definition allows you to select the name of the defined fences (hard
or soft) to be used for each pass type. This restricts auto routing and all auto route sub-modules
that automatically route traces; Tune, Fanout, Route & Re-Route to a user-defined area (route
fence) of a board for a sub-set of the total board connectivity (Local Routing). It also provides
for the appropriate behavior of such areas with regard to Global Routing.
After creating fences ( Draw Properties > Route Fence) you can specify the fill color for hard
and soft fences on the Display Control > General Tab under Board Items. There are two types of
Route Fences:
• Hard - The perimeter (edge) of a hard fence cannot be crossed when auto-routing.
• Soft - The perimeter (edge) of a soft fence can be crossed but only when auto-routing to,
or from, a connection object located inside the fence area.
The Polygon, Rectangle or Circle are the only valid draw objects that can be placed as a route
fences. You can select the polygon, rectangle or circle option from the Draw toolbar which
displays automatically. The Properties dialog changes to reflect the chosen drawing option.
Hard Fences
When a Hard Fence is specified in the "Fences" option of an Auto Route pass, all routing occurs
only within the specified hard fence, subject to the selected Items to Route filter and layers. No

other routing occurs outside the active hard fence, (all other fences outside the hard fence - hard
and soft - are ignored). However, soft fences that are defined inside the active hard fence are
routed.
For the specified Hard Fence, only pins, traces, vias and thermal connections located inside
route fences are candidates for auto-route. If their nets have connections outside the fence, those
outside connection points are excluded. Traces & vias are contained within the fence area but
edges may touch the fence polygon edges. The "Items to Route" filter is applied to the
candidates as well as the allowed layers. External partial routing treats route fences as a route
obstruct if not allowed entry. Internal partial routing is allowed between two pins inside the hard
fence.
The following figures show the connection candidacy and results of routing when a hard fence
is specified. The route fence is in red, legal netline candidates for auto-routing are in green,
traces are in blue and netlines, not candidates for auto-routing, are in yellow.
Figure 3-29. Route Fence Candidates
Soft Fences
Soft fences define areas wherein routing may begin or end. Pins, traces, vias and thermal
connections located within this area are candidates for auto-route. If their nets have connections
outside the fence, those outside connection points are also candidates. For specified soft fences,
traces & vias may escape the area to complete routes to connections located outside the route
fence. The "Items to Route" filter is applied to the candidates.
Note
Spread, Via Min, and Smooth Auto Route passes do not respect soft fences. Via Min does
not treat a soft fence as a route obstruct when routed.
Routing outside a soft fence are subject to push & shove when routing inside soft fences.
Overlapping fences are treated as individual fences - they do not merge. Common connection
points are controlled by the first fence definition found for the connection, then picked up by the
next if the previous fence fails to connect. External partial routing treats encountered route
fences as a route obstruct if not allowed entry. Internal partial routing is allowed between two
pins inside the soft fence.

Auto Route Fences Pass Definition

The following figures show the connection candidacy and results of routing, when the Fences
option is selected for each soft fence defined on the board. The route fence is in red, legal
netline candidates for auto-routing are in green, traces are in blue and netlines, not candidates
for auto-routing, are in yellow.
Figure 3-30. Soft Fence Candidates
Auto Route Board Pass Definition

The following figures show the connection candidacy and results of routing, when the "Board"
option is selected for each soft fence defined on the board.
Move Parts
During the design process, it is normal to move/push parts. Once your critical nets are routed,
you may need to create additional space for your parts due to noise or heat problems. There are
numerous options available in Expedition PCB to move parts; Move Part, Push Part, Pushback
Part, move parts with the keyboard arrow keys and move parts by file.
Run the Auto Router

Once your critical nets are routed, the Auto Router should be used to route the majority of the
connections on the design.

You can graphically review the connections while they are made to determine if they are
routing as desired. For many connections, the Auto Route command is preferred over the Route
command because Auto Route can be set up for multiple effort levels and algorithms. The
Route command only routes a single algorithm and effort level.
Using the Editor Control - General tab, you can disable routing on your design’s cover layers
and enable routing on the design’s inner layers.

2. Turn on Memory, Route, Tuning (if necessary), Via Min and Finishing.
3. Set the appropriate start and end efforts.
4. Once a route is complete, the Auto Router does not continue with extraneous effort
requests. If the Auto Router is unable to complete route, and you have set the effort to
the maximum for that pass, the Auto Router spends considerable time trying to place a
route that could be better placed interactively.
5. Ensure that select All Nets is still selected in the Route choice box and select Route.
Dynamic Teardrops and Breakout Traces

Interactive teardrop placement (dynamic teardrops) allows you to place a single teardrop on a
selected pad. If you are folding no-connects, or you have a pad on which the automatic teardrop
command could not place a teardrop because it would cause violations, you can route or modify
the trace and place a teardrop on the connecting pad.
Interactive breakout traces placement (dynamic breakout traces) provides the ability to place a
single breakout trace on a selected pad. If for any reason a breakout trace could not be created
for either a pin/trace or via/trace combination, the pin/trace or via/trace combination is
highlighted once the command has finished execution. In that case, you can edit all the
highlighted pads on the board then go back into the Breakout Traces dialog and manually enter
the width and length settings for the selected pads.
Finish Remaining Opens

If the router did not finish 100% of the connections, the remaining opens have to be completed
manually. The Plow, Move and Reroute commands are primarily used in this mode. If
connections are impossible to complete, you have to modify part placement, the board outline,
or the number of layers to achieve completion.
Review Design
While the routing stages are constrained to your rules, you should always confirm that none of
the rules have been induced by temporary rule overrides. The Review Hazards command can be
used to find Online DRC errors in the design, and locate them on the display. The Hazards

Clean-Up for Manufacturing
dialog is updated dynamically, so you can instantly see the effects of efforts to fix the online
hazards. You can also cross probe the corresponding schematic to identify related symbols and
signals.
The Cross Probe Select command allows you to select any item or group of items and have the
corresponding item or group of items highlighted in the one of the design’s attached schematic
entry tools.
Clean-Up for Manufacturing

Once all connections have been made, the design should be run through a manufacturing pass to
clean up excess vias, and smooth out the routes. This can be accomplished using either the last
two passes of Auto Route, Gloss or Reroute.
The Smooth pass of the Auto Router uses the advanced glossing features that can be setup in the
Gloss Tab of Editor Control. The Breakout Traces command may be executed at this point to
reduce the number of pad/trace breaks during the hole drilling process. Teardrops also can be
generated at this point. If your board has high-speed signals that require rounded traces, Modify
Corners can be run to convert angled corners to rounded corners.
Modify Corners
If your application requires the use of rounded corners, use the Modify Corners command to
change the trace corners from angles to arcs. You should only arc your corners once your board
is routed to 100%. Arced corners are not maintained when parts and or traces are moved or
rerouted.
If you intend to modify corners that are fixed, locked, or both, you must select the Include
Fixed and Locked Corners check box
You can enter the same value for minimum radius and maximum radius to specify an exact
radius for all arcs, added to your design.
Reviewing the Design

It is wise to check the status of your design. The following utilities and commands not only
allow you to check the state of your entire design but also specific elements within the design.
If you want to:

Learn about design status Information on page 185
Learn about signal integrity attributes Information on page 185
Learn about hazards Information on page 185

Reviewing the Design
If you want to:

Learn about generating reports Information on page 185
Design Status
The Design Status command generates an ASCII file that provides information relative to your
entire design. The information gathered includes data about the board size, layers, nets, netlines
and placement information.
Signal Integrity Attributes

To calculate the velocity of propagation and the characteristic impedance of a trace on the
board, select a segment of trace. The Background Field Solver uses the trace layer, width and
the materials stackup to determine these values. If a Layer Stackup/Options table is defined for
a given layer, the Vp and Z0 values for that layer are used as the override when the trace
segment is selected.
Hazards
Whenever the status of the design changes, Review Hazards Online should be reviewed to
ensure your high-speed rules have not been violated and all of your connections have been
made.
The hazards are not affected by the status of the Optional Net Rules in Route tab of the Editor
Control. This allows you to temporarily disable a rule without losing track of any violations
caused in that mode. The graphic options (Select/Highlight/Fit) are useful for identifying
problem nets and acting on them.
Once your design is routed, Batch DRC should be run to verify the clearances within your
design, the connectivity of your design and whether your design meets your manufacturing
needs. Review Hazards Batch can be used to review and fix any hazards found by Batch DRC.
Once you have fixed any of these hazards, Batch DRC must be re-run to ensure no hazards
where created while making changes to your design.
Generating Reports
The Report Writer offers a unique, window-based interface for generating user-defined reports -
from a simple default report to a comprehensive user-defined matrix, detail or summary report.
The Report Writer gives you simple, direct ways to view and work with the information
collected.
Several report definition sample files are delivered with this product. These example files can
be edited and be used as the basis for your own reports using a third party product called Crystal

High Speed and Critical Nets
Reports. Crystal Reports is a powerful, yet easy to use program for creating custom reports, list
and form letters using data extracted from your existing databases.

The Auto Router controls all high speed/critical nets with rules defined in Net Classes and
Clearances, Net Properties and Editor Control. This way you can avoid multiple iterations of
layout and checking passes to see if the design conforms to your rules. There are times when
you want to override a rule, and that capability is provided. Because this may introduce design
inconsistencies, the hazard checker always lists the violations.
If you want to:

Review general comments on high speed nets Information on page 186
Learn about pin ordering control Information on page 186
Learn about impedance control Information on page 187
Learn about length / delay control Information on page 187
Learn about group length control Information on page 187
Learn about differential routing Information on page 190
Learn about crosstalk control Information on page 191
General Comments on High Speed Nets

When working with critical signals that need to be routed first and then fixed, you can use the
Auto Router to give you a good starting point. Because the design is empty, the Auto Router
achieves the routes with a minimum of trace length. The router also has the ability to tune the
nets during routing or when all routing is accomplished using a special tuning algorithm.
Remember to fanout all SMD pads before placing the critical signals. It is important that all
SMD pads have access to the inner layers. If there is a large number of critical nets to route,
these can easily block valuable via placement points.
If pins on a custom or chained order net are placed closer than the stub length apart, it is
possible that the router does not follow the specified connection order. This is most likely to
happen between the last load and the terminator because of their proximity.
Pin Ordering Control

You may define the order in which a net’s pins are connected by setting the net to either custom
or chained. If a net is chained, algorithms are used to order the net as efficiently as possible. If
the net is custom, a user-defined pin ordering is used. Any ordering may be manually modified
using the Netline Order command. The net’s type may also be altered in this way.

Since the advent of SMD technology, getting into and out of padstacks in a true custom
topology has become difficult. Previously, with through-hole parts, every layer was a valid I/O
point, but with SMD parts that is no longer true. With the fine pitched devices now in use, it has
become harder to fanout all the pins. If a true custom topology net were required, every pad that
was in the custom topology would require 2 fanout vias rather than just one. Because of this
limitation, the stub length net property allows you to specify the amount of “shared” trace that
can be used when attempting to route these connections.
Impedance Control
Its thickness and width, its distance to plane layer(s), and the surrounding dielectric material
(e.g. dielectric constant) determine the impedance of a trace. These properties can be defined
and evaluated in the Layer Stackup.
To control impedance along a net, you can define trace widths for each layer of the design. This
is accomplished in Net Classes and Clearances by defining the width for a layer and calculating
the impedance, or vise-versa. You can also restrict routing to specific layers. The impedance of
a selected trace segment is displayed in the command window. Plane layers must be defined
within your layer stackup in order for Expedition PCB to calculate impedances.
Length / Delay Control

In high-speed design, it is often necessary to fix the length boundaries that a signal can route
within to achieve critical timing for a signal. Because clock rates are increasing and the
propagation delays of gates are falling there is a critical time when an expected signal must
appear at a pin. To achieve this, signals are given a maximum delay, expressed in length or
time. If a signal has this restriction (set in the Net Properties dialog), these settings are respected
and routing is only allowed within that boundary. Maximum delays are applied to the net’s
electrical length (calculated as the total net length divided by the velocity of propagation (Vp)).
The interactive routing commands use a tuning ellipse to guide you to the correct length.
The Tuning Ellipse displays differently for 45 degree routing and 90 degree routing. When in 45
degree routing, the Tuning Ellipse displays as an oval or ellipse. When in 90 degree routing, the
Tuning Ellipse displays as an octagonal shape.
To constrain specific from - to’s, use delay formulas defined in the Net Properties dialog. These
formulas can be used to match delays between sets of pins, or to define relationships between a
set of pins.
Group Length Control

In high-speed design, it is often necessary to have a group of signals within a delay or length
tolerance to each other. This is to achieve critical timing for that group of signals and the ability
for the “on” state for all those signals to arrive at the same time at their destination (usually
found in data buss signals). To achieve this, the Auto Router automatically tunes these nets.

Because of the critical nature of these nets, they are usually routed first and then fixed in
position.
The automatic tuning feature is invoked as soon as the last connection of the group of signals is
made. Checks to find the longest signal of the group and then attempts to match (to within the
tolerance set up in Net Properties) the rest of the signals to that length. If a modified net is in a
matched length group and it is pushed outside the tolerance, the system automatically tries to re-
match the rest of the signals to the new length. When there is a large number of signals in a
matched length group, this procedure can take a long time.
When working with a matched length group, it is recommended that you find the signal in the
group with the longest Manhattan length and route that first using the shortest distance possible.
This helps eliminate unwanted trace length.
Note
If an unusual amount of trace length appears with matched length groups, it is normally
associated with a group of signals that have a rogue net(s). If there are 32 signals in a
matched length group and 31 of these are approximately 5 inches long and one is 12
inches long, 7 inches of trace length per signal multiplied by 31 signals are attempted to
be added. This would need 217 inches more trace length than was really needed. Be sure
to check placement and matched hazards.
The Tune command can also be used to tune matched length groups. This command only makes
nets longer to match rules. The situations in which it works are:
1. When delay formulas on a net are not within tolerance.

2. When the difference in net lengths in a matched length group exceed the defined
tolerance.
In the case of matched length nets, the selected net is not necessarily the one that is modified.
All nets are modified to match the longest net in the group. The longest net in the group is
determined once the nets have been rerouted to their shortest possible length.
The Router reroutes an item based on the rules in the Editor Control - Tuning tab. If the rules
cannot be satisfied, any improvements toward the rules are kept.
This command does not make a net shorter because there are so few ways to violate the
Manhattan Length rule. A net can be too long because:
• Its Manhattan Length is greater than the Maximum Length rule.

• The Maximum Delays and Lengths rule was turned off.
• The design rules of a net, or group of nets were changed after routing was completed.

Pin Package Length

Creating a text file (PinPkgLengths.txt) and putting it into the ../config directory, you can define
a length value on a per-pin/per part basis that will be added to the trace length when checking
the length of the signal against the length rule. If any errors occur, a log file
"PinPkgLengthLog.txt" is created in the ../LogFiles directory that can be viewed using File
Viewer.
Whenever there is a check to determine if the trace length matches any length rule (below), the
PinPkgLength value associated with the pins on the signal is added to the length of the trace
data.
• Any formula (Total Excess Length in both top and bottom lists, Numerical Formula and
Computer Formulas)
• Min/max length (Excess and Routed),
• Match length (Length and Delta)
• Plow tuning ellipse
Hazards
The calculation of actual trace length now includes the PinPkgLengths.
If the sum of the actual trace length plus the total of the PinPkgLength is within the tolerance of
the length rule, there is no hazard.
If the sum of the actual trace length plus the total of the PinPkgLength is outside the tolerance of
the length rule, there is a hazard.
This means that can adjust the trace length until the hazard disappears. The hazard shows by
how much the sum of the trace length plus the PinPkgLength is outside of the tolerance. Since
the PinPkgLength is a constant, you can adjust the trace length by that amount.
Routines affected
• Tune (interactive and automatic) whenever it is used, including AutoTune.
• Hazards
Routines not affected

• Everything but Tune (and routines that apply tune) and Hazards.
• All trace length reports - Whenever a trace length is reported it will still be a trace length
and will not include the PinPkgLength.

Format of PinPkgLengths.txt file

UNITS <value>
PART_NUMBER <part_number>space delimiter
<pin_number> <value> Pin Number, not Pin Name. Space delimiter
UNITS must be the first line of the file or an error will be reported.
If the pin number or part number has a space in it, it is assumed that all non trivial characters
past PART_NUMBER are part of the name and that the <pin_number> is the first part of the
line up until the last numeric value.)
Notes
1. If the unit of the PinPkgLength is different from the unit of the rule in the design, the
PinPkgLength is converted.
2. The following checks are done. These errors are reported in a log file
"PinPkgLengthLog.txt", available in the ../LogFiles directory.
More than one assignment of same pin - ignore second and subsequent same pin
assignments
Unrecognized keyword - ignore line
Missing required arguments - ignore line
3. The following may occur but is ignored:
Missing part pin numbers: not all part pins require assignment.
Part Number not in design: allows use of archived file.
4. Valid values for units are Thousandths or th, Microns or um, Millimeters or mm, and
Inches or ins. These entries are case insensitive.
Differential Pair Routing

The characteristics of two signals can be matched by classifying them as a differential pair. This
is common when two nets, one carrying a signal and the other carrying its inverse, are active
simultaneously and are expected to cancel each other out. To achieve this, these nets are routed
with adjacent traces, paired vias and matching lengths.
Differential pairs are defined in the Net Properties - Timing and Differential Pairs tab, and can
be routed by any of the following Expedition PCB commands: Route, Forced Plow, Route
Plow, Multi - Plow and Auto Route.
Trace to trace clearances for differential pairs is set in the Net Class - Clearances dialog. This
value defines the distance between the two nets that comprise a differential pair. It is not a
clearance value between differential pairs and other nets.

Post Processing
If a differential pair net is to be tuned, route one of the nets using a large meander and once the
net is routed, fix it and route the unrouted portion of the differential pair using the appropriate
routing command.
Routing differential pairs with mismatched node counts

If you have differential pairs with mis-matched terminations, (one branch may have five nodes
and the other branch only has four because there may be a capacitor or other termination resistor
attached), set up the route passes as follows:
In the Auto Route dialog, run a fanout pass before the route pass, the differential pairs are
routed. Interactively, if you select the F2 action key first and then the F8 action key, the nets
will route completely.
Crosstalk Control
Coupling between two parallel signals in the form of capacitance and inductance generates
noise known as crosstalk. Unfortunately, the same techniques that reduce delays in signals, such
as increasing dielectric thickness, also increase the coupling capacitance between those signals,
thereby increasing crosstalk effects.
You may define hazard conditions for crosstalk and parallelism in Net Properties. These
guidelines do not constrain the router, but are used to check for violations shown in hazards.
Crosstalk can be reduced by: Shortening parallel segments; Increasing the clearance between
parallel segments; Separate the parallel segments with a plane; Increasing the driver rise times
and / or reducing the line impedances (i.e. increase dielectric constants, increase trace widths
and thickness, reduce trace-to-ground thickness, or increase trace clearances).
Post Processing
Once the design has been placed and routed, it should be prepared for the manufacturing and
documentation processes. The Post Processing steps prepare the design by modifying reference
designators, preparing Gerber photoplot output, CAM files and final documentation.
If you want to:

Learn about test points Information on page 192
Learn about the Padstack Editor Information on page 194
Learn about Migrating Plane Data Information on page 197
Learn about Plane Assignments Information on page 197
Learn about the Planes Processor Information on page 194
Learn about design verification Information on page 200

Post Processing
If you want to:

Learn about running Batch DRC Information on page 200
Learn about running Batch DFF Information on page 201
Learn about renumbering reference designators Information on page 203
Learn about modifying text with the Draw tool Information on page 204
Learn about generating silkscreen Information on page 204
Learn about NC Drill Information on page 205
Learn about Gerber 274X Information on page 209
Learn about Gerber 274D Information on page 210
Learn about general interfaces Information on page 211
Learn about plotting Information on page 214
Test Points
Designs that are tested using an automatic test system require that test points be added and
assigned to the nets to be tested.
The test points must be created in the Cell Editor with a cell type of Test Point.
Test Points must be placed in accordance with the test systems that the design connects to.
Some test systems only test one side of the design; others test both the top and bottom sides
together. Using a test system that requires all test points to be on one side may result in extra
vias having to be placed manually in order for all required nets to be accessible.
Test systems require that all test points be a specified distance apart and usually on a predefined
grid pattern. If your design must meet this criterion, that fact must be taken into account during
the routing phase. If vias are not routed to the grid needed for test point assignment, it may be
difficult to arrange the vias to meet the grid requirements afterward. Depending on testing
needs, varying numbers of test points may be required for each net. For example, signal nets
may only require a single test point, but power and ground nets may need to be tested at several
different points on the design.
To place all test points on a design, use the Automatic Test Point Assignment command. This
command uses the following test point definitions defined in Setup Parameters, cell name, ref.
des prefix, test side, grid, and use closed polygon assembly outlines as test point obstructs. Test
points may also be placed one at time interactively using the Place Test Point command. This
command allows the test point to be attached to connections either by designating an existing
via, through hole or trace.

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When placing test points, use the Fix commands within the Auto Assign Test Points Menu. This
helps prevent the test points from being moved or deleted in subsequent revisions of a design,
which could result in having to create a new test fixture.
When a design is edited and traces are connected in a different configuration, there are
occasions when the assigned net for a test point may differ from the new net it is connected to.
The Assign Net Name command allows you to change the netname on floating test points.
Within the Automatic Test Point Assignment menu is the Test Point Report generator. The
reports generated apply to all test points regardless of how they were placed. The Test Summary
report (testptsum##.txt) is the data that should be used to prepare the test fixture and program
the test system. It contains information used for drilling the test fixture and programming the
test equipment.
• The net name to which the test point is connected

• Test point reference designator, if used
• The XY location of the test point
• Test point location type (part pin, via or trace)
• Side of the design where the test point is located
Many companies find it useful to know the difference between the test point data from one
revision of the design to the next. The ECO Report shows that test points were added, which test
points were deleted and which test points changed from when Expedition PCB was invoked.
The ECO report (testpteco.txt) should only be executed when all test points changes have been
completed and the design is ready for archive. Once the ECO Report has been run, the old
report is removed and replaced with the new report.
Place Test Points from File

Test points can be placed using the testptlog_nn.txt files. These files reside in the
<design_dir>/pcb/ LogFiles directory. To display this option, the following environment
variable is required:
MGC_TESTPOINT_READOUT
Delete Unused Test Points

Unused test points can be deleted from the selected net using the Edit > Delete Unused Test
Points command.

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Padstack Processor
The Padstack Processor performs operations on the padstacks in the design. Padstack
definitions are layer specific, therefore if you change a padstack on an SMD part and then push
that part from the top to the bottom layer or visa versa, the padstack used is one within the
padstack database. Thermal and clearance pads are not listed in this dialog. Changes to these
pads must be done with the Planes Generator. The operations are:
Changing Pads by layer – This allows you to increase of decrease the pad size or shape to
meet electrical or manufacturing needs.
Deleting Pads by layer – This allows you to remove pads of internal layers that are not
connected by a trace or plane data.
Changing Padstacks – This allows you to change the entire padstack shape to meet electrical
or manufacturing needs.
Resetting Padstacks – This allows you to reset padstacks back to their original library
definition.
Since these operations can invalidate the pads and holes assigned to a part, care should be given
not to make changes that effect the manufacturability of the design. Also, changes to the pads
may create clearance violations. Batch DRC should be run after the Padstack Processor has
altered the design.
Plane Classes and Parameters

The Plane Classes and Parameters is used at the point in the design process when part placement
and routing is complete and is used to generate plane data within a design. Plane data is an area
of metal that may or may not be connected to a specified net. Plane data may possibly be used to
aid heat dissipation, provide an even distribution of current, or to act as a shield for sensitive
signals. Existing plane data is deleted when new plane data is created. Plane data can also be
deleted from the design using the Delete Plane Data command. See Discard Plane Areas for
more information.
When you are ready to process planes, a dialog appears showing the elapsed time. You can
select the Cancel button on this "wait" dialog if the process is taking too long.
A plane may be a signal plane, which is one that has an associated net, or a shielding plane,
which has no associated net. For plane data to be generated for specific areas, a plane shape
must exist. The Plane Clearances and Parameters allow the option to use either user defined
plane shapes or the route border as the plane extents. Planes that use the route border as their
shape must be defined within Setup Parameters before the routing stage.

Post Processing
The clearance used between objects like pads/traces and plane metal is the larger of the Net
Class and Clearances Trace to Pad clearance and the Other Object (Minimum) defined in the
Planes Processor dialog.
When generating negative planes flashed anti-pads the Plane Clearances and Parameters will
use any round pad that has been defined in the design’s padstack database based on the
clearance pad this is required. However, if the design has been setup to generate 274-D Gerber
for manufacturing based on the Gerber Machine Format file defined for the designs attached
Gerber Plot Setup file, it will use only the route D-Code sizes that are defined within the D-
Code Mapping file assigned to each specific plane layer.
If a D-Code of the correct size can not be found, then the Plane Clearances and Parameters will
draw the clearance pad instead of flash. If the design is defined to use 274-X as the Gerber
generation mode or no mode has been defined, then the Planes Processor will use any round pad
that has been defined in the designs Padstack database based on the clearance pad this is
required.
Plane Clearances and Parameters also allows the creation of negative planes. Negative data
generation produces plane data that represents the clearances for the plane. This type of plane
data represents the places where metal does not exist. For plane artwork, the negative of the
plotted image is used to represent the plane metal.
Positive plane data may be added to an area as a solid shape, or may be generated in several
crosshatched patterns. Using the crosshatch patterns allows the plane data to be generated based
on hatch width and distance or by assigning a percentage of total plane coverage.
Both positive and negative planes allow the creation of Split Planes. To determine the plane
generation method, positive or negative, you must weigh the advantages/disadvantages of each.
The following table allows you to determine which plane method is best for you.
Table 3-3. Advantages/Disadvantages of Positive and Negative Planes

Positive Planes Negative Planes
Pro Con Pro Con
Allows hatch Large Gerber files for Smaller Gerber Files Hard to view data, is
patterns layers which are 50% or not WYSIWYG
more plane data
WYSIWYG Good for planes which Small conductive
cover 50% or more of areas create large
the layer Gerber files
Good for small Creates smaller design
conductive areas files
Allows for snapping Thermals can be
of plane elements flashed during Gerber
generation

Post Processing
Split Planes
A split plane is a plane layer that has been divided into at least two different non-connected
plane areas. Each of these plane areas is used for a different signal. To create a split plane, place
plane shapes for each of the nets required. This should be done in a highlight mode to verify that
all points of the net are within the boundaries of the plane shape.
When Plane Clearances and Parameters is run, it connects only the nets of the particular plane
shape, providing clearances for all other nets. If the Split Plane shapes overlap each other, the
plane shapes priority will be used to determine how plane shapes cut into each other. Higher
priority plane shapes will cut into lower priority plane shapes when the plane metal is generated.
Discard Plane Areas

There are two options within the Plane Classes and Parameters menu that allows you to remove
pieces of plane data. These options are “All Untied Areas” and “Any Areas Less Than”.
The “All Untied Areas” option removes any plane areas that are isolated and do not connect to
the rest of the plane because of plane clearance, hatch width, and other factors. With this
parameter you can eliminate these unconnected portions. The All Untied Areas option has a
sub-option, “Areas tied to a single pad”, that allows areas tied to a single pad to be discarded.
Since these areas are not used to connect multiple pins, they can be removed automatically.
The “Any Areas Less Than” option allows you to define a minimum linear area that should be
removed from the plane net being generated. This option also removes small areas of plane
metal that could cause slivers of conductive metal.
Delete Plane Data or Actual Plane Shapes

The Delete Plane Data command allows you to delete plane data and actual plane shapes from
the board. There are two options of removing plane data from your design:
• All - Removes both positive and negative plane data from all layers of your design.
• Layer - Allows you to remove positive planes by net for the selected layer. If the plane
layer has negative planes, you are only allowed to remove all the plane data from the
selected layer.
• Actual Plane Shapes - If Delete Plane Data by Layer is selected, this option becomes
available. When checked it allows you to select actual plane shapes on the board. Actual
plane shapes outline and represent the true plane data including obstructs or hole, islands
and tie legs as they would be plotted. These shapes are always enclosed shapes and
adhere to the clearance rules and connection types defined within the parameters of each
tab.

Post Processing
Migrating Existing Plane Data

When a legacy design is opened in the new plane environment, you may want to compare the
original plane data with the results from using the new planes engine. This can be achieved by
comparing new fill data with generated Gerber files in the layout editor.
Note
A Fablink XE license is required to import Gerber files into the layout.
To simplify the verification process:
1. Open the legacy design in the new environment.

2. Generate Gerber files for all layers containing the original plane data. You can omit
everything apart from the plane data when generating the Gerber files.
3. Import Gerber files onto user draft layers. Requires a FabLink XE license.
4. Change all plane layers and plane nets in design from Static to Dynamic.
5. Display each board layout in turn, with the corresponding imported data.
Plane Assignments
Using the Plane Assignments dialog allows you to manage plane assignments for each plane
layer and plane net on the board. These display in the Layer/Net column of the table. The
default plane net state is inherited from the current plane layer state. For example, if layer 1 is
set to Dynamic, any new plane nets on this layer inherit the same plane state by default.
Individual plane nets can then be defined with a different state.
The Plane Assignments menu option is only visible in the right mouse button popup if one or
more plane shapes are selected. When opened the corresponding plane net(s) selected in the
table are displayed.
Overrides cannot be overridden by making a class assignment change in the Plane Assignments
dialog.
Signal Flooded Planes

Signal flooded plane layers allow you to route and simulate nets on designs that have no solid
power planes. When the signal layers are flooded, you can use those layers as reference layers
when determining the transmission line characteristics of nets.
When the signal layers are set as reference layers, they are used as a reference in the CES Net
Class impedance calculations and carry through in the AutoActive environment. Additionally,
when data is extracted from the AutoActive environment and pushed to ICX classic or
HyperLynx, the reference plane information is also included.

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You can select a layer to be used as a plane reference and change that reference easily during
the design process. For example, you may need to do some analysis with layer two as a
reference plane and then change the reference plane to be layer four. When the layer description
is set to Flooded Signal, then the plane type is set to Positive and it cannot be changed.
The Plane layer indicators in the General Tab of Editor Control are signified with a letter P
appended to the layer number. The Flooded Signal layers are treated the same as other signal
layers and therefore do not have a P appended.
Net Information Extraction in the AutoActive Environment

The net information that is extracted from AutoActive and sent to the various simulation tools
(including ICX Pro Verify from within AutoActive) includes the default clearances between the
area fills and the traces. This default clearance is used when determining the transmission line
characteristics of the nets that are routed beside the area fills.
The flooded signal layer type is passed to the various simulation tools in cases where the area
fills have not yet been created; the simulation treats the layer as if the fill already exists. This
feature allows you to do some what-if analysis on various net topologies before creating all of
the area fills.
Data Differences
Due to fundamental differences in the data used to estimate transmission line characteristics in
AutoActive and that used to simulate nets in the ICX, ICX Pro and HyperLynx environments,
data differences are seen.
Estimated characteristic impedances for a trace width on a specific layer can be seen by
selecting a trace segment in AutoActive or by looking at the Typical Impedance column in the
Traces and Via Properties tab of CES. Additionally, you can see the characteristic impedance of
a specified trace width in the Basic or Z0 Planning tabs of the CES Stackup Editor.
Because the CES Stackup Editor, CES and the AutoActive environment are all using the same
field solver and making the same assumptions about plane layers and flooded signal layers, the
impedance calculations in these three tools should match. On the other hand, when extracting
transmission line characteristics for simulation purposes, neighboring nets and exact location of
plane data (area fills) is used. Utilizing this extra data results in more accurate trace
characterization.

Post Processing
Example Illustrating Differences

The following figure illustrates a cross section of a very simple example of a four layer design
with layer 2 and layer 3 having area fills.
Net A and Net B use the area fills as references in the real design and in a simulation
environment. The arrows in the following figure indicate the reference plane used for Net A and
Net B.
If you set layer 2 to be a Flooded Signal layer, then layer 2 is used as the reference layer for Net
A and Net B. The transmission line characteristics for Net A will not be calculated properly, as
indicated by the red trace color in the following figure.
Likewise, when layer 3 is used as a reference layer, Net B characteristics will be wrong, but Net
A will be correct.
When the flooded signal layer types are used, the transmission line characteristics are different
than those used during simulation. The AutoActive transmission line characteristics are only
estimates. Usually, these estimates are close to the actual characteristics but in cases where area
fills and partial plane shapes exist, the estimates are not as accurate.

Post Processing
Design Verification
A full Design Rule Check (DRC) should always be run prior to generating manufacturing data
and/or documentation. DRC verifies that none of the design rules that were defined in Editor
Control, the Net Classes and Clearances menu or in Design Capture have been violated.
If any design rules were violated, DRC identifies and locates the errors to enable you to correct
them prior to sending the design to manufacturing. Online DRC should not be used as a
substitute for a full Batch DRC run, as it does not have all of the capabilities of Batch DRC.
If a valid license is available, you can run Batch DFF to inspect the design for potential
fabrication and assembly problems. Any problems are available for viewing using the Review
Hazards > DFF options.
Running Batch DRC

Batch DRC can verify your design for proximity, connectivity and manufacturing rules
violations. Proximity checks verify that the clearances defined in Net Classes and Clearances
are not in violation when compared to the elements placed in the design file. Connectivity
verifies that using traces or planes connects pins of the same net defined in the schematic or
netlist. Manufacturing Rules verifies that designs are not created with situation that can cause
manufacturing problems.
Caution
It is important to check the drc.txt file after each run of Batch DRC. This file can be
viewed through File Viewer. Batch DRC hazards limit is 10,000 for proximity checks and
10,000 for connectivity checks. If this limit is passed, Batch DRC stops before
completing verification.
Additional element to element rules can be defined for your manufacturing needs. By default
we load all of the clearances defined in the Net Class and Rules General Rules list. But other
clearance requirements can be added by selecting the Advanced Element to Element Rules
button. This displays a DRC element to element matrix that can be changed by adding
additional clearances to meet your manufacturing needs.
The Batch DRC command can verify proximity clearances on sections of the board defined by a
DRC window placed in the design, or on the entire board. Running DRC in windows is
especially useful on large designs. It allows you to concentrate on small sections of the design
minimizing the need to change the viewed area of the board. A run of the entire board should be
done prior to creating manufacturing data and/or documentation. See Review DRC Hazards for
further information.
If you are going to run DRC in windows, place the windows in the design using the Place DRC
Window command. Next, enter Batch DRC and select, from the menu, the options desired for
the DRC run. You can select any combination of options and make iterative DRC runs.

Post Processing
When Batch DRC finishes, you should review the log files using the File Viewer. The log files
details, which checks were performed and which violations, if any, were found.
Review DRC Hazards

Review Hazards lists both Online, Batch and DFF DRC hazards. Online hazards are updated on
the fly while the design is being created. Batch Hazards are based on the last run of Batch DRC.
DFF hazards only display if a valid license is available.
After reviewing the log files, you should use the Review Hazards command to find the
violations in the design file and correct them. All of the Expedition PCB commands are
available for use while Review DRC Violations is active, which enables you to fix violations as
they are highlighted in the review session. Batch and DFF DRC should always be re-run after
fixing violations to ensure that new violations were not created during the editing process.
Running Batch DFF

If you want to run either Hole Registration analysis, and/or the Text Stroke Width analysis, the
Gerber and drill files must already be defined and attached to the job before DFF is run.
Therefore, run the Output > Gerber… and the Output > Drill… commands before starting the
DFF analysis. If you don't wish to run either/both of these analyses, this setup step may be
bypassed.

Post Processing
Figure 3-31. DFF Flow
Complete Design (placement, routing, etc...)
Run Batch DRC
No
DFF Errors Found?
Yes
Creates
Analysis data Reports
Loads results into Analysis > within Design\PCB\LogFiles within Design\PCB\Work directory
Review Hazards > DFF > directory: DffSilverViolations.dat
Signal Drc.txt DrcDffViolations.dat
Plane DrcDff.txt
Drill
Soldermask
Silkscreen
Correct errors identified and save Rerun batch DRC
Create CAM Build Package
You must edit the DrcDffParameters.dat file to setup the DFF Analysis variables file. This file
is ocated within the ,,.PCB/config directory. The UNITS defined in the DrcDffParameters.dat
file do not have to be the same as in the design and if they are not the same, the data in the file is
converted to the units defined for the design. You should also make sure that the number of
layers within this file matches the number of layers within the design.
This file should be opened with a text editor (Word Pad or Notepad).
Note: All text that is shown in the sections below using the "Courier New bold font" identifies
what the user is allowed to edit. If the user modifies anything else, the DFF analysis may a) not
completely run, or b) cause the system to crash.
General notes on modifying the file:

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1. After the initial header block, the first line of every block is name of a particular DFF
analysis that will be run. If you do not want to run this test, change the word YES to
NO. If the system sees a NO, the system will go onto the next analysis block.
Do not leave the analysis as YES and just edit the values to non-realistic numbers, as the
analysis will still be done.
2. For those analyses that can be defined by layer (within Signal, Plane, and Drill
analyses), define separate values for each layer. For example, this:
.TRACE_WIDTHS YES
..LAYER1
..LAYER 2
..LAYER 3
..LAYER 4
...MINIMUM 15
...MAXIMUM 25
is NOT equivalent to:

.TRACE_WIDTHS YES
..LAYER 1
...MINIMUM 15
..MAXIMUM 25
..LAYER 2
...MINIMUM 15
...MAXIMUM 25
..LAYER 3
...MINIMUM 15
...MAXIMUM 25
3. Within each line of the DrcDffParameters.dat file, anything that follows an exclamation
point character ("!") is considered a comment for the rest of that line by the system.
4. For both Soldermask and Silkscreen analyses, different values can be set for both the top
and bottom side and of the design.
Renumbering Reference Designators

When the placement and routing phases are complete, the reference designators can be
renumbered in sequence to make parts in the final design easier to locate.
The most efficient way to accomplish reference designator re-sequencing is through the use of
the Renumber Reference Designator command. This command allows the parts to be
renumbered in one of eight numbering schemes. The Renumber Reference Designator
command renumbers the design's reference designators one side at a time, or renumbers both
sides at once.
Note
We recommend that you renumber the entire design instead of sections. This way
duplicate reference designators are not introduced into the design.

Post Processing
Once the Renumber Reference Designators command completes, the reference designator
changes are back annotated into the schematic.
A file, RenumberRef.txt, is created by Back Annotation and contains the reference designators
changes created by Renumber Reference Designators. You can view this file using File Viewer.
Text Modification using Draw

When the appropriate reference designators have been placed on the parts, in the order desired,
the text may need to be moved and/or rotated to more readable locations.
Using the Text option of Draw, the reference designator text within a cell can be selected and
moved, rotated or resized. For companies whose design specifications state that all reference
designators must be readable and clear of part outlines, this command provides the quickest way
to modify reference designator locations. After entering the command, select the text and move
it to the new location. By default the Placement Outline for the selected text is highlighted.
Generating Silkscreens
Silkscreens are used to easily identify parts on a board. The silkscreen can contain a variety of
data, but usually all contain at least the silkscreen reference designators and silkscreen outlines.
The Silkscreen Generator allows silkscreen graphics to be processed for manufacturing so the
silkscreen material is broken away from Soldermask or Etch pads. This is to ensure silkscreen
does not interfere with soldering processes. Silkscreens are used to easily identify parts on a
board. The silkscreen can contain a variety of data, but usually all contain at least the silkscreen
reference designators and silkscreen outlines.
Note
In order to edit graphics generated by the Silkscreen Generator, the Edit > Modify >
Allow Cell Graphic Edits option must be enabled.
Silkscreen information can be automatically generated and placed it on the silkscreen level.
Using the options you can generate silkscreen with breaks in the lines and text to avoid pads in
the design, thus preventing manufacturing errors resulting from non-conductive ink coming in
contact with the pad area.
The Silkscreen Generator extracts component outlines for buried parts if they exist in the cell,
even if the cell is on the internal layer. It is recommend that you build buried parts using resistor
shapes and not component outlines.
The break sections of the menu allow you to specify how the items are to provide clearances for
pads and by what distance the silkscreen must clear the pads. The purpose is to prevent the

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silkscreen ink, which is non-conductive, from contacting areas where soldering may be
required.
If cells are built in such a way that all silkscreen data does not touch pads, silkscreen generation
can be skipped and Gerber can be processed using the silkscreen reference designators and
silkscreen outlines.
Drill
Drill is used to automatically generate numerical control (NC) drill output for drilling and
routing printed circuit boards (PCBs). The drill output is used to drill the proper size holes in
precise locations on a PCB. You can set an option to predrill holes larger than an entered value
that must be greater than 0.0 and less than 9999.0. Large holes (> .250") can be predrilled with a
smaller drill bit creating a pilot hole. This is helpful to insure that the larger holes location is
drilled accurately.
The drill chart and drill symbols are not associated with the board/panel instance. When
performing any operation (flip, move, delete), use the Group/Ungroup options to get the desired
behaviour. For example, before moving the board/panel instance, group it with drill symbols so
that drill symbols move with the instance.
For those drill machines that support the router option, NC Drill also generates NC profile
router output which can be used to cut slots, make cutouts within the board area and route
boards out of a panel.
If mezzanine capacitors exist in the design they are extracted to a separate drill file
(mezzanine.ncd) as they are depth dependant not layer to layer. The mezzanine.ncd file resides
in the job's ../output/NCDrill directory. The separate drill line entry is placed in the main drill
log file for the mezzanine capacitors.
NC Drill allows you to:
• Extract from the design all drilled and punched holes and routed and punched slots.
• Sort the holes in such a way as to minimize tool movement, tool changes, etc.
• Create files to enable manufacturing to drill and route boards.
• Create charts and reports that summarize the drilling operation.
• Place drill symbols at correct locations in the design.
• Support complex contour output of lines, polylines, polyarcs, rectangles and circles.
• Change the drill manufacturing output format.
The drill executable reads design data from the Layout, Padstack and JobPreferences databases.

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The Layout database contains each instance of thru hole, via, mounting hole and slot, including
its from/to layers, X, Y location relative to the NCDrill origin or, if the NCDrill origin is not
defined, the board origin.
The hole data is sorted so that separate output files can be created for each combination of thru-
holes and via spans, plated and non-plated holes, whether the hole is drilled or punched.
Characteristics of each pin and via, such as hole diameter, plating, whether drilled, punched or
routed, shape (round, square, slot), +/- tolerances and drill symbol assignment are contained in
the Padstack database.
Via span definitions, the number of layers in the design and the design units are extracted from
the Job Preferences database.
Format File Parameters

• Excellon or TruDrill data
• Modal/Non-modal output
• Absolute/Incremental step mode
• Units for drill output files and log file (English(inches) / Metric(millimeters))
• Format of output (number of decimal places before/after the decimal point)
• Zero suppression
• Character Set used (ASCII or EBCDIC)
• Arc style to be used (Quadrant(I#J#), Radius (A#) or None
• Delimiter
• Comments on or off
• String that determines if data is a comment (; for Excellon)
• Comment String
• Sequence Numbering (On or Off)
• Record length
Drill Output Files

The drill output files will be formatted for Excellon drill machines and according to the
parameters specified in the Drill Format File. The files should be identical (except for date/time
info) each time they are generated, assuming no changes were made. This is to prevent the
automatic tests from failing. All files generated in previous runs will be deleted.

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Each resulting file will be optimized by hole diameter and tolerance, and by location using a
shortest-distance algorithm. A tool number will be assigned in each file for each unique
diameter/tolerance combination.
Drill File Naming Conventions

The individual created drill files will use a specific naming convention that includes the layer
range of the hole, type of hole and type of plating, in that order. All drill files will carry a .ncd
file extension, by default. These files should be sent to the board vendor for fabrication. Some
common drill file names are:
• 1-2Plated.ncd
• ContourNonPlated.ncd
• ContourPlated.ncd
• ThruHoleNonPlated.ncd
• ThruHolePlated.ncd
• ThruHolePunchNonPlated.ncd
• ThruHolePunchPlated.ncd
Drill Log File

A log file is created, detailing the total number of holes of each type and layer span, number of
holes per tool as well as a summary for the entire job. Additionally, the log file will summarize
the reading and optimization of data, as well as summarizing the creation of files and charts.
Any errors or warnings will also be output to this file. The log file will be written in the job's
../LogFiles directory and will be named NCDrill.txt. Each output file name and hole summary is
contained in the log file.
Drill Data
The NC Drill data is output in two formats; standard english (default) (drillenglish.dff)
and standard metric (drillmetric.dff). These files can be copied to a new filename
(.dff extension) that can then be modified.
Note
If the data is set to one of the standard WG2002 *.mmm files, the system will
automatically map to the equivalent new file.
A drill chart for all thru-holes and each via span will be placed in the design when the setup is
complete. The drill chart will be formatted according to the specified, selected columns and
order.

Post Processing
Additionally, drill symbols will be placed in the vicinity of all holes that must be drilled,
punched or routed. For drilled holes, punched holes and punched slots, the drill symbols will be
centered over the hole or slot origin. For drilled slots, the drill symbol will be placed at the edge
of the slot where the drill bit will initially be drilled because the slot will be "routed" with the
drill bit.
In the output files created for the drill machine, the holes to be drilled are grouped smallest to
largest according to size. This grouping allows holes of the same size to be drilled before
changing the drill bit for other hole sizes. This greatly reduces the `dead' time that is required
when drill bits are changed.
The drill software removes any duplicate holes at the same X, Y coordinate, eliminating all but
the hole with the largest diameter. This ensures that the drill machines do not drill the same hole
more than once if holes are accidentally placed on top of each other in the design file.
Eliminating duplicate holes helps prevent the drill machine from breaking drill bits and
produces a more accurate printed circuit board.
Drilling time is further reduced by optimizing the movement of the drill head. Each group of
holes (each of the same size and requiring the same drill bit) are sorted according to their
location on the board. Board optimization is continuous, which causes the drill head to move
along a sweep axis within a specified bandwidth until it reaches the edge of the board. The drill
head then moves to the next axis and drills in the opposite direction.
The following figure shows an example of a drill drawing that is placed in the design.
Figure 3-32. Drill Chart
Through Holes
All Drills (unless specified) +/- 0.0000 (in)
Diameter (in) Quanity Hole Name Tolerance (in) Plated

0.0380 28 Rnd 38 +0.050 / -0.0030 Yes
0.1250 2 Rnd 125 =/-Tol 5 +/- 0.0050 Yes
0.1250 1 Rnd 125 +Tol 3 -Tol 0 +/- 0.0050 N0
0.0620 1 Rnd 62 +/- Tol 3 Non-Plated +/- 0.0030 No
The diameter column contains the hole dimensions and rotation. The rotation is indicated by a
capital "R" followed by the rotation angle. For example, 0.0300 R45.
If a hole is a square punched hole and there are many rotations in 90-degree increments, all of
those rotations will be seen as zero because the rotation of zero is equivalent to 90, 180 or 270.
However, if you have a square hole that is rotated at some other increments that are not
equivalent, then those holes will be listed separately. For example, if a 22.5 degree rotation and
a 45 degree rotation of the same hole are found, those holes will be listed separately.

Post Processing
Holes that are actually slots are treated differently depending on whether the slot is specified as
"drilled" or "punched" in the padstack. If the hole is drilled, the drill diameter will be specified
and no rotation will be seen because the drill will be converted to contours, which only use the
drill diameter. However, if the slotted hole is "punched", then the height, width and rotation
angle of the punched slot will be seen in the drill chart.
The same rotation principles are used for slotted holes (punched versus drilled) in the drill
output files.
The drill chart units are in either MM (millimeter) or IN (inches) and are determined by the
Units value. It is important to note that the drill chart units can be different from the generated
output file units. This enables you to create drill output files in the formats that different vendors
prefer without having to create a new drill table. The precision of the drill chart is determined by
the Precision value in the NC Drill Generation dialog.
Gerber (274X)
When the design is complete, the next step in the design process is the creation of Gerber output
data. The Data Type can be either 274X (default) or 274D. This information is sent to a
photoplotting vendor who provides artworks. The artwork is what is used to actually create the
physical printed circuit board.
Gerber output data is created in Expedition PCB via the Gerber Output command. Gerber
requires that a valid Gerber Machine Format File has been created. This file determines the
format of the Gerber data that will be produced. D-Codes are assigned to Pads and draws on the
fly. If a flash cannot be generated for a pad, the pads will automatically be drawn during Gerber
output. To generate Gerber, select the Process Checked Output Files button.
Header and Trailer

If desired, you may also specify comment text, to appear either in the header, trailer, or both. Up
to 128 character lines may appear in each of these comment sections. This field can be used to
show the job name, company name and/or date.
Defining Screen Contents

Once you have defined each gerber filename that will be created the Contents tab allows you to
define the graphics objects that make up these files. Typically, each gerber file consists of a set
of elements that is used to manufacture your printed circuit board. You should generate one file
for each route layer within your design, and one file for each of the following: top and bottom
soldermask pads, the top and bottom solderpaste pads, the top and bottom silkscreens, the drill
drawing and the assembly drawings.

Post Processing
Gerber (274D)
Follow the steps below to generate gerber in 274D.
1. Copy the delivered ..\config\VBExpPCB\sample.dmf file to your job's ..\config

directory to create your <new>.dmf file.
2. In Expedition PCB, from the Setup pulldown, select Gerber Machine Format and create
a new file with 274D as the Data Type.
3. In Expedition PCB, from the Output pulldown, select Gerber. Create or select a Gerber
Plot Setup file (.gpf). Create and define the output files to be processed.
4. In the Gerber dialog, bottom left corner, verify that the new Gerber Machine Format file
with 274D Data Type is attached. If not, browse for and attach.
5. In the Gerber dialog, in the D-Code Mapping File section browse for and attach your
<new>.dmf file to each output file to be processed.
6. In the Gerber dialog, choose either Flash or Draw Pads for each output file to be
processed.
7. Toggle ON each check box for the layers to process and then select the Process
Checked Output Files button.
An error message appears if your job specific apertures haven't been defined in your
<new>.dmf file.
8. Invoke File - File Viewer and review the log file "GerbPlot.txt" which lists all the
necessary D-Codes for each layer processed.
9. Update your <new>.dmf file with the required D-Codes and then process your gerber.
Notes
1. A D-Code Mapping File (.dmf) is required when using 274D output.
2. A .dmf file requires D-Codes for "all" the apertures in the design.
3. Use the Flash/Draw option to specify whether to flash or draw all the pads for a layer in
the output.
Custom Pads
274X
Drawn - Using the (Automatic) D-Code Mapping File option in the Gerber Output dialog the
custom pad are drawn in the output.

Post Processing
Flashed - Using a D-Code Mapping File (.dmf) in the Gerber Output dialog specify the D-Code
using the .Custom option and the custom pad are flashed in the output.
.Custom ..Dcode 100 ..Name "Smiley Face 30 x 35" ..Angle 0
274D
Drawn - Using a D-Code Mapping File (.dmf) in the Gerber Output dialog exclude the D-Code
for the custom pad and it are drawn in the output.
Flashed - Using a D-Code Mapping File (.dmf) in the Gerber Output dialog specify the D-Code
using the .Custom option and the custom pad are flashed in the output.
.Custom ..Dcode 100 ..Name "Smiley Face 30 x 35" ..Angle 0
Gerber Machine Format

This command is used to define the method in which the plotter interprets and plots design
information. The data type can be in either 274X or 274D format. It is important to know your
plotter's capabilities when setting up your Gerber device. Failure to setup the device properly
can cause inaccurate results.
The Gerber Machine Format file contains the flashes and draws of your design data that is used
to generate manufacturing artwork and is referenced by Gerber Output.
Gerber Machine formats are not translated from a previous version of PCB. Any previous
Gerber formats have to be redefined.
You can select the Polygon Fill Method to be either Raster or Draw. Raster uses raster fill to
create the data with "sharp" corners. Draw uses vector fill to create the data with drawn or
"rounded" corners. Raster is only available for the 274X data type.
Caution
Although the setting in the dialog is Draw, the example file displays STROKE. If hand
editing the file, STROKE must be the entry or the format will be invalid.
General Interfaces
Expedition PCB supports the following outputs via the General Interfaces dialog. This data then
can be used by third party software to do manufacturing verification, thermal analysis and
manufacturing outputs.

Post Processing
Hyperlynx Thermal
This command produces an output file that is compatible with HyperLynx. The output filename
is HyperLynxOut.txt.
Generic AIS and Generic ATE

Individual Automatic Insertion Systems and Automatic Test Equipment Systems are not
addressed by Expedition PCB. However, the system generates a generic output for both of these
type CAM systems. Once these generic ASCII files have been created, they can be edited via a
text editor to meet the specific needs of your company’s individual CAM systems. The output
files generated are vb_ate.txt for ATE and vb_ais.txt for AIS.
Mitron GenCad
This command produces an output file that is compatible with the Mitron CIMBridge
manufacturing framework system. This allows machine development via CB/Pro and test
development via CB/Test. The output filename is gencad.cad.
Fabmaster
The Fabmaster command produces output files which can be used with the Fabmaster package.
General Interfaces outputs the same log file, generalinterfaces.txt, every time one of the options
is selected. A <design_name>.fab file is also generated and can be located in the design's
../PCB/Output directory.
The supported version of Fabmaster, at board level only, is FATF Rev 1.2.
C-Link
The C-Link command produces output files which can be used with the C-Link package.
is selected. Two additional files are created in the design's ../PCB/Output directory:
<design_name>.dif and TESTFILE.PSH.
The supported version of C-Link, at board level only, is Version 4.0.
Detailed Views
Detailed views are user-defined areas of the board that can be scaled to clearly show design
detail to create customized documentation details. Detailed views have their own scale factor,
can contain specific Display Control settings and are read-only.
Note
There is a limit of 250 detailed views within any one design.

Post Processing
The only manipulation within a detailed view is the addition of text, dimension data and
graphics. Any manipulation should be created on a user-layer defined in Setup Parameters.
Caution
If a dimension is added to a detailed view, after exiting and reopening a design, the
association is lost.
The detailed view can be placed with cursor data points. When placing the detailed view, you
have the following options: polygon, rectangle or circle. You can select the drawing option
from the Draw toolbar which displays automatically. The Draw Properties dialog changes to
reflect the chosen drawing option.
Detailed views may be moved anywhere within the design plane, including the board area or
outline. The detailed view always displays on top and if placed within the board outline, the
design data may be hidden.
A copied detailed view numerically increments the last placed detail view name. This can then
be edited and the displayed layers in Display Control can be changed. The Display Control >
General Tab displays the viewable layers within the detailed view.
If the detailed view is included within the selected plot are, the information is plotted as any
other element within the design. Detailed views are WYSIWYG, therefore you should display
the elements and layers within the detail view prior to plotting.
Annotation Mode
Annotation mode is accessed by clicking the left mouse button within the scratch pad. The
scratch pad border turns red and the design displays in shadow mode. This mode allows you
access to the dimension, text and graphic placement commands. The Properties Text options are
only allowed within the annotation mode.
Dimension data within the detailed view is stored on the selected detailed view layer and is
placed within the scratch pad area. Applying dimension data is only available in annotation
mode.
To return to modification mode select the scratch pad border. To exit from annotation mode,
either select anywhere in the design or select the right mouse button and click Exit from the
popup.
Modification Mode
Modification mode allows you to change or modify the following parameters: name, scale,
mirror, rotate and font by single-clicking in the detailed view area.

Post Processing
Example
The Detailed View source rectangle is the selected user-defined area or boundary within the
design file that is displayed as a detailed view. This area can be a polygon, rectangle, or a circle
selected from the Draw commands menu, however, the source area displays as a rectangle. This
source rectangle is displayed over the layout of the design. This area is modifiable to the extent
that it can be increased/decreased in size without changing the scale and this allows it to
increase the volume without having to recreate it.
The purpose of the scratch pad is to allow an area for additional associated data such as
dimension data, text and graphics. The scratch pad area is only modifiable from within the
detailed view. Selecting the detailed view and then a handle allows you to enlarge the area.
Scratch pads may overlap.
The scratch pad can be modified or stretched only when in modification mode. When increasing
or decreasing the viewed area, the scratch pad changes; the selected area or design view does
not. The scratch pad area cannot be modified smaller then the detailed view area.
All additional data is placed on a user-specified layer. It is recommended, prior to the creation
of a detailed view, that user layers are defined and logically named.
Plotting - Archive Plots

When the design is complete and has been approved, it is time to prepare the files for archive.
For most companies, this means preparing some type of archive prints or plots. The
documentation is created and signed by the appropriate people, usually the design engineer,
CAD manager, CAD designer and the Checking department.

Chapter 4
Circuit Move and Copy
Using a selection filter you can select a region of circuitry in a design and copy it to a common
clipboard. This makes the data accessible at any time during an editing system. The stored
layout data is then used to replicate the exact layout data in either a new design or the host
design.
When Circuit Move and Copy is applied to a circuit from within the RF toolkit (license
required), the copying and moving of circuits containing RF shapes is supported. When Circuit
Move and Copy is applied to a selection outside of the RF toolkit without an RF license, RF
elements are Read Only.
The default clipboard is stored on the hard disk in the user temp directory (\Local
Settings\Temp\mgc_icc_clipboard) on a PC and in /tmp on UNIX. You can set an environment
variable (MGC_LAYOUT_CLIPBOARD_PATH =<user defined path>) to define a different
location for the layout clipboard directory.
Caution
Circuit Move and Copy does not copy constraints or constraint data to the clipboard. The
connections in the new copy inherit the net constraints that already exist in the constraints
database for those nets. The layout circuit that is pasted form the layout clipboard inherit
the net constraints that already exist in the host design.
After the objects are selected, you can access the action keys to Move (F2), Rotate 90 (F3),
Rotate 180 (F4) or use the options on the popup that displays when you click the right mouse
button.
Parts selected using the Selection Filter display in the Find > Part tab and selecting parts in the
Find > Part tab synchronizes selection in the Selection Filter.
Caution
The Edit > Circuit Move and Copy command is available when DRC Off is active. The
DRC Off selection is on the Editor Control > General tab.
If the selected objects do not include a part object, they are moved at the physical center of the
extents of the selected objects. If the selected objects include any part object(s), they are moved
at the physical center of the extents of the selected part object(s).
You can use the Instantiation Wizard to automatically map all equivalent parts in the host
design. This dialog displays even if all the parts were automatically instantiated, allowing you to

General Methodology for Copy & Paste
browse the list of devices and verify the mapping. If there are parts in the copy circuit that have
not been automatically associated to parts in the local design, this dialog lets you manually
assign equivalent parts.
With a Move operation, a warning dialog displays indicating that Xtreme protected areas are
Read Only. With a Copy operation, Xtreme protected areas are copied along with their
parameters: handle, layer and assignment.
General Methodology for Copy & Paste

1. Invoke Circuit Move & Copy command
2. Define selection area around circuit to be copied.
3. [Optional] Use Selection Filter to determine which objects are to be included.
4. Select the Copy to Layout Clipboard.
5. Remain in local design or open another design.
6. Select Paste from Layout Clipboard command.
7. [Optional] Use the Instantiation Wizard to map unassigned parts.
8. Place copied circuit into layout.
Moving Circuits
1. Select Edit > Circuit Move and Copy. The Selection Filter dialog displays and the status
bar displays the name of the selected object or if multiple objects were selected, the total
number of selected objects. Two options on the Selection Filter dialog allow you to
Select All or Clear All objects or layers.
2. Select the Object tab and check the required object(s).
3. Select the Layer tab and check the required layer(s). To view information about the
selected objects, click the right mouse button and from the popup select Selection List.
4. Select Move from either the F2 function key or right-mouse click popup. The following
changes are seen within the display window:
If a part that is selected is contained within a Group, a message displays warning you
that all parts of the group will be affected. You have the option of cancelling the Move
and re-selecting objects or you can accept, which results in the entire grouping being
moved.
• The cursor is attached at the physical center of all selected objects.
• The cursor changes to a four-arrow Move cursor.

Copying and Pasting Circuits
• All selected objects are displayed in motion graphics.

• Only the F3 Rotate 90 and F4 Rotate 180 action keys are available when in Move
mode.
5. If required, rotate the objects using commands from either the F3 or F4 function key, the
right mouse button popup or the rotate keyin. All selected objects rotate as a complete
group.
r delta angle. You must select the Enter key if you are using the keyin for the angle to be
applied to the selected objects.
6. Before placing the objects, you can select snap point options from the right mouse
button popup.
7. Place object(s).
Copying and Pasting Circuits

1. Select Edit > Circuit Move and Copy.
2. Select object(s) using the basic selection techniques. You can select the objects before
accessing the command. The Selection Filter dialog displays and the status bar displays
the name of the selected object or if multiple objects were selected, the total number of
selected objects. Two options on the Selection Filter dialog allow you to Select All or
Clear All objects or layers.
3. Select the Object tab and check the required object(s).
4. Select the Layer tab and check the required layer(s). To view information about the
selected objects, click the right mouse button, and from the popup, select Selection List.
5. If required, rotate the objects using commands from either the F3 or F4 function key, the
right mouse button popup or the rotate keyin. All selected objects rotate as a complete
group.
r delta angle. You must select the Enter key if you are using the keyin for the angle to be
applied to the selected objects.
6. Use Ctrl + C to copy and Ctrl+V to paste. The Instantiation Wizard appears.
Deleting Objects
Using either the Delete key or the Delete icon, you can remove selected objects while in Circuit
Move and Copy. This can be used to clear space in layout for a circuit to be placed.
1. Select Edit > Circuit Move and Copy.

2. Select object(s) using the basic selection techniques. You can select the objects before
accessing the command.

Differences between Copy Circuit and Circuit Move and Copy
3. Select either the Delete key or the Delete icon. A warning dialog appears asking you to
confirm the removal. Selected parts are unplaced and all other items (trace, vias, draw
objects) are removed from the design.
Differences between Copy Circuit and Circuit

Move and Copy
Copy circuit, by default, does not account for any unrouted connections (logic netlist) between
the pins of the circuit. Only routed pin-to-pin connections are considered. For unrouted parts,
the circuit is viewed as a set of parts with no connections between them and these sets of parts
can be matched with other set of parts, even if the connections between the "instances" differ.
Circuit Move and Copy, by default, accounts for all connections to the circuit part pins (all
logical connections) and accounts for both routed and unrouted connections.
If Circuit Move and Copy sees that the netlist definitions are different, it views those circuits are
not equivalent and automatically excludes several parts to find a partial solution / circuit that
matches the netlist definitions of the circuit.
Objects that are not allowed to copy in Circuit Move &

Copy
The following objects are not copied using the Circuit Move & Copy command.
1. Virtual and Guide pins

2. Target Areas
3. Bus Paths
4. Any data in generated copper balancing shapes

5. Non Electrical Shapes - DRC window
6. Non Electrical Shapes - Room
7. Fabrication Layers - Redline Layer
8. Fabrication Layers - Material mask and Material overglaze
9. Dimensioning has limited support. An object with its associated dimensions can be
copied.
Alternate Cells
For a cell to be used by a particular device, it must be referenced by the local parts database; as
a Top, Bottom or Alternate cell. By default, the Instantiation Wizard must select the same cell to

place in the host design as the one used in the source layout. For example, if the source layout
part is using an alternate cell, then this same cell name must be used in the equivalent host
circuit. Even if the part is already in layout, it must be changed to match the one referenced by
the source design.
Cell Name Mismatches

There may be situations where the source part has been modified to reference a cell that is not
used by the local part in the host design. In other words there is a discrepancy between the two
layout libraries. Expedition PCB requires that parts can only use cells that are referenced by the
part in the local design Parts library.
The Report file indicates when this situation occurs. For example, part RES50R in the source
uses a cell called 0805R. In the host design this cell is not referenced at all; instead the local part
references 0805RES. The Instantiation Wizard must use the local Top cell for the part mapping.
Part Placement Criteria

By default, equivalent local parts are only used for placement if their current state is Unplaced
or Distributed (outside the board outline). Parts that are already placed inside the board outline
are ignored when placing the new circuit layout.
Multiple Equivalent Circuit Instances

If multiple instances of the copied circuit exist in the host design then as each circuit instance is
placed the Instantiation Wizard is displayed allowing you to instantiate and place the next
circuit.
You can cancel the paste operation and return to the Paste from Layout Clipboard command at a
later time to place the remaining circuits. There may be situations where the layout clipboard
data is cleared or overwritten by another copy circuit operation. In this case, you will have to
recreate the original copy circuit in order to continue pasting the remaining instances.
Via Span Definitions

Via span definitions are automatically copied from the clipboard layout if they do not exist in
the local design. Setup Parameters is automatically updated to reflect any new via span that is
required in the design. The log file reports on new via spans that have been added to the design.

Multiple via objects structures are maintained when pasted into the local design; multiple via
objects definitions are NOT copied. You must add the new multiple via objects definitions to
the ASCII MVO_Rules.txt side file.

Plane Shapes and Net Assignments

Plane shapes can be automatically mapped to plane nets in the host design if they touch
associated part pins. For a net to be automatically mapped to a host net, it must contain at least
one part pin connection. All other objects that are in the clipboard and associated to this net are
also automatically mapped.
A net in the clipboard is treated as floating if it does not contain any part pins and therefore is
not automatically mapped to a host design net. These nets must be manually mapped.
Rule Area Scheme Assignments

When rule areas are pasted into the local design from the layout clipboard the original scheme
name assignments are preserved so long as the same scheme exists in the local design. If the
scheme name does not exist, the rule area is reassigned to the (Master) rule scheme.
You must add new equivalent schemes to the local design constraints database (CES) if they do
not already exist.
Rooms and Clusters

Rooms are not copied between designs using the Move & Copy Circuit command; therefore
room and cluster assignments are not maintained.
Mounting Holes
Mounting holes can be automatically mapped to nets in the host design if the net is connected to
a part pin in the clipboard.
A net in the clipboard is treated as floating if it does not contain any part pins and therefore is
not automatically mapped to a host design net. These nets must be manually mapped.
Virtual Pins and Guide Pins

Virtual pins and guide pins are not supported.
Test Points
By default, test point reference designators are preserved when copying between designs.
However, where duplicates are found in the local design, new references are assigned to the
copied test points to prevent conflicts with existing data.

Using Find with Circuit Move and Copy
Jumpers
By default, jumper reference designators are preserved when copying between designs.
However, where duplicates are found in the local design, new references are assigned to the
copied jumpers to prevent conflicts with existing data.
The jumper settings in Editor Control are updated with matching jumper settings from the copy
circuit design if they do not already exist in the local design.
Using Find with Circuit Move and Copy

Selecting parts using the Selection Filter in Circuit Move and Copy allows synchronization with
the Part tab of Find; selecting parts in the Find > Parts dialog synchronizes in the Selection
Filter. The Highlight option of Find does not simultaneously occur between the Find dialog and
the Selection Filter of Circuit Move and Copy.
Using in conjunction with the Circuit Move and Copy area extent control options you can select
parts using the Find dialog and extents the selection to include traces and parts.
Circuit Clipboard
This allows you to manage multiple clipboard circuits. This makes the data accessible at any
time during an editing system. The stored layout data is then used to replicate the exact layout
data in either a new design or the host design. There is no limit to the number of clipboard
objects that can be stored.
The default name of the circuit is based on the original source PCB design name (.pcb) but this
can be renamed. Subsequent clipboard designs from the same board name will have a numerical
extension appended to the name to avoid directory conflicts (_01 for the second instance, _02
for the third and so on).
Result: The multiple clipboard directory is located at a different location to that of the single
clipboard directory used with the Copy to Layout and Paste From Layout clipboard. Circuit data
that has been copied to the single object clipboard is not available from the Multiple Clipboard
Object dialog. The default multiple clipboard is located by default in the
%USERPROFILE%\Local Settings\Temp\mgc_icc_mco directory.
Caution
A Reuse license is required to enable the Circuit Clipboard functionality. The license is
available from the splash screen or from within the application by selecting Setup >
Licensed Modules > Reusable Block.
1. Enter Circuit Move and Copy mode.

2. Select circuit data.

Selection List
3. Select Circuit Clipboard from the RMB popup. You can select Circuit Clipboard first
and then select the circuit.
4. Select the Copy button on the dialog.
You can use the Browse icon to open an existing or define a new clipboard location. The default
location is the %USERPROFILE%\Local Settings\Temp\mgc_icc_mco directory.
When the circuit is selected, the name of the design is loaded into the Copy Circuit Name field:
this can be renamed. You can use the Delete icon to remove a selected circuit.
The creation date field displays the date and time this circuit was copied.
The User Name field displays the username and name of the machine that generated the copy.
An informational message displays if there were problems and directs you to the
PasteCircuit.txt file. This file can be viewed using File > File Viewer.
Retrieving a Circuit
1. Enter Circuit Move and Copy mode.
2. Select Circuit Clipboard from the RMB popup.
3. Select the required Copy Circuit Name.
4. Select the Paste button on the dialog.
5. The Instantation Wizard is launched and an attempt to find an equivalent circuit in the
local design is made. An informational message displays if there were problems and
directs you to the PasteCircuit.txt file. This file can be viewed using File > File Viewer.
6. Paste the equivalent circuit in the design.
Selection List
This dialog displays a complete non-editable listing of all the items (parts, pins, traces, vias)
selected to be moved. Whenever the RF toolkit is invoked, the current selection is removed.
You can use either Ctrl + left mouse button to select additional single rows or Shift + left mouse
button to select multiple rows. If a description is not available, the column entry is left blank.
The total number of objects that are presently selected for moving, and the number of objects
that are currently highlighted in the dialog displays at the bottom of the dialog.

Selection List
Table 4-1. Selection List Options
Object Displays the selected objects.

When a part is selected only the part itself displays; the
objects of the part are not displayed, outlines, pins,
shapes, etc.
Name Displays the name of the selected object (reference
designator or via name).
Description Displays the description of the object.
Net Name Displays the net name(s) associated to the object
Net Class Displays the net class name associated to the object.
Layer Displays the layer(s) on which the object is associated.
Length Displays the overall length of the object.
Width Displays the overall width of the object.
Fit View All selected objects on every selected row are fitted in the
graphic view.
Blink It The object(s) in the selected row flash on and off (blink)
three times.
Define Sort Order Displays a number within each column header (from left
to right) from 1 to 8. In the dialog box's message field, the
following appears:
Click on column to set order: #
Starting with number 1, you can prioritize the order (from
left to right) in which the columns display. While defining
this order, you may either:
Select the order of each column from start to finish or if
you only want to order a few columns, you can click the
Complete sort order button after completion.
Result: The order is saved in the JobPrefsDB2HKP.txt file
for future design sessions.
Remove from Selection Removes any highlighted row(s), and deselects the
object(s) from being included in the Move.
Close Dismisses the dialog.
Table Associations
Pos = displays the absolute (X, Y) location of the object's origin.
Draw Sub-type = Displays the Draw object type (i.e. Draw Object, Test Point Obstruct, Rule
area).

Selection List
Table 4-2. Table Associations
Object Name Desc. Net Net Layer Length Width

Name Class
Conductiv N/A Pos = Name NC Where Overall Overall
e Shapes found
Design Board Outline, Pos = N/A N/A N/A N/A N/A
reference Manufacturing
Outline, Route
Border
Draw Sub-Type Pos = N/A N/A Where N/A N/A
found
Fiducials / Padstack Pos = Name N/A Range Pad Pad
Mounting Name Diameter Diameter
Holes
Multiple Via Pattern Pos = Name NC Layer Overall Overall
Via Span
Parts Ref Des Device Name N/A Where Overall Overall
found
Pins Pin Number Pos = Name NC Layer N/A N/A
Plane N/A Pos = Name NC Where Overall Overall
Shapes found
RF Group Group Name Pos = N/A N/A N/A N/A N/A
RF Node Parent Name Pos = Name NC Where
found
RF Parent Name Pos = Name NC Where Overall Overall
Segment found
RF Shapes Ref Des Pos = Name(s) NC Where Overall Overall
found
Teardrops Teardrop Pos = Name NC Where N/A N/A
Breakouts Breakout found
Test Ref Des Pos = Name NC Where Overall Overall
Points found
Text N/A Pos = N/A N/A Where Text L Text W
found
Traces N/A N/A Name NC Where Overall Greatest
found Width
Vias Padstack Pos = Name NC Range Pad Pad
Name Diameter Diameter

Selection Filter Layers
Multiple Via Objects Usage

Multiple via object data structures are supported in Circuit Move and Copy operations. The
multiple via object is controlled by the vias object checkbox in the Selection Filter dialog. Each
multiple via object is treated as a separate entity; it is identified in the Selection List by a single
line item instead of listing all of it's parts, therefore, the Selection List does not list the
individual conductive shapes and vias that form the multiple via object.
Object Displays Multiple Via.

Name Displays as the via pattern; 2x6.
Description Displays the x and y position; Pos=1.275, 1,050.
Net Name Displays the net name to which the multiple via object is
connected; GND.
Net Class Displays the net class name associated to the net.
Layer Displays the multiple via object layer span; 1-4.
Length Displays the length of the longest side of the multiple via object.
Width Displays the length of the shortest side of the multiple via object.
Limitations
If a circuit being moved or pasted from the clipboard has non-round vias, it can only be rotated
in 0, 90, or 270 degree increments. This limitation also applies to the rs < angle> and r <angle>
keyins. Rotations other than stated, display a warning message stating that the rotation is invalid
as the circuit contains multiple via objects.
Selection Filter Layers

When the Circuit Move and Copy option is selected, this dialog appears with all checkboxes
selected by default. The Close button saves the settings within each tab, and dismisses the
dialog.
The Layers tab allows you to select/unselect the individual layers of the design. As all
checkboxes are selected by default, you can quickly select only the required layers by selecting
the Clear All button and then manually checking the layers. The Select All button quickly
selects all layers. The order that the layers display is:
1. All of the conductive layers are listed first in a top-down order.

2. Then the fabrication layer pairs (Top and Bottom) for assembly, silkscreen, soldermask
and solder paste. Selecting these layers allows you to select and move objects not
associated to a part or cell.

Selection Filter Objects
3. Lastly, any user-definable layers are displayed in an alphabetical, top-down order. These
are the layers that are displayed in the Setup Parameters > General > Layers > User
defined layers section.

When the Circuit Move and Copy option is selected, this dialog appears with all checkboxes
selected by default except for Design Reference. The Close button saves the settings within
each tab, and dismisses the dialog. All available objects are displayed alphabetically. You can
quickly select only the required objects by selecting the Clear All button and then manually
checking the objects. The Select All button quickly selects all objects.
All package, mechanical or drawing cell database elements and layers are grouped as a part
object. When any part is selected, everything associated with that part (whether it is visible or
not) moves. Conductive shapes are displayed when you select both the Display Control > Layer
> Traces checkbox and the physical layer that the shape was drawn on. Conductive shapes are
created using the Edit > Place > Conductive Shape command.
Design Reference Objects

If the Design Reference setting is selected in the Object Tab, items such as the board outline,
board and NC Drill origin, route border and manufacturing border may be manipulated. A
dialog displays asking you to confirm the selected action for these items, and if accepted, the
existing board items are replaced.
Caution
In the case of the board and NC Drill origin, there is no Undo available for the move or
copy.
The following commands affect the board outline, board and NC Drill origin, route border and
manufacturing border.
• (F2) Move
• Dialog Message: Please confirm the MOVE action for the following items.
• (F3) Rotate 90; (F4) Rotate 180
• Dialog Message: Please confirm the ROTATE action for the following items.
• (F5) Push
• Dialog Message: Please confirm the PUSH action for the following items.
• (F6) Change Layer.
• Dialog Message: Please confirm the CHANGE Layer action for the following items.

• (F7) Copy Circuit.

• Dialog Message: Please confirm the COPY CIRCUIT action for the following items.
• Edit > Copy to Layout Clipboard
• Dialog Message: Please confirm the COPY to CLIPBOARD action for the following
items.
• Edit > Paste from Layout Clipboard
• Displays the Instantiation Wizard > Ref Des Tab.
Part Selection
Part is checked Selecting any segment of a part (outline, pin, a shape, embedded into a cell,
mounting hole, embedded fanout trace or via) causes the part to be selected.
Other settings in the selection filter dialog, such as traces, shapes and vias
do not affect selection of parts. For example, if only the Part option is
checked, selection of any item within the part object results in the selection
of the entire component - even when traces and vias are not checked in the
Selection Filter dialog.
Teardrops and Breakout Traces - These can be selected and can be moved or
copied without the associated traces and pads being selected, however, they
cannot be moved or copied and pasted without the associated trace and/or
pin or via.
Plane Shape, Actual Plane Shapes and Tie Legs - These can be selected,
moved and rotated. Copy and paste operations only support input plane
shapes.
Restriction: Actual plane shapes and tie legs are not copied to the clipboard.
Part is Selecting any segment of a part (outline, pin, a shape, embedded into a cell,
unchecked mounting hole, embedded fanout trace or via) will not cause the part or the
part objects to be selected. Other settings in the selection filter dialog, such
as traces, shapes and vias do not affect selection of parts.
For example, with only the Traces option checked, selecting the embedded
fanout trace will neither cause the selection of the embedded trace, nor the
selection of the part or any of the part's items.
Dimension Objects
These are a set of draw objects, comprising arrows, lines and text that are associated to a other
design objects such as mounting holes, pins, board outline etc. When an object the dimension is
associated with is moved or modified, the dimension also moves, reflecting the new position.
Dimensions are not selectable in Circuit Move & Copy commands and so are not supported in
the Copy to Layout Clipboard operations.

Copy to Layout Clipboard
Selection Filter Outside RF Toolkit

The Selection Filter outside the RF toolkit only contains the RF Groups checkbox. RF Shapes
cannot be manipulated individually without the RF toolkit. Only the entire RF Group is allowed
for the operation. If Circuit Move and Copy is invoked within the RF toolkit, RF shapes can be
manipulated individually. The Selection Filter will also have both the RF Shapes and RF
Groups checkbox.
Multiple Selected Objects Priority

To handle situations when multiple objects are located in the same position a priority order is
used. The priority order determines which object gets selected or accessed first, second, third
and thereby also determines what action to perform if any. You can step through multiple
objects using the TAB key.
The priority can be changed through a configuration file, DefaultSelectionFilterPriority.cfg.

This file is located at %SDD_HOME%\standard\config\pcb\ and must be a plain ASCII file.
Note
To apply changes from the configuration file the application needs to be re-started.
Example SelectionFilterPriority.hkp File

• ConductiveShapes 6
• Parts 4
• Pins 2
• PlaneShapes 7
• RFGroups 11
• RFNodes 1
• RFSegments 5
• RFShapes 3
• Traces 8
• Vias 9
• Netlines 10
Copy to Layout Clipboard

If the Design Reference filter setting is checked in the Selection List > Object tab, items such as
Board Outline, Manufacturing Outline, Route Border and Board and NC Drill Origin may be

Instantation Wizard
manipulated using the action keys but you are asked to confirm the action. If you accept, the
existing board items are replaced. You can use Ctrl+C to copy to the layout clipboard.
Note
The Undo action is lost if the board and/or NCDrill origins are moved or copied.
The default clipboard is located by default in the %USERPROFILE%\Local

Settings\Temp\mgc_icc_clipboard directory. You can change this location by setting an
environment variable:
MGC_LAYOUT_CLIPBOARD_PATH=<user defined path>
Note
To avoid copy and paste conflicts, the single clipboard directory will be in a different
location to that of the multiple clipboard directory. Circuit data that has been copied to
the single object clipboard is not available from the multiple Circuit Clipboard dialog.
The following conditions display this dialog:
1. Edit > Copy to Layout Clipboard is selected.

2. Design Reference is checked
3. One or more design reference objects are selected.
4. One of the following commands is selected from either the action keys or the popup.
Appropriate messages display in relation to the action selected:
Action Keys: (F2) Move, (F3) Rotate 90, (F4) Rotate 180, (F5) Push, (F6) Change Layer
(F7) Copy Circuit.
Additional Commands from the RMB Popup: Mirror Horizontal, Mirror Vertical, Copy
to Layout Clipboard, Paste from Layout Clipboard.
Instantation Wizard
Equivalent circuitry is matched using the following criteria:
Connectivity - The matching algorithm searches for connectivity patterns in the host
design that match the clipboard layout. The net names do not have to match.
Part Numbers - Looks for parts in the host design that match.
The default operation is for the Instantiation Wizard to automatically map all equivalent parts in
the host design, however, where connectivity in the host design differs from the clipboard
circuit you can manually assign the equivalent nets through the dialog. If you selected design
reference as an object on the Selection Filter's Object tab, the F7 Copy Circuit option, displays

Instantation Wizard
within the Board Outlines Selection dialog. You can use Ctrl+V to paste from the layout
clipboard.
It is possible to ignore unresolved parts during placement. There will be situations where the
local design does not contain all the data that exists in the clipboard layout. You can also force
selected parts to be unmapped even if they do exist in the host design.
The Instantiation wizard identifies these unresolved parts but still allows the circuit to be placed
and only include the matched parts. When the OK button is selected, a warning dialog appears
informing you that some parts have not been resolved and it allows you to continue placing the
circuit or cancel and return back to the Instantiation Wizard to resolve the problems manually.
The Show Report button displays an ASCII report on the found problems.
The following set of instantiation rules has been implemented.
1. The basic matching procedure will never find a match where a circuit net is split or
merged (in found instance), except for single-pin nets.
2. If the net is a single-pin circuit net in the circuit definition it incorporates only one
component pin. Within the whole design the net may (and typically does) incorporate
more than one pin even if it is a single-pin net in circuit definition. The matching
procedure is allowed to merge single-pin circuit nets with other single-pin circuit nets.
In the cases of merging of an interface circuit net with a global net used in circuit and the
merging of global nets, you would use the Instantiation wizard > Nets tab to make
manual assignments. For example; you could map signals A2, A3 and GND of the
circuit net to net GND in host design.
For instances where split net situation are really required the matching results in a partial
match. The components that hold nets to be split are excluded from instantiation
(unmapped). They are marked unmapped in the Instantiation Wizard allowing you to
manually assign them and re-run instantiation.
3. Matching procedure allows a match where the equivalent net in the found instance is
larger (contains one or more additional pins). This match is also true for private nets.
Instantiation Wizard Ref Des

The Ref Des tab is where parts from the source design can be assigned to specific components
in the host design. The list can be sorted in ascending or descending order depending on the
column header selected.
If there are unresolved mapping errors, warning dialogs are displayed upon either selecting
Resolve, OK or another tab.

Instantation Wizard
• Unmapped components found (red) ñ There is a component in the clipboard circuit that
has not been mapped to an equivalent part in the host design. The possible causes for
this could be:
• That the part does not exist in the local design and the matching engine did not find a
solution. You may want to verify if it is alright to ignore the message and continue with
the instantiation, or use the Wizard to manually map the unmapped part.
• The connectivity of the circuit in the local design is different. The matching algorithm
found a partial solution excluding parts with connections differing from source circuit.
• You excluded certain parts in the Ref Des tab and set the Lock status for them to by-pass
their placement.
If you choose to Ignore and continue to place the circuit, the unmapped parts (marked red) are
omitted.
• Duplicate Reference Designator found (light blue) ñ a reference designator in the local
design has been mapped to more than one part found in the clipboard design. The
possible cause could be:
• You mistakenly mapped one reference designator to more than one part in the
Instantiation Wizard.
Clicking Ignore creates the partial circuit where only one part is mapped to a ref des; other parts
that were mapped to the same ref des are excluded from placement.
Ref Des Displays the original reference designators for the

copied circuit design. This is a read-only field.
Part Number Displays the part number of the copied circuit.
Number of Pins Displays the number of pins on the part. This is
displayed as an aid for when manually assigning
unmapped parts. Choosing a large pin-count part to
map helps seed other components when subsequently
using the Resolve button.
Equivalent Cell Displays the equivalent cell name found in the host
design. The cell name, by default, matches the cell
found in the source design. If the source design
references an alternate cell (listed in the Part entry for
the part used), the same cell is used in the circuit to
be pasted.

Instantation Wizard
Equivalent Ref Des Displays the reference designator of the equivalent

part in the host design. A list of candidate parts
(matching part number) found in the host design are
listed in the drop down.
If you leave the entry as unmapped, when you select
the OK button, a warning dialog appears stating the
number of unmapped components. These unmapped
components display in red. If you select OK, the Tab
re-displays allowing you to correct the mapping.
You have the option to un-map parts so as to not
place equivalent parts in the host design.
Lock Allows parts that have been mapped manually to be
locked, preventing the Instantiation Wizard from
assigning a new part. If the Use same reference
designators only checkbox is selected, this option is
unavailable.
Use same reference This checkbox allows a more simplified instantiation
designators only process to take place and is used to map parts purely
on matching reference designators. The Resolve
button and Lock option are deactivated with this
option checked.
Show Report Displays the InstantiationWizard.txt report file in
ASCII.
Resolve Button In situations where some parts cannot be resolved
automatically, it is necessary to manually instantiate
the remainder. Manually mapping a large pin count
device increases the chances of success when using
the Resolve option to automatically map the
remaining parts.
Instantiation Wizard Physical Layers

The Physical Layers tab allows you to map the layers if the layer stackup in the host design does
not match the copied circuit. This is similar to the layer mapping option in the Setup Parameters
dialog.
You can also omit Physical layers from the paste operation by mapping them to none.

Instantation Wizard
Circuit Layers
Layer Displays the circuit layers for the copied circuit design. This is a read-only
field.
Number of Displays the number of copied objects found on the associated layer. This is
Items a read-only field.
Map To Allows you to map objects on the original circuit layer to a different layer.
You can omit Physical layers from the paste operation by mapping them to
none.
Restriction: You cannot remap the top and bottom layers.
Plane Nets Displays the circuit plane nets on the associated layer. Displayed plane nets
display in red if you try and remap the layer to a layer that does not contain
the displayed plane net. This is a read-only field.
Allowing Mapping more than one circuit layer to one host

layer
If this option is selected, you are allowed to map multiple layers to a single host layer.
Table 4-3. Host Design Layers Preview
Layer Displays the original host layers. This is a read-only field.
Accepts Circuits Displays the circuit layer(s) that have been mapped to the original host
Layer layer. This is a read-only field; however, as layers are mapped in the
Circuit Layers: Map To section, the layers change to reflect that
mapping.
Plane Nets Displays the host plane nets on the associated layer and displays the
host design's plane net assignment (in black) and plane nets that come
from the copied design (in blue).
As layers are mapped in the Circuit Layers: Map To section, if the
layer contains a Plane Net and is re-mapped to a layer that does not
contain the plane net, it is removed from the list and the Accept
Circuit Layer displays "none".
This is a read-only field.
Instantiation Wizard Physical Layers

The Nets tab can be used to map nets that cannot be mapped automatically. For example, the
source layout may have 0V net, whereas the host design may use GND. If you leave a circuit net
unassigned, when you select Resolve, OK or another tab, a warning dialog appears.

Instantation Wizard
Empty Net Name detected - A net name in the clipboard design has not been mapped to a net in
the local design. The empty nets display in red. A possible cause for this could be that a net
name for one or more floating items is not found in the local design. You should inspect the
Floating Items list and map their clipboard net assignments to local net names. If you select
Ignore, the partial circuit is created where unmapped floating items will be omitted. If you select
OK, the Tab re-displays allowing you to correct the mapping.
Circuit Pins Net: Circuit Displays the original circuit nets for the copied circuit design.
Net This is a read-only field.
Circuit Pins Net: Host If the nets have been automatically assigned, the entry appears
Net with a pulldown menu. This allows you to change the mapping
of the nets.
Allows you to assign the host net to the circuit net. Red
indicates that there is not mapping. Yellow indicates that two
or more host nets are mapped to the same circuit net.
Circuit Pins Net: Lock Allows nets that have been mapped manually to be locked,
preventing the Instantiation Wizard from assigning a new net.
Floating Items: Circuit Displays any circuit nets that have no corresponding host net
Net (floating). This is a read-only field.
Floating Items: Host Net Displays unassigned nets in the host net that you can manually
map to the floating circuit net items.
Show Report Displays the InstantiationWizard.txt report file in ASCII.
Resolve Button In situations where some nets cannot be resolved
automatically, it is necessary to manually instantiate the
remainder. Manually mapping the nets increases the chances of
success when using the Resolve option to automatically map
the remaining nets.
Instantiation Wizard User Layers

The User Layers tab allows you to map user layers in the source design to user layers in the host
design.
User layers that do not exist in the host design are automatically created if the Create checkbox
was selected. The new layers maintain their original names. Setup Parameters and Display
Control are updated to reflect the new user layer name in the host design. You can use this tab to
omit any user layers from the paste operation by mapping them to none.
Circuit Layer Displays the user-layer name for the copied circuit design. This is a
read-only field.
Number of Items Displays the number of copied objects on the associated user-layer.
This is a read-only field.

Change Layers
Map to Host Layer Provides a drop-down containing all the host user-layer names. Select
the appropriate host user-layer to which to map the circuit layer.
Create The checkbox allows you to create a user layer-name in the host
design that exists in the source design.
Change Layers
When this command is selected, the layer-mapping table automatically displays showing the
last used mapping scheme. It allows the mapping of physical and draft layers. The default layer-
mapping configuration is that the mapping is a one to one relation. The Layer Mapping Table
dialog provides the ability to:
• Map pair layers (physical layers and draw layers)

• Store (on disk) and retrieve mapping table settings with user defined filenames. The
scheme files are stored in the job's ../pcb/config directory and have the extension of .chs.
• Recall the last mapping table used, between editing sessions for a given design.
Selecting the OK button initiates the change layer operation based on the current mapping
scheme, verifies the via spans, and if no problems exist, the dialog closes and the circuit remains
selected.
Restriction: Change Layer does not change the layers of objects built within a cell.
If errors in the mapping are present, an error message is displayed and you are returned to the
dialog until they are fixed. A situation that may occur is where changes to the mapping or new
via spans were defined in Setup Parameters
Although you are prevented from initiating the change layer operation it is still possible to
continue defining the mapping scheme and subsequently saving it to a scheme file until Setup
Parameters has been updated.
Selecting the Cancel button closes the dialog and any/all layer changes are ignored.
The top of the dialog displays the number of mounted parts on the board and shows that
mapping for the top and bottom layers. Mounted parts are not affected during the change layer
operation.
The next section displays information on the Physical Layers
Before Displays the number of physical layers.

Item Count Number of items selected for a given layer. ë0í means that there are no
items on this layer for the selected circuit.

Save Schemes in Push and Change Layer
After Dropdown box lists all physical layers. All layers are available for
mapping so long as the layer type matches and the via span is
compatible. Entries in the fields turn blue if you make changes to the
After column.
Plane Nets Indicates the plane net names associated to a plane layer.
Draw layers are only listed if they are found in selected circuit.
Before Displays draw layers within the selected circuit.

Item Count Number of items selected for a given draw layer.
After Dropdown box lists all draw object layers. Entries in the fields turn blue
if you make changes to the After column.
Incompatible Via Spans

All via spans used in the selected circuit are identified, using the settings on the Via Definitions
tab of Setup Parameters. Incompatible layer assignments in the table are checked during the
mapping process. The following warning displays for invalid layer mapping due to via span
definitions:
Change Layer cannot be applied to the selection due to the Via Span
definition.
For microvias and blind/buried vias, the selection of a via and mapping the from or to layer for
the span will cause the span to change. For example, with a via 2-15 and traces on layers 2 and
11, you should not select the via if you want to swap the traces layer. If all items are selected
and Change Layer has an order to map layer 2 to layer 11 and layer 11 to layer 2 then via span
2-15 will be converted to 11-15.
Reusable Blocks
Change Layer can be applied to a Reusable Block. If Forward Annotation is run, the changed
layers within the Reusable Block remain.
Save Schemes in Push and Change Layer

Schemes are provided as a means to preserve settings for specific activities (Push, Change
Layer). The drop-down menu that accompanies this field can be used to display the available
schemes. User-generated schemes can be edited, saved and deleted.
To Select a Pre-Defined Scheme

1. Select the drop-down menu button to gain access to the list of defined schemes.

Mirror
2. Select a scheme from the list. Once selected, the scheme's parameters are loaded to the
dialog.
To Create and Save a New Scheme

Once all the changes to the dialog are complete, enter a name in the Scheme name field. The
scheme can be saved locally or to the system configuration directory.
If a scheme name is entered which is a duplicate, a warning dialog appears asking if you want to
overwrite the original scheme.
If you select the Save locally with design check box, the scheme is created and prefixed with
Loc:. If you select the Save with product system files checkbox, the scheme is prefixed with
Sys:. Select OK to save the scheme.
To Delete a Scheme
1. Display an existing Scheme in either the Push or Change Layer dialogs.
2. Select the Delete icon . A message appears asking you to confirm the deletion.
Note
The default scheme cannot be deleted.
To Use an Existing Scheme as a Template

1. Load an existing Scheme.
2. Make the necessary changes to the dialog.
3. Enter a new scheme name in the Scheme name field of the Save Scheme dialog.
4. Select OK to save the scheme.
Mirror
The Mirror command processes circuit elements so that non-cell objects (routing, shapes,
drawings, etc.) undergo a true Mirror operation and the connectivity and clearances between
items in the mirrored circuit are preserved. Also, cell objects are only shifted and rotated along a
predefined algorithm (no true mirror). Both the connectivity of the traces to the component pins,
and clearances between items in the mirrored circuit are not preserved, and should be resolved
manually after the operation.

Mirror
Dynamic Mirror
1. Select the circuit to be mirrored.
2. Select Move.
3. Select either Mirror Horizontally or Mirror Vertically. The entire circuit will be
transposed but remains attached to the cursor.
4. Click the left mouse button to place the circuit on the board.
The selected data is transposed about the x or y axis relative to the circuit origin. The default
circuit origin is the center of the selection box that defines the extents of the selected items. You
may override the default origin using the Set Origin command.
Static Mirror
1. Select the circuit to be mirrored during a Move operation.
2. Select either Mirror Horizontally or Mirror Vertically.
The selected data is transposed about the x or y axis relative to the circuit origin. The default
circuit origin is the center of the selection box that defines the extents of the selected items. You
may override the default origin using the Set Origin command.
DRC Violations after Mirroring

The mirror function does not fail when DRC violations have been created. When violations
occur the operation continues and it is your responsibility to fix these violations.
Figure 4-1. DRC Violations Example

Mirror
The above image shows a typical DRC violation resulting from a mirror operation involving
parts. The traces have been mirrored exactly about the y-axis but the parts have only been
moved; the component pins remain in their relative position with respect to the component
body. Consequently the traces need to be re-routed by hand to restore connectivity.
Examples of cells with an axis of symmetry

A cell has an axis of symmetry if the mirroring of the cell elements relative to this axis leaves
the cell elements unchanged. If the cell has an axis of symmetry, the Mirror operation for the
cell instance is completely replicated.
The cases are limited to cells with pins arranged along one axis (if there are pins in the cell), and
other shapes symmetrical relative to this axis. Pad reference points must be on the symmetry
axis.
Examples of the cells where there is no axis of symmetry.
The following two cells cannot be considered to be axis-symmetrical ones;
• In the left cell the pin pad offsets result in pin reference points that are not aligned with
pin row axis;

Mirror
• In the second cell the component body is not symmetrical relative to pin alignment axis.
Transformation of cell instances on Mirror command

For each cell instance in the selected circuit:
• The vector is defined

as aligned with
long axis of
the
geometric
al set of
points
representing
pins.
• In the coordinate system, associated with the cell, the minimal box covering all pin
reference points is calculated.
• The vector origin is set to the center of the box.
• The vector direction is set along maximal side of the box. If the sides of box are
equivalent (within some small value) the vector orientation is set to be equal to the
orientation of the cell instance.
• The transformation of the cell instance is shift (displacement) plus rotation.

The New position of the cell instance is calculated so that the vector origin is mirrored relative
to required axis of mirror (Y axis ñ for Mirror Horizontally, X axis ñ for Mirror Vertically). The
New orientation of the cell instance is calculated so that vector direction is transformed as
• 180 -a for Mirror Horizontally

Push
• -a for Mirror Vertically where a is the original orientation of the vector (before
transformation)
The following figure illustrates the transformation on Mirror Horizontally.
Push
When the Push command is selected, the layer-mapping table automatically displays showing
the last used mapping scheme. It allows the mapping of physical and draft layers during push
operations. The Layer Mapping Table dialog provides the ability to:
• Map pair layers (physical layers and draw layers)

• Store (on disk) and retrieve mapping table settings with user defined filenames. The
scheme files are stored in the job's ../pcb/config directory and have the extension of .pus.
• Recall the last mapping table used, between editing sessions for a given design.
When a circuit is pushed from one side of the board to the other, consideration is made for the
mapping of external and internal layers, especially when the layer stackup is asymmetrical. The
default layer-mapping configuration is that the mapping is from the lowest to highest, 1 to 6, 2
to 5, 3 to 4, etc., with the exception of plane layers which remain the same.
Selecting the OK button initiates the push operation based on the current mapping scheme,
verifies the via spans (and any other constraints), and if no problems exist, the dialog closes and
the circuit remains selected.
If errors in the mapping are present, an error message is displayed and you are returned to the
dialog until they are fixed. A situation that may occur is where changes to the mapping or new
via spans were defined in Setup Parameters
Although you are prevented from initiating the push operation it is still possible to continue
defining the mapping scheme and subsequently saving it to a scheme file until Setup Parameters
has been updated. Selecting the Cancel button closes the dialog and any/all layer changes are
ignored.

RF Shapes and Groups
If there are fixed or locked items found within the selection list, a warning dialog displays
asking you to continue or cancel. If you choose to continue, the fixed and/or locked items are
moved to the designated layer.
The top of the dialog displays the number of mounted parts on the board and shows that
mapping for the top and bottom layers.
The next section displays information on the Physical Layers
Before Displays the number of physical layers.

Item Count Number of items selected for a given layer. 0 means that there are no items
on this layer for the selected circuit.
After Dropdown box lists all physical layers. All layers are available for
mapping as long as the via span is compatible. Entries in the fields turn
blue if you make changes to the After column.
Plane Nets Indicates the plane net names associated to a plane layer.
Draw layers are only listed if they are found in selected circuit.
Before Displays draw layers found within the selected circuit.

Item Count Number of items selected for a given draw layer.
After Dropdown box lists all draw object layers. Entries in the fields turn
blue if you make changes to the After column.
Incompatible Via Spans

All via spans used in the selected circuit are identified and incompatible layer assignments in
the table are checked during the mapping process.
For example, if the board has vias spanning 1-3, 3-6, 6-8 and an attempt was made to map the
circuit data from layer 2 to layer 4, a message displays; Push cannot be applied to selection due
to the via span definition.
RF Shapes and Groups

Selection of a component of an RF Shape or Group results in the inclusion of the parent object
into the Circuit Move and Copy operation.
Move and Rotate Selection (Including Mirror and Push)

RF Shapes or Groups move or rotate based on their selection. If a shape is selected that does not
belong to an RF Group, the RF Shape moves independently. If it belongs to an RF Shape it
moves as part of the RF Group.

Embedded Passives
Copy Selection
Copying RF shapes produces the following behavior:
• Only selected elements are included in the copy operation.

• If the selected element belongs to a shape or group, only the selected objects are copied.
The source group assignments are ignored.
• Group assignments in the equivalent circuit are preserved.
• Multiple groups are supported in a Copy operation
• Μatching of RF shapes differs from regular components as defined in RF Elements.
RF Elements in the Instantiation Wizard

The ability to select, move and copy circuits that contain RF elements when invoked from the
RF Toolkit are supported.
Restriction: RF elements are Read Only outside of the RF Toolkit when an RF Toolkit license is
not available.
RF Shapes are not cell based; they are created and maintained on the fly and may change if
rotated or moved to a different layer. Additionally, RF Shapes always use a common part
number. The Instantiation Wizard uses a different matching algorithm than is used for regular
parts.
Instantiating RF Shapes
During the instantiation process, if an RF Shape is included in the copy, the following
component properties are compared when validating RF component matches:
• Library Element Name

• Physical shape (compares X/Y of segment vertices in RF shapes)
If a local RF component matches the above criteria then it is selected as a candidate part for
instantiation. If the above criteria are not met, the source part is not a candidate for placement
and is assigned as unmapped in the Equivalent Ref Des field of the Instantiation Wizard.
Embedded Passives
Circuit Move & Copy supports the ability to select, move and copy circuits that contain
embedded components. During circuit move operations you can rotate the circuit, however, if
the selected rotation is not allowed the placement will fail and following error displays in the
status bar:

Team PCB
EP Rotation incorrect
Certain information, such as materials, process library and parametric data is not copied
between designs. The synchronization of materials and process library data is your the
responsibility. You must ensure that the correct materials and library data exists in the local
design if copying of embedded passives is to be performed.
Embedded passive devices are based on a generic cell template that has little in common with
the size and shape of the resistor or capacitor that is eventually created. They are created and
maintained in an unstructured manner and may change if rotated or moved to a different layer.
Embedded passive devices always use a common part number (EC-RES for resistors and EC-
CAP for capacitors), so the Instantiation Wizard uses a different matching algorithm than that
which is used for regular parts.
Instantiating Embedded Passive Devices

During the instantiation process, if an embedded passive device is found (part number will be
EC-RES for a resistor or EC-CAP for a capacitor) the following component properties are
compared and the material name and process name that was copied with the part from the
clipboard are compared:
• Value property
• Tolerance or Tol properties
• PowerRating or Power or PowerDissipation or Rating properties
If a local part matches the above criteria it is selected as a candidate part for instantiation. If the
above criteria is not met, the source part does not have a candidate for placement and is assigned
as unmapped in the Ref Des field.
When all necessary parts are mapped and the OK button is pressed (in the Instantiation Wizard),
all the embedded components that have been mapped are synthesized to generate the correct
physical shape and size. The parts placed in the local design exactly match the original
geometries from the source design.
Team PCB
The following describes how Circuit Move & Copy works in Team PCB Split Partition mode.
Selection
Circuit Move & Copy only allows the selection of items that completely reside in a split
partition (in reserved area). Other items in the design are not selectable. For example, a Ctrl-A
(Select All) selects all the items in the split partition except for the reserved area shape itself.

Team PCB
The split partitions layer specifications (All Layers, Top, Bottom, Inner, Draft) are also
accounted for when checking the items that completely reside in split partition.
The reserved area is not selectable in split partition mode.
The Add to Selection functions also limit operation to involve only items that are local to split
partition.
A Group is considered to be local to the split partition, and can be selected; if all involved
components are completely within the reserved area.
Move / Rotate
You can start Move / Rotate and any other Circuit Move & Copy operations only with items that
reside within a split partition. Circuit Move & Copy only allows placement of the selected items
within the split partition. This is the same behavior as for Place / Route / draw modes.
Paste and Instantiation

If you want to use intra-design copy circuit (copying / pasting of the items within the same
design) you can copy only items that reside within the split partition. You cannot copy items
from another partition because you cannot select them.
The following actions are prohibited when pasting in a split design:
• Creating new via spans

• Adding new padstacks and holes
• Adding cells and parts
• Creating user layers
During the instantiation the set of parts/candidates is limited to only parts that are assigned to
the split partition. In other words the Instantiation Wizard does not allow you to place parts that
are not assigned to split partition.
Special considerations are made for partitions whose layer properties are different from All
Layers, namely for partitions with Top, Bottom, Inner or Draft specifications.
Instantiated / pasted items from the clipboard that do not comply with the split partition layer
specifications are removed from the pasted group after you select OK in the Instantiation
Wizard. The report shows all the removed items.
For example you can copy circuit with traces on all layers and paste it into split design with the
partition defined on Top layer. All the items which are not on layer Top are not created. The
report details these items.

Team PCB

Chapter 5
Product Integration
This chapter describes the integration that has been established to carry information between
Expedition™ PCB and other products.
If you want to:

Learn about IDF Information on page 247
Learn about DXF Information on page 250
Learn about IFF Information on page 254
Learn about ICX Information on page 256
Learn about Schematic Integration Information on page 256
Learn about Project Integration Information on page 257
Learn about DX Designer Information on page 273
Learn about Design Architect Information on page 276
Learn about Cross Probe Configuration Information on page 278
Learn about Variant Manager Information on page 282
Learn about OBDG Interface Information on page 282
Learn about OBD++ Information on page 284
Learn about Enterprise 3000 Information on page 290
Learn about Scepter Information on page 290
Learn about OrCAD Information on page 290
Learn about HyperLynx Information on page 291
Learn about XTK/QE Information on page 292
IDF
The Intermediate Data Format (IDF) allows the exchange of mechanical information between
the PCB design environment and a mechanical design environment that supports IDF
Import/Export. IDF Import only imports those items which are supported by IDF Export. IDF
versions 2.0 or 3.0 can be imported into the PCB environment.
IDF supports only through via obstructs and no layer specific information is present for via
obstruct in the IDF exported file, therefore, any via obstructs are imported to ALL layers. Any

Product Integration
IDF
warning messages display in the IDFImport.txt log file. By using IDF files, PCB mechanical
features can be moved into the mechanical design environment, where interference checking
can be performed to ensure that the design can be built.
Figure 5-1. Import IDF
If mechanical interference problems are found, elements can be moved in the mechanical
environment and then these changes can be integrated back into the design environment by
importing the modified IDF file.
Note
Design rule violations are not prevented during IDF import. Parts are moved to their new
locations without regard to what may already be in that area of the board. The board file
places / replaces the following elements in the design file.
Table 5-1. IDF and Expedition PCB Elements

IDF Name Expedition PCB Name
Part Placement Parts
Board outline Board outline
Board outline (cutout option) Contours
Drilled holes Mounting holes
Route outline Route border
Route keepout Route obstruct
Place keepout Placement obstructs
Place region Rooms

Product Integration
IDF
Note
Parts that were placed in the design in PCB are moved to any new XY locations defined
in the IDF file. However, if the part was not previously placed but is in the IDF file, it will
NOT be placed from the library into the design.
The IDF board file does not contain netlines, traces and/or vias. The library file contains
information that defines each part in the design. Electrical and mechanical parts are defined. We
do not support the specification of properties for electrical parts.
The Library file contains the following information.
Table 5-2. IDF and Expedition PCB Library File

IDF Name Expedition PCB Name
Geometry Name Package Cell name
Part number Part number
Units definition (mm or thou) Units definition (mm or thou)
Part height Height
Part outline Placement outline
In Export IDF, nested mechanical cells are not exported to IDF separately. Only the package
cell is exported with an outline which includes the nested mechanical cells. The default value
for Board thickness is .062 inches. The default height for part height is .100 inches. The default
part height is only assigned to those parts that do not have a part height assignment in the part
entry or the cell database. The order in which a height is checked is:
• In the Part Editor

• In the cell database
• The default on the dialog.
Buried cells are not exported to IDF, they are ignored. Test points placed with the Place Test
Point command are not exported to the IDF file. Only schematic test points placed with the
Place Part command are exported to the IDF file.
Route obstructs, built within cells and padstacks, are exported and they are written out as if they
were board level objects. Route obstructs by layer are also exported to IDF.

Product Integration
DXF
Figure 5-2. Export IDF
A Mechanical Verification log file, IDFExport_out.txt, and an ECAD / MCAD Name

Correspondence file, ecad_hint.map are created. The Mechanical Verification log file contains
the IDF version number and any information regarding objects which could not be exported.
The final line of the log file states whether the process was successful and reports the total
number of warnings. The ECAD / MCAD Name Correspondence file is only used by Pro-
Engineer. Previous versions of the IDF translator used ecadhint.map as the filename, however,
the underscore must be present in the filename for Pro-Engineer to recognize the file.
A correspondence does not always exist between the elements found in the PCB design file and
the IDF file. In cases where an IDF record is necessary but the particular attribute is not found in
the PCB design file, default settings are used.
DXF
DXF (Drawing Interchange) is a file format created by AutoDesk, Inc. which you can use to
exchange data between Expedition PCB and many CAD and graphical applications. Expedition
PCB supports R14 DXF ASCII files. DXF data is only allowed to be imported into user defined
layers. DXF Import creates a DXF cell of all the data that is imported, stores that data in the cell
library and the DXFCell is placed on the board.
Note
DXF data is only allowed to be imported onto Expedition PCB User Layers.

Product Integration
DXF
Figure 5-3. DXF Import
Once the dxf file is imported, the original extents (min/max x/y) display in the dialog. These
extents cannot be edited.
Multiple DXF cells reside in the local cell library after import completes. The Place Parts and
Cells dialog should be used to place the DXF cells within a single layout design. DXF cell types
are listed as drawing cells. You can select individual components of the DXF cells in Draw
Mode. Place Mode will allow you to move DXF cells to a different location. To differentiate the
DXF cells from other drawing cells the name must be prefixed with "DXF_".
It is important not to change the object type of DXF imported elements, you should make a copy
of the element and then change those properties. If a DXF file is placed in a design and then the
elements are moved from user-layer to another object, it is not possible to carry out an ASCII
Export then ASCII Import on the layout.hkp file because of errors that the drawing cell may not
contain the other objects' keyword.
If the DXF Cell Name field is blank, the Import mode is New. This allows a new DXF file to be
created in the local library. If an existing DXF filename is selected the Import Mode displays
the following options:
• Append Cell - Adds selected information to existing selected DXF cell. The orientation
and location of the cell, within the layout design, stays the same.

Product Integration
DXF
• Overwrite Cell - Completely overwrites the original cell. The orientation and location of
the cell, within the layout design, stays the same.
• Overwrite Layers only - Overwrites existing selected cell layer.
When the Custom Pads and Drill Symbols tab is active in the Padstack Editor, the Padstack
Editor’s File pulldown allows you to display the Import DXF dialog that allows you to append
or overwrite data on DXF layer names.
Figure 5-4. DXF Import From Padstack Editor
This dialog has limited functionality from the one accessed from within Expedition PCB, you
cannot map DXF layer names to User Layers and font Mapping is not available. DXF files
created in Expedition PCB contain no electrical intelligence. This version of DXF is only
graphical.
In DXF Export there is a 255 character string limitation in the DXF Export Layer Name field,
however the DXF file format only allows 31 characters for Layer Name.
Although there are no restrictions other than spaces for the layer names, AutoCAD only allows
characters A-Z, 0-9, $, _, and -. If any of the layer names contain characters other than these and
you plan to import this DXF file into AutoCAD, you will want to edit the layer names to remove
the other characters.
Schemes to use with export DXF can be created for future use and can be selected from this
pulldown.

Product Integration
DXF
Figure 5-5. DXF Export
When writing out DXF data, the only DXF element types written are:
• DXF Line - used for all lines

• DXF Arc - Used for all arcs
• DXF Polyline - Used for all closed shapes. Arcs have to be stroked.
• DXF Text - Used for all text.
• DXF Circle - Used for all circles.
• DXF Solid - Used to represent a filled rectangle placed at 0, 90, 180 or 270 degrees.
• DXF Hatch - Used to fill circles and closed polylines. (Note: the DXF Hatch element is
not supported by Microstation SE.)
MicroStation will truncate layer names to 16 characters, but will put the full layer name in a
comment field. If this DXF file is to be imported into MicroStation and the truncation will be a
problem, you will need to edit the default DXF Layer Names to be 16 characters or less.

Product Integration
IFF
IFF
IFF (Intermediate File Format) is a file format created by Agilent Technologies ADS tool which
you can use to exchange data from Expedition PCB into many CAD and graphical applications.
The imported data is a flat graphical object within Expedition PCB. If an ADS layer is not
mapped, the data associated with that layer is not imported.
Note
Import / Export IFF should not be used for round trips between Expedition PCB and
ADS. Each of these functions are independent of each other and should be used
independently.
Figure 5-6. IFF Import
The integration is performed using .iff files and when the .iff file is imported into Expedition
PCB, the local part is populated with the part number and cell information needed for the RF
circuit and it is fixed to prevent modification to any conductive layer, however all layers can be
moved and rotated as a block.
You can also use the Cell Editor to adjust port pins, padstacks, parts and/or cells to improve the
design's routing.

Product Integration
IFF
The IFF Export dialog allows you to modify the IFF output filename, select the layers to be
exported, change the IFF layer name(s) to be used and optionally select the area of the design to
be exported.
Figure 5-7. IFF Export
You can export the entire design or a portion of a design to an (.iff) file located in the ../output
directory for the current design. This file can then be imported into the Agilent Advanced
Design System (ADS) tool for analyst / simulation.
A port-mapping file is also produced in the ../output directory, with a .txt extension. This file
contains properties for the pins and ports exported to the IFF file.
The IFF Layer Name field has a 255 character string limitation, however the IFF file format
only allows 31 characters for Layer Name. A warning dialog appears if you have more than 31
characters and /or spaces in the Layer Name. Although there are no restrictions other than
spaces for the layer names, the only characters allowed are A-Z, 0-9 and _(underbar). If a layer
is specified, all of the above elements are written out, however, if only Layer 1 is specified and
the vias go from layer 1 to layer 2, only the layer 1 via pad is written. Elements which may be
included in the output file are:

Product Integration
ICX
• Traces
• Pads
• Vias
• Pins
• Component outlines
• Area fills (plane data)
ICX
The Import from ICX interface was developed to extract the necessary data within ICX® and
create an Expedition database. When you are finished using the ICX application, you use the
ICX to Expedition interface to get IS data into Expedition format. The ICX to Expedition
Interface gives you the ability to:
• Export all, or a partial set of trace and via definitions from an open IS design.
• Export all, or a partial set of component placement definitions from an open IS design.
The Export to ICX option allows the exchange of high speed information from PCB to the
Mentor Graphics Interconnect Synthesis (IS) environment. This provides a single integrated
environment for electrical rules entry, signal integrity and delay analysis, crosstalk analysis and
rules checking.
The files necessary to launch the IS tools are created and are stored in the <jobs>/output/icx
subdirectory and, if required, these data files can be moved to a UNIX based environment.
When all the files have been created, IS automatically displays with the data files loaded.
Schematic Integration
Back Annotation and Forward Annotation are the methods used to pass data between the
schematic databases and Expedition PCB. Forward Annotation is run from within Expedition
PCB and loads the schematic’s logic data into the board. Batch Annotation takes any logic
changes made on the board and sends this information back to the schematic databases. Back
Annotation from PCB layout to the schematic is accomplished automatically when you perform
a save. Back Annotation is performed interactively using the Project Integration Back
Annotation icon and from the ECO Back Annotation command in PCB layout. All commands
that require a back annotation to the schematic can be deactivated by deselecting the Back
Annotation option in the Project Integration dialog in PCB layout or in the PCB Integration
dialog in Design Capture.
Use Forward Annotation if there have been changes made to the schematic since the last
compiled database. As with Back Annotation, using the PCB Integration dialog in the schematic
capture package can prevent Forward Annotation. This status may be set to prevent extraction if

Product Integration
Project Integration
the schematic designer is making changes to the schematic and does not want data to be
extracted from the database until it is ready.
Project Integration
The Project Integration command is used to establish a link between a schematic, CES and a
PCB design and to designate how the flow of information between the two is to be handled;
either through Back Annotation or Forward Annotation. This association enables you to see
which functions of integration are available by the colored buttons displayed in the Schematic
status settings.
Figure 5-8. Project Integration
If a DXDesigner, Design Architect, CAE, Keyin, or Foreign iCDB netlist is going to be used,
this dialog allows you to edit the project file by associating the foreign netlist.

Product Integration
Project Integration
If the design will be using schematic data from Design Capture, the project file should be placed
so its location is relative to both the schematic and PCB jobs. Design Capture also provides an
interface to allow creation and editing of the project file.
Project Indicator Light in Layout

Indicator lights display in the Status Bar area as shown below:
Figure 5-9. Project Indicator Lights
The indicator lights show the status of the connectivity and constraint data between the front-
end and back-end central database.
The lights are green when Forward Annotation is not required; there are no available pending
Schematic CES changes and no available pending PCB CES changes.
Caution
Caution: If all lights are green this does not necessarily mean that everything is in sync. It
simply means that there are no outstanding changes on the front-end to be pulled into the
PCB and there are no outstanding PCB CES changes to be loaded.
The lights flash amber when there is data on the schematic that needs to be forward annotated or
loaded (in the case of CES constraints) into the PCB.
(1) This light is for Connectivity and it indicates if Forward Annotation is needed based on
schematic changes. Clicking on this indicator invokes ECO > Forward Annotation.
• If Red:
Schematic connectivity changes are pending.
Forward Annotation is disabled in Schematic.
• If Amber
Schematic connectivity changes are pending.
Click to run Forward Annotation.
• If Green
Schematic connectivity and board in sync.

Product Integration
Project Integration
(2) This light is for schematic CES constraints and it indicates that CES changes have been
made in the schematic and need to be loaded into the PCB. Clicking on the this indicator, loads
the schematic CES constraints into the PCB.
• If Amber
Schematic CES changes are pending.
Click to pull schematic constraint changes into board.
• If Green
There are no pending schematic CES changes to be pulled into board.
(3) This light is for the PCB CES constraints and it indicates that CES changes have been made
but have not yet been loaded into PCB. Clicking on this indicator, loads the PCB CES
constraints into PCB.
• Ιf Amber
PCB CES changes are pending.
Click to load PCB CES constraint changes into the board.
• If Green
There are no pending PCB CES changes to be loaded into the board.
Schematic Connectivity and Constraint Status Section

These buttons indicate the status and also, when pressed, perform the associated function. There
are four different areas that allow synchronization in the PCB design:
• Front-end changes - connectivity.

• Front-end CES changes.
• Back-end CES changes.
• Back-end changes ñ gate and pin swaps, renumber reference designators, etc.
When the front-end or back-end are not in synch, the buttons are amber, indicating that you can
select those buttons and synchronize the data. If back annotation or forward annotation has been
prevented by settings in the schematic, and the data is out of synch, then the buttons are red and
you cannot synchronize by pressing the button. When you press a red button, an informative
dialog displays explaining why you cannot synchronize the data.
When there is no specific action to be taken, all the indicators appear green. However, that fact
that the indicators are green does not indicate that all the data in the front end and back end are
synchronized.

Product Integration
Project Integration
Loading PCB CES Data

When you press the Load pending CES changes into PCB indicator, the CES changes are
loaded and the Back Annotation required indicator is changed to Amber or Red, depending on
whether Back annotation is prevented or allowed. This acts as a reminder that a Back
Annotation is necessary to ensure that PCB CES changes are synchronized with the Schematic
CES data.
Synchronization Options
There will be times when all four different areas that allow synchronization need to be
synchronized. When this situation occurs, some rules are applied to stop the changes
overwriting.
Forward and Back Annotation Order

When forward and back annotation changes exist, a back annotation must be run before a
forward annotation. The rules to be following during a back annotation and forward annotation
process are defined in the project file. The rule definition basically tells whether a front-end or
back end change wins, when the information has been changed on both sides.
If you select the Front-end changes button first, back-annotation is automatically run so you
cannot do things in the wrong order.
Load pending schematic CES changes into PCB

When this option is selected, any CES data that can be loaded into PCB is loaded. There are
times when there may be nets available in the schematic that are not yet available in the PCB. If
the schematic nets have constraints on them and those nets are not yet in the PCB, we cannot
push those constraints into PCB CES. Therefore, to make absolutely sure that all CES data is
synchronized, we recommend you run forward and back annotation because connectivity will
always match at that point.
Disabled Forward Annotation / Back Annotation - DxDesigner

Flow
You can allow or prevent forward and backward annotation from occurring in a design project
by setting the appropriate options in the DxDesigner Design Configuration dialog. When
forward or backward annotation is disabled in this dialog, information is presented explaining
why the front-end and back-end cannot be synchronized.
When the annotation is disabled and annotation is required due to changes in the schematic or
PCB, the Project Integration status buttons are displayed in red and continue to display the
appropriate status. However, when you press the forward or back annotation required buttons, a
warning dialog is displayed.

Product Integration
Project Integration
Forward /Back Annotation is required to synchronize the schematic and PCB

data. However, forward / back annotation is displayed in the DXDesigner
Design Configurations dialog. Enable forward / back annotation in
DXDesigner and then try again.
Additionally, when an annotation is disabled but annotation is not required, the indicators are
green. No annotation is necessary, however, because the indicator is green, there is no clear
indication that annotation is prevented because of settings in the schematic. In order to clearly
communicate the status of the annotation, warning dialogs are displayed when the green
indicator is pressed.
Forward Annotation was requested but forward annotation is disabled in the

DXDesigner Design Configurations dialog. If you want to run forward
annotation, enable forward annotation in DXDesigner and try again.
Back Annotation was requested but back annotation is disabled in the PCB Project Integration
dialog or in the DXDesigner Design Configurations dialog. If you want to run back annotation,
enable back annotation in the PCB or schematic and try again.
Disabled Forward Annotation / Back Annotation - DC Flow

You can allow or prevent forward and backward annotation from occurring in a design project
by setting the appropriate options in the Design Capture / Design View PCB Integration dialog.
The same messages display referencing the design Capture / Design View PCB Integration
dialog. These messages only apply when the indicator is red.
Forward /Back Annotation is required to synchronize the schematic and PCB

data. However, forward / back annotation is displayed in the PCB
Integration dialog. Enable forward / back annotation in Design Capture or
Design View and then try again.
Additionally, when an annotation is disabled but annotation is not required, the indicators are
green. No annotation is necessary, however, because the indicator is green, there is no clear
indication that annotation is prevented because of settings in the schematic. In order to clearly
communicate the status of the annotation, warning dialogs are displayed when the green
indicator is pressed.
Forward Annotation was requested but forward annotation is disabled in the Design Capture or
Design View PCB Project Integration dialog. If you want to run forward annotation, enable
forward annotation in Design Capture or Design View and try again.
Back Annotation was requested but back annotation is disabled in the PCB
Project Integration dialog or in the Design Capture or Design View PCB
Project Integration dialog. If you want to run back annotation, enable
back annotation in the PCB or schematic and try again.
Library Extraction Section

The library extraction options allow you to:

Product Integration
Project Integration
• Only extract missing library data

• Update local libraries with newer Central Library data
• Rebuild local library data; preserve locally built data. Anything that was built locally for
the design is preserved, but all part, cells, etc., built through the Central Library are
updated from what is currently in the Central Library.
• Delete local data; then rebuild all library data. Removes everything (built locally and
through the Central Library) and extracts everything from the Central Library.
• Select to allow Forward Annotation to respect alpha-only reference designators. If this is

option is not checked, all reference designators are changed to alpha-numerics.
Trace Removal Options

The trace removal options allow you to:
• Select to remove floating traces and vias.

• Select to remove hangers.
• Select to allow Forward Annotation to assign nets to unused pins; this enables fanout
and facilitates routing.
• Select to allow any reference designator changes in the schematic to be annotated to the
output file.
Back Annotation Options

You can disable back annotation in the AutoActive environment by selecting the Disable
commands that create Back Annotation changes option. Another way to prevent back
annotation is to modify the project file and set the prevent back annotation flag.
Back Annotation to the Schematic

Back Annotation compares the design file with the current schematic database. Back
Annotation must be executed when changes, not reflected in the schematic database, are made
to the board design. Back Annotation is automatically performed during the save, after you
execute the following commands:
Place -> Automatic -> Swap by Part Number
Route -> Swap -> Pins
Route -> Swap -> Gates
ECO -> Renumber Ref. Des.

Product Integration
Project Integration
Route -> Planes -> Routed Plane Pins
Setup -> Editor Control (Rooms and Clusters Tab)
These commands do not require a back annotation but are sent back to the schematic database
on a save:
Setup -> Setup Parameters
Setup -> Net Class & Clearances
Setup -> Net Properties
Route -> Netline Order
The design entry tools control whether the data is back annotated into the schematic. The
automation of these steps is controlled by the design entry tools and the Project Integration
command, therefore certain commands which need to be back annotated are disabled until the
schematic engineer allows Back Annotation into the schematic.
Table 5-3. Back Annotation Schematic Information

DX Designer The NetpropsBack.hkp (optional), expedition.cfg and the
expedition.cns (constraint definition) files are created in the
DXDesigner component directory. These files are
processed by DXDesigner to apply changes to the design
viewpoint.
If changes have been made in PCB and are to be back-
annotated to DXDesigner, you may receive a message that
states that the process was successful. However, it is wise to
check the dxdbck.txt file in the ../LogFiles directory to
check that there were no errors.
Closing and opening the schematic ensures that the changes
are seen in DXDesigner.
Design Architect An ASCII backannotation file (expbackanno.txt) is created
in the Design Architect component directory. This file is
processed by Design Viewpoint Editor to apply changes to
the design viewpoint.
Design Capture After an iCDB compile is performed by Design Capture,
the "Schematic and PCB Design database synchronized"
indicator in PCB layout turns red indicating a change on the
Design Capture side. The layout engineer should run
Forward Annotation (after the iCDB has been compiled) to
synchronize the schematic and PCB layout databases.

Product Integration
Project Integration
Forward Annotation - Database Load and Netload

Forward Annotation prepares the board for layout based on the logic contained in the schematic
tools and attached Central Library. Database Load compiles the netlist source (Design Capture
iCDB, DXDesigner, Design Architect, Keyin Netlist, CAE Netlist, or GDB) into a binary
format and builds databases that can be accessed by PCB layout. The database includes
information extracted from the netlist and the attached Central Library. Database Load
automatically creates a local Parts Database and local cell library using paths to the Parts
Databases and cell libraries found in the Central Library.
For DC > CES designs, if there have been any connectivity changes in the schematic (renaming
nets), and the new foreign integrated common database is exported, when the pcb job is opened
in the back-end, a warning message is displayed.
Warning: Some of the layout data for this design conflicts with data being
loaded from CES. Some constraints may not be loaded properly. See the
logfile ces_load.txt for details.
Running Forward Annotation will update the changes in layout and back-end CES.
Forward Annotation is the mechanism to provide integration between design entry schematics
and PCB design files. When invoked from the ECO pulldown, the settings defined in the Project
Integration dialog are used.
Note
Packager is used for Forward Annotation, therefore, any changes made to the local library
in the Part Editor must be transferred to the Central library before Forward Annotate is
run.
If the schematic is ready for Forward Annotation, (the LED is green on the Project Integration
dialog and the Forward Annotation option on the ECO pulldown is sensitive), the Database
Load and Netload commands are automatically run.
Database Load provides integration between design entry schematics and PCB design files.
Database Load translates the CAE input into a binary format and builds a database that can be
accessed by PCB layout. The database includes information extracted from the iCDB, the Parts
Database, and the cell library. Database Load automatically creates a local Parts Database and
local cell library using paths to the Parts Databases and cell libraries found in the Central
Library.
Netload runs after Database Load and is used to update the design based on any changes that
have been made since the last Forward Annotation has been run. This includes changing cells,
nets, optionally removing parts that are no longer used in the schematic and traces that conflict
with the new schematic’s logic.
If the Net Classes and Clearances or Setup Parameters dialog changes in Design Capture,
opening the same dialog from Expedition PCB will ask you to copy over the newer Design

Product Integration
Project Integration
Capture database into Expedition PCB. These two commands do not require a forward
annotation. However, a change to the Net Properties dialog in Design Capture does require a
forward annotation.
If there are any errors during Forward Annotation, a dialog appears directing you to view the
files using File Viewer. If there are any errors during the Database Load portion of Forward
Annotation, Netload is not run. Correct any errors and re-run Forward Annotation.
Requirements
If the pin name of a component, especially in terms of BGAs are in lower-case (m10, n10), this
causes a problem if you are using the KEYIN.netlist in the .KYN format. The file is not forward
annotated unless the entries are in upper-case (M10, N10).
Any changes made to the Cluster and Room definitions (within Editor Control) and the Routed
Plane Pin command must be Back Annotated so the data is not lost during the next Forward
Annotation.
If you change any of the Component Properties for a part in the Part Editor, you are required to
run the Reset option in the ECO > Replace Cell command before running Forward Annotation.
This ensures that the correct Component Properties are attached to the part in the Database.
CES Integration
CES synchronization works in this manner to provide more opportunities for constraint
alignment in all of its flows. Because both forward annotation and back annotation result in full
constraint synchronization, overall design state is less of an issue for update purposes.
For example, when your DxDesigner data is changing less frequently as you move toward
manufacturing start, forward annotating to PCB gives you more opportunities to acquire
constraint changes made in PCB-CES. Due to the large volume of design changes that can occur
in the back-end at the end of the PCB creation cycle, forward annotating to get back-end
constraint changes saves time because there are few or no schematic changes to communicate to
your layout design.
Load Pending Schematic Changes into PCB using the Project Integration
Dialog
When this option is selected, any CES data that can be loaded into PCB is loaded into PCB and
the schematic and PCB CES data are synchronized.
Sometimes, there may be nets available in the schematic that are not yet available in the PCB. If
the schematic nets have constraints on them and those nets are not yet in the PCB, those
constraints cannot be pushed into PCB CES; therefore, the data cannot be fully synchronized.
To make sure that all CES data is synchronized it is recommended to run forward and back
annotation because connectivity will always match at that point.

Product Integration
Netlist Types
Save in CES
CES immediately updates the central database with every change, so there is no longer a Save
capability in CES. The indicator buttons alert you to CES changes and allow you to pull them
into the layout database.
Roll Back Constraint Changes Warning

You can selectively roll back constraint changes made at any time during your current CES
session. This includes all commands for which undo/redo is supported. For example, modifying
constraint classes and net classes, adding clearance rules, and creating differential pairs.
Caution
When rolling back constraint changes made in CES, the forward and back annotation
indicator lights for your design flow do not reflect these undo actions. For example, after
you make a single change in back-end CES and then rollback that change, your back-end
system will still indicate that you need to perform back annotation.
Netlist Types
Expedition PCB supports different types of schematic input; Schematic iCDB, Foreign iCDB,
DXDesigner, Design Architect (DA), Keyin Netlist, CAE Netlist, and GDB Netlist.
Schematic iCDB
This is created by Design Capture. The following is how the project file indicators behave when
an Expedition PCB and Design Capture are using the same project file.
Forward Annotation allowed - This indicator will always be green except when Back
Annotation needs to be run or Design Capture has selected the option to not allow Forward
Annotation.
Schematic and Layout databases synchronized - This indicator will be red anytime the
information has changed on the board or in the schematic that causes the job to become out of
sync.
Back Annotation Allowed - This indicator is only red when the Disable commands that create
Back Annotation changes checkbox is selected and when Forward Annotation is required.
The following are the commands that respect the Back Annotation Allowed project file
indicator:

Product Integration
Netlist Types
Setup -> Editor Control (Rooms/Clusters Tab)
The following are the commands that will run even if back annotation is NOT allowed:
Setup -> Net Class & Clearances
Foreign iCDB
This is created by Design Capture. This is the same database used when Design Capture and
Expedition PCB are integrated to the same project file but this iCDB is used when the
Expedition PCB and Design Capture are not sharing the same project file. The following is how
the project file indicators behave when a Foreign iCDB is used as the schematic netlist:
Forward Annotation allowed - This indicator is always green except when the project file
does not point to a iCDB Foreign Netlist.
information has changed on the board that needs to be manually sent back to Design Capture.
Since Forward Annotation updates the Net Properties database, this indicator will be red as soon
as Forward Annotation is run.
Back Annotation changes checkbox is selected.
indicator:

Product Integration
Netlist Types
Setup -> Editor Control (Rooms/Clusters Tab)
Setup -> Net Classes & Clearances
If you want to keep all the netline ordering, delay formulas and parallel rules which are created
when using Net Properties and you are running a foreign iCDB, you must manually copy the
following files from the Expedition PCB \logic\CDBBAM directory to the Design Capture
schematics \CDB\Layout directory:
iCDBBackAnno.bam
JobPrefsDB.jpf
NetClassDB.ncl
NetPropsDB.npr
PadstackDB.psk
RtdPlane.caf
Once these files are copied, you must run Back Annotation from the Design Capture Other
Utilities dialog on the iCDBBackAnno.bam file. If Back Annotation is required and you run
Forward Annotation a message appears stating that Back Annotation changes will be lost if you
continue.
Keyin Netlist
User keyin of the schematic connectivity using an ASCII Text editor typically creates the Keyin
Netlist. The following is how the project file indicators should behave when a Keyin Netlist is
used as the schematic netlist:
Forward Annotation allowed - This indicator is always green as soon as the Keyin netlist is
attached to the job.

Product Integration
Netlist Types
"logic\ NetlistBackAnno.txt" file exists with data. This file contains the changes made to the
schematic since the last Forward Annotation.
Back Annotation Allowed - This indicator is only red when the "Disable commands that create
Back Annotation changes" checkbox is selected.
indicator:
Place->Automatic->Swap by Part Number
Route->Swap->Pins
Route->Swap->Gates
ECO->Renumber Ref. Des.
Setup->Editor Control (Rooms & Clusters Tab)
Route->Planes->Routed Plane Pins
The following commands are allowed to run even if back annotation is NOT allowed:
Setup->Setup Parameters
Setup->Net Classes & Clearances
Setup->Net Properties
Route->Netline Order
CAE Netlist
A program to represent the connectivity of a schematic creates this Netlist. This ASCII file is
the same format as a Keyin Netlist except it has a %symbol section. The following is how the
project file indicators should behave when a CAE Netlist is used as the schematic netlist:
Forward Annotation allowed - This indicator is always green as soon as the CAE netlist is
attached to the project.
Schematic and Layout databases synchronized - This indicator is red anytime the "logic\
NetlistBackAnno.txt" file contains changed. This file is used to update the schematic source of
the CAE Netlist. It contains the changes since the last forward annotation.
Back Annotation Allowed - This indicator is only red when the "Disable commands that create
Back Annotation changes" checkbox is selected.

Product Integration
Netlist Types
indicator:
Place->Automatic->Swap by Part Number
Route->Swap->Pins
Route->Swap->Gates
ECO->Renumber Ref. Des.
Setup->Editor Control (Rooms & Clusters Tab)
Route->Planes->Routed Plane Pins
The following commands are run even if back annotation is NOT allowed:
Setup->Setup Parameters
Setup->Net Classes & Clearances
Setup->Net Properties
Route->Netline Order
These results of the previous commands do not require a back annotation when a CAE Netlist is
used as schematic input.
DXDesigner
This is created by DXDesigner. This is the same database used when DXDesigner and
Expedition PCB are integrated to the same project file. The following is how the project file
indicators behave when a DXDesigner netlist is used as the schematic netlist:
Forward Annotation allowed - This indicator is always green except when the project file
does not point to a DXDesigner Netlist.
Schematic and Layout databases synchronized - This indicator will always be greyed out
(inactive).
Back Annotation changes checkbox is selected.
indicator:

Product Integration
Netlist Types
Setup -> Net Classes and Clearances
The DxDesigner/Expedition PCB interface will support limited electrical net property passing.
This functionality will be implemented through the ePD 3.0 DxDesigner constraint interface,
which includes DxDesigner constraint entry, electrical net class creation, and forward and back
annotation of electrical net properties. These net properties will be passed through the
Expedition Net Properties file.
Table 5-4. Supported Electrical Net Properties
Constraint Description
Diff Pairs Pairing of two nets to be routed as a differential pair
Max Length/Delay Maximum length of a net, in time or distance
Matched Length Matches the length a group of nets within a specified tolerance
Max Crosstalk Maximum voltage caused by crosstalk, mV(Ignored if Parallelism
Rules assigned)
Parallelism Rules Maximum distance/length parallelsim rules for nets related to all
other nets.(Overrides Max Crosstalk)
Max Parallelism Maximum length a net may be routed parallel to another
Max Stub Length Maximum length of a trace branch on an ordered net
Max Vias Maximum number of vias allowed on a net
Supply voltage Voltage level of a signal net
The Max Crosstalk constraint will be written to the NetProps file. If there are parallelism rules
defined they will be written to the Parallelism Rules file (ParallelRules.txt). This file causes the
Crosstalk tab of the Net Properties dialog to be disabled and all rules are then taken from the
rules file. In the event that both Max Crosstalk and Parallelism Rules are assigned to a net, the
DxDesigner forward annotation process (pcbfwd) will report a warning.
If Back Annotation is required and you run Forward Annotation a message appears stating that
Back Annotation changes will be lost if you continue.
Multiple PCB Designs in DXDesigner Project

Additional checking is performed when a project is selected in the Project Integration dialog
because DXDesigner projects may contain multiple PCB designs.

Product Integration
Netlist Types
By default, when a DXDesigner project is selected in the Project Integration dialog, it is

evaluated to determine if the project contains a properly named PCB design. By default, the
PCB design name in the project should match the name of the active PCB design.
If no matching PCB design name is in the project, a warning dialog appears and you can select
the PCB design name to be used in the active project.
Once the desired PCB design is selected and OK is selected, the associated project file is
accepted and the Project Integration dialog is again active.
If you select a DXDesigner project that does not contains a PCB design, you cannot use that
project. In this case, a warning dialog displays and are forced to return to the Project Integration
dialog and select a valid project name. Upon return to the Project Integration dialog the Project
file input field is blank (to clearly show you had a problem) and you must browse (or keyin) to a
valid project file.
Design Architect
This is created by Design Architect. This is the same database used when Design Architect and
Expedition PCB are integrated to the same project file. The following is how the project file
indicators behave when a Design Architect netlist is used as the schematic netlist:
Forward Annotation allowed - This indicator is always green except when there is updated
PCB data that needs to be Back Annotated to the schematic.
Schematic and Layout databases synchronized - This indicator will always be greyed out
(inactive).

Product Integration
DXDesigner Flow
Back Annotation Allowed - This indicator is always green except when there is updated
schematic data that needs to be Forward Annotated to the PCB or the Disable commands that
create Back Annotation changes checkbox is selected.
indicator:
Setup -> Net Classes and Clearances
If Back Annotation is required and you run Forward Annotation a message appears stating that
Back Annotation changes will be lost if you continue.
DXDesigner Flow
1. In Dashboard:
a. Set the project as the active project.
b. Invoke DxDesigner from Dashboard ->Toolboxes -> Board-level (PCB) Design
Folder.
2. In DxDesigner:
a. Open Design Roots in the ProjectNavigator Tree.
b. Select the source schematic.
c. Select Tools -> Create PCB Netlist from the pulldown menu.
d. On the Basic tab:
For Design Name - browse for source schematic.
For Netlist Format - choose Expedition.
For PCB Configuration File - browse for ../\ePD\3.0\standard\expedition.cfg.
For Process to Run - choose Create Netlist for Layout…
e. Select Run.
f. Correct any errors, verify any warnings and then save the schematic.
3. Adding Net Properties in DxDesigner for use in Expedition PCB:

Product Integration
DXDesigner Flow
a. Select a net.
b. In the Attributes Editor, choose Expedition Constraints for Assignment.
c. Enter the required constraints.
d. Repeat steps c and d from the above Step 2.
4. In Library Manager:
a. Create a new Central Library.
b. Create entries for all the parts in the design:
Padstacks - physical pads for footprints.
Cells - physical footprints.
Parts - part name pin mapping.
5. PCB Job Creation Options
a. ViewPCB.
i. During Create Netlist For Layout process, select “Run command line after
processing” check box in the Processing Options section of the Basic tab.
ii. Select Run.
iii. Select the Create new PCB design option.
iv. Browse for Central Library.
v. Select a layout template.
vi. Enter the directory where you want the new Expedition pcb job to be created.
vii. Select OK.
viii. The new job will be created and Expedition will be invoked on the new job.
OR
b. Job Management Wizard:
i. Create a new PCB job.
ii. Enter a new project file, for example: Demo.prj.
iii. Select NO to schematic message.
iv. Select OK to Central Library message.
v. Browse for the Central Library.
vi. For Netlist, choose "DxDesigner".

Product Integration
DXDesigner Flow
vii. Browse for the DxDesigner Project directory.

viii. Select a PCB Layout Template.
ix. Complete the job creation.
6. In Expedition PCB:
a. Open the new <project name>.pcb file.
b. Invoke Setup -> Project Integration.
c. If you have part and net properties information to import use Additional Options.
d. Run Forward Annotate, verify successful.
e. Invoke Place -> Place Parts and Cells and place all unplaced parts within the board
outline.
f. If necessary, run Route -> Swap -> Gates.
g. If desired, run ECO -> Renumber Ref Des.
h. Invoke Setup -> Project Integration.
i. Run Back Annotate, verify successful.
j. Save PCB design.
7. In DXDesigner
a. Select Tools->Create PCB Netlist from the pulldown menu.
b. On the Basic tab:
i. or Design Name - browse for source schematic.
ii. For Netlist Format - choose Expedition.
iii. For Process to Run - choose Back Annotate Information From Layout To
Schematic.
iv. Select Run.
v. Correct any errors and verify any warnings.
vi. The changes from PCB should now be present in the schematic.
To complete the round-trip between DxDesigner and Expedition PCB insuring that the
data is in-sync you must perform the following steps.
8. In DxDesigner:
a. Select Tools -> Create PCB Netlist from the pulldown menu.
b. On the Basic tab:

Product Integration
Design Architect Flow
For Design Name - browse for the source schematic.

For Netlist Format - choose Expedition.
For Process to Run - choose Create Netlist for Layout...
c. Select Run. If the “Run command line after processing” option is set you can use the
DxDesigner To Expedition menu to launch Expedition if it is not already running.
d. Correct any errors and verify any warnings.
e. Save schematic.
a. Invoke Setup -> Project Integration.
b. Run Forward Annotate, verify successful.
c. Save the PCB design.

In order to minimize the disruption of the existing DA/BA process flow, a copy of Package
(EN2002.2 or later) will be required. Set the following environment variable:
MGC_PKG_XINFO=1
This will enable PACKAGE to provide additional information that is needed by Expedition to
deal with heterogeneous components.
Steps to translate a DA schematic to Expedition PCB

1. In DA schematic:
a. Set the PCB Design Viewpoint.
b. Exit.
2. In Package:
a. Run Check Build, verify no errors.
b. Run Build, verify no errors.
c. Exit Package with a Save.
3. In Library Manager:
a. Create a new Central Library.
b. Create entries for all the parts in the design:

Product Integration
Padstacks - physical pads for footprints.

Cells - physical footprints.
Parts - part name pin mapping.
4. In Job Management Wizard:
a. Create a new PCB job.
b. Enter a new project file, for example; Demo.prj.
c. Select NO to schematic message.
d. Select OK to Central Library message.
e. Browse for the Central Library.
f. For Netlist choose "Design Architect".
g. Browse for the Design Architect Component directory.
h. Select a PCB Layout Template.
i. Complete the job creation.
a. Open the new <project name>.pcb file.
b. Invoke Setup -> Project Integration.
c. Run Forward Annotate, verify successful.
d. Invoke Place -> Place Parts and Cells.
e. Place all unplaced parts within the board outline.
f. If necessary run Route -> Swap -> Gates.
g. If desired run ECO -> Renumber Ref Des.
h. Invoke Setup -> Project Integration.
i. Run Back Annotate, verify successful.
j. Save PCB design.
6. In DVE:
a. Set the PCB Design Viewpoint.
b. Run Import ASCII BA, browse for /<jobname>/expbackanno.txt.
c. Verify changes from PCB are present in the schematic.
d. Exit DVE with a Save.

Product Integration
Cross Probe Configuration
To complete the round-trip between Design Architect and Expedition PCB insuring that
the data is in-sync you must perform the following steps.
7. In Package:
a. Run Check Build, verify no errors.
b. Run Build, verify no errors.
c. Exit Package with a Save.
a. Invoke Setup -> Project Integration.
b. Run Forward Annotate, verify successful.
c. Save the PCB design.

Cross Probe is the communication link between Expedition PCB and design entry tools and
CES. This allows selection of nets, parts, and pins within the schematic, board or simulator to be
communicated between products.
After you enable cross probing in the appropriate design systems, you can cross select design
objects. When cross probing from DxDesigner, for example, selecting a net in DxDesigner
causes Expedition PCB to highlight its view of the same net. When cross probing is enabled in
all design systems, selecting a design object in one tool cross probes to the other two design
tools. For example, selecting a design object in CES cross probes to both DxDesigner
Enabling Cross Probing Between Design Views

You can enable cross probing between DxDesigner, CES, and Expedition PCB to perform cross
selection of design objects in multiple design views. For example, after enabling cross probing
from DxDesigner to CES, clicking a design object in DxDesigner results in CES highlighting its
view of the same design object.
This design flow supports the following types of cross probing between tools:
• DxDesigner to CES - Selecting a design object in DxDesigner results in CES

highlighting the corresponding object in its spreadsheet.
• Expedition PCB to CES - Selecting a design object in Expedition PCB results in CES
highlighting the corresponding object in its spreadsheet.
• CES to DxDesigner or Expedition PCB - Selecting a design object in CES results in a
selection in schematic entry or PCB layout, depending on the design view from which
you launched CES.

Product Integration
• DxDesigner to Expedition PCB (uni and bi-directional) - Selecting a design object in

DxDesigner highlights the corresponding object in Expedition PCB. Choosing a design
object in Expedition PCB results in DxDesigner highlighting its view of the object. You
can turn off cross probing from one design view (e.g. DxDesigner to Expedition PCB) to
provide just uni-directional cross probing from the other design view.
• One to all - Selecting a design object in DxDesigner, CES, or Expedition PCB
highlights the corresponding object in all other design systems.
DXDesigner (Cross Probe)

You can select a top level DxDesigner schematic and launch DxDesigner from the dialog. If the
root schematic is set in the project file then this value is pre-loaded and you can launch or
connect to an already running instance of DxDesigner passing it the selected root schematic. If
the root schematic is not defined in the dialog, DxDesigner opens with the project directory
specified as the input source.
The Connect Button launches or connects to an already running instance of DxDesigner

passing it the selected root schematic. This button is not enabled if a schematic has not been
chosen.
Using Cross Probing

1. In DxDesigner, enable the Cross Probe window by going to View -> Other Windows
and selecting Cross Prober.
2. In the Cross Prober window select the “Enable cross probing for design” check box.
3. From the “Layout system” drop down list select Expedition
4. In the “Layout document” field enter the path to the Expedition .pcb file or use the
browse button “…” to locate the file.
5. If Expedition is not currently running, the button at the end of the “Layout system” field
will show Launch. If Expedition is running then it will say Connect. Select the button
in either case. If Expedition is not running this should start the program. If Expedition is
running this should connect to that instance of Expedition.
Note
If an Expedition job other than the existing project is already open, the “Layout
document” path will update to point to it. You will need to exit Expedition and reset the
“Layout document” path.
6. To see the best results set the two Select boxes at the bottom of the Cross Probe window
to “Zoom to Selected”.

Product Integration
Xplore (Cross Probe)
Note
In Expedition there is a Setup -> Cross Probe -> DxDesigner menu item. This will display
a dialog that can be used to launch DxDesigner. DxDesigner will only launch if the
schematic in this menu matches the data for the currently active project selected in
Dashboard.
Using Setup -> Cross Probe -> DxDesigner only starts DxDesigner. You will still need to
follow the steps listed under Using Cross Probing to initiate cross probing between
Expedition and DxDesigner.

The Xplore Tool Module dialog lists all the registered Xplore tool modules. You can use the
dialog to select the schematic tool to which you want to cross probe.
Invoking from Expedition

1. Invoke Setup -> Cross Probe -> XPlore.
2. Select the appropriate schematic module from the list of tool modules, then select the
Connect button.
3. On the Connect Tool Module dialog make sure the Schematic design is correct, select
OK. If the schematic module is not open, select the Launch tool checkbox and then
select OK.
4. Select a component, net or pin in graphics and the corresponding item should select and
fit view in the schematic tool.
5. Select a instance, net or pin in the schematic tool and the corresponding item should
select and fit view in graphics..
6. To discontinue cross probing, on the XPlore Server dialog, select Disconnect for PCB
Design File.
7. Choose whether to close the PCB application.
8. Select the schematic module from the list of tool modules, then select Disconnect.
Connect Tool Module

The Connect Tool Module dialog is used to gather information needed for cross probing. When
opened, the Tool module selected in the Xplore dialog displays.
1. Select the path to the schematic tool directory if not already displayed.

Product Integration
2. Select the Launch Tool check box if you want the schematic tool to be launched on the
selected schematic design directory. If this option is chosen, you are prompted to select a
design viewpoint by using a browse dialog.
3. Select OK.
Invoking from Design Architect

1. Open the viewpoint of the design you want to use for cross probing.
2. Enter into session scope by selecting the SESSION button.
3. Select Setup -> Cross Probe -> Setup Crossprobe. Browse to the Mentor product
directory and locate the Xplore.exe program. To keep from having to enter this path
more than once create a $HOME/mgc/userware/xprobe_da directory. The path to the
XPlore program will be saved in a file called da_session.startup. See Design Architect
Commands below for additional information.
4.
5. Select Setup -> Cross Probe -> Invoke XploreServer.
6. On the XPlore Cross Probe Server dialog, browse to the .pcb file.
7. Choose Expedition PCB from the drop down list.
8. Select the Connect button or select the Connect to running instance if possible
checkbox, then Connect.
9. Select a instance, net or pin in DA and the corresponding item should select and fit view
in graphics.
10. Select a component, net or pin in graphics and the corresponding item should select and
fit view in DA.
11. To discontinue Cross Probing, on the XPlore Server dialog, select Disconnect for PCB
Design File, choose whether or not to close Expedition PCB. Next, select Design
Architect from the list of tool modules, then select Disconnect.
Design Architect Commands

• Enable Crossprobe
Used to open the communication pipe. Use this command when Expedition is already up
and has Design Architect cross probing turned on. If you need to launch Expedition
from Design Architect use the Invoke XploreServer command.
• Disable Crossprobe
Used to close the communication pipe.

Product Integration
Variant Manager
• Setup Crossprobe
Used to define the location of the Xplore server. This program is used to communicate
with Expedition.
• Invoke XploreServer
Used to launch the Xplore server. The Xplore server handles the communication
between Design Architect and Expedition. The server can also be used to launch
Expedition. If Expedition is already up and cross probing has been enabled you should
use the Enable Crossprobe command to initiate cross probing.
• Unselect All
Used to unselect all selected items in Design Architect.
Xplore Cross Probe Server

When you are finished cross probing, you need to disconnect all tool modules and
Expedition PCB before the Exit button will be enabled.
Variant Manager
A variant of a PCB board is a subset of a Master PCB that uses the same bare board as the
master PCB board. The variation consists of removing components and/or replacing
components with other components that fit in the same space as the original component. Variant
Manager can communicate with our other tools by using cross probe highlighting and this
communication can be bi-directional.
The Variant database is based on a database scheme. As new features are added to the Variant
Manager, this scheme may change in order to accommodate the new functionality. The Variant
Manager allows you to upgrade a database from an older database scheme to the current
database scheme.
The library information for the Expedition tools is maintained in a Central Library. This library
contains all information on parts, cell, symbols, etc. Variant manager needs the information
contained in the parts database partitions to determine which parts are available when replacing
components. To optimize the search speed for parts and to be able to create Report Writer
databases, Variant Manager stores the parts database information in a different structure inside
the Central Library. An automated tool to execute this task is supplied with Variant Manager. It
is called the Variant Manager Central Library Data creator.
OBDG Interface
The OBDG interface is used to provide a link to the ODBG family of tools. This is
accomplished by generating an ODB++ Gateway (ODBG) file. The created output filename is
<pcbname>.odb and it is placed in the ../output directory.

Product Integration
OBDG Interface
ODBG to ODB++ Conversions

From the Installation or SupportNet you can download a translator that converts the ODBG
output into the ODB++ format. This is sometimes needed if the vendor you provide data to can
only accept the ODB++ version of the data.
If this program is installed on the same machine as the software, the ODBG dialog displays two
new options. The output from both options will be in the ../output directory.
Launch ODB++ Launches the GW2ODB program which converts the

Convertor ODBG output into the ODB++ format. The output from the
GW2ODB program is a directory structure that is named
<job name>_dir.odb.
Compress Output Only available if the Launch ODB++ Convertor option is
selected. This option causes the output of the GW2ODB
program to be a single compressed file instead of the
directory structure and the output is a single file named <job
name>.tgz.
To run ODBG to ODB++ on UNIX

After selecting the ODBGateway to ODB++ product during installs, a variable needs to be set to
run the interface on a UNIX machine.
The variable should be defined as below:
Solaris setenv GW2ODB_DIR $SDD_HOME/odbpp/sunos5/

HP setenv GW2ODB_DIR $SDD_HOME/odbpp/ux11/
Linux Not Available
For the Valor Gateway converter to run in standalone mode (on command prompt) an additional
variable IPLHOME needs to be set and point to the ODBG converter installation directory; by
default; $SDD_HOME/odbpp/iplhome.
To Define ODBG Output

1. Select the output options; Part numbers, Assembly layers, Generated Silkscreen layer
and Drill Drawing layer.
2. Select a Package Outline Layer from the drop-down field.
3. Check the User Layers option and then select the appropriate user layer and assign the
appropriate mapping layer(s).
4. To select a mapping layer, click on the layer and a drop-down appears allowing you to
select one or multiple mapping layers to the user-layer.

Product Integration
OBD++
Requirement: If a User Layer is selected, one or more mapping layers must be

assigned. If a mapping layer is not defined, a warning message displays. If the layer is
mapped to DOCUMENT then a documentation layer with the same name as the user
layer is created in the output file.
When the OK button is selected, an ODBGInterface.txt file is created in the ../logfiles
job directory containing information based on the options that were selected in the
dialog. This file can be viewed using File Viewer.
OBD++
The OBD++ interface allows you to generate the data directly in ODB++ format, removing the
necessity of the Valour converter unlike the Output > OBD++ Interface which outputs the data
in ODB format (as defined by Valor) and then uses the Valor Converter to convert the data to
ODB++. The created output filename is <pcbname>.ocf and it is placed in the ../config
directory.
ODB++ is an ASCII open format, which captures all CAD/EDA database, assembly and PCB
fabrication knowledge in one single, unified database. This structure allows you to attach
attributes to individual features and save them within the database as the need arises, further
expanding the applicability of ODB++ to suit any purpose.
The ODB++ format represents the complete layout design for interfacing with Valor assembly
and manufacturing tools and other third party applications that accept ODB++.
ODB++ describes a board as steps (panels, boards, and coupons) composed of layers. These
layers consist of positive or negative features with several entities linking features to
components and nets. Data can be easily changed, whether on a localized basis or across the
board. There is no longer any need to deal with complicated definitions: shaves and teardrops
are made of negative and positive lines and cross-hatched areas are drawn as they appear. In
addition, electrical entities are included in the data so the netlist is accurate, apertures and full
electrical attributes are identified and route profiles created.
You can select to Compress the output ODB++ job which is made up of several files describing
the output. If selected, the compression creates a single tar’d and zipped file. The default is
unselected (not compressed).
For all platforms (Windows and Linux), packaging format is gtar followed by gzip utilities. On
Windows these utilities are shipped with the installation CDs and on Linux they are packaged
with the operating system.
If the ODB++ output fails, extraction failure, unable to find gtar/gzip executables, file access
issues or the process generation is cancelled, a dialog is displayed informing you to view the log
file for details.

Product Integration
OBD++
To Define the Output Options

1. Select an existing ODB++ Setup file or create a new definition. By default, these files
are created within your jobs ../config sub-directory with the extension ".ocf".
2. To select an existing file, select the browse button then browse to a directory that
contains this file.
3. To create a new file, select the browse button and keyin the new ODB++ setup filename
in the displayed dialog. The filename cannot contain the following characters, \
(backslash), ! (bang), : (colon), * (asterisk), > (less than), ? (question mark) or ( )
(parenthesis).
4. Select or browse for the output path. By default this path is the job's ../output directory.
5. Select the ODB++ output job name. By default, this is the name of the job with "odb"
appended. You may overwrite this default by keying in a new name.
6. Select or browse for the log file path. By default this is the job's ../LogFiles directory. A
new log file (odblog_xxx.txt) is created for each translation where xxx is incremented in
by 1 for each translation.
7. Select the Append check box to add the log messages to the latest defined log file.
To Define the Basic Export Options

1. Select the Export Mode: Full, Fab or Assy.
Full (Default) All ODB++ job data is represented.

Fab Only fabrication data is represented.
Assy Only assembly data is represented.
The following elements are output to ODB++"
Comp/Pkg + logical nets Outputs ODB++ components, packages and

logical nets which represent a logical connection
between component pins.
Outer layer copper pads Outputs all outer signal layers with data
regarding pads only (not traces or surfaces).
Mask/Paste/Screen Layers Outputs all data on soldermask, solderpaste and
silkscreen layers.
Drill/Route layers Drill and Route layers are output.
Doc layers Documentation layers are output.
Physical Nets Outputs netlist data which is used in the netlist
analyzer of Trilogy / Enterprise.

Product Integration
OBD++
Outer copper layers non- Outputs the data on the outer copper layers; pads,
pads vias, traces, surfaces, etc.
Inner layers Outputs the inner layers.
Raw data files All files that are not essential to the design are
located in the ODB++ format under: checklists,
user, input, forms, flows, etc.
2. Select the Remove EDA data check box if you do not want to export nets, components
and packages information to the ODB++ job. Uncheck to export EDA elements. Default
is unselected.
3. Select the Neutralize nets check box to assign random names to nets. Default is
unselected.
4. Select the Generated Silkscreen data option to allow silkscreen data using the Silkscreen
Generator to be exported to the ODB++ job. If this option is not selected, regular
silkscreen data is exported.
5. Select the Part Numbers option to allow the part numbers to be exported to the ODB++
job.
To Define the Additional Parameters

1. Select the Read DRC features check box to export DRC data (DRC Window, Insertion
Outline, Placement Obstruct, Plane Obstruct, Route Obstruct (Trace, via and both),
Testpoint Obstruct, Route Border) into the ODB++ job. When this is checked, a DRC
button displays. Clicking the DRC button allows you to select the DRC feature and its
ODB++ DRC Layer name. The default is unchecked.
2. Select the Round Corners check box to create round corner surfaces, according to fill
brush or the traces file description. The default is unchecked.
3. Select the Read net0 information check box to allow you to enable read in net0
information.
4. Select the Read in unplated check box to builds padstacks for unplated holes. The
default is checked.
5. Select the Ignore component layout check box to disregard the
Component_Layout_Type property that affects the .comp_mount_type attribute of a
ODB++ component. The default is unchecked.
To Define the Pins, Pads, Via and Package Options

The non-functional pad removal options enable padstack optimization of unused pins and pins
with no net.

Product Integration
OBD++
1. Select a Pins option from the pulldown.
None (Default) There is no removal of non-functional pads.

Unused Pins Removes isolated pads not connected to any
other copper pad, trace or surface.
Pins with No Net Removes pads in net $NONE.
The following rules are applied:

a. Pads are removed on signal layers only.
b. Pads are not removed for external signal layers of the padstack span.
c. SMD pins are not processed.
d. Only isolated pads (not connected to any other copper pad, trace or surface) are
removed.
e. Each modified padstack is assigned with the attribute .pf_optimized on the pad in the
matching drill layer. This enables the identification of layers where padstack
optimization, the removal of pads, has taken place.
f. In case Pins with No Net option is selected, rules b and d are ignored.
2. Select a Vias option from the pulldown. This enables padstack optimization of unused
vias. The rules are the same as described above. Rule f is not applicable.
None (Default) There is no removal of non-functional pads.

Unused Vias Removes isolated pads not connected to any
other copper pad, trace or surface.
3. Select the appropriate package outline layer. The options are:

• Placement Outline
• Assembly Outline
• Insertion Outline
• Silkscreen Outline
• Default User Layer
• Any User Layers
• Cell Graphics
• Edge Copper
• Plating Layer
• Dimension Layer

Product Integration
OBD++
• Panel Layer (Only displays in FabLink XE in a Panel design)

• Panel Text (Only displays in FabLink XE in a Panel design)
3. Select the Rotate by Components option if you want the system to rotate the ties together
with the component. The default is Rotate by Component.
4. Select the No rotation option is you want to rotate the ties manually.
Define User Layer Mapping

You have the option of exporting the user layers to a ODB++ job by mapping the user layers to
one or many layers. A user layer can be mapped to more than one intelligent layer by selecting
multiple boxes in the list.
1. Select the one or more user layers from the list.

Requirement: To include a layer for output, the checkbox for that layer has to be
selected.
2. Select the drop-down in the mapped layer column to assign one of the mapped layers to
the user layer. If the layer is mapped to DOCUMENT, a documentation layer with the
same name as the user layer is created in the ODB++ job. A user layer can be mapped to
more than one intelligent layer by selecting multiple boxes in the list.
Compress Output
You can select to Compress the output ODB++ job which is made up of several files describing
the output. If selected, the compression creates a single tar’d and zipped file. The default is
unselected (not compressed).
ODBG ++ DRC Features

This button displays when the Additional Parameters > Read DRC Features option is checked in
the main ODB++ Output dialog. All the options are checked in the initial opening of this dialog.
The first column allows you to select the DRC feature and its ODB++ DRC Layer to include in
the output. To include a DRC feature and layers for output, the checkbox has to be selected. The
DRC Feature column lists all the DRC data that can be output to the ODB++ job in the ../layers
directory of the step.
The ODB++ column is populated with the default ODB++ DRC layer names. If you want to
change the layer to output the DRC features, you can edit the layer names by clicking on a layer
and then using the Delete keyboard key to remove the name or by double-clicking on the layer
name, which cause it to highlight, and then typing the new name.
Select OK to save the scheme. This is saved by default in a setup file in the ../config directory of
the design. On reopening the dialog the previous settings are restored. If you have made changes
and select Cancel, a warning message appears informing you that all changes to the dialog will

Product Integration
OBD++
be lost. Pressing OK in this message box rejects the changes; pressing Cancel returns you to the
DRC features dialog.
Creating Special Properties

Special properties for inclusion into ODB++ must be created in Library Manager (Tools >
Property Definition Editor), and then assigned as required to the parts in the Part Editor and then
be Forward Annotated to the designs.
The properties have the form 'ODB++.<name>. For example; the property required for
.COMP_TYPE is 'ODB++.COMP_TYPE'. The software strips off the 'ODB++' part when it
creates the ODB++ file.
The values available for the ODB++.COMP_TYPE are defined in the file
..\SDD_HOME\standard\config\pcb\sysAttr.att in the section # .comp_type.
To Create ODB++ Properties

1. Open Library Manager and select the appropriate central Library.
2. Select Tools > Property Definition Editor.
3. Click the New Property icon. The software places a new entry at the bottom of the list
(New Property1).
4. Click in the Name field, and key in ODB++.COMP_HEIGHT property name and select
a format from the dropdown list. The available options are; Character String, Integer or
Real.
5. Tip: Continue creating specific ODB++ property names as required.
6. Select the checkbox, if you want to place the property in the schematic when Packager
or Place Device is used.
7. Select the Advanced button. This allows you to set up all the options which are available
in the centlib.prp file. Regular expression options can be built up from "single-
characters.
8. Select Apply and the OK button. The dialog dismisses.
9. Open Tools > Part Editor.
10. Select the appropriate Part Listing.
11. In the Component Properties section, Select the New Icon.
12. Under Name select the ODB++.<name> property and assign a Value.
13. Select File > Save in the Part Editor.

Product Integration
Enterprise 3000
14. Open Expedition PCB and load the design. An informational dialog appears telling you
that changes require a Forward Annotation. Select Yes.
15. The Project Integration dialog appears. Double-click on the Amber light next to the
Forward Annotation Required button.
Enterprise 3000
The Enterprise 3000 option allows you to view an area and layer combination as if it were
displayed in Enterprise 3000. The view pans and zooms to display the same board area in
Expedition PCB as is displayed in Enterprise 3000. Items in the Display Control dialog may be
turned on or off to facilitate the change of view.
Scepter
The Scepter Panelization product offers an environment that allows you to create panel boards
from single board gerber data and NC Drill data created by Expedition PCB. You can take
advantage of easy to use panel creation features to step-and-repeat boards and create venting
and thieving features and then create panelized gerber and drill files from the interface.
1. From the Expedition PCB pulldown menu, select Output -> Scepter Interface. A
message displays when the Scepter interface has completed its creation of the Scepter™
files.
2. Change directory to the ../output/Scepter directory located in the job directory.
3. Start Scepter by double-clicking the exppcb.set file.
OrCAD Interface
The OrCAD to Expedition Interface is used to establish a link between an OrCAD schematic
and an Expedition PCB design and to designate how the flow of information between the two is
handled; either through Back Annotation or Forward Annotation.
The figure gives the flow of information (forward and back annotations) across the interface.
The arrows indicate flow of information. The netlist information along with net names
information is generated by the MentorKYN netlister. The input for the MentorKYN netlist
formatter is the OrCAD .onl netlist file. The net names information (netprops.hkp) is used in the
Net Properties/Net Class dialogs in the interface. This file (netprops.hkp) is produced by the
netlist formatter.

Product Integration
HyperLynx
Figure 5-10. OrCAD to Expedition Flow
The Net Class and Net Properties dialogs are present in both the interface and the PCB. The
Back Annotation (BA) information generated by the PCB is used by the interface to generate
back annotations in OrCAD's .swp format.
HyperLynx
The Export to HyperLynx option allows the exchange of high speed information from the
PCB environment to the HyperLynx® environment. BoardSim® reads the data representing a
routed PCB and performs signal-integrity and EMC analysis on the board. In BoardSim, signal-
integrity results appear either as signal waveforms in an oscilloscope (interactive mode) or in a
multi-net analysis report (batch mode). EMC analysis works the same way, except that it occurs
in the frequency domain and interactive results appear in a spectrum analyzer.
When this option is selected, the following files are created and are stored in the
<jobs>/output/ subdirectory:
<jobname>.hyp - A .hyp file is an ASCII file in a HyperLynx-proprietary format. It contains

all of the information about a PCB layout needed for signal-integrity simulation. This file is
loaded into BoardSim and simulated.
• Board Outline - The board outline data defines the shape of your board.
• Stackup - The stackup data defines your board's layer stackup. A stackup includes
information about signal, power-plane, and dielectric layers.

Product Integration
XTK/QE
• Devices - The device data defines the components on your board. Device information
includes reference designators, component names (for ICs), and component values (for
passive components).
• Padstacks - The padstack data defines the various pad stacks used on your board.
• Nets - The net data defines the nets on your board. Net information includes definitions
for each metal segment, via, pad, and device pin on the board.
The net information is required. BoardSim must have detailed information about trace
metal to model and simulate the net.
• Comment Lines - Comment lines in the .hyp file must have an asterisk (*) in the first
column. On rare occasions, you may wish to remove an element from a .hyp file by
commenting out the element's line. For example, if you wished to remove a resistor's pin
from a certain net, you could precede the pin's record with an asterisk:
*(PIN X=2.100 Y=2.350 R=Udrv1.1 P=PS4) This is now a comment line
<jobname>.ref - This file contains discrete model information. The .ref file can be used to
maps model to reference designators, is required to assign .EBD models, and it is also required
to back annotate model changes to your PCB design system (ECO - engineering change order).
GeneralInterfaces.txt - This log file can be viewed using the File Viewer dialog.
XTK/QE
The Export to XTK/QE option allows the exchange of high speed information from the PCB
environment to the XTK™ and Quiet™ Expert environments. XTK (the Crosstalk Tool Kit)
identifies and analyzes signal integrity problems caused by electromagnetic interference.
Electromagnetic interference, or crosstalk, occurs when the magnetic field created by one trace,
affects the current on an adjacent trace. You use XTK to identify and analyze the sources of
crosstalk within the PCB design.
When this option is selected, the following files are created and are stored in the <jobs>/output/
subdirectory:
<jobname>.mdi - Defines the Model Data In format (MDI) file. The MDI file contains default
models for all devices that may cause series connections in the design. Such parts are resistors,
capacitors, inductors, diodes, and resistor packs (SIPS and DIPS).
<jobname>.qnf - Defines the Quad Design Netlist Format (QNF) file for this design. The QNF
file details information about the physical placement as well as connectivity information. The
physical placement section (PARTS) associates the location designator with the part type,
rotation, position, and package type. The connectivity section (NETDEF) associates a net name
with the part pins to which it is connected.
<jobname>.isf - Identifies the location of every conductor, segment, pin, and via in the design.

Product Integration
XTK/QE
<jobname>.gcf - This is an ASCII text file that helps define many of the physical
characteristics of your design. The .GCF file is divided into 6 sections and each section contains
a series of keywords that require a value. These keyword/value pairs define the design's
characteristics. Detailed information about the .gcf file can be found in the online help delivered
with the XTK product.
GeneralInterfaces.txt - This log file can be viewed using the File Viewer dialog.

Product Integration
XTK/QE

Chapter 6
Microvia Routing Strategy
With the Microvia design option, you have control over the via spans the router uses and which
layers are to be targeted. If a via range partially overlaps the via range of another via or, if a via
range starts on the same layer another via ends on, and the via range is not fully included in the
other via range, then the via is considered a microvia.
• In the Net Classes and Clearances dialog box, you can specify that certain via spans are
not to be used for that Net Class by choosing "(None)" for the span.
• When setting up the routing passes, you can disable certain layers on a per pass basis,
thus restricting which via spans are used by the router.
When using microvias, the routing algorithms are affected by the settings on the Vias tab in
Setup Parameters and the use of the Auto Route Schemes. The router looks at the layer type
settings (either Buildup or Laminate) for each layer and uses special algorithms dependent on
the setting. The setup of the auto router for microvia designs is also different.
Fanout with Micro and Blind/Buried Vias

The following are the rules used to determine how a single user-defined Auto Route "fanout"
pass will be rationalized into multiple fanout passes. A via fanout pass from 1-6 will be broken
down (rationalized) into the available via spans, for example, 1-2, 2-3 & 3-6.
Laminate Designs
A laminate design is defined as any design that does not have any buildup layers defined on
Setup Parameters - Vias tab. The following rules apply to Laminate designs:
Laminate Rule 1
This first rule describes the behavior of a fanout when layers 1-k are enabled during the fanout
pass and layer k is not the bottom layer.
• When the laminate design has no defined via span that goes directly from layer 1 to layer
k, a single user-defined fanout pass will be rationalized into multiple fanout passes, each
using a via span that allows the vias to be staggered or stacked until layer k is reached.
Therefore, if 1-k are the enabled layers and there is no existing via that spans 1-k within
the design, multiple fanout passes will be run with each pass using a via span allowing
these vias to staggered or stacked until layer k is reached. For plane nets, the vias will
stagger or stack until the plane layer is reached as long as the layer is less than k.

Buildup Designs
• When the design has a via span defined spanning 1-k, a single fanout pass will be run
using the 1-k via. This will allow fanout to use one via span 1-k to fanout directly to the
target layer k.
Laminate Rule 2
This second rule describes the behavior of a single fanout pass with all layers enabled and the
top-to-bottom or bottom-to-top options are NOT selected.
• When the Auto Route fanout pass is run with all layers enabled, a single fanout pass will
be run using the shortest via span, starting from the top. For plane nets a via span starting
from the top that connects directly to plane layer will be used if available.
Laminate Rule 3
The third rule describes the behavior of a single fanout pass with the top-to-bottom or bottom-
to-top Auto Route layers option selected.
• When the design has no through via defined, a single user-defined fanout pass will be
rationalized into multiple fanout passes, each using a span that will allow vias to stagger
or stack until the target layer (top or bottom) is reached. If the vias spans within the
design are not defined so the top or bottom layers can be reached by staggering or
stacking spans, then it will fanout into the design as far as it can. For plane nets, the vias
will staggered or stacked until the plane layer is reached.
• When the design has a through via, a single fanout pass will be run using the through
via.
Buildup Designs
A buildup design is any design that has one or more layers defined within the Setup Parameters
Vias tab as a buildup layer. The following rules apply to Buildup designs:
Buildup Rule 1
This first rule describes the behavior of a fanout when layers 1-k are enabled during the fanout
pass and layer k is not the bottom layer.
• When the buildup design has no via span defined that goes directly from layer 1 to layer
k, a single user-defined fanout pass will be rationalized into multiple fanouts passes,
each using a via span that allows the vias to be staggered or stacked until layer k is
reached or the first laminate via span is placed. For plane nets, the vias will stagger or
stack until the plane layer is reached as long as the layer is less than k.

Buildup Designs
• When the design has a buildup via span defined that includes layers 1-k, a single fanout
pass will be run using this 1-k buildup via span. This will allow fanout to use one via
span 1-k to fanout directly to the target layer k. However, if the via 1-k span defined is a
laminate via, the user-defined fanout pass will be rationalized into multiple fanouts
passes each using a via span that allows the vias to be staggered or stacked until layer k
is reached or the first laminate via span is placed.
Buildup Rule 2
This second rule describes the behavior of a single fanout pass with all layers enabled and the
top-to-bottom or bottom-to-top options are not selected.
• When the design has all layer defined as buildup (very rare), a single fanout pass will be
run using shortest via span starting from the top or a via span starting from the top that
connects directly to plane layer.
• When the design has buildup and laminate layers defined, a single user-defined fanout
pass will be rationalized into multiple fanouts passes, each using a via span that allows
the vias to be staggered or stacked until the bottom layer is reached or the first laminate
via span is placed.
Buildup Rule 3
The third rule describes the behavior of a single fanout pass with the top-to-bottom or bottom-
to-top Auto Route layers option selected.
• When the design has no through via, a single user-defined fanout pass will be
rationalized into multiple fanouts passes each using a via span that allows the vias to be
staggered or stacked until the target layer, top to bottom, is reached. If the via spans
within the design are not defined so the top or bottom layers can be reached by
staggering or stacking spans, then it will stagger or stack the spans into the design as far
as it can. For plane nets, the vias will staggered or stacked until the plane layer is
reached.
• When the design is a through via and all layers are defined as buildup (very rare), a
single fanout pass will be run using the through via span. However, if the through via
span is used in a design that has both buildup and laminate layers defined, the user-
defined single fanout pass will be rationalized into multiple fanouts passes each using a
via span that allows the vias to be staggered or stacked until the target layer, top to
bottom, is reached.
Note
These rules are not used if the route during fanout option is enabled or if "Simple fanout"
passes are run. Also, if a layer is disabled in Editor Control for routing, fanouts will
rationalize and stop at this disabled layer.

Examples of Laminate and Buildup Fanouts

Rationalizing a single fanout pass into multiple fanout passes allows vias to be staggered or
stacked based on the available via spans. The examples below are setup with a single user-
defined fanout pass that is automatically turned into multiple fanout passes during Auto Route.
Examples 1-3 are based on the via span and layer setup defined as seen below in Setup
Parameters. The design is setup to have 8 layers with via spans 1-2, 2-3, 6-7 and 7-8 defined as
buildup vias and via span 3-6 defined as a laminate via.
Figure 6-1. Setup Parameters Vias Tab Example 1
Example 1
If a single Auto Route fanout pass is defined with layers 1-4 enabled for routing and Setup
Parameters vias are defined as seen above, a single fanout pass would rationalize into:
• Fanout 1-2
• Fanout 2-3
• Fanout 3-6
This method of rationalizing a fanout pass allows the router to stagger or stack vias until the
laminate via is placed. Figure B-1 shows these spans as they were staggered through the design
until the first laminate via was placed.

Figure 6-2. Stagger vias to target layer 4
Example 2
If a single Auto Route fanout pass is defined with All Layers enabled and Setup Parameters vias
are defined as seen above, a single fanout pass would rationalize into:
• Fanout 1-2
• Fanout 2-3
• Fanout 3-6
This method of rationalizing a fanout pass allows the router to stagger vias so they reach the
first laminate layer. Figure B-1 shows these spans as they were staggered through the design
until the first laminate via was placed.
Example 3
If a single Auto Route fanout pass is defined with All Layers enabled and the Top-to-Bottom
option is selected, a single fanout pass would rationalize into:
• Fanout 1-2
• Fanout 2-3

• Fanout 3-6
• Fanout 6-7
• Fanout 7-8
This method of rationalizing a fanout pass treats the bottom layers as if all nets had a target
plane shape on the bottom of the design. Therefore all nets, except plane nets, would stagger
vias until it reached the bottom layer of the design.
Figure 6-3. Stagger vias to target layer bottom

Example 4
For this example all layers are defined as laminate as seen in the setup defined below within
Setup Parameters.
Figure 6-4. Setup Parameters Vias Example 4
If a single Auto Route fanout pass is defined with layers 1-6 enabled and all layers are laminate,
a single fanout pass would rationalize into:
• Fanout 1-2
• Fanout 2-3
• Fanout 3-6
This method of rationalizing a fanout pass simply staggers vias until it reaches the target layer
which is layer 6 as defined in the enabled layers for the Auto Route pass.


Chapter 7
Rule Areas
Rule Areas are user-defined shapes that provide you with the ability to define a region of the
board where special trace widths or clearances should be used. This functionality greatly
improves routing around BGA's and other fine-pitched parts, where the normal routing rules do
not allow the part to be connected to the rest of the design. A rule area may be any of the
standard closed objects: Polygon, Rectangle and Circle, by using the Draw Properties dialog.
Note
A DFF license is required to view the DFF Schemes that contain Rule Areas in the Draw
> Properties > Rule Area dialog.
Rule Areas can be defined on a per layer basis or defined to affect all layers within that area.
Each Rule Area, when placed, should be assigned a Net Class scheme while in Draw. Rule areas
can be selected, added, deleted or modified only in Draw mode .
The Net Class schemes are defined in the Net Classes and Clearances menu. You can use
existing schemes as a starting point for defining new schemes by using the "Copy Scheme"
command on the active scheme. If you want to use the Master scheme as the starting point for a
new scheme definition use the "New Scheme" command.
Figure 7-1. Rule Area Property Dialog and Example

Rule Areas
Master Scheme
Rule areas allow you to route into, and through the areas of fine pitch parts (BGA, etc.) as seen
below. Notice how the trace widths and the clearances change when traversing into the rule
area. You may also change via sizes and spans in a rule area to maximize route completion.
Figure 7-2. Rule Area Example
• If the Display Control - Rule by Area option is selected; the color of the rule area is the
same as the traces for that layer. If the Rule Area is set to "All" layers, the color is a
preset color defined by the system.
• If a rule area is dropped on existing traces or vias, pre-existing traces and vias stay the
same, however, all new trace and vias follows the rule area.
• If a rule area is deleted, all the pre-existing traces and vias remain the same. Any new
trace or via added to the area will use the default settings of the pre-existing traces and
vias.
• If a Change Width command is activated inside a rule area, it takes precedence over the
area rules.
• If a Change Via command is activated inside a rule area, it takes precedence over the
area rules
Two defined net class schemes, Master and Minimum, have been provided as defaults. Other
user-defined schemes can be created and saved in the Net Classes and Clearances dialog.
Master Scheme
The master scheme represents the majority of your board's clearances and widths. These
clearances and widths are used for all areas and for layers which do not have a rule area and
scheme assigned.
Net class names can only be added or removed when the master net class scheme is selected.
Also, the routing layers that are enabled or disabled for each net class can only be changed for
the master net class scheme. All other net class options can be changed for any new net class
schemes that are created.

Rule Areas
Minimum Scheme
Minimum Scheme
The rules in the Minimum scheme reflect the minimum rules required for manufacturing
purposes. Traces, vias and pads within a rule area are checked according to the Net Class
Minimum scheme. Because each rule area can have a different net class scheme, and because
each net class scheme can have a full set of widths and clearances, it may be difficult to tell if
some of the rules have been set below the minimum acceptable rules for manufacture. The
Minimum scheme allows you to have confidence that you are not violating manufacturing
minimums.
Typically, the minimum net class scheme is not assigned to a rule area on the board, however if
you have an area that requires the absolute minimum clearances that you have defined across all
other net class schemes, this scheme could be assigned to a rule area on your design. To have
more direct control over a scheme, it is suggested that you create one yourself and only change
the clearances and widths that are necessary to complete the routing within an area.
Overlapping Areas - Same Layer

It is possible to have overlapping rule areas and when they do the rule of the smaller area is
applied.
Figure 7-3. Example of Overlapping Areas in Rule Area
The rules found in the blue area apply, no matter whether the rules themselves are smaller or
larger than those found in the green area.
Overlapping Areas - Adjacent Layers

It is possible to have rule areas in the same area but on different layers. In this case, the rules of
the smaller area apply just as they do for overlapping areas on the same layer. The only objects
that this rule applies to are vias. When a via passes through more than one rule area, the via span
assigned to the smallest area is used.
If rule areas overlap and are the same size, then the priority is based on the alphabetical order of
the Net Class scheme names assigned to each shape.

Rule Areas
Remap Rule Area Schemes

If you type remap in the keyin window, a dialog displays that allows you to align rule areas
within a cell’s scheme with that of the design the cell is being applied to. Once the assignments
are made, the rule areas for each cell within the localized library and design are adjusted to the
user settings.
Cell Name Displays the name of the cell within the local cell library.
Scheme Displays the cell's current scheme assignment.
Design Displays a listing of available schemes within the design’s Net
Schemes Class & Rules database.
By default, if a new scheme name matches one already defined, it is matched with the one in the
design. If there is no match, the scheme is defaulted to (Master) and you can use the drop-down
list to assign the scheme to the appropriate name.
Caution
There is a potential for excessive memory allocation if too many rule areas are used in
any particular design.
To access the Remap Rule Area Schemes dialog

1. Click in the keyin window.
2. Type remap and click Enter.
If the keyin window is not displayed, select View > Toolbars > Customize and in the
Toolbar Tab make sure that Keyin Command option is checked, then select Close to
dismiss the Customize dialog.
Rule Area Schemes Information

Within Draw, rule areas can be placed within package cells on the Top, Bottom, Mount,
Opposite, Inner layers or All layers when applied to the design. You would not typically assign
the rule area to be layer specific at the cell level. At the design level, the Top, Bottom, Mount,
and Opposite layer setting on rule areas will be mapped to the appropriate design layer (1, 6,
etc.).
Once a rule are is placed within a package cell, you will be able to select it from the design level
and adjust its assignment without having to re-enter Cell Editor.
The basic design behavior that occurs today when rule areas overlap or are contained within
other rule areas is the same for those within cells. In other words, the behavior would be the
same as if you manually place a rule area outside of the cell within or overlapping another area
on the design.

Rule Areas
Rule area shapes that are built into cells are not permitted to be separated from the cells at the
design level. Once you have designated the appropriate Rule Scheme mapping at the design
level, the information is maintained for future cell updates from the Central Library, so you are
not required to remap the schemes when cells are updated from the Central Library.

Rule Areas

Chapter 8
Reusable Blocks
This Appendix describes the process flow of using the Expedition PCB reusable block
enhancement within the Central Library, Schematic and Layout Design. At the end of this
Appendix is a list of reusable block definitions.
The reusable block can contain parts, interconnects, vias, shape fills, plane information, design
rules, obstructs, contours, slots, mounting holes, user-defined graphics and rules by area. It
cannot contain a board outline or route border.
Instance changes within the Reusable Blocks Editor are not saved with the reusable block cell,
therefore they are not reflected once placed within a design. Instance changes (for example, text
modification) are changes to objects built within cells within the Reusable Block Editor.
The Central Library stores both a reusable block design (both Design Capture schematic and the
Expedition PCB design) and a reusable block cell. The reusable block design is used to
generate the data needed to save a reusable block cell that can be used by other designs.
Central Library Storage

All reusable blocks created within the Central Library are stored within the Central Libraries’
ReusableBlocksLP sub-directory. Under this sub-directory each reusable block has it's own
directory which contains a Work and Cert sub-directory. The Work sub-directory contains the
reusable block design layout and schematic data.
Once the reusable block cell is saved, all referenced schematics are copied to the Cert sub-
directory as read-only files and these files are used when the reusable block is placed within
schematics, so they keep in sync with the current, saved reusable block cell. These schematic
files are also made read-only to ensure no changes are made to invalidate the reusable block. At
no time should Design Capture or Expedition PCB be run directly on these databases. Changes
made directly to these databases will corrupt the reusable block contents. The Reusable Block
interface within the Central Library editor must be used to make all changes to the reusable
block.
Reusable Block Interface

Library Manager provides tools to create , copy , rename and edit a reusable block.
The reusable blocks stored in the Central Library are accessible to all Design Capture
Schematics and Expedition PCB designs referencing this same Central Library.

Reusable Blocks
Reusable Block Interface
Interface List - The Reusable Blocks interface has a list of all Reusable Blocks within the
central library. This list contains columns that state the Block Layers, Status, Design Modified
and Cell Modified dates.
• The Block Layers column displays the minimum number of layers that are needed in
order to use the reusable block within other designs. The number of layers is defined
within the reusable block design just like any other Expedition PCB design. The Block
Layers can be changed by editing the reusable block and using Setup Parameters to
remap the number of layers used by the design.
• The Status column displays the current status of the reusable block design as Verified or
Unverified.
o A Verified reusable block design is ready to be used within other designs and has
had a reusable block cell saved. This does not mean that the reusable block design
and reusable block cell are physically the same. It just means that the requirements
to save a reusable cell have been meet and no changes to any of the referencing
Central Library objects have been made since the reusable block cell has been saved.
o An Unverified reusable block means the reusable blocks cell has not been saved, or
that changes have occurred to one or more of the reusable blocks library objects
within the Central Library.
• The Design Modified column displays the Date, Time and the name of the user who last
edited and saved the reusable block design. Because changes are allowed to the physical
reusable block design while others are using the reusable block cells, the date and time
maybe different between the reusable block design and cell generated by the design. By
reviewing the difference between the date and time of the reusable block design and cell,
you will be able to determine if changes have been made to the reusable block design
that might require the reusable block cell to be re-saved.
• The Cell Modified column displays the Date, Time and the name of the user who last
saved the reusable block cell. Because changes are allowed to the physical reusable
block design while others are using the reusable block cells, the date and time maybe
different between the reusable block design and cell generated by the design. By
reviewing the difference between the date and time of the reusable block design and cell
you will be able to determine if changes have been made to the reusable block design
that might require the reusable block cell to be re-saved.
Create New - This option allows you to insert an existing Expedition PCB design, as well
as its schematic, into the Central Library and assign it a unique reusable block name. The
existing design inserted into the Central Library may be purposely created as a reusable block
design or an existing board that is adjusted to contain only the circuitry needed for the replicated
circuit. If a design is to be converted, the conversion can be done before or after it has been
inserted into the Central Library. The creation of a reusable block does not create the reusable
block cell used by other designs, this is done after the reusable block has been inserted into the
Central Library, opened for editing and the Save Reusable Block command has been selected.

Reusable Blocks
Reusable Block Design
Copy - This option allows you to take an existing reusable block and create a copy of it
with a different reusable block name. By default, this new reusable block is unverified. Copy is
primarily used to create new versions of a reusable block once a logic change is required to an
existing verified reusable block. Copy does not make a duplicate of the reusable block cell,
therefore, in order for the reusable block to become verified, the reusable block has to be
opened, verified and the reusable block cell saved.
Rename - This option allows you to change the name of your reusable block which causes your
reusable block to become unverified. Once you have renamed the reusable block in order for it
to become verified, you will have to open it and save the reusable block cell. A rename of a
reusable block does not affect any of your schematics, already referencing this reusable block
before the rename, therefore, these schematics have to be manually updated to reference this
new reusable block name.
Edit - This command opens a reusable block using Expedition PCB. An Expedition PCB
license as well as a Reusable Block license is required, in order to open a reusable block. Once
in Expedition PCB, you can edit your reusable block, then once verified, save it as a reusable
block cell. The Expedition PCB interface, when run on a reusable block design has been
streamlined to only include the core layout functionality.
Delete - This option allows you to remove a reusable block from your Central Library.
However, if you have existing schematics that reference this reusable block, they have to be
manually edited and the block removed. It is suggested that blocks only be removed if they are
no longer referenced or used by any designs; including designs that have been archived.
Undo Delete - This option allows you to undo the removal of a reusable block after it has
been deleted from the Central Library. This option is only selectable while you are still in the
reusable block dialog and restores the last deleted reusable block.

The reusable block design is made up of a Design Capture schematic and an integrated
Expedition PCB design. The reusable block design is inserted into the Central Library based on
an existing data set that may need to be adjusted in order to reflect only the logic and physical
parts required by the reusable block. This adjustment, described below, can be done before or
after the data set is inserted into the Central Library.
Schematic Adjustments
If an existing design has a circuit that needs to be converted into a reusable block, the design's
schematic needs to be cleaned up to only include the logic required by the physical reusable
block. Once a reusable block has been placed within a Central Library, Design Capture should
only be run on the database by launching it from within Expedition PCB during an edit of the
reusable block. The following changes to the schematic must be made in order for it to be used
with the reusable block software:

Reusable Blocks
• Reusable blocks do not support multiple instance hierarchy of the same schematic block.
The schematic should be built as a single, multi-page, flat schematic or if hierarchical
bocks are used, they can only exist once within the reusable block.
• The schematic must be reference the Central Library that it will be incorporated into.
You will not be able to create a reusable block within a Central Library if the design
does not reference the Central Library the reusable block is being inserted into.
• All schematic symbols within the reusable block schematic should exist within the
Central Library symbol partitions.
• All schematic symbols should be verified that they are the latest, as defined in the
Central Library. It is critical that the reusable block schematic be up-to-date with the
latest symbols and parts within the Central Library.
• Hierarchal pins must be defined within your reusable block schematic to represent any
inputs or outputs needed to connect your reusable block to other circuitry.
• All iCDB properties must be absorbed into the root schematic. The iCDB is not used
once the reusable block design has been saved as a reusable block cell.
• The schematic block name and sbk name must be the same as the reusable block name.
• The project file’s root block must be defined. Verify, using the Design Capture Block
view, that the correct schematic is referenced as the root block.
Layout Adjustments
Once the reusable block schematic has been updated, the reusable block layout can be defined
or adjusted to meet the needs of the reusable block schematic. This design should be treated the
same as any other Expedition PCB design and the same processes can be used in its creation.
The following adjustments should be made to the layout before the reusable block cell is
created:
• It is very important that the extraction partition search order scheme used by the reusable
block is the same as the one used for designs using the reusable block, especially if
multiple symbols and cells of the same name exist in your Central Library. Verify the
correct Central Library extraction scheme is selected and run Forward Annotation to
compile your reusable block’s schematic. Because it's important to keep your reusable
block design in sync with the library objects within the Central Library, Forward
Annotation will always delete the local libraries to reflect the Central Libraries data set.
• Verify that the number of physical layers used by your reusable block is the minimum
that will be used for all designs that use this reusable block. Reusable blocks will not be
used in designs with fewer layers than the reusable block itself.
• The board outline and route border are only used to create the design and are not used
once it is saved as a cell. Define these large enough to encompass your part placement

Reusable Blocks
and routing. The board outline will be used as the physical extents of your reusable
blocks placement and routing.
• Verify the board origin is placed correctly as this will be used as the cell origin of the
created, reusable block cell, and thus the point on which the reusable block cell is placed
in other designs. Changing the board origin after a reusable block cell has been used in
other designs will cause all connections to that block to be ripped up or lost so it is
important to place this origin correctly the first time.
• Plane layers defined in Setup Parameters without a plane shape are not saved as part of
the reusable cell used within other designs. All defined, planes should also have a
placed, physical plane shape unless these shapes will be defined globally within the
designs that used the reusable blocks.
Saving the Reusable Cell

Once your reusable block design is complete and all physical and logic changes have been
implemented and verified, it is time to create the reusable block cell. At this point, you must
ensure the design is finished as if it is being readied for manufacturing. Therefore, all of the
normal processes to ensure a design is correct must also be used on a reusable block before it is
saved as a reusable block cell. Once the reusable block cell has been saved, no other logic
changes are allowed. If logic changes are required after a reusable block cell is saved, the
reusable block must be copied to another reusable block name and then the logic changed. The
following should be done before you save your design as a cell:
• Verify that your physical design is in sync with the schematic, no Forward or Back
Annotation should be needed.
• Verify all parts referenced by your reusable block schematic have been placed.
Unplaced parts within your reusable block will cause problems once the reusable block
cell is placed in other designs.
• Verify that all connections within the reusable block have been made and the reusable
block design is 100% routed.
• Verify that the physical design does not have any DRC violations, using both Online and
Batch DRC. All hazards should be resolved before the reusable block cell is saved.
• Select File -> Save Reusable Block
When a reusable block cell is saved, the software automatically performs the following
verification:
• All of the library objects, PDB's, cells, padstacks and symbols are the latest, as defined
in your Central Library.
• The logic within your reusable block schematic is in sync with the reusable block design
and Forward or Back Annotation is not needed.

Reusable Blocks
• The iCDB and schematics are in sync and the iCDB does not need to be compiled or the
schematics, needing the iCDB instance properties, absorbed.
• The schematic block and schematic names are the same as the reusable block name.
• The reusable block layout name is the same as the reusable block name.
• All library objects exist in the Central Library.
Once the reusable block cell has been saved, it is marked as verified and can be used by other
designs referencing the Central Library.
The following objects placed within the reusable block design are not saved with the reusable
block cell:
o Batch DRC Window

o Board Outline
o Copper Balancing Shapes
o Detailed Views
o Drill Drawing - Through Layer
o Guide Pins
o Instance changes (fro example text modification)
o Placement Rooms / Clusters
o Plane Data generated by the Planes Processor
o Reserved Areas
o Route Border
o Virtual Pins
o All Net Properties and net classes, defined within the reusable block design, are not
saved with the reusable block cell. These have to be redefined, within any design
that uses rule areas in the reusable block.
Becoming Unverified
Once a reusable block has had its reusable block cell saved, any changes to padstacks, parts or
cells within the Central Library, referenced by the reusable block, will cause the reusable block
to be marked as unverified. Unverified means that a change has occurred that requires re-
verification of the reusable block and a re-save of the reusable block cell. A reusable block that
is unverified is not allowed to be placed within schematics or extracted into Expedition PCB
designs until it is re-verified. If there are newer, cells or padstacks referenced by the reusable
block, Forward Annotation does not bring them into the local design until the reusable block is

Reusable Blocks
Using a Reusable Block
re-verified. This insures that the local reusable block cell remains in-sync with the Central
Library.
Re-verification is achieved by re-entering the reusable block design and following the same
steps as was used to save the reusable block cell. Once the reusable block cell is saved, it is set
to verified once again. The only time a reusable block is not allowed to be re-verified is when a
PDB part number used by the reusable block is changed. PDB changes require that the reusable
block is Forward Annotated before the reusable block cell can be save and verified.
Forward Annotation is not allowed once a reusable block cell has been saved. At this point you
will have to copy the reusable block to a different name, Forward Annotate and then save the
reusable block cell. This new reusable block has to be referenced by all schematics that
referenced the original reusable block.

Once a reusable block has been added to the Central Library and the reusable block cell has
been verified and saved, the reusable block can then be used within any Design Capture
schematic referencing the same Central Library.
Reusable Blocks used within Design Capture

In order to place a reusable block within your Design Capture schematic you must first make
sure the schematic is referencing the Central Library that will be used by both the schematic and
Expedition PCB layout. Once you select the Place -> Block command, the dialog lists all of the
verified reusable blocks located within the referenced Central Library. The reusable block can
then be selected from the list and once the OK button is selected, the reusable block will attach
to your cursor. Changes to a reusable block's schematic invalidates your reusable block and
causes errors when it is used within Expedition PCB, thus all reusable block schematics are
placed read-only.
Now that you have placed a reusable block within your schematic, you must run the iCDB
Compiler and Packager in order to prepare and verify your schematic data to be used by
Expedition PCB. The Packager updates the reference designators used within the reusable
block so they are unique within your design. This is done by pre-pending the block’s unique ID
to each reference designator defined within the reusable block.
Reusable Blocks within Expedition PCB

Once the schematic reusable block is placed, compiled and packaged within the Design Capture
schematic, the reusable block can be placed in the physical Expedition PCB design. The first
thing that must be verified is that the extraction search order scheme, used within Expedition
PCB, is the same as the one used to build the reusable block. Reusable block cells only
reference their sub-cells and these must be extracted from the Central Library. If your Central
Library has multiple cells in different partitions using the same name, then the cell used in your

Reusable Blocks
reusable block cell, within your design, may not be the same as the cell used within the reusable
block design in your Central Library, if your extraction search order schemes are different.
Therefore, it is critical to verify that the partition search paths that were used to created the
Reusable Block Design are the same before Forward Annotation is run.
Forward Annotation
Forward Annotation extracts all verified reusable block cells referenced in the schematic into
your local design. If a reusable block cell becomes unverified before Forward Annotation is
run, then Forward Annotation provides a warning stating that reusable block changes within the
Central Library cannot be extracted until the reusable block within your Central Library is re-
verified. Once Forward Annotation has successfully completed, you can use the Place Part
command to place reusable blocks cells within your design.
If a reusable block was built with more layers, than are defined within your design, Forward
Annotation will error stating that reusable blocks referenced within your schematic can not be
placed within your design because they exceed the number of layers defined within your design.
At this point, you will have to increase the number of layers within your design, or re-evaluate
the reusable blocks number of defined layers.
While extracting the reusable block cell from the Central Library, Forward Annotation makes
sure that all padstacks, parts and cells defined within the reusable block cell exist and are
extractable into your local design. If one of the library objects referenced by your reusable
block cannot be found, Forward Annotation will not allow the reusable block to be placed
within your design.
All vias placed within your reusable block cell must have their spans defined in your local
design. If a via span is used, but not defined within your local design, Forward Annotation will
fail with an error. At this point, Setup Parameters can be run on your local design and all
missing spans added, then Forward Annotation must be re-run so it can successfully complete.
Placing Reusable Blocks

To place the reusable blocks, defined within your schematic on the board, select the Place Part
command and then the reusable block criterion option. This should list all reusable blocks that
are placed and packaged within the schematic. The reusable blocks listed within Place Part can
be placed like any other parts referenced by your schematic. Options (rotate and push) can be
used while the reusable block is in dynamics, or after is has been placed.
Reusable blocks, defined with less layers than the local design, will have their layer mapped
from the top/bottom in. Therefore, if your reusable block is built using four layers and placed in
a six layer design the following layer mapping automatically occurs:
Reusable Block(4)-> Design(6)

1->1
2->2

Reusable Blocks
3->5
4->6
Reusable Block Clearances

If your reusable block has different Net Classes & Clearances than the design in which it is
placed, you will need to adjust your design by adding rule areas for each of your reusable
blocks, containing the rules used within the reusable block design. If these rules are not added
to your local design, then placement manipulation may be limited and both Online and Batch
DRC will flag violations within your reusable blocks cell, based on the clearances defined in
your Minimum Net Class rules scheme. Objects within the reusable block cell are verified to
the other objects placed within the design using the (Master) Net Class clearances scheme.
Rule areas placed within your reusable block cells have the associated scheme, defined as
(Master), regardless of the scheme name that was assigned in the reusable block design.
Therefore, any net class schemes defined in your reusable block will now need to be also
defined in your local design, then any rule areas, defined within your reusable block cells, will
have to be selected and re-associated to a scheme name, defined in your local design.
Reusable Block Net Properties

If you defined Net Properties within your reusable block design, these properties will not exist
in your local design. You will have to re-define these properties for each net within your
reusable block cells to be the same as defined in your reusable block design.
Reusable Block Manipulation

Once placed within your design, reusable block cells can be moved, pushed, fixed, locked and
rotated like any other cell. However, you will not be able to edit this cell within the local
design’s cell library with the Cell Editor or manipulate individual parts, traces, vias or draw
objects within the reusable block cell. Since the logic information for a reusable block is locked,
you will not be able to swap part, gate or pin for parts within the reusable block.
All of the objects within a reusable block cell are fixed and cannot be changed except for the
following:
• Reference designator and part number locations can be changed.

• Rule area scheme name can be changed, however, location cannot be changed.
Flatten Reusable Block

At some point, you may need to make changes to the physical objects within a reusable block,
the reusable block can be selected and the Flatten Reusable Block option can be chosen. This
command ungroups the reusable block elements, allowing manipulation as with any other

Reusable Blocks
elements within the design. Once a reusable block is flattened, you will not be able to turn it
back into a reusable block to be manipulated as a single object.
Making an ECO to an Reusable Block

Once a reusable block has been saved and used by others within their designs, making changes
to the reusable block will cause an Engineering Change Order (ECO) to occur. There are two
different scenarios of making an ECO to a reusable block, the first is a pure physical change to
the layout of the reusable block, and the other is a schematic logic change to the reusable block.
Physical changes to a reusable block are handled on the fly just like any other cell within the
Central Library. You can edit the reusable block within the Central Library by modifying
placement, routing or any other physical change to the reusable block. After the changes have
been made, the timestamp on the reusable block is updated, then the designs that have used this
reusable block are automatically updated the next time Forward Annotate is run with one of the
options to extract newer Central Library data.
Logic changes to a reusable block, once saved, are more difficult. These changes have to be
completed in a new version of the reusable block currently not used within existing designs.
Therefore, the existing reusable block that requires a logic change should be copied to a new
reusable block name, that is similar to the existing block name, and is just changed to denote a
newer version. Then, within this new reusable block all schematic and layout changes can be
made following the same process as any other reusable block. Once the new version of the
reusable block is complete, each user that referenced the original reusable block will have to be
notified to delete their existing block and place the new version of this block within their
schematics. Once the schematics have been updated to reference the new version of the
reusable block, Forward Annotation can be run in the Expedition PCB design to pull in the new
version of the reusable block cell so it can be placed within the design.
Definitions
Reusable Block - This defines all of the Reusable Block data stored in the Central Library
represented by the Expedition PCB Design, Design Capture Schematic, and saved Reusable
Block Cell. The Reusable Block is referenced by a unique user defined name.
Reusable Block Design - An Expedition PCB layout and schematic database that represents a
repeatable circuit. This defines the data that is used to create the Reusable Block Cell which is
the object placed within other Expedition PCB designs.
Reusable Block Cell - This defines the cell created from a verified Reusable Block Design
while in Expedition PCB. This cell is used in other Expedition PCB designs that reference the
Reusable Block from its attached Central Library.
Reusable Block Schematic - This defines the schematic referenced within the Reusable Block
Design that contains the logic required by the Reusable Block.

Chapter 9
Embedded Components
DXDesigner and Design Capture only require a minimum number of parameters. This
functionality requires a minimum of four parameters defined at the schematic level, Reference
Designator, Part Number, Value and the Parametric property.
Caution
If you change the value of a DxDesigner symbol for any embedded part number and you
are using CES, you need to update the value information in CES because the CES value
overrides the schematic value property when Forward Annotating to Expedition PCB.
Figure 9-1. Embedded Component Flow
Setting up Embedded Passives Support in a DxDesigner

and Design Capture Flow
Prior to synthesizing Embedded Passives, you need to create EC-RES/EC-CAP part numbers in
your Central Library and pull these part numbers into your local design. If this is not done and
the passives are synthesized, a warning message is displayed stating that the system cannot find
these part number and changes done to passives will not be backannotated.
If you then run a forward annotation, all your changes will be lost.

Embedded Components
Schematic Parametric Symbol Definition

The part number is the basis for defining Embedded components through the Parts database.
The generic part numbers for these components are:
• Embedded Resistor - EC-RES (not case sensitive)

• Embedded Capacitor - EC-CAP (not case sensitive)
These Part numbers link the schematic symbol to the generic embedded component footprint
stored in the library. The generic footprint is then changed into the optimized footprints based
on the parameters specified within the Material Editor and Embedded Optimizer dialogs.
Standard part numbers and cell definitions can be defined for common parts. For instance, you
may have a standard configuration and parameters set for a specific resistor or capacitor. These
parameters and footprint can be created and stored in the library under a separate and unique
part number.
Schematic Parameter Definition

There are only three required parameters which need to be set on the schematic symbol:
• Reference Designator
• Part Number
• Value
Additional Schematic Symbol Properties

These additional parameter are available and definable within the Embedded Component tab of
the Symbol Property dialog or definable within the Optimizer dialog on the layout side. If
defined or changed in the layout, the parameters can be back annotated to the schematic. Not all
parameters will be required for capacitors. The additional parameters are:
• Tolerance
• Power rating
• Voltage
• Form
• Material
• Trim Range
• Trim Factor

Embedded Components
• Value Property - Defining a value on the schematic symbol allows you to specify
numerous parametric components and allow their creation based on the additional
properties and materials defined for the design. This methodology prevents the time
consuming task of creating a Part Database and/or library cell for each instance.
• Parametric Property - The parametric property identifies the symbol as a parametric
entity and passes the symbol information through the PDB/iCDB to the Optimizer
dialogs, bypassing the Part Placement dialog. Where a reference designator needs to be
visible on a symbol, the parametric parameter does not. This property defines the part as
parametric and is written in a comma separated format (Parametric='material', 'form',
'tolerance', etc).
Layout Template Cell Definition

Embedded component cells are created the same as any other cell is created within the Cell
Editor. One cell should be created for each of the different embedded component part numbers,
EC-RES and EC-CAP. The cell acts as a place holder for the parametric cell. Once defined and
compiled within the iCDB all parametric component information is read into the Optimizer
dialogs. Within the Cell Library there is only one generic cell representation for each parametric
type component; Resistor, Capacitor, or Inductor. This means that at optimization within layout
the generic cell is changed based on the parameters specified for each type and reference.
The Optimizer offers options for embedded component synthesis based on form, size, material,
or other specified options. Once the embedded component cell information is available, you can
choose which cell option is the best choice for the design. Parameters are read by the layout
tool and the correct cell geometry is created based on these parameters.
Template Cell Requirements

These parameters are required for the creation of embedded component generic cells. All other
placement defining properties can be entered at the layout stage.
• Package group - Embedded Resistor or Embedded Capacitor

• Padstacks - Any surface mount pad (must be an SMD pad)
• Reference designator
• Part number
Parametric Cell Creation

Embedded component parametric cell creation is handled as any other cell within the Cell
Editor
• Reference Designator

Embedded Components
• Part Number
• Value
• Pin placement - Any SMD pad contained within the padstack list can be used within the
cell.
Parametric Pad Definition

Parametric pads are not defined in the Padstack Processor. When the Optimizer has successfully
completed, the surface mounted pad in the template cell is converted to a 'parametric pad' based
on the parameters specified in the Material Editor. The pad definitions are stored within the
Pads database, but will not show up in the pads list for Pads Processor. The pads display in the
Editor Control > Pad Entry tab. The display is controlled based on the pad layer in Display
Control.
Parametric Pad Name

The internal pad name for these dynamic pads is created based on their size. For instance, if
Properties is selected for a 'parametric' pad, the padstack information displayed in the dialog
will be ParametricPad46X80Off0,0.
• ParametricPad - identifies the pad as being parametric

• 46X80 - defined the size of the pad (round will be handled in the future)
• Off0,0 - defines the pin offset within the pad
Note
These pad names are not displayed in the Padstack list of the Padstack Editor.
Parametric material definition

The parametric material definition is determined based on parameters defined within the
Materials Library and the Optimizer dialogs. Display is controlled by the Display Control
dialog.
Additional parametric parameters

The additional parameters listed below can be defined within the layout tool. These parameters
are definable within the front end interfaces and pushed to the layout via Forward Annotation.

Embedded Components
Embedded Passives Technologies
Each of these parameters can be defined within the schematic interface or within the Optimizer
dialog and are stored within the database under the parametric property.
Resistor Material
Form (geometry)
Value
Tolerance
Power rating
Voltage
Trim Range
Trim Factor
Capacitor Material
Form (geometry)
Value
Tolerance
Voltage

Resistor and Capacitor values supports two formats; Spice and IEC format. Spice is case
insensitive and can therefore not differ between m as in milli and M as in Mega. Instead M
means milli and mega is abbreviated MEG.
• Spice
• 0.5 1K 1.3MEG. I.e. 4.7K is 4700Ohms
• IEC60062
• 12K7 2M1. I.e. 4K7 is 4700Ohms
Embedded Resistors
The following resistor forms are supported for parametric resistors:
Rectangle A simple shape. Automatically sized to

achieve the Value resistance of the resistor.
Tophat Similar to a rectangle but with extended trim

range. Automatically sized to achieve the
Value resistance and TrimRange or
RectangleToTophat for extended trimming
possibilities.

Embedded Components
Folded Similar to a rectangle, but with the contact on

the long side, folded to make it more compact.
Automatically sized to achieve the Value
resistance of the resistor.
Serpentine Similar to a rectangle but folded to reduce the

length. Automatically sized to achieve the
Value resistance of the resistor.
Embedded Capacitors
The following forms are supported for parametric capacitors. The interdigitated capacitor is
placed on a single electrical layer and is fabricated as an integral part of the conductive pattern.
The connection point is in the center of the effective capacitor pad (red areas in figure below).
Mezzanine Capacitors
These are placed on a single layer with the dielectric layer and electrical material on top. The
top plate is accessed with a laser drilled via hole. This via is treated as a pin in the data model
and can be moved around as with any other component pin.

Embedded Components
Integration in FabLink XE and Expedition PCB
In the following figure, A is the bottom to the dielectric delta and B is the top plate to the bottom
plate delta. The top plate is always smaller than the bottom plate.
Screen Printed
This capacitor is placed on a single layer and the dielectric and top plates are screen printed.
Bottom plates are a part of the conductive layer. The connection point is in the center of the
bottom plates.

Note
Embedded components cannot be created, placed, moved, edited or deleted without the
Advanced Technology Pro (EP) License.
This section defines the commands within either Expedition PCB or FabLink XE Pro (on a
design or a panel) that have modification in regards to embedded components.

Embedded Components
File Command Modifications
Save (Exp)
When the Save command is invoked, if no Advanced Technology Pro License was acquired at
the start of or during the design session, no embedded component changes would have been
possible. Whenever the license is acquired during a design session, any embedded component
changes after the license acquisition can be saved. Back Annotation is called so that parametric
information is stored in the iCDB and no loss of parametric data occurs.
Save (FLXE Pro)

Inside FabLink XE or FabLink XE Pro, when the Save… command is invoked, no changes are
allowed to be made to a design that is placed within a Panel. Panels that have had panel cells
created with embedded component using material layers are saved.
Save Copy (Exp)

When the Save Copy command is invoked, if any changes (embedded component related or
not) were made to a design since the last Save, a dialog box appears asking you to save/not save
the current design before attempting to save the design copy.
• If you select Yes, any/all changes to embedded components are saved to the design first
before the copying of the design is done.
• If you select No, all embedded component changes are discarded, and the copy of the
design is based on the last Save.
File Viewer (Exp and FLXE Pro)

An embedded component license is not required for any file made available within this
command. The files are modified to report any embedded component information.
Export
GDSII (Exp and FLXE Pro)
All embedded component objects are exported.
General Interfaces (Exp)

With the exception of Generic ATE, if a design contains any embedded components, an ATP
license is required before generating any output files.

Embedded Components
Generic AIS
Generic AIS groups embedded placed parts, embedded integral parts and standard parts within
this output format. For example, embedded placed parts are usually assembled at the same time
as they would be on an outer layer.
Edit Command Modifications

Circuit Move & Copy
Circuit Move & Copy supports the ability to select, move and copy circuits that contain
embedded components. During circuit move operations you can rotate the circuit, however, if
the selected rotation is not allowed the placement will fail and following error displays in the
status bar:
EP Rotation incorrect
Certain information, such as materials, process library and parametric data is not copied
between designs. The synchronization of materials and process library data is your the
responsibility. You must ensure that the correct materials and library data exists in the local
design if copying of embedded passives is to be performed.
Embedded passive devices are based on a generic cell template that has little in common with
the size and shape of the resistor or capacitor that is eventually created. They are created and
maintained in an unstructured manner and may change if rotated or moved to a different layer.
Embedded passive devices always use a common part number (EC-RES for resistors and EC-
CAP for capacitors), so the Instantiation Wizard uses a different matching algorithm than that
which is used for regular parts.
Instantiating Embedded Passive Devices

During the instantiation process, if an embedded passive device is found (part number will be
EC-RES for a resistor or EC-CAP for a capacitor) the following component properties are
compared and the material name and process name that was copied with the part from the
clipboard are compared:
• Value property
• Tolerance property
• PowerRating property
If a local part matches the above criteria it is selected as a candidate part for instantiation. If the
above criteria is not met, the source part does not have a candidate for placement and is assigned
as unmapped in the Ref Des field.

Embedded Components
When all necessary parts are mapped and the OK button is pressed (in the Instantiation Wizard),
all the embedded components that have been mapped are synthesized to generate the correct
physical shape and size. The parts placed in the local design exactly match the original
geometries from the source design.
Review > Minimum Distance… (Exp and FLXE Pro)

The following is a listing of all embedded component objects that can be measured to either
another embedded component object, or to a panel/design object:
• Embedded component Mask

• Embedded component Resistor body
• Embedded component Capacitor plate
Properties (Place Mode - Exp)

The only fields with changes are within the "Other:" section:
• The identifier Board Side: is replaced with the identifier Layer:, which represents the
layer the embedded component is placed on.
• The identifier Mount Type: is replaced with the identifier EC Type:, which displays EC-
CAP or EC-RES.
• The identifier Type: displays either "Parametric" or "Package Cell."
Setup Command Modifications

Library Manager > Reusable Blocks
EC Parametric devices are allowed within Reusable Blocks. If the Reusable Block is
"smashed", any parametric device will remain a parametric device.
Non-parametric devices are also allowed within Reusable Blocks. If the Reusable Block is
"smashed", any non-parametric device will remain a non-parametric device.
Library Services
Library Services now has Materials and Processes tabs to enable copying processes and
materials between central libraries and designs. When Library Services is invoked from the
Library Manager, the following applies:
• Materials can be copied from Central Library to Central Library

• Materials can be imported/exported to/from Central Library via ASCII

Embedded Components
• Processes can be copied from Central Library to Central Library

• Processes can be Imported/exported to/from Central Library via ASCII
When Library Services is invoked from within Expedition PCB, the following applies:
• Material tab is not available (grayed out)

• Processes can be copied from Central Library to design. Materials defined in the process
will automatically be copied with the process.
• Processes can be exported from design to ASCII
Cell Editor (Exp) (FLXE Pro)

Opening a parametric embedded passive in Cell Editor changes the part/cell or panel so that the
component is no longer parametric. The optimizer ignores these components and they are
treated as any other standard component.
Setup Parameters (FLXE Pro)

The Setup Parameters > Layer Stackup tab recognizes any design layer with any/all embedded
component materials placed within a panel.
Net Class and Clearances > Clearances (EXP)

On the Clearances tab you can set embedded passives clearance rules. For the additive resistor,
clearance rule Resistor-to-<any metal> is used. The overglaze is optional in this manufacturing
process and is not checked by DRC. The subtractive resistor uses the mask-to-trace rule. The
subtractive resistor have a more restrictive way of handling the entry rules as it should only
allow entry/exit on the outer side of the pad.
Since the resistor body is a part of the manufacturing data of the resistor it can never overshoot
the pads like an additive resistor.
Material/Process Editor
In order to design with embedded passives a number of material properties must be defined. An
embedded passive is built into the product and is a device that does not add energy to the signal
it passes, for example: resistors, capacitors, insulators.
The materials are stored in a material library and all editing of material and process properties is
done in the Material/Process Editor. To limit the number of materials and processes within the
Embedded Planner and Embedded Optimizer dialogs in the Layout Editor, Library Services is
used to create and modify the local libraries as well as the importation of material and process
information from external sources.

Embedded Components
Since embedded components are part of the fabrication processes and not an assembly process,
the Bill of Materials (BOM) does not reflect the components as physical components.
Embedded Resistors
An embedded resistor resides on a single layer and can be on any physical layer on the board,
even plane layers. A resistor has two copper pads and resistance material between the two pads.
The shape of the resistance material can be a simple rectangle, a tophat shape, a folded rectangle
shape or a meander resistor shape; serpentine, tophat or folded. In all cases, the resistance
material overlaps the copper pads. A layer specific trace/via/drill keepout and placement
outline is required around the area of resistance material, to prevent signal shorts/openings with
the resistor body.
Embedded Capacitors
Typically, capacitors represent the largest percentage of component numbers on a printed
circuit board. Today, there are two techniques for fabricating embedded capacitors:
• Capacitors through dielectrics (Dielectric Layer Capacitor)

• Thick-film process (Additive Capacitor)
There may be one to many capacitor dielectric layers on the board and a dielectric layer could
support one to many capacitors. Since the signal actually flows through the dielectric, the pads
of a capacitor (for trace connections) can be located on opposite sides of the dielectric layer (s).
Discrete capacitors have parasitic inductance limiting frequency behavior, an advantage to
embedded capacitors because they have almost no parasitic inductance.
Embedded capacitors can also be added as a “thick-film” screening process directly on to a

layer. This technique is used in today’s Multi-Chip Modules (MCM) and Hybrids. The
capacitor material overlaps the copper pads and therefore, the pads are on the same layer.
Like embedded resistors, a layer specific trace/via/drill, and placement outlines from the
capacitor material (dielectric or screened) needs to be established and respected throughout the
design process.
Embedded Passives
The Planner dialog is used to display feasibility analysis on the use of embedded resistors and
capacitors in the design. The Planner dialog can be used before components are placed or
synthesized. The Planner operations do not modify the design.
The Optimizer dialog generates a list of component alternatives and allows you to select an
alternative for each component and synthesize the component using he parameters and material.
Embedded passives are fabricated within substrates and provide potential advantages for many
applications over passive components:

Embedded Components
• Increased circuit density through saving real estate on the substrate.

• Decreased product weight.
• Improved electrical properties.
• Cost reduction through increased manufacturing automation.
• Improved reliability through elimination of solder joints.
Supported Embedded Technologies

There are two types of supported embedded technologies: Parametric Components and Non-
Parametric Components. The resistor and capacitor values supports two formats, Spice and IEC
format standards:
Spice 0.5 1K 1.3 MEG, for example: 4.7K is 4700 Ohms

Spice is case insensitive and cannot differentiate between m
as in milli and M as in Mega. Instead M means milli and
meg is abbreviated MEG.
IEC 12K7 2M1, for example: 4K7 is 4700 Ohms
Parametric Components - Resistor

The following resistor forms are supported.
Rectangle A simple shape. It is automatically sized to achieve

the Value resistance of the resistor.
Tophat Similar to a rectangle but with extended trim range.
It is automatically sized to achieve the Value
resistance and TrimRange or RectangleToTophat
for extended trimming possibilities.
Serpentine Similar to a rectangle but folded to reduce the
length. It is automatically sized to achieve the Value
resistance of the resistor.
Folded Similar to a rectangle but with the contact on the
long side, folded to make it more compact. It is
automatically sized to achieve the Value resistance
of the resistor.

Embedded Components
Parametric Components - Capacitor

The following capacitor forms are supported.
Interdigitated This capacitor is placed on a single electrical layer.

This type of capacitor is fabricated as an integral
part of the conductive pattern.
The connection point is in the center of the
effective capacitor pad.
Mezzanine This capacitor is placed on a single layer, but with
the dielectric layer and electrical material on top.
The top plate is accessed with a laser drilled via
hole. The via is treated as a pin in the data model
and can be moved around as with any component
pin.
Screen Printed This capacitor is placed on a single layer; dielectric
and top plates are screen printed. The bottom plates
are a part of the conductive layer. The connection
point is in the center of the bottom plates.
Optimizer
The Optimizer is the process that generates a list of component alternatives and then through
user input and/or optimization algorithms selects one of the alternatives for each component and
synthesizes this component using the parameters of the component and the material.
Synthesis is done on unplaced and placed components, however, cells are only created for
placed components.
If the Optimizer was invoked from the Planner dialog, selected materials are inherited from
those defined within Planner.
You must assign materials to layers on the Layers tab; insulator and conductive materials can be
assigned to dielectric layers. If multiple layers are using the same material, embedded passives
default to the first valid layer. The Optimizer uses the synthesis functionality to calculate and
create the component. Embedded passives already synthesized and placed continue to be on the
same layer, unless forced by a change of material. A material to layer assignment is not allowed
to be removed if there are placed embedded passives on the layer that is using the material.
A Mirror flag can be set on the layers where embedded passives should be mirrored. This is
controlled from the first row in the spreadsheet named mirror.

Embedded Components
Note
The mirror flag is not allowed to be changed if there are embedded passives currently
placed on the layer.
Setup Parameters in Expedition PCB

Relevant changes to Setup Parameters in Expedition PCB prompt you with the need to re-
synthesize capacitors and/or resistors using the Optimizer. The relevant changes are:
• Add/Delete of Signal Layer (Resistors & Capacitors)

Consult the online help for the Material Editor for further information.

An additional icon displays on the Clearances tab of Net Classes and Clearances if you have the
correct license feature. This allows you to set resistor and mask clearances. The Auto Router
supports spacing rules between features on different layers (including features on dielectric
layers) and between different materials on the same layer.
Additive Resistors
For the additive resistor, clearance rule Resistor-to-<any metal> is used. The overglaze is
optional in this manufacturing process and is not checked by DRC. The following table shows
examples on how a trace can connect to a pad even if the clearance rule normally would prevent
it. It is only the Resistor-to-trace rule that is affected, Resistor-to-Via, Mask, Pad or other metal
elements are always valid.
The exceptions in the table are valid for all resistor shapes. A trace may violate the clearance
area if the trace is of the same net as the embedded passive pin.
Map
Green = Resistor-to-trace clearance
Blue/White = Legal entry
Red = Trace and Pad
Grey = Resistor body

Embedded Components
Additive resistors (when routing from or to resistor

pads)
Allowed Routing Not Allowed Routing

Embedded Components
Additive resistors (when routing from or to resistor

pads)
The physical order of the elements is not showing the ‘real’ order. Traces are placed on the top
and clearance area on the bottom to make the picture more viewable. Legal pad entry rules are
controlled with keep-outs within the embedded passives. For additive resistors the keep-out is
the resistor body expanded by resistor-to-trace clearance. To allow connections to the pads the
keep-out is tagged with the associated pin.
Subtractive Resistors
The subtractive resistor uses the mask-to-trace rule. The subtractive resistor has a more
restrictive way of handling the entry rules as it should only allow entry/exit on the outer side of
the pad. Since the resistor body is a part of the manufacturing data of the resistor it can never
overshoot the pads like an additive resistor.
Map
Green = Resistor-to-trace clearance
Blue/White = Legal entry
Red = Trace and Pad
Grey = Resistor body
Pale Blue = Production Mask

Embedded Components
Subtractive resistors (when routing from or to resistor pads)

The physical order of the elements is not showing the ‘real’ order. Traces are placed on the top
and clearance area in the bottom to make the picture more viewable. Legal pad entry rules for
subtractive are controlled with keep-outs within the embedded passives. For subtractive
resistors the keep-out is the production mask expanded by the mask-to-trace. To prevent illegal
pad entry the keep-out also extends with the pad length as illustrated in the following figure.
The resulting keep-out area resembles the following figure and keeps out all nets.

Embedded Components
Mezzanine capacitors
Embedded passive mezzanines are fabricated by screening a dielectric material onto the signal
layer. On top of this dielectric the second plate of the capacitor is plated. A mezzanine capacitor
could resemble:
Cross section View
Top View
RCC - Resin Coated Copper
FR-4 - Flame Retarded epoxy coated fiberglass (pre-preg / core)
S 1..n - Signal layers (S2 treated as graphical)
D 1..n - Dielectric layers
V1/2 - Blind Via between Signal 1 and Signal 2
The size of the dielectric (D2) is typically larger than the bottom plate (S3) but can be defined as
smaller. Foreign vias (V1/3) are allowed to cut through the dielectric but must stay clear from
the bottom plate. This is controlled with bottom plate to via clearance. Top plate (S2) can be of
same size or smaller than the bottom plate as long as it's not larger than the dielectric.

Embedded Components
Connection to the top plate would typically be done using a laser-drilled blind via. This via is
defined as a pin in the data model but must be supported by production output as a laser-drilled
via. No normal routing is allowed on the S2 layer as it will be treated as graphical.
The pin/connect point on the capacitor would normally be located in the center of the capacitor
but can be moved as with a normal component pin.
Note
No check is done to see if the pin is inside the top plate shape. If the pin is moved outside
the top plate the design is not viable.
Bottom plate (S3) follows normal conductive clearance rules. The connection pad (S1) uses
normal conductive clearance rules.
Screen printed capacitors

Screen plated capacitors are fabricated by screening a dielectric material onto the signal layer.
On top of this dielectric a second plate of the capacitor is screen printed.
Like with the mezzanine capacitor, clearance is handled from the bottom plates. The plates
(pads) are a part of the conductive layer and follow normal clearance rules. The connection
points are in the center of the plates. Space between the plates is restricted area for all kinds of
objects on the signal layer.

Embedded Components
Interdigitated capacitors
Embedded passive interdigitated capacitors are fabricated as an integral part of the conductive
pattern. All normal clearances are to be applied. The connection point would normally be in the
center of the effective capacitor pad.
Note: Star denotes connection point
In order to have a "correct" capacitance calculation an extra clearance area is added.
No conductive elements (trace/via/pad/shape) are allowed within the effective clearance area
when routing from the capacitor pad. When routing nets not associated with the capacitor, the
clearance would look like this:

Embedded Components
Note
There will be a separate keep out in the middle to keep escape traces away from the
fingers. The clearance values for the fingers change depending on the type of object it is
in proximity with and the net class it belongs to.
Place Command Enhancements

The following table summarizes as to whether selected embedded components are required to
be regenerated at any time when using any of the following Placement commands:
Place pulldown command Regeneration required?

Automatic > Swap/Rotate by Cell Name Yes
Automatic > Swap/Rotate by Part Number Yes
Place Parts and Cells Yes
Polar Place Yes
Unplace Parts Yes. The unplaced parts are regenerated the
next time there is an attempt to place them.
Swap Parts Yes
Move No
Move Circuit No
Copy Circuit Yes. Regenerated after the parts are placed at
the destination location with an LMB click
before the command is completed.
Push Yes. Regenerated after pushed.
Rotate 90 Yes. Regenerated after rotation.
Rotate 180 Yes.Regenerated after rotation.
Group No
Ungroup No
Align Left No
Align Right No
Align Top No
Align Bottom No
Fix No
Unfix No
Lock No

Embedded Components
Unlock No
Snap to Grid No
Additional Rotate Keyin Commands (All Require Regeneration)

The following keyin commands can be used with ECs:
pr -polar <coord> radius Polar placement. The default start pr -p xy=0,0 1000 18.0
delta_angle {- angle is 0.0 degrees with the parts -a=90.0 R101:120
start_angle=angle} {-bottom}{- placed on the top side of the
additional_part_rotation=angle} board. The embedded component
ref-des-lit parts' rotation angle is set equal to
the placement angle, an additional
rotation may be applied to each
part as it's placed.
pr <coord> {-angle=angle} Place specified part at given pr 200,500 -a=45 R101
refdes coordinate and optionally at
specified angle.
r delta angle Rotate objects in dynamics r 30
through the specified angle.
rr deltaAngle refdes-list Rotate all specified parts thru the rr 90 R101:120
specified delta angle.
rs delta angle Rotate selected objects through rs 90
the specified angle.
Swap Commands Involving Multiple Materials and/or Layers

All Place > Swap commands first verifies that the materials of the target layers are supported for
the parts before the swap. If the swap involves either different placement layers or different
orientations between these two parts (the first part is placed according the orientation of the
second part, and the second part is placed according to the orientation of the first part), the
system regenerates any parametric component.
Toggle Parametric
Only parametric embedded passives from the layout are listed within this dialog. Clicking
Apply toggles the selected embedded passives to use the cell it had before it became parametric.
If an embedded passive has been pre-defined from the schematic it cannot toggle to a placed
cell.
Push (Exp)
The following are the actions performed by Push with embedded components:

Embedded Components
Caution
If the Editor Control > DRC Off option is checked, pushing is allowed.
• Pre-determine only those embedded components that need to be pushed.

If the design's stack-up hasn't been pre-defined prior to selecting any type of
embedded components, no pushing is possible.
• Individual embedded components may be selected through the Place > Place Parts and
Cells dialog box in the Reference Designator (Ref Des) field.
If there are no other matching sequential layers available that match the present embedded
component layers, no pushing is possible.
Embedded components do not necessarily mirror when passing over the board's Z-center. As a
bottom layer part of a board sandwich very well may face "upwards" due to the core/prepreg
stackup chosen by the manufacturer, this is controlled by layer. Embedded capacitors have a
mirror option on the Layer tab of the Embedded Optimizer. For more information, see the
Embedded Optimizer online help.
Example
A 6 layer board built as 3 cores and 2 prepreg sections (each prepreg is typically composed of
several prepreg layers). In this example, the system can't just mirror on passing the center of the
stack up.
Note
Termination resistors are often preferred placed on the ground plane layer.
Figure 9-2. Push Example

Embedded Components
Route Command Enhancements

Planes > Copper Balancing (FLXE Pro)
Copper balancing recognizes embedded component objects that exist within the Panel Outline
but not within any Board Outline.
ECO Command Enhancements (Exp)

Replace Cell (Exp)
This command never recognizes any parametric embedded component, even if they are the only
things selected.
Update Materials and Processes

This command updates all the materials and processes in your design with any changes made
within the Setup > Material/Process Editor. This command can be used to insure that the
materials and processes in the design match the data in the Central Library.
Analysis Command Enhancements

DRC Window (FLXE Pro)
The DRC Window respects embedded component objects that exist within the panel, and not
analyze anything within a placed design(s).
Review Hazards
A new Batch hazard, EP Violations is available. This hazard notifies you of problems resulting
from material or process changes that might invalidate the embedded component. The hazards
can be fixed by re-synthesizing the embedded components.
Gerber… (Exp and FLXE Pro)

All embedded component objects (except a spiral inductor) are required to have sharp corners.
There is no pad overlap on embedded thin film resistors (using OhmegaPly).
Note
X-Gerber output has to be true polygon descriptions for all EC polygons to give true
sharp corners.
The following two figures show unacceptable and acceptable output data:

Embedded Components
Figure 9-3. Unacceptable X-Gerber Output
Figure 9-4. Acceptable X-Gerber Output
Mask Generator (FLXE Pro)

The individual mask layers that make up each type of embedded components are recognized by
Mask Generator. The related element list is available in the Mask Generator dialog only when
the design contains embedded component elements.
Layer definitions are based on the design layer structure as it is today; top, bottom, layer 2 or 3,
internal. Embedded passive component elements are extracted by type or material. The resistor
body is directly tied to a material within the material list.
FabLink XE (Exp)
When you invoke the FabLink XE command from within Expedition, if you have the Advanced
Packaging License active on your design, the system automatically opens FabLink XE Pro. If it
does not have the Advanced Packaging License, it only opens FabLink XE.
If a design or panel with embedded components is invoked within FabLink XE:
• All Output commands work, except that you cannot select and/or output any embedded
component material layers.
If a design or panel with embedded components is invoked within FabLink XE Pro, all Output
pulldown commands are enabled.
Neutral File… (FLXE Pro)

Generating fabrication and assembly data (including EC output) in an ASCII format is possible
through the Neutral File command. You still need to manually validate (and when necessary,
manipulate) all embedded component design objects within the Neutral File itself.
Note
The neutral file properties are not supported during back annotation.

Embedded Components
ODBG Interface… (FLXE Pro)

Embedded component output is possible, however, there are limitations and the result is that
artwork in ODBG is generated that is "visually" correct, but the Valor tools:
• Cannot process the component placement data.

• The netlist check routines will flag short circuits for all resistors and inductors.

Embedded Components

Appendix A
Draw and Dimension
This Appendix describes in detail the functionality of the drawing module called Draw and
Dimensioning. The drawing module is for creating and editing lines, polylines, polygons,
circles, rectangles and text graphics, as needed in electronic applications. The draw
functionality is enabled when you enter Draw mode. The following are explanations of
keyboard operations, which apply to all addition and editing functions.
Tab key - Tab serves several functions: It cycles through draw objects within a selection
location (Default operation) and it also allows you to cycle through the available snap points on
an object.
Tip: In order to cycle through the snap points, deselect the selected object in Draw.
Shift Key – Restricts the movement of the objects, being modified or placed, to orthogonal
directions and can be used in conjunction with all events.
Ctrl Key – Provides some additional freedom in the movement of the object, based on angle
lock being turned off. It can be used in conjunction with all events, including the Shift key and
when used with the mouse it can be used to Copy objects.
To copy objects while in Draw mode the Ctrl key must be pressed and held, if it is not you
initiate a Move command:
1. Select Draw mode.

2. Select the object(s) to be copied and press and hold the Ctrl key.
To select multiple objects, either drag a box around objects with the left mouse button or
select in the objects in sequence while pressing and holding the Ctrl key.
3. Position the cursor over (any one of) the selected object(s); the cursor changes to a four
arrow cursor signifying a Move/Copy operation.
4. Press and hold the left mouse button and drag the copy(ies) of the selected objects to the
desired location. When you drag the objects, ghost images of the selected objects appear
attached to the cursor and the cursor changes to a four arrow icon with a + sign,
signifying a Copy operation as opposed to a Move operation.
5. Release the left mouse button once the objects are at the desired location.
The objects are placed and maintain the attributes and layer of the original objects. If
you want to make multiple copies of the same objects (which by default remain

Draw and Dimension
selected), press and hold the Ctrl key and left mouse button and drag the copies to the
desired position then release the left mouse button.
Using the Ctrl and Double-Click the Left Mouse button

Using this method allows you to make a copy of objects that are not usually allowed; for
example the route or board outline. The attributes and layer are not maintained and are defaulted
to a Type of Draw Object and a Layer of Assembly Top.
1. Enter Draw mode.

2. Select an object.
3. Position the cursor over the selected object; the cursor changes to a four arrow cursor
signifying a Move/Copy operation.
4. Press and hold the Ctrl Key and double-click the left mouse button. The object is copied
and displays over the original object.
5. Move the object to the appropriate place.
Alt Key - Is used in conjunction with all events, including Shift and Ctrl. The Alt Key is used
to enable and disable the Snap Grid, during the placement or modification, of a draw object.
Esc Key – Used during the operation of any function, it aborts the operation and returns you to
the previous condition before the function started.
Selected Objects – If an object is moved or stretched, it remains selected after the operation,
until another selection is made, or Esc is chosen.
Selection Locations – You may select an object anywhere on the element. Clicking in the
center of a closed object does not cause the object to become selected unless the object was
filled.
Snap Grid – If this is enabled, objects move on the Snap Grid. Snap Grid always applies, if
defined, unless the ALT key is selected.
Add - When adding an object, the anchor point and any other points that define vertices
are on the Snap Grid.
Move - While moving an object, the origin snaps to the grid, but the object shape does
not change.
Stretch - When stretching an object, the lines and vertices that are modified snap to the
grid. If a line is stretched (because it is attached to a segment that is being moved) only
the endpoint snaps to the grid.
Key in – If you key in a value for an object location or dimension and the value is not
compatible with the Snap Grid, the Snap Grid is ignored.

Draw and Dimension
Draw Toolbars
Angle Lock – This restricts the adding or stretching of the object to the angle specified. If Snap
Grid and Angle Lock are both set, the object snaps only to those points that are common to
both.
Handles – Handles are vertices and the center point of lines. They appear when one of these
objects is selected. If the zoom scale is such that the handles overlap, you can turn center
handles off using the Properties dialog.
Line Widths – The line width is the width of the line, in design units. Not all draw objects can
have line width. Polygons, that are considered solid objects, do not have line width.
Pen Widths - This is the width that will be used to draw text during Gerber generation.
Cancel – Aborts the current operation. Selecting the Esc Key or clicking the right mouse button
returns you to the default mode, Select.
Units – Units for the whole design are specified in the Setup Parameters dialog.
Undo – Deletes the previous step.
Redo - Reverses the effects of the last Undo.
Selection Appearance - When an object is selected, it appears with the handles as shown in the
details for each object and with dotted lines. These are colored based on the defined Display
Control selection color, for the layer the object is placed on.
Handles - Are used to manipulate draw objects and are described in the details for each object.
Cursors - Are used for each object and operation are described in the details for each object.
There are specific cursors for move, stretch horizontal, stretch vertical and stretch diagonal.
Multiple or user-definable cursor colors are not supported.
Origin Markers - For circles and arcs, the origin marker is a small plus sign (+). For lines,
rectangles and polygons, the origin is shown as a plus sign in the handle that represents the
origin of the object.
Draw Toolbars
The Draw toolbars are dockable and the toolbar icons reveal all the Draw commands. You can
use the keyins while in Draw mode.

Draw and Dimension
Draw Toolbars
Push Button – This button never remains depressed. Each click, causes the button to
momentarily become depressed, and applies the action. This applies a function to the selected
object, for example, Mirror or Rotate.
Toggle Button – Each time you click the button, the state changes from depressed and active to
un-depressed and inactive. This activates a command, for example, place line, place arc, etc.
Multi-State – If you click on the button once, it behaves like a toggle button for just one action.
If you double-click the button, it toggles and remains depressed and active until another action
or Esc is chosen.
For example, if you click on the button to add a rectangle, it becomes depressed and
allows you to add one rectangle before it resets to the un-depressed state. If you double-
click it, you can continue to add rectangles until you select another action or hit Esc.
Select Toggle Button
Default - This is the default Draw command – depressed by default. When depressed, you are
simply in selection mode. If you Esc from another Draw command, this function becomes
selected. The only time a draw object can be selected is while in this mode.
Selection Methodology – Selection of objects in Draw is somewhat different from selection of

traces and components in Expedition PCB. Differences are noted.
Note
If two or more objects are selected and the attributes are changed, this affects all
attributes not just the selected objects. For example: if you have two placement obstructs,
one on the top of the board and one on the bottom and you want to change the height, the
layer also changes; and if you want to change the layer, the height changes.
Polygon Select
Toggle Button Operation - This function allows you to select items using a closed polygon.
Clicking the desired vertices forms this polygon. You may close the polygon by double clicking
at the start point, or by choosing “Close Polygon” from the right mouse pop-up menu. All items
completely enclosed within this polygon become selected.

Draw and Dimension
Draw Toolbars
Snap Grid
Appearance – The Snap Grid appears as one-pixel-wide points, white in color. This gives you a
graphical way of seeing the draw grid.
Cursor - The cursor does not snap to the draw grid.
Objects – The behavior of objects relative to the Snap Grid is described in detail for each
object.
Pulldown - The right side of the snap button is a pulldown menu. This menu allows you to
change the draw grid, that is used when the snap grid is enabled.
Angle Lock
When the button is depressed, the Angle Lock is on. Objects that can have angles are restricted
to the Angle Lock setting.
When the button is not depressed, the Angle Lock is not active, and objects that can have angles
are free to move without any angle restriction (unless otherwise restricted by Shift that usually
restricts movement to 90-degree angles).
Pulldown - The right side of the icon is a pulldown menu. This menu allows you to change or
define the angle that will be used when angle lock is enabled.
Snap to Grid

Draw and Dimension
Draw Toolbars
Selected objects have their origins snapped to the defined draw grid. Individual vertices (other
than the origin) do not snap to grid by themselves.
Join
The purpose of this function is to join line segments together so they share a common end point.
If two selected objects share a common end point, they are joined into a polyline or polygon. If
the end points are not coincident, then both segments should be extended (red lines) to join at
their intersection.
If the extension does not allow the segments to intersect, then a new straight-line segment is
added that joins the two original objects together at the closest end points, resulting in:
Create Polyline / Polygon
This command can be used to create a polyline or polygon from existing lines, arcs and/or
polylines. This is useful, when a complex board outline cannot be manipulated as a shape
because arcs are not tangent to lines. This board outline can be copied to a user layer, dissolved,
modified, and then created back into a shape. This shape can then be changed to a board outline
type.
The Create Polyline / Polygon icon is only active if the selected lines, arcs and/or polylines have
coincident end points. If the resulting object becomes closed, then a polygon is created. If the
resulting object is open, then a polyline is created.
To use this command, select a set of lines, arcs and/or polylines, and then select this icon. All
the objects are joined into one polyline or polygon. To aid in creating, you can select two
objects and then select the Join icon so that the endpoints are coincidental before using the
Create Polyline / Polygon command.

Draw and Dimension
Draw Toolbars
Dissolve Polyline / Polygon
This command can be used to dissolve complex polyline and polygon objects into individual
elements, so they can be easily manipulated. This is useful when a complex board outline
cannot be manipulated as a shape because arcs are not tangent to lines. This board outline can be
copied to a user layer, dissolved, modified, and then created back into a shape. This shape can
then be changed to a board outline type. To use this command, select a polyline or polygon and
then select this icon. The polygon will be dissolved into individual objects.
The following objects cannot be dissolved because the type requires the draw object to be a
closed shape. These objects should be copied to a user layer, dissolved and changed, created
back into a shape, then changed back to the original draw type. This removes the old object and
you now have your edited object.
• Board Outline
• DRC Window
• Insertion Outline
• Placement Obstruct
• Placement Outline
• Plane NoConnect
• Plane Obstruct
• Plane Shape
• Resistor Shape
• Room
• Route Border
• Solder Mask Shape
• Test Point Obstruct
Delete End Point Handle
The selection of a polyline or polygon causes this button to be selectable. Selected end point
handles can be deleted; however, you cannot delete a center point handle.
A single line segment is added that replaces the two segments (lines and / or arcs) that were
joined at the end point.

Draw and Dimension
Draw Toolbars
Trim
Selected segments are deleted. If you trim a segment and one of the new end points becomes
coincident with another end point, the two segments are joined as part of a polyline or polygon.
Flip Horizontal
A selected object is flipped horizontally about its centroid.
Multiple selected objects are flipped horizontally about the centroid of the extents of the
selected objects. If Snap Grid is turned on, the centroid is defined as the nearest grid to the
actual centroid.
Flip Vertical
A selected object is flipped vertically about its centroid. Multiple selected objects are flipped
vertically about the centroid of the extents of the objects. If Snap Grid is turned on, the centroid
is defined as the nearest grid to the actual centroid.

Draw and Dimension
Draw Toolbars
Rotate
A selected object is rotated about its centroid. Multiple selected objects are rotated about the
centroid of the extents of the objects. The rotation is restricted to the angle defined in Angle
Lock. If Snap Grid is turned on, the centroid is defined as the nearest grid to the actual centroid.
Bring Forward
Selected plane shapes are placed in front of the other plane shapes, giving them a higher
priority. This allows you to adjust which plane shapes are processed first and cut into other
shapes that overlap.
Send Backward
Selected plane shapes are placed in back of other plane shapes, giving them a lower priority.
This allows you to adjust which plane shapes are processed first and cut into other shapes that
overlap.
Move
To move an object you may either select the object, choose move, then place the object in a new
location or choose move, select the object and move it to a new location.
When an object is selected, you may initiate a Move by selecting any location where there is no
modification handle. Modification handles are used to modify the draw objects and are located
at each vertex and the center point of lines. The handles for an object appear as described in the
details for each object.
When you are in Select Mode, you may initiate a Move by a drag event on the object.
The object does need to be selected before the drag move can occur. The object remains
selected after a drag event.
The move cursor is present when the cursor is over a selected object, but not over the
handle. The object origin snaps to the grid, and the coordinate readouts are for the origin
of the object, not the cursor.
To move a set of objects, select them and then initiate a drag move when the cursor
changes to the move cursor while over one of the selected objects. The origin for this set
of objects will be the lowest of the origins remaining in the set.

Draw and Dimension
Draw Toolbars
It is not necessary to hold down the shift key to move all of the selected objects. Initiate
the drag on one of the selected objects and all of them will move.
Scale
Using Scale, you can select shapes and scale them by a user-defined percentage. When you
select the first shape, the Scale icon becomes selectable. If you click the Scale icon, any selected
value is used to scale the shape. Continuous clicking of the Scale icon will scale the selected
shape.
If you click the down arrow on the scale icon a dialog displays allowing you to enter the
distance value or the scaling factor. The numeric entry must be greater than zero. To set the
value, either click in the design or press the Enter Key.
The new shape consists of the same segment types as the original one, unless the radius value
turns to small, then the round corner may be replaced by a simple corner.
Merge
Selected areas/polygons are merged. Merge can be applied to the areas and polygons with
closed contours. You should click the first target shape (1) - the base area, then click the Merge
icon and then click the second target shape (2) - the manipulating area/polygon. The two areas

Draw and Dimension
Draw Toolbars
become one as long as they intersect. The second target shape inherits the properties of the first
target shape.
Subtract
Selected areas/polygons are subtracted. Subtract can be applied to the areas and polygons with
closed contours. If the shape touches or overlaps it is subtracted; if it is contained within, it
becomes a cutout or hole.
Cutouts are allowed on the following Draw types:
• Actual Plane Shapes

• Conductive Shapes
• Draw Objects
o Assembly Layer (filled/unfilled)
o Silkscreen Outline (filled only)
o Soldermask (filled only)
o Solderpaste (filled only)
o User Layer (filled only)
• Placement Obstructs
• Placement Outlines
• Plane Shapes
While the outer (parent) shape must be one of the supported objects listed above, the inner
(cutout) shape can be any shape (filled or non-filled); it does not have to be one of the supported
shapes.
Once a cutout shape has been established, you can copy it to create additional cutouts within the
parent shape. Cutouts cannot overlap the parent shape or other cutouts, if this happens a
warning is displayed.

Draw and Dimension
Draw Toolbars
Board Outline Behavior with cutouts

A cutout is not moved when the board outline is moved. Cutouts for board outline behave as
contours in post processing.
To Subtract Shapes
1. Click the first area/polygon (1). This is the base area.
2. Select the Subtract icon.
3. Click the second area (2). This is the manipulating area/polygon. The second selected
area is removed from the first one, under condition that both areas intersect(3).
4. If the second area divides the first area in two halves, two independent areas are created,
and they no longer exist as a related area (3 below).
To create a cutout using Subtract

1. Place the parent or outline shape first.
2. Place the shape to cutout inside the parent shape (it must not touch the parent shape).
3. Select the parent shape.
4. Select the Subtract icon. You will be prompted to "Select shape to subtract".
5. Select the shape that was created in Step 2. This will create the cutout.
Multiple cutouts can be created by selecting the Subtract icon then selecting the shape to
cutout. Follow this sequence to create multiple cutouts.
A cutout has no properties; it is just a sub-element of the filled area.
An existing cutout of an object can be modified, moved and deleted like any other draw object.
The association between cutout and the object never gets lost in a design or cell.

Draw and Dimension
Draw Toolbars
The space inside a cutout is equal to the space outside of the object. Any other object inside the
cutout behaves as it would do outside the object area.
ASCII File Entry Example

.SILKSCREEN_OUTLINE
..SIDE TOP
…SHAPE_OPTIONS FILLED IS_MENTORGON
Rules surrounding Cutout shapes

Cutouts can consist of any closed drawing shape; circle, polygon, rectangle, closed polyline,
etc.
Cutouts must be fully contained within the parent shape (no overlap) Utilizing the subtract
command changes the element properties to a “cutout” shape.
If a cutout or parent shape is selected all associated shapes become selected.
If element(s) are selected and Delete is selected all associated shapes are removed.
Modifing an Element
Using standard draw operations you can modify an area by selecting a handle and stretching, or
moving a shape within the parent shape. No cutout shape is allowed to overlap
the parent shape. If you move a cutout overlapping the parent shape, once a placement point is
selected the cutout returns to the original location and the following error message displays:
Modified object is outside the parent shape.
Extend
Selected segments are lengthened. Extend can be applied to lines, arcs and line objects such as
polygons, squares and circles. In order for Extend to be activated, two different segments must
cross each other's path. If you select two segments and choose extend, the last segment is
lengthened.

Draw and Dimension
Draw Toolbars
Text
This command allows you to place text within your design. The properties of the text being
placed; layer, font, size, etc., are defined on the Draw Properties dialog.
If you click on the Draw text icon or select it from the pulldown in the Draw Properties dialog,
when text is entered into the "String" field it is attached to the cursor ready for placement. If the
Enter key is pressed, the Draw Properties dialog disappears. If you place the text, without
pressing Enter, the Draw Properties dialog loses its fields and you have to select Text from the
pulldown to enter more text.
If you double-click on the Draw icon, you may enter as many strings of text as necessary
without having to refresh the Draw Properties dialog. However, if you select the Enter key, the
Draw Properties dialog will still dismiss
Note
If the option, Control Panel - Display Properties - Plus! for Smooth Edges on screen fonts
is enabled on your computer, it can cause the text to dim and make it difficult to view the
text when placed using Draw and VeriBest Gerber fonts.
Dimension
Dimensioning functionality is designed to aid you in the areas of documentation and creation of
manufacturing outputs.
Only elements that are typically needed in CAM or manufacturing output are recognized for
dimensioning; board outline, mounting holes, component pins, test points, fiducials, contours
and cutouts. Traces and vias are not accessible. Dimensioning data can be placed on assembly,
silkscreen or user-defined layers. Data cannot be placed on copper layers.
It may be necessary in some cases for you to dimension a drawing or element using a
combination of stacked dimensions and non-stacked dimensions. In this case, you may place
stacked dimension data, then select a right mouse click (reset) to exit the stacked mode and then
start a new series of dimensions.
If the Dimension icon is selected, the dimension icons become available in the environment
window.
Figure A-1. Dimension Toolbar

Draw and Dimension
Draw Toolbars
Dimension options - This icon displays the Dimension Parameters dialog allowing you to
define the dimension parameters for your dimensions.
Place Dimension along a linear dimension - This icon allows you to place a single
dimension along a linear element. When this option is selected, you are prompted (in the status
bar) to "Select edge to be dimensioned"; click on a line and the dimension is placed.
Place dimension between two elements - This icon allows you to select two points and
place a dimension in a desired location. When this option is selected you are prompted (in the
status bar) to "Select first point": click a point and then you are prompted to "Select second
point", a rubber band line appears; click the second point and the dimension is attached to the
cursor, you are now prompted to "Move dimension to desired location" and the next mouse
click places the dimension.
Place stacked dimension - This icon allows you to place consecutive stacked dimensions.
When this option is selected you are prompted (in the status bar) to "Select first point"; click a
point and then you are prompted to "Select second point", a rubber band line appears, click the
second point and the dimension is attached to the cursor, you are now prompted to "Move
dimension to desired location" and the next mouse click places the dimension.
After you have placed the dimension you are prompted to "Select second point", a rubber band
line appears, click the next point and the dimension is placed automatically using the Stacked
Text Distance setting from the Dimension Parameters dialog. The status bar continues to
prompt you to "Select second point" until you perform a right-mouse button click to exit the
command.
Place an ordinate dimension - This icon allows you to place consecutive dimensions
consisting of single extension lines with associated dimension text specified from a common
origin. When this option is selected, you are prompted (in the status bar) to "Select first point",
the dimension is attached to the cursor and you are prompted to "Move text into position" and
the next mouse click places the dimension zero (0), which is the datum point. The status bar

Draw and Dimension
Draw Toolbars
continues to prompt you to "Select next element" until you perform a right-mouse button click
to exit the command. The datum for ordinate dimensioning is always the Board origin.
Angle from X-Axis of Linear Element - This icon allows you to place a dimension
defining the angle of a linear element in relation to the X-axis of the design. When this option is
selected, you are prompted (in the status bar) to "Select edge to dimension", click a line and you
are prompted to "Move dimension to desired location", the dimension is attached to the cursor
and the next mouse click places the dimension.
Angular Dimension Between Two Linear Elements - This icon allows you to place a
dimension between two lines defining the angle between them. When this option is selected you
are prompted (in the status bar) to "Select first edge", click a line and the selected line
highlights, you are now prompted to "Select second line for angular dimension", click the
second line and the dimension is attached to the cursor, you are now prompted to "Move
dimension to desired location" and the next mouse click places the dimension.
Place a Radius or Diameter Dimension - This icon allows you to place either a radius or
diameter dimension for any mounting holes (pcb) or shearing and tooling holes (pnl). When this
option is selected, you are prompted (in the status bar) to "Select element for diameter/radius
dimension", click an arc or circle, you are now prompted to "Move dimension to desired
location", the dimension is attached to the cursor and the next mouse click places the dimension.
For European Radial Dimensions, while placing a dimension on a circle, select the Tab key to
toggle the dimension between Standard, Inside Leader Note or Inside. While placing a
dimension on a circle, select F11 to toggle the prefix between diameter and radius.
Dimension Layer - This selects the layer in which the dimension data is
to be placed. Dimension data can be placed on assembly, silkscreen or user-defined layers.
Data cannot be placed on copper layers.
Properties
All property dialogs have a Draw Type combinational box and a properties list at the top of the
dialog.

Draw and Dimension
Draw Objects
The Draw Properties dialog is a modeless dialog. It can remain open while all other editing is
allowed. The contents of this dialog change depending on the object type selected. Any changes
within this dialog immediately affect the selected draw object.
Type - A listing of all the acceptable draw types. A draw type is a specific object, for example,
Board Outline, Route Border, Plane Shape or Rule Area.
Property List - Allows settings for the specific type to be loaded. An example would be the
netname for a Plane Shape or a layer for a Route Obstruct.
Multiple Selections - If you select a group of objects that are not the same type the Draw
Properties dialog appears with dissimilar fields. If the objects are the same, then the common
properties are loaded into the dialog
Confirming Property Fields - If a new value is typed into a field, it is confirmed by pressing
the Return key or by changing the focus. At that point, the entries are checked and the graphics
are updated.
Draw Objects
Draw objects are the basic graphical objects that can be placed. These are independent of the
type that can be assigned to them. Line, Arc, Polyline, Polygon, Rectangle, Circle and Text are
draw objects.

Draw and Dimension
Draw Objects
Arc
The origin of an arc is the center of the circle that the arc would form if it were 360 degrees.
Consider the blue section to be the arc and the dashed red portion, the extension of the arc.
If a new value is typed into a field on the Properties dialog, it is confirmed by pressing the Enter
key. At that point it is checked and the graphic is updated.
Line Width - This is the width of the line forming the arc. A width can be selected from the
drop down list box or it can be edited and a new width can be entered. Any new widths entered
into this field are accessible next time you use this dialog.
Radius - This is the value of the distance from the arc center to the arc.
Center X, Center Y - These entries define the location of the center (origin) of the arc.
Vertices - This is a list of vertices that define the two end points of the arc. Any changes made
in the graphics causes the coordinates in these fields to be automatically updated.
Sweep Angle - This is the value in degrees of the angle of the arc.
Operation
Add – When an arc is added, you can use three click events or a drag & release event and one
click. The arc is added as a portion of a circle.
Three Click Events - The first click establishes the location of one of the ends of the
arc. The second click defines the radius and anchors the origin (center) of the arc. The
third click sets the second end point of the arc.
First two clicks:

Draw and Dimension
Draw Objects
Third click:
The numbers are not shown in graphics while you are adding the arc, but the cursor, origin
marker and the dashed radius line are.
Drag & Release and One Click - The first click defines the first point on the arc, the release is
the same as the second click that defines the radius (center of the arc), and the third click defines
the sweep angle.
While in drag mode, if you selects the Alt Key, the release point is independent of the Snap
Grid.
Ctrl Add – This action turns the arc into a line. If an arc has been started and the second point
has been digitized, when the Ctrl button is pressed, the second point is aborted and you will
have a straight line, extending from the first point.
Selection - The arc displays handles at end points. The origin (center) has a plus mark, and the
center of the arc line has a diamond.
When the cursor is moved over a selected arc, an arrow on the end points and the center
diamond are displayed. These are to indicate that the action is different from the handles on a
rectangle, line or circle in which the object is stretched.
Double-clicking with the left mouse button on an arc selects the arc and displays it’s properties
within the Draw Properties dialog.
Move - The cursor with four arrows plus the standard pointer appears when the cursor is on a
segment where the handles do not exist. This indicates that you can drag move the entire object.

Draw and Dimension
Draw Objects
When moving the object, the original object remains in the same position, and the object in
dynamics appears as follows:
When releasing the mouse button, the object is moved and it remains selected.
Shift Move – If the shift key is pressed and held while performing a Move, the object is
restricted to moving orthogonal to itself.
Ctrl Move – If the Ctrl key is pressed and held while performing a move, when it is released, a
copy of the object is made. Note that the cursor has changed.
At the end of the copy/move, the original item is unselected and the copy becomes selected.
Alt Move – This allows the arc, while being dragged, to be moved independent of the Snap
Grid.
Stretch – With an arc you can either stretch the diamond or the end points. Stretching the
diamond changes the radius, while stretching the end points, changes the sweep angle.
Stretch Endpoint (Floating Arc Only) – When you stretch one of the end point handles, it
increases or decreases the sweep angle of the arc, keeping the same radius, and it has the
following appearance.

Draw and Dimension
Draw Objects
Stretching on the Diamond - If you drag on the yellow diamond, it increases or decreases the
radius of the arc, keeping the end points tangent to the imaginary tangent lines (red) to the end
points of the original arc. This operation is independent of the Snap Grid, therefore; the Arcs
center (origin) can be off the Snap Grid.
The center point of the newly formed arc is displayed. The original center point and the original
diamond do not appear during this operation because they could obscure the visibility of the
dynamics.
This operation is useful when the arc is connected to perpendicular lines.
Shift Stretch on the Diamond – (same as Stretch). With an arc you can either stretch the
diamond or the end points.

Draw and Dimension
Draw Objects
Circle
The origin of the circle is its center. If a new value is typed into the Draw Properties dialog, it is
confirmed by pressing the Enter key. At that point it is checked and the graphic is updated.
Line Width - This is the width of the line defining the circle. You can select a width from the
drop down list box or you can edit the field and enter a new width. Any new widths entered into
this field are accessible the next time you use this dialog box. If the Fill checkbox is set, this
option is grayed out.
Diameter - This is the value for the size of the circle.
Center X, Center Y - These entries define the location of the center (origin) of the circle.
Fill - If this check box is set, the circle is filled solid instead of drawn with an outline. When
selected in the design, the handles appear, but only the outline has the selection color. The fill
option is only selectable by a few generic draw types. Otherwise fill is not selectable.
Operation
Add – When you add a circle you may either use two click events or a drag and release event.
Two Click Events – The first click anchors the origin of the circle, which is the center.
As you move the cursor away from this anchor point, the radius of the circle increases.
The second click completes the circle.
During this operation, the center marker appears along with the cursor and the circle
itself, but the red radius line is not visible, it is displayed for demonstration purposes.
Drag and Release – The start of the drag anchors the origin of the circle, which is the
center. As you move the cursor away from this anchor point, the radius of the circle
increases. Releasing the mouse button completes the circle.

Draw and Dimension
Draw Objects
While in drag mode, the Alt Key allows the circle diameter to be placed independent of
the Snap Grid.
Selection – Choose a circle by selecting any location that does not have a handle on the circle’s
shape. If the circle is filled, click anywhere inside the circle to select it.
If you double-click with the right mouse button on a circle, the circle is selected and the
Properties dialog box is displayed.
When a circle is selected, its handles appear as shown below along with the center (origin)
marker.
As you move the cursor around the circle (without pressing the button), the following standard
cursor images display:
Move – The origin (center) moves on the Snap Grid.
Shift Move – If the Shift key is pressed and held while performing a Move, the object
will be restricted to moving orthogonal to itself.
Ctrl Move – If the Ctrl key is pressed and held while performing a move, when it is
released, a copy of the object is made.
Alt Move – Allows the circle being dragged, to be moved independent of the Snap Grid.

Draw and Dimension
Draw Objects
Stretch - The double arrows indicate that if you drag at that point, it moves the handle in the
direction indicated.
The result of moving the handles will be to increase the radius of the circle. The origin will not
move.
Alt Stretch – Allows a circle to be dragged and/or stretched independent of the Snap Grid.
Line
The origin of a line is the first point entered. If a new value is typed into the Draw Properties
dialog, it is confirmed by pressing the Enter key. At that point, it is checked and the graphic is
updated.
Line Width - This is the width of the line. A width can be selected from the drop down list box
or it can be edited and a new width can be entered. Any new widths entered into this field are
accessible next time you use this dialog.
Length - This is the value of the length of the line.

Draw and Dimension
Draw Objects
Angle - This angle is relative to the positive X axis.
Vertices - This is a list of vertices that define the line. All the fields are editable, and if edited
the line is automatically updated. Any changes made in the graphics causes the coordinates in
these fields to be automatically updated.
Origin X, Origin Y - These entries define the X and Y origin of the line. The origin of a line is
the first entered point. You can enter a "d" before a location in order to change the vertices
location by delta.
Display center handles - If this checkbox is set, center handles appear when the object is
selected in the design. If unset, even though the center handles are not displayed, they can still
be selected.
Operation
Add – You may add a line by either two click events or by drag & release events.
Two Click Events – The first click anchors the first end point. The second click defines
the other end point.
Drag & Release Events – The start of the drag is the first end point, the release of the
drag defines the other end point.
The angle of the line is according to the Angle Lock setting for the line. This is defined in the
Properties dialog for the line.
Shift Add – This forces the line to be drawn only in 45 and 90-degree angles regardless of the
angle lock.
Alt Add – This temporarily disables the Snap Grid, but the Angle Lock setting remains active.
This only occurs for second end point placement. During a drag, for example, a left mouse
button click is required.
Selection - The lines display handles at each end point, and one in the midpoint. The
midpoint handle is a red diamond.

Draw and Dimension
Draw Objects
As you move the cursor around (without pressing the button), the following standard
cursor images are displayed:
The end point cursors at 135-degrees, the center cursor perpendicular to the line.
The end point cursors at 0-degrees, the center cursor perpendicular to the line.
On a line that is horizontal, all the cursors are vertical. On a line that is vertical, all the cursors
are horizontal. Double clicking on a line, selects the line and displays the Properties dialog.

Draw and Dimension
Draw Objects
Move - The cursor, with four arrows plus the standard pointer, appears when the cursor is on a
segment where the handles do not exist. This indicates that you can drag move the entire object.
When moving the object, the original object remains in the same position, and the object in
When releasing the mouse button, the object is moved, and it remains selected.
Shift Move – This restricts the line to movements that are strictly parallel or perpendicular.

Draw and Dimension
Draw Objects
Ctrl Move – If the Ctrl key is pressed while performing a move, when it is released a copy of
the object is made.
Alt Move – If the Alt key is selected and held, while dragging the line to a new location, the line
can be placed independent of the Snap Grid.
Stretch an End Point Handle – You can move the end point of the line based on the snap grid.
Stretch a Center Point Handle – When you stretch a center point handle it moves the line
perpendicular to itself.
Shift Stretch an End Point Handle – This causes the line to extend in either direction.
Alt Stretch – This allows the end point handle or center point handle to be dragged and placed
independently of the snap grid.
Ctrl Stretch a Center Point Handle – This operation inserts a corner, it adjusts the length
without effecting the angle.
Once the line has been modified in such a manner, it becomes a polyline.

Draw and Dimension
Draw Objects
Resulting in:
Polyline
A polyline is a set of line segments and / or arc segments that are joined together at their
vertices, but they do not form a closed object. If the set of polylines were closed, they would
form a polygon.
This operation is the same for a polygon with the exception of the Closing option on the popup.
Any other differences in operation have been noted. Graphic examples are of polylines, not
polygons, however enough information is provided to assist you in creating a polygon without
visual aids.
The origin of a polyline is the first vertex placed. A polyline must have the same type, layer and
width throughout. If you change one of these values on one of the segments, then all segments
in the polyline are changed as well.
If a new value is typed into the Draw Properties dialog, it is confirmed by pressing the Return
Line Width - This is the width of the line forming the polyline. The width of the line is the
same on all segments. A width can be selected from the drop down list box or it can be edited

Draw and Dimension
Draw Objects
and a new width can be entered. Any new widths entered into this field are accessible next time
you use this dialog.
Vertex Type - The three types are Corner, Round and Chamfer.
Corner - If this setting is selected, you can place multiple lines without any
modification of the intersections of the lines. The sharp corner mode allows you to place
multiple lines without any modification of the intersections of the lines.
Round - If this setting is selected, as lines are placed, the intersection of the lines
become an arc. The arc radius is determined by the setting on the properties dialog. The
following graphic displays the dynamics of the placement of the third vertex of a
polyline when the corner mode is set to “round”.
As the cursor is moved down, dynamics change as soon as there is enough room to insert
the arc according to the arc radius.
Chamfer - As lines are placed, the intersection becomes a chamfered corner. The
chamfer length is determined by a user-setting on the properties dialog. The following
graphic displays the dynamics of the placement of the third vertex of a polyline when the
corner mode is set to “chamfer”.

Draw and Dimension
Draw Objects
As the cursor is moved down, dynamics change as soon as there is enough room to insert
the chamfer according to the chamfer length.
Vertices - This is a list of vertices that define the polyline. All the fields are editable and if
edited the polyline is automatically updated. If the vertex is at the start of an arc, the entry will
have an "a" to the right of the vertex number. Any changes made in the graphics causes the
coordinates in these fields to be automatically updated.
Origin X, Origin Y - These entries define the X and Y origin of the polyline. The origin is the
first entered point. You can enter a "d" before a location in order to change the vertices location
by delta.
selected in the design. If unset even though the center handles are not displayed they can still be
selected.
Operation
A polyline must have the same type, layer and width throughout. If you change one of these
values on one of the segments then all segments in the polyline are changed as well.
Add – The addition of a polyline follows the exact same methodology as adding a line. You
may add a line by either two click events or by drag & release events
Two Click Events – The first click anchors the first end point. The second click defines
the other end point.
Drag & Release Events – The start of the drag is the first end point, the release of the
drag defines the other end point.
The angle of the line is according to the Angle Lock setting for the line. This is defined in the
Properties dialog for the line.
Starting With an Arc – Polylines cannot be started with an arc.

Draw and Dimension
Draw Objects
Additional Segments - After the first segment is added, more line segments can be added by
simply clicking at the next end point.
Ending the Polyline - When you are finished with the polyline, select another function, choose
End polyline from the pop-up menu, or double-click the last end point.
Overlapping Segments – Segments are allowed to overlap; however, they are not joined at the
intersections.
Note
Polygon types do not allow overlapping segments.
Intersection between lines – The intersection between lines as they are placed can be Sharp,
Round and Chamfer.
Shift Add While Adding a Line - This forces the line to be drawn only in 45 and 90-degree
angles, regardless of the Angle Lock.
Selection - The line segments displays handles at each end point, and one in the midpoint. The
arc segments display the diamond in the middle of the arc line. Of course, connected segments
share handles at end points.
As you move the cursor around (without pressing the button), cursor images consistent with the
ones for lines and arcs are displayed.

Draw and Dimension
Draw Objects
Cursors at vertex and center handles

The following cursors would appear as you move your cursor over the handles. The example
consists of all the cursor images.
Move - The cursor with four arrows, plus the standard pointer, appear when the cursor is on a
segment where the handles do not exist. The standard pointer indicates that you can drag/move
the entire object.
When moving the object, the original object remains in the same position and the object in
When releasing the mouse button, the object is moved, and it remains selected.
Shift Move – This restricts the movements to 90-degree angles relative to the origin.

Draw and Dimension
Draw Objects
Ctrl Move – If the Ctrl key is pressed and held while performing a move, when it is released, a
copy of the object is made.
Alt Move – While dragging the polyline object, if the Alt Key is pressed and held, the polyline
can be placed independent of the Snap Grid.
Stretch an End Point Handle

Two Line Segments - If the end point joins two line segments, the corner moves “freely”
depending on the Snap Grid. If the Alt key is selected, the corner moves independent of the
Snap Grid. This means it will stretch freely, but it will be restricted to the defined Angle Lock.
A Line Segment and an Arc / Two Arcs – A vertex at an Arc start or end point to be moved is
not allowed. If an endpoint from a segment, that is tangent to an arc, is moved, the arc adjusts to
stay tangent to the segment.
Stretch a Center Point Handle

A Line Segment Attached to Another Line Segment – The line moves parallel to itself and
the other line segment stretch or shrink as needed. This dynamically snaps to the grid.
If the polyline is a rectangle, it behaves as shown in stretch rectangle. If the angles are non-
orthogonal, it stretches or shrinks:

Draw and Dimension
Draw Objects
A Line Segment Attached to An Arc – The line moves parallel to itself and the arc moves with
it, keeping the same radius. This may cause the line connected to the other end of the arc to
stretch or shrink.
If the line attached to the other end of the arc is non-orthogonal, if you drag on the yellow
diamond, it increases or decreases the radius of the arc, keeping the end points tangent to the
imaginary tangent lines (red) to the end points of the original arc. Since the radius of the arc
remains constant, the line you are stretching in this case stretches or shrinks.
Stretching on the Diamond - If you drag on the yellow diamond, it increases or decreases the
radius of the arc, keeping the end points tangent to the imaginary tangent lines (red) to the end
points of the original arc. This operation is independent of the Snap Grid; therefore, the Arcs
center (origin) can be off the Snap Grid.
The center point of the newly formed arc is displayed. The original center point and the original
diamond do not appear during this operation because they could obscure the visibility of the
dynamics. This operation is useful when the arc is connected to perpendicular lines.

Draw and Dimension
Draw Objects
Shift Stretch on the Diamond – (same as Stretch). With an arc you can either stretch the
diamond or the end points.
Shift Stretch an End Point Handle

A Line Segment Attached to an Arc – Stretch on an Arc start or end point is not allowed.
Ending the polyline
You may end a polyline/polygon by double-clicking on the last end point, or by choosing Close
Polyline/Close Polygon from the popup menu accessed by selecting the right mouse button.
Polygon
A polygon must have the same type, layer and width throughout. If you change one of these
values on one of the segments, then all segments in the polygon are changed as well. The
definition of a polygon includes arcs. See the Polyline Operation for a detailed explanation.
Differences in behavior between polygons and polylines are noted.
Note
Polygon types do not allow overlapping segments. An error message appears if you try to
assign an illegal type to a polygon with overlapping segments.
Line Width - This is the width of the line forming the polygon. The width of the line must be
the same on all segments. If the fill checkbox is select this option is grayed out and is
unavailable to change.
Vertex Type - The three types are Corner, Round and Chamfer.
Corner - If this setting is selected, you can place multiple lines without any modification of the
intersections of the lines.

Draw and Dimension
Draw Objects
Round - If this setting is selected, the intersection of the lines become an arc as lines are placed.
The arc radius is determined by the setting on the properties dialog. When the corner setting is
set to “Round” as lines are placed the intersection of the lines becomes an arc. The arc radius is
determined by the setting on the Properties dialog. The following graphic displays the dynamics
of the placement of the third vertex of a polyline when the corner mode is set to “round”.
As the cursor is moved down, dynamics will change as soon as there is enough room to insert
the arc according to the arc radius.
Chamfer - When this setting is selected, the intersection will become a chamfered corner as
lines are placed. The chamfer length is determined by a user-setting on the Properties dialog.

Draw and Dimension
Draw Objects
The following graphic displays the dynamics of the placement of the third vertex of a polygon
when the corner mode is set to “chamfer”.
As the cursor is moved down, dynamics will change as soon as there is enough room to insert
the chamfer according to the chamfer length.
Fill - If this check box is set, the polygon is filled solid instead of drawn with an outline. The fill
option is only selectable for basic Draw Types.
Vertices - This is a list of vertices that defines the polygon. All the fields are editable. The
polygon is automatically updated if it is edited. If the vertex is at the start of an arc, the entry
will have an "a" to the right of the vertex number. Any changes made in the graphics causes the
Origin X, Origin Y - These entries define the X and Y origin of the polygon. The origin is the
first entered point. You can enter a "d" before a location in order to change the vertices location
by delta.
Grow/Shrink - This keyin field is used to inflate or deflate the polygon by moving the vertices
away from the centroid by the distance specified. If a number is entered in the field, and the
Enter key is pressed, it grows (if no sign or a plus sign(+)) or shrinks (if a minus sign (-)).
Display center handles - If this checkbox is set, center handles will appear when the object is
selected in the design. If unset, even though the center handles are not displayed they can still be
selected.

Draw and Dimension
Draw Objects
Ending the polygon
You may complete a polygon by choosing Close Polygon from the popup menu accessed by
selecting the right mouse button, or by double-clicking on the first vertex. The close function
will insert a line segment, (line and arc for round corner) from the previous click point. If the X
and Y origin value is the same as one of the placed points, this will terminate the command,
completing the polygon.
Rectangle
The origin of a rectangle is the lower left corner. If you rotate a rectangle, it becomes a polygon.
If a new value is typed into the Draw Properties dialog, it is confirmed by pressing the Return
Line Width - This is the width of the line forming the rectangle. The width of the line is the
same on all sides. A width can be selected from the drop down list box or the field can be edited
and a new width entered. Any new widths entered into this field are accessible the next time you
use this dialog. If the Fill checkbox is set, this option is grayed out.
Fill - If this check box is set, the rectangle is filled solid instead of drawn as an outline. When
selected in the design, the handles appear, but only the outline has the selection color. Only
basic draw types are allowed to be filled.
Convert to Polygon - The convert to Polygon option changes a rectangle to a polygon type.
This allows you to use the polygon modification options that are not allowed for a rectangle.

Draw and Dimension
Draw Objects
Width - This entry is the X dimension of the rectangle.
Height - This entry is the Y dimension of the rectangle.
Vertices - This is a list of vertices which defines the rectangle. You can enter a "d" before a
location in order to change the vertices location by delta. All the fields are editable. If edited, the
rectangle is automatically updated. Be aware that if you change one of the fields, another field
has to be edited to keep the shape as a rectangle. Any changes made in the graphics causes the
Origin X, Origin Y - These entries define the X and Y origin of the rectangle. The X origin is
the lower left corner. Keying in a new origin location can change the location of a rectangle.
You can enter a "d" before a location in order to change the vertices location by delta.
Grow/Shrink – This keyin field is used to inflate or deflate the rectangle by moving the vertices
away from the centroid by the distance specified. If a number is entered in the field, and the
Enter key is pressed, it grows (if no sign or a plus sign(+)) or shrinks (if a minus sign (–) sign).
selected in the design. If unset, only corner handles appear. However, although the center
handles are not displayed they can still be selected.
Operation
Add – When you add a rectangle you may either use two click events, or a drag and release
event.
Two Click Events – The first click anchors the first corner. The second click defines the
opposite corner. Depending on which direction you move the cursor after the first click,
you can get four different relationships to the anchor point. The red line is for your
reference only in this specification; it does not appear in graphics.
Drag & Release Events – The start of the drag is the anchor point. The location of the drag
release is the opposite corner. The graphics are the same as the two click events.
While in drag mode, if you select the Alt Key, the edge of the rectangle can be placed
independent of Snap Grid.
Key in – You may key in the Width and/or Height values instead of dragging the
rectangle. Both width and height values are required to attach the rectangle to the cursor
in order to be placed.

Draw and Dimension
Draw Objects
Selection – You can select a rectangle by selecting any location that does not have a handle on
the rectangles shape. If the rectangle is filled, you can select anywhere inside it in order to select
it.
If you double click with the left mouse button on a rectangle, the rectangle is selected and the
properties dialog is displayed.
Selection Handles - The rectangle displays handles at each corner and the midpoint of each
side. The midpoints are red diamonds.
As you move the cursor around (without pressing the button), the following standard cursor
images display:
Move - The cursor with four arrows plus the standard pointer appears when the cursor is on a
segment where the handles do not exist. It indicates that you can drag move the entire object.
When moving the rectangle, the original object remains in the same position, and the object in
When releasing the mouse button the object is moved, and it remains selected.

Draw and Dimension
Draw Objects
Shift Move – If the Shift key is pressed and held while performing a Move, the object is
restricted to moving orthogonal.
Ctrl Move – If the Ctrl key is pressed while performing a move when it is released, a copy of
the object is made.
At the end of the copy/move, the original item is unselected and the copy becomes selected.
Alt Move – This allows the rectangle, while being dragged, to be moved independent of the
Snap Grid.
Rotate - If you rotate a rectangle to angles other than 0, 90, 180, or 270, it becomes a polygon.
Stretch - The double arrows indicate that if you drag at that point, it moves the handle in the
direction indicated.

Draw and Dimension
Draw Objects
Ctrl Stretch – This allows the lines attached to the handle to move at angles other than 90
degrees. Once the rectangle has been modified in such a manner, it becomes a polygon.
If a center handle is stretched using the Ctrl key, this effectively inserts a new corner.

Draw and Dimension
Draw Objects
If a corner handle is stretched using the Ctrl key, it allows that corner to move.
Alt Stretch – This allows a rectangle to be dragged and/or stretched independent of the Snap
Grid.
Text
The text object allows the placement of text strings within the design. These objects can be
based on any True Type font loaded on the system.
If a new value is typed into the Draw Properties dialog, it is confirmed by pressing the Enter
If you click on the Draw text icon or select it from the pulldown in the Draw Properties dialog,
when text is entered into the "String" field it is attached to the cursor ready for placement. If the
Enter key is pressed, the Draw Properties dialog disappears. If you place the text, without
pressing Enter, the Draw Properties dialog loses its fields and you have to select Text from the
pulldown to enter more text.
If you double-click on the Draw icon, you may enter as many strings of text as necessary
without having to refresh the Draw Properties dialog. However, if you select the Enter key, the

Draw and Dimension
Draw Objects
Draw Properties dialog will still dismiss but any text changes are saved and display when this
dialog is re-opened.
If the option, Control Panel - Display Properties - Option for Smooth Edges on screen fonts
is enabled on your computer, it can cause the text to dim and make it difficult to view the text
when placed using Draw and VeriBest Gerber fonts.
Text - This displays all TrueType and Vector fonts on the system.
B (Bold), I (Italic), U (Underline) - These options change the properties of the selected text
string. These are toggle buttons.
Display only Gerber-compatible fonts - This checkbox filters the Text combinational box to
display only vector fonts. TrueType fonts are not recommended for Gerber.
Height - This is value of the height of the text string.
Rotation - This value is the rotation of the text string. If values, other than 0, 90, 180, and 270,
are typed into the field, the text must be clicked on, to move it the rotation of the text. After that,
the entered value displays in the field and allows you to use the Enter key to rotate the text.
Text origin - This displays the text/justification of the text string. There are nine valid
justifications which are depicted by the + symbol.
Pen width - This value is used when the text is stroked to be plotted or photoplotted. Each line
that makes up the text is given this width value.
Mirror - The selection of these buttons allows the text to be mirrored either horizontally or
vertically.

Draw and Dimension
Draw Objects
Location X, Y - These values decide the X and Y origin of the text in the design.
String - This is the text string that is displayed. Only single strings are allowed.
Operation
Add – Text can be added to a design by keying in the string in the dialog, the string dynamically
displays attached to the cursor. The text attachment to the cursor is based on the user-defined
text origin. At any point after the text it keyed in, you can place it in the design.
Selection – You can select text by clicking anywhere on the text string.
Move – Text is moved so its origin is on the draw grid.
Alt Move – If you select the Alt Key while dragging a text string, the string is placed
independent of the Snap Grid.

Appendix B
FabLink XE
FabLink™ XE is a licensed product that can be invoked on a design (.pcb) or a panel (.pnl).
Licensing
There are two different licenses for FabLink XE; FabLink XE and FabLink XE Pro. There are
five design scenarios relating to functionality:
• Expedition PCB (no FLXE Pro or FLXE license acquired).

• Expedition PCB (either a FLXE Pro or FLXE license acquired).
• FabLink XE invoked through Expedition PCB (either a FLXE Pro or FLXE license
acquired).
• Stand-alone FLXE on a Panel (*.pnl).
• Stand-alone FLXE Pro on a Panel (*.pnl).
When FabLink XE is invoked, an "xeFabLink" license is required and enables only single-
design panel creation. When FabLink XE Pro is invoked, a "xeFabLink" and a "xeFabLinkpro"
license are required and allows both single-design and multi-design panel creation.
Acquiring FabLink XE Pro and FabLink XE

licenses
A FabLink XE Pro or FabLink XE license can be acquired in one of three design scenarios.
Standalone is the only way FabLink XE Pro or FabLink XE is directly invoked after acquiring
the license(s).
Standalone
Invoke as a stand-alone application (Start > Programs > Mentor Graphics SDD >
DXDesigner - Expedition Flow > Manufacturing> FabLink XE) or (Start > Programs >
Mentor Graphics SDD > Design Capture / DesignView - Expedition Flow >
Manufacturing> FabLink XE).
If you have purchased both FabLink XE Pro and FabLink XE licenses, the following splash
screen is displayed (FabLink XE Pro is selected as the default).

FabLink XE
Acquiring FabLink XE Pro and FabLink XE licenses
Figure B-1. FabLink XE license splash screen
Regardless of the selected license, the splash screen displays briefly before the FabLink XE tool
appears.
From within standalone FabLink XE you cannot acquire a FabLink XE Pro license in the same
session. You must exit and reinvoke FabLink XE and select the FabLink XE Pro license on the
splash screen.
Through the Expedition PCB License Splash Screen

Invoke an Expedition PCB design session (Start > Programs > Mentor Graphics SDD > WG
2004 > Expedition PCB > Expedition PCB).
The Expedition license splash screen appears and you can then optionally select either the
FabLink XE Pro or FabLink XE product license. When one of the FabLink XE options is
selected the other will desensitize. If a mistake is made, the selected option will have to be
unselected for the desensitized option to reappear and be selectable.
Figure B-2. Expedition PCB license splash screen

FabLink XE
Invoking FabLink XE and FabLink XE Pro from within Expedition
Through Setup Licensing in Expedition PCB

In an opened Expedition PCB design session, you can select either a) Setup > Licensed
Modules > FabLink XE Pro license or b) the Setup > Licensed Modules > FabLink XE
license.
Figure B-3. Acquiring a FabLink XE license within an Expedition design

session.
For all three-design scenarios, if FabLink XE or FabLink XE Pro licenses are not available, an
error message displays.
Invoking FabLink XE and FabLink XE Pro from

within Expedition
Standalone FabLink XE can be accessed from the Expedition Output pulldown menu. If a
license is available, selecting Output > FabLink XE will open the selected product in
standalone mode. The FabLink XE / FabLink XE Pro license displays the following features
within Expedition PCB:
Independent of the FabLink XE license

• Adding a Manufacturing Outline
• Copper Balancing display options in Display Control.

FabLink XE
Panel Wizard
After acquiring a FabLink XE/FabLink XE Pro license

• File > New > Panel Wizard
• File > Import > Gerber
• File > Import > Drill
• File > Export > GDSII
• File > Export > IPC-D-356B
• Edit > Place >Detail View
• Edit > Place >Copper Balancing Shape
• (PCB) Planes > Copper Balancing > Place Copper Balancing Shape
• (FLXE) Route > Copper Balancing > Place Copper Balancing Shape
• (PCB) Planes > Copper Balancing > Processor
• (FLXE) Route > Copper Balancing > Processor
• (PCB) Planes > Copper Balancing > Delete Copper Balancing Data
• (FLXE) Route > Copper Balancing > Delete Copper Balancing Shape
• Output > Mask Generator
• Output > PDF
• Output > FabLink XE
• Output > XE Neutral file
• Output > Manufacturing Output Validation
Panel Wizard
The Panel Wizard can be invoked by one of the following methods:
1. Within FabLink XE (on a panel design), File > Panel Wizard. This invokes the
Welcome page of the Panel Wizard and allows you to chose the appropriate option.
2. Within FabLink XE (on a panel design), File > New. This invokes the Panel Wizard’s
Create command.
3. In Windows, from the Start > Programs > Mentor Graphics SDD > DXDesigner -
Expedition > Manufacturing > Panel Wizard or Start > Programs > Mentor
Graphics SDD > Design Capture / DesignView - Expedition > Manufacturing >
Panel Wizard option.

FabLink XE
Design Placement
The Panel Wizard allows you to:
• Create a separate project file for the panel.

• Provide a means to create a panel.
• Provide a means to copy/move/rename the panel without losing critical files.
• Provide a means to cleanup and/or delete a panel.
• Automatically update the library and Setup Parameter paths.
A default template is provided in the ..\xe\win32\FabLinkxe\Templates\Central Library\Central
Library.lmc.
Design Placement
A single design or an array of designs can be placed within the panel outline using this
command. You can place the center of the array into the center of the panel or you can designate
your own design placement options.
Note
If the size of the design or array of designs is too large for the panel, placement is not
allowed.
All designs of the array can be placed at a rotation other than the original design (90, 180 or 270
degrees) and can also be mirrored. If Flip is checked, the design(s) that are already placed
mirrored on the X-axis.
To include spaces between the designs of the array (to allow for shearing and/or milling
operations), a value can be entered for either or both of the rows and columns. The default is 0
(no space between designs).
The Place > Unload all Design Data command allows you to remove (unload) PCB data that
resides in the panel and when this command is accessed, the PCB data disappears and only the
board outline displays. When changes have been made to the PCB data, you can use the Place >
Upload all Design Data command to re-import (upload) PCB data in the panel.
Import Gerber
You can load a Gerber file onto a user-defined layer. Only Gerber generated by the Expedition
or FabLink XE systems is supported. The display of these elements can be handled through the
user layers defined within Display Control. Within a PCB file without a valid FabLink XE or
FabLink XE Pro license this information is Read Only.

FabLink XE
Import Gerber
Multiple Gerber files can be created within the design. The filename must have a prefix of
GPF_. If the Import Cell field is blank, the Import mode is New; this allows a new Gerber file to
be created in the local library.
The Gerber Plot Setup Format (.gpf) file that was used to generate the Gerber files for the
current design is required. The default path will be the path of the .gpf file for the current
design. The .gpf file contains a reference to the Gerber Machine Format (.gmf) file which is
automatically read. All information required to import the Gerber files is contained within the
.gmf and .gpf files. This includes the file offset, the file type (274X or 274D), the modes, etc. If
an offset was given to the generated data, this is used to move the data back to its original place.
This is done so that the Gerber layer can be overlaid and compared with a design layer. If a
274D file is specified, the .gpf file's '.DcodeToApertureFile' entry can be used to define the
aperture sizes.
To make sure that the .gpf file is in sync with the generated Gerber data the timestamps of the
.gpf file and the generated Gerber files are compared, and if .gpf file has a timestamp later than
the timestamps of any Gerber file, a prompt appears with a warning message asking whether to
proceed with the import.
The list of Gerber files inside the .gpf file which have their ..ProcessFile attribute set to Yes will
be searched for on disk. This list is used to create a Gerber layer mapping list with a check box
to determine if the file should be loaded (defaulted On), the Gerber file name, and the default
User Layer name which can be changed by typing in a new name or selecting an existing user
layer. The default User Layer name is "GER_<file name, no extension>". If a particular Gerber
file cannot be found, an error is generated and the list entry is greyed out.
The new user layers are created in a cell. You may type in the name of a new cell or select an
existing cell in the Import Cell field. For existing cells, the Import Mode allows you to append
to the cell, overwrite the cell or overwrite layers within the cell.
• If the Overwrite Cell / Data option (default) is selected, any data in the cell is deleted
before new Gerber data is read in.
• If the Append Cell / Data option is selected, the existing data in the cell is untouched and
new data is read into the defined user-layers.
• If the Overwrite Layers Only option is selected, data on defined user-layers in the
existing cell is deleted and replaced by new data imported to those same defined user-
layers, any other user-layers within the cell are unaffected. You must edit the Cell
through Cell Editor.
A "GerberImportLog.txt" log file is created in the ../logfiles directory which contains all
logging information (files imported, warning and error messages).
New Gerber user-layers appear in Display Control and Gerber pads are shown (filled) in their
true shape as defined by the Gerber aperture list.

FabLink XE
Import Drill
Rendered Objects
Gerber objects are rendered in a WYSWYG manner: pads are shown in their true shape as
defined by the Gerber aperture list, filled.
Import Drill
You can load a Drill file onto a user defined layer. Only Drill data generated by the Expedition
or FabLink XE systems are supported. The display of these elements can handled through the
user layers defined within Display Control. Within a PCB file without a valid FabLink XE or
FabLink XE Pro license this information is Read Only.
Only imported Expedition-generated Drill files are supported. The path to the Drill directory
containing the drill files is required. The DrillPreferences.hkp located in the jobs ../config
directory contains the path to the Drill Plot File Format (.dff) file that was used to generate the
drill file. All required information to import the file, including the file offset, is contained within
the .dff file and the DrillPreferences.hkp file. If an offset was given to the data when generated
it is used to move the data back to its original placement. This allows the Drill layer to be
overlaid and compared with a design layer.
Figure B-4. Drill Import Dialog
The list of drill files inside the directory is used to create a Drill layer mapping list with a check
box to determine if the file should be loaded (defaulted On), the Drill file name, and the default
User Layer name, which can be changed by typing in a new name or selecting an existing user
layer. The default User Layer name is "DRL_<file name, no extension>". You can overwrite
this layer name in the User Layers type-in box.
The new user layers are created in a cell. You may type in the name of a new cell or select an
existing cell in the Import Cell field. For existing cells, the Import Mode allows you to append
to the cell, overwrite the cell or overwrite layers within the cell.

FabLink XE
GDSII
If the Overwrite Cell / Data option (default) is selected, any data in the cell is deleted before
new Drill data is read in. If the Append Cell / Data option is selected, the existing data in the cell
is untouched and new data is read into the defined user-layers.
If the Overwrite Layers Only option is selected, data on defined user-layers in the existing cell
is deleted and replaced by new data imported to those same defined user-layers, any other user-
layers within the cell are unaffected. You must edit the cell through Cell Editor.
The Drill Targets option will add drill targets at the appropriate drill location if selected. The
size of the target will be defined by the Drill Target Diameter field. A "DrillImportLog.txt" log
file is created in the logfiles directory which contains all logging information (files imported,
warning and error messages).
Rendered Objects
Drill objects appear as un-filled circles at their defined diameter. If the Drill Targets option was
selected during import, a target in the shape of a '+' is drawn with the length of the line segments
equal to the Drill Target Diameter value.
Milling data appears hollow, at width with arrows indicating their direction. The arrow is placed
at the center of the line, filled solid, and its size equals the milling width. If the ratio (length of
milling segment) / (width of milling segment) is less than a constant, the arrow is not displayed.
Milling 'moves' (where the milling head is pulled up, moved, then plunged down) is indicated
by a dashed line with a direction arrow.
GDSII
GDSII allows you to take data from an IC vendor and create a template that can be used in
defining parts and generates a GDSII format single file in binary output for either an Expedition
PCB or Panel design. The GDSII file is generated in the form of layers; each layer is mapped to
a separate logical layer in the GDSII file.
• In Expedition PCB a GDSII layer can contain a list of selected layers (signal, plane)
with board items, cell items and user-defined layers.
• In FabLink XE a GDSII layer can contain a list of selected panel layers, panel and board
items, panel and board cell items and user-defined layers for the panel.
The Contents tab allows you to define the graphics objects which make up the output files.
Typically, each GDSII file consists of a set of elements that is used to manufacture your printed
circuit board or panel design. You should generate one file for each route layer within your
design and one file for each of the following: top and bottom soldermask pads, top and bottom
solderpaste pads, top and bottom silkscreens, drill drawing and the assembly drawings.

FabLink XE
IPC-D-356B
When generating GDSII a dialog displays showing the process of the generation. You can stop
the generation of the .gds file by selecting the Cancel button on the Process dialog. Any errors
and warnings are displayed in a popup window and can also be viewed in the generated
../LogFiles/GDSIIExport.txt log file.
Embedded Passive Requirements

Embedded Passive output options are only available when embedded passive components are
present within the open design.
Within FabLink XE Pro, since the first placed design on the panel assumes its stackup,
embedded passive selections are only available if the first design placed on the panel contains
embedded passive components.
Export of embedded passive related information requires an ATPro license in Expedition and a
FabLink XE Pro license for export from FabLink XE. These options are not available with a
standard FabLink XE license.
IPC-D-356B
This export standard describes a data format for transmitting bare board electrical test
information. When used as a netlist input to test data processing, the receiver of IPCD35B data
will determine test point assignments and positioning.
Being essentially a netlist test format, this standard has been crafted to represent interconnect
substrate graphics and test in a balanced way. Although substantial support is given to convey
the graphical image of conductor shapes, the standard is not graphically correct. It is not
intended to serve as a means to produce artwork or other board fabrication tools, but rather
serve as a useful aid in conducting electrical test, analysis and repair.
FabMaster Panelization
Note
A FabLink XE / XE Pro license is required to access the General Interfaces > FabMaster
Panelization option.
The Fabmaster command produces output files which can be used with the Fabmaster package.
is selected. A <design_name>.fab file is also generated and can be located in the design's
../PCB/Output directory.
The supported version of Fabmaster, at board level only, is FATF Rev 1.2.

FabLink XE
Detail Views
Detail Views
With a FabLink license detailed views can be placed and manipulated within an Expedition file.
All detailed views are listed in the Display Control dialog. Within a PCB file without a valid
FabLink XE or FabLink XE Pro license this information is Read Only.
detail. This allows you to create customized documentation details. Detailed views have their
own scale factor, can contain specific Display Control settings and are read-only. The only
manipulation within a detailed view is the addition of text, dimension data and graphics and any
manipulation should be created on a user layer defined in Setup Parameters. There is a limit of
250 detailed views within any one design.
Note
If a dimension is added to a detailed view, after exiting and re-opening the design, the
The detailed view can be placed with precision keyins or with cursor data points. We
recommend that you pre-define a number of layers that will be exclusively used for detailed
views. This will eliminate user-defined information being displayed incorrectly within the
detailed view or design layout.
Once the area has been defined you can change the scale factor. The default is 1:1 (displayed a
1). A scale factor in positive numbers and in increments of tenths can be input. Legal scale
factors are: .5, 1.1, 1.7, 2, 2.3, etc. The top limit for the scale factor is 100:1. If the scale is
changed for a defined detailed view, the associated scratch pad is scaled appropriately and if the
new size overlaps or infringes on other design elements, the detailed view will need to be
manipulated.
Detailed views may be moved anywhere within the design plane, including the board area or
outline. The detailed view always displays on top and if placed within the board outline, the
design data may be hidden.
A copied detailed view increments the last placed detail view name by one. This can then be
edited and the displayed layers in Display Control can be changed.
Figure B-5. Displayed Views in Display Control
If the detailed view is included within the selected plot area, the information is plotted as any
other elements within the design. Detailed views are WYSIWYG, therefore you should display
the elements and layers within the detail view prior to plotting.

FabLink XE
Detail Views
Modification and Annotation Modes

There are two different modes; one allowing changes and one allowing additions within the
detailed view area. The following diagram shows the two modes; yellow highlight for
modification and red highlight for addition.
Note
If a dimension is added to a detailed view, after exiting and reopening a design, the
Figure B-6. Detailed View Areas
Modification mode allows you to change or modify the following parameters: name, scale,
mirror, rotate and font by single-clicking in the detailed view area. While in this mode, you can:
• Move - Select the scratch pad border and move the entire detailed view.
• Modify the scratch pad area - Select a handle of the scratch pad to stretch the detailed
view.
• Modify the detailed view area - Select a handle on the board selected area and stretch the
viewing area. This only changes the detailed view area, it does not change the scale or
scratch pad area.
Annotation mode is accessed by clicking the left mouse button within the scratchpad. The
scratch pad border turns red and the design displays in shadow mode. This mode allows you

FabLink XE
Copper Balancing
access to the dimension, text and graphic placement commands. The Properties Text options are
only allowed within the annotation mode.
Dimension data within the detailed view is stored on the selected detailed view layer and is
placed within the scratch pad area. Applying dimension data is only available in annotation
mode.
To return to modification mode select the scratch pad border. To exit from annotation mode,
either select anywhere in the design or select the right mouse button and click Exit from the
popup.
Copper Balancing
Copper Balancing refers to adding copper patterns made up of either: copper lines, copper circle
or copper shapes that are not associated with any electrical net of a design on any layer of either
a panel or board design. Copper balancing generation is different for a board design versus a
panel design. When balancing a panel, the system will not add copper balancing inside of any
board design (board outline), so these areas of the panel will act as copper balancing obstructs.
No graphics will appear until after all of the layers have been completed. You can use the ESC
key to abort the process, but the process will only stop after it is finished completing the copper
balancing on its present layer.
No trace(s) can be routed though a Copper Balancing shape (i.e. re-routing a trace with
Expedition's Plow command). If you need to modify the design (re-route traces), the Copper
Balancing shape must be manually edited/deleted or automatically deleted.
In the PCB design process, Copper Balancing is not attempted until the a) the entire board
design is placed, routed and copper planes have been finished, and b) all Batch DRC errors have
been identified and corrected.
Copper balancing is never identified as part of a schematic circuit, as it is only added after
visually assessing the board/panel design if copper balancing will improve the electrical and/or
ease of manufacturing.
Copper balancing is not added to the panel design until all board designs and other necessary
panel objects have been placed.
Adding thieving to the outside layers is sometimes needed to balance the plate-able area across
the panel. The addition of thieving patterns should be used on circuit designs that have an
uneven distribution of copper on the outer layers to insure the even electroplating of copper.
The additional copper steals from the circuit image so that traces and pads are not over-plated.
On a board design with tight spacing, over-plating may lead to shorts. This should be designed
to conform to the printed circuit board vendor's specifications.

FabLink XE
Copper Balancing
Venting provides for more consistency in the lamination process. When a board is pressed, the
venting helps to retain an even distribution of prepreg material to adhere the layers. Without it,
the prepreg would freely flow away from the circuit board, decreasing or causing uneven
adhesion of layers.
In general, any copper-free area (including breakaways) exceeding 0.5" x 0.5" [12.7 x 12.7]
should have copper thieving. Again, these values are only a suggestion, as you may need to
change either or both of these values to accommodate a unique design. The "Discard any area
less than" X and Y fields (within the Copper Balancing Processor dialog) should be used to
define the minimum area for not attempting to place copper balancing.
Before any Copper Balancing is generated (for either the board design and/or panel design):
• All Route obstructs and Plane obstructs should be created.

• For the board design, the design must be 100% routed, and all planes created.
• For the panel design, all board design and panel cells should be placed within the panel
outline (the panel border needs to be created as well).
• All DRC rules for element-to-element spacing should be established.
Terminology
Copper balancing data is the term used for physical copper patterns that are added to either a
signal or plane layer that has no net name assigned. These patterns can be generated as shape
patterns (squares, diamonds, circles) or line patterns (line segments). The layer must have the
variable "Positive" selected within Setup Parameters - Planes Tab - Plane Layer field.
Copper balancing shape is an area that contains copper balancing patterns. The shape is not
output to manufacturing, as its purpose is to define the area where the copper balancing data is
generated. A copper balancing shape is placed using the Draw functionality.
Thieving - this is a PCB industry term refers to adding copper balancing only on the outer layers
of a PCB design or panel. Copper objects (line segments or solid shapes) are added to a layer to
produce a uniform density of copper throughout the layer. These objects prevent excess plating
from accumulating on critical copper areas (thieving the excess plating away), to prevent
potential shorting conditions.
Venting - this is a PCB industry term refers to adding copper balancing only on the inner layers
of a PCB design or panel, for purposes of venting the gases incurred when layers are
sandwiched together in a lamination press.

FabLink XE
Copper Balancing
Display Control
Within Expedition PCB, the Display Control > Layer tab displays Copper Balancing data that
has been added within a *.pcb Design. However, you can not add, edit or delete copper
balancing within Expedition until either a FabLink XE Pro or a FabLink XE license is acquired.
Figure B-7. Copper Balancing on the Display Control Layer tab
The Copper Balancing Data option displays metal generated by the Copper Balancing
Processor.
The Copper Balancing Shapes option displays the Copper Balancing shapes placed on
signal/plane layers.
Place Copper Balancing Shapes

A Copper Balancing shape can be placed on positive plane type layers. The line pattern or shape
pattern within the Copper Balancing shape is based on the layer setting(s) and values found
within the Copper Balancing Processor dialog.
The Drawing Grid (as defined within the Editor Control > Grids Dialog Box) may be used to
define a grid spacing. This would allow you to begin with an exact starting vertex when drawing
a rectangular Copper Balancing area. This grid only defines the area for where you want to add
Copper Balancing, and does not control the placement of the Copper Balancing patterns.
You can change the default value to another value, or to zero, which would then allow you to
draw a Copper Balancing shape from wherever the cursor is presently located.
When the command is selected in either Expedition or the Panel Editor, the mode automatically
changes to the Draw, and the following Draw Properties dialog appears with the Type "Copper
Balancing Shape" selected.
The dialog only displays the individual positive layers (based on the variable Positive from the
Setup Parameters > Planes > Plane Type field), and the word "(All)" at the end of the list,
which allows you to add the user-defined Copper Balancing shape simultaneously on all of the
design's positive layers.
When you select a layer to add Copper Balancing, the Display Control > Layers tab settings
change and the graphics view reflects these changes:
• Traces: On
• Pads: On

FabLink XE
Copper Balancing Processor
• Lyr and Description: Layer to have Copper Balancing added to it - On. All other layers -
Off.
• Planes: All checkboxes are selected.
• Copper Balancing: All checkboxes are selected.
For drawing Copper Balancing Planes for Hatch patterns, you can draw a shape with either the
Add Polygon, Add Rectangle, or Add Circle option. All remaining draw options are
desensitized.
For drawing Copper Balancing Planes for Shape patterns, the system only enables the Add
Rectangle option. All remaining draw options are desensitized.
Adding User-defined Copper Balancing to the

Board/Panel design
Once all fields of the Draw Properties dialog are selected, you can then define the shape where
Copper Balancing is to be created by either defining the shape via the left mouse button in the
display window, or typing in the co-ordinates within the dialog.
After you complete the drawing of each Copper Balancing shape, the created Copper Balancing
shape is based on respecting any/all pre-existing route obstructs and/or any/all pre-existing
plane obstructs that intersect with or reside within the Copper Balancing shape.
The shape/line pattern within any/all user-defined Copper Balancing shapes is not generated
until the OK button is selected.
Copper balancing rectangles exception handling

There are situations where two (or more) Copper Balancing rectangles created are either:
• Near each other

• Share a common side with each other
• Intersect each other (overlap).
For the last two categories, the user-defined shapes will remain unique and separate editable
shapes. These Copper Balancing shapes are resolved at Copper Balancing generation time into a
single, consistent pattern.

Only those layers that have been setup with a positive plane are displayed.

FabLink XE
Figure B-8. Copper Balancing Processor Dialog
The following matrix defines which options may be selectable for the selected Copper
Balancing pattern:
Table B-1. Copper Balancing Pattern Matrix

Copper Balancing Fill Non-Square Restrict Balancing to Snap to Hatch Grid
Pattern Hatch Areas Orthogonal Patterns (Option if Restrict
Balancing option is
selected)
Vertical N/A Available If
Horizontal N/A Available If
Diag. Slash N/A N/A N/A
Diag. Backslash N/A N/A N/A
Crosshatch Available Available If
Diag. Crosshatch Available N/A N/A
Square N/A Available If
Circle N/A Available If
Diamond N/A Available If
The Clearance value is used as the clearance between all Copper Balancing shapes generated
and all other board design/panel design objects. This value does not apply between any pair of
Copper Balancing shapes.
You can define offsets for where the balancing pattern starts with respect to the origin of the
active rectangle (that has just been drawn), or where the system determines the design's origin
for generating the Copper Balancing (if the design's lower left hand corner is orthogonal, then it
will begin from the lower left hand corner of the board/panel design; if the design's lower left-
hand corner is non-orthogonal, the lower left corner of the bounding rectangle becomes the
origin of the balancing pattern).

FabLink XE
Delete Copper Balance Data
The Width value should be less than or equal to the Copper Balancing Distance. The Distance
number should always be greater than the CuBal Width for Hatch patterns, and considerably
larger (as much as a 1:2 ratio) for Shape Patterns. If there is not enough spacing allowed, there is
a potential that the copper balancing added would not achieve the success desired.
The Metal Percentage Formula from Expedition's Hatch Option Dialog box (Route > Planes >
Processor… > Hatch Options For Positive Planes…) is used.
The Fill Non-square Hatch Areas option only applies to line patterns and allows the elimination
of irregular areas within the crosshatch and diagonal crosshatch pattern.
The Restrict Balancing to Orthogonal Patterns option only applies to line patterns and
eliminates arcs and odd angles being generated in the plane metal. If this option is not set,
clearance outlines and hatch lines may contain arcs and odd angles. This option is only available
for horizontal, vertical and horizontal/vertical cross hatch patterns.
The Snap to Hatch Grid option is enabled when the Restrict Plane Data to Orthogonal Patterns
is selected. This snaps all clearance and hatch lines to the hatch grid. A combination of the
board origin or the panel origin and the hatch distance define the hatch grid. This option is
helpful in cases where you want to place plane data on the same grid as the route grid or via
grid. Clearances tend to be larger than the user-defined clearances because the metal is snapping
to grid.
Copper balancing is automatically added to the selected entire layer when the Auto Balance
option is selected and the OK button on the dialog is selected. Selecting the Auto Balance
option automatically uses the Route Border (for a board design), and the Panel Border (for a
panel design). A layer should initially be free of all copper balancing shapes before using this
option. This would eliminate any possible problems created by nesting Copper Balancing
shapes. If a copper balancing shape exists on a layer that is to be auto balanced, informational
dialogs display walking you through the available options.
When the Discard any plane area less than switch is selected, the system will not attempt to
place any Copper balancing data within any clear area of the size defined or smaller. This area
size applies to every layer Copper Balancing is applied.
Delete Copper Balance Data

This option allows you to automatically remove all copper balancing data from every layer of
the board design.
When the Delete copper balancing data by layer is selected, the Plane layer selection field will
contain only those positive plane layers that presently have any copper balancing. This will
automatically remove all copper balancing data from every layer of the panel design.

FabLink XE
Copper Balancing DRC
Figure B-9. Deleting Copper Balancing Data
Within a Panel design, when you select the Delete copper balancing data by layer command, the
Plane layer selection field will contain only those positive plane layers within the panel design
that presently have any copper balancing, and will not remove any copper balancing data of any
board design within the panel design.
You can select any one layer to be deleted in this field, and then either select the Apply button
(which will keep this Dialog box open after all of the copper balancing has been removed from
that layer), or select the OK button, which will close after the copper balancing removal is
completed.
Copper Balancing DRC

Note
Copper balancing DRC checking does not require a FabLink XE license although no
copper balancing data can be modified or deleted without a license.
The copper balancing DRC check is based on the layers selected within the DRC dialog and the
copper balancing clearance specified in the Copper Balancing Processor dialog. Copper
balancing is typically placed on copper layers and therefore should not come into contact with
any copper elements within the manufacturing outline. Copper balancing is checked to any
panel added element within the panel design. If (panel) cells are placed within the FabLink XE
design, the Copper balancing respects the cell to the cell placement outline. Violations are listed
in the hazards list.
The Copper balancing shapes that exist within a board design cannot be altered within the Panel
Editor. If copper balancing is resident within the design file it is checked against all other
copper elements on the defined layer.
Mask Generator
The Mask Generator allows you to create custom masks made of design elements to use for
design verification, plotting, area calculations and documentation. A mask is the result of
applying functions (sizing and or geometric operations) on a group of elements. The result of
the operation can be sent to a specific user-layer and into a user-defined cell.

FabLink XE
PDF
When elements are masked, the elements are copied from the input design file, converted to
shapes and placed in the output design file. Elements are always converted to shapes unless the
Extract operation is used to copy the elements; in this case the elements are not copied. After the
mask is created, it can be reduced or enlarged based on the sizing specified for the mask.
Defined masks can be used in other operations, which allows sequential mask definition.
For instance, some designs may call for Soldermask defined pads, which are Soldermask pads
smaller than their associated pad. Not all padstacks within a design may be defined this way, so
to create a custom paste mask layer, the Mask Generator can be used to combine all of the top-
side pads with the top-side soldermask pads with this Mask.
If you want to process the mask without writing out data, you may leave both the Mask and
User Layer check boxes un-selected. When the fields are correctly defined, select the ADD
button to enter the defined output mask to the list of masks to process in the Mask Listing table.
If changes are made and a previously defined mask is selected, pressing the Add button results
in a modification of the selected mask rather than an addition to the list.
PDF
Customized documents for either a PCB or panel design or drawing file can be generated into
PDF files. The PDF document is generated in sheets; each sheet is a separate page within the
generated PDF document and can contain for a PCB or Panel design a list of selected layers
(signal, plane) with board items, panel / cell items and user-defined layers.
Text from the assembly, drill drawing, silkscreen, soldermask, solderpaste and user-defined
layers is searchable text within the document. An existing PDF setup file (.pcf) can be loaded or
custom parameters can be set and saved to a new PDF setup file. After the parameters have been
defined, you can set the name and location of the generated PDF file.
To display the Output PDF dialog on Linux or Unix, the following environment variable has to
be set or a warning message displays.
PDF_VIEWER=1
The PDFOutput.txt file is created if any errors or warnings are generated and is located in the
jobs ../LogFiles directory.
Current Limitations
The following are the current limitations:
• Mirrored output is not supported

• Netlines and classlines are not displayed
• Different fill patterns and grid display is not supported

FabLink XE
XE Neutral File
• Selected and highlighted items cannot be drawn in the current view

• Viewport is not supported with the current view for Panel Editor PDF Output
• A detailed view of a detailed view is not supported.
The Sheets tab of PDF Output allows you to set the parameters for the generated PDF file on a
PCB or panel design.
Detailed Views in PDF Output

When you click the Detailed View option within the Board list, a Browse dialog appears .
Selecting this, displays a dialog where you can select individual detail views to be output in the
defined PDF file.
detail to create customized documentation details. You can create detailed views from Draw
Properties > Detailed Views.
Caution
Scaled boards and panels appear correctly in the PDF Output for the drawing. However,
if a detail view covers the scaled instances, then it is not displayed properly in PDF. The
problem is that some of the elements in the detailed view scale up while others do not.
XE Neutral File
The XE neutral file is an intermediate file for automated manufacturing. The file is in ASCII
format and designed so you can readily access the PCB data by writing a simple parser.
The XE neutral file (xeneutralFile.txt) provides information about board attributes, component
data, geometries, nets, pads and holes and after generation is located in the jobs ../output
directory. The file can be viewed using File Viewer or any ASCII editor.
Manufacturing Output Validation (MOV)

Note
An FLXE PRO license is required to access the Manufacturing Output Validation option.
Manufacturing Output Validation validates Gerber and NC Drill outputs. This command is used
to validate the manufacturing outputs against the panel design within the design database.
Manufacturing output validation validates manufacturing data of bareboard, assembly and test.
Artwork and drill-related errors can be reviewed using the log file.
You should run manufacturing output validation on a design after the layout has been completed
and the panel design is ready for manufacturing. This should be the last step in the design flow

FabLink XE
when the design is ready to be sent to the manufacturing unit. A log file
(MfgOutputValidation.txt) lists the errors generated in a single run and is created when the
Validate Checked Output files button is checked. This file is overwritten every time this option
is checked.
By default, the first time manufacturing output validation is invoked on a design all generated
files are selected for validation based on the pre-defined paths and extensions files. You may
unselect any files to prevent them being packaged and subject to validation. Personal
information that is printed in the manifest file can be entered. This information displays in a
.hkp file (MovUserDetails.hkp) in the designs ../config directory.
Note
If you select a .gpf file that contains output files that do not exist in the output directory, a
warning message is displayed, listing the missing .gdo files. Also, if the selected Gerber
plot setup file specifies a Gerber Machine Format file that does not exist, a warning
dialog is displayed informing you that the default Gerber Machine format file delivered
with the product will be used.
Gerber (RS274D and RS274X formats) - The D-code files are read from the .gpf file in the
…/config directory. If multiple .gpf files are found, a browse button is available. The D-Code
Mapping file section displays the directory and filename of the mapping file if in 274D format,
and displays Automatic if in 274X format. For the 274D option, area fill percentage errors that
are less than 99% are reported.
NC Drill - This tab displays the NC Drill file with the corresponding .map file. Precision errors
occur when the resolution of the Gerber, defined in the .gpf file, is not adequate to represent the
data as defined in our 0.1nm database. Therefore, if you define your Gerber precision to be 2.5
(one hundred of a th) and you require all database objects to use this precision, the grids within
Expedition PCB should also be defined for all objects to be placed in the database with this
precision. If you are routing without a defined grid, there will be precision errors because the
maximum resolution of the Expedition PCB database far exceeds the maximum resolution
possible for Gerber data.
Pre-Validation Checks
The purpose of pre-validation checks is to do a quick sanity check on the outputs. These checks
are carried out before proceeding for packaging. The pre-validation checks are:
• Layout 'mfg-readiness' check: This is a very basic manufacturing readiness checks:

design is 100% routed and all planes are processed.
• Errors in generation of outputs: This case arises when errors are found in the log files
created by the output generators.

FabLink XE
• Layers: Verifies if outputs for all signal and plane layers have been generated. If you
purposefully generated for some of the layers and not all, you may ignore the generated
warning.
If errors are found in the pre-validation checking, a dialog is displayed and the errors are placed
in validation log file. You can continue or cancel the validation. If you continue after the errors
review, packaging is carried out.
Package Creation
After the pre-validation phase, all the manufacturing outputs, selected for validation are
combined into a package. The name of the package is the design name. Validation is carried out
only on the files in the package. After validation, log and manifest files are also added to the
package. For all platforms (Windows and Linux), packaging format is gtar followed by gzip
utilities. On Windows these utilities are shipped with the installation CDs and on Linux they are
packaged with the OS.
If any errors are found in the packaging stage, a message is displayed. You cannot add new
outputs to the package at a later time once validation is complete. This is done outside of the
tool.
Validation Process
The features of validation are:
• Validation includes the matching of properties of each of design elements. For example,
width is a property of a trace.
• Validation is a detailed element-to-element audit of various outputs against the design
database. For example, each data segment in Gerber output file is checked against the
design database.
• An error is generated if an object appears in the manufacturing data but not within the
design intent or variant inside the database.
• An error is generated if an object exists within the design intent or variant inside the
database, but does not exist within the manufacturing data.
• An error is generated if any parameter/property of an object within the manufacturing
data varies at all with the equivalent object's parameter/property within the design intent
or variant inside the database.
Note
When comparing Gerber elements, the precision used for Gerber generation is as
specified in the .gmf file.

FabLink XE
A progress meter displays indicating the progress of validation with an option for cancellation.
The dialog also shows what is currently being analyzed and displays the number of errors and
warnings for each output category. If you Cancel at this stage, validation ceases and the log file
records that the validation is incomplete. As errors are logged as they were found in validation
process, the log file records them to the extent validation is done and records that the package is
invalid for manufacturing purposes.
Error Processing
Manufacturing output verification with regard to errors found in the validation process is to log
the errors and proceed. At the end of validation, the status of validation is reported in a dialog
and is also recorded clearly in the log file. This file is generated for each validation session.
Precision errors: If any precision errors are found in the validation, they are reported.
Gerber/NCDrill-based errors can be reviewed using View Validation Errors. All other errors are
listed in the log file.
Errors for each output type (Gerber, NCDrill) are further categorized as 'Extra Elements',
'Missing Elements' and 'Property mismatch'. Here the term 'element' refers to artwork element
(in case of Gerber, elements are the segments and flashes).
• Extra Element: Errors pertaining to elements that are found in output but not in layout.
For example, a line segment is found in Gerber output for layer1 that does not have a
matching design element in layout.
• Missing Element: Errors that are missing in outputs compared to layout.
• Property mismatch: Errors where an output element's property is not matching to that in
layout.
Table B-2. Property Mismatch Errors

Gerber The width (D-code) of a segment in output compared to that in
layout.
Drill Contour Contour: direction and width
Drill Holes Hole type (drilled/punched)
Geometry (round/square/slot),
Creation method (planed/non-plated),
Diameter and Via span
The only exception is for drilled slots; a property mismatch of length
is represented in both 'missing element' and 'extra element' error
types. Drilled slots are represented as contour and both contour data
and drilled slots data go to the same output file, therefore, they are not
distinguishable.

FabLink XE
Panel DRC
Panel DRC
Panel Design Rules Checking (DRC) performs specified proximity checks against a matrix of
user-defined elements. Proximity checks the distance between elements placed within the
design based on the custom element to element rule clearances. Online Panel DRC is not
available in this release.
Caution
It is important to check the PanelDRC.txt file after each run of Panel DRC. This file can
be viewed through File Viewer. Panel batch DRC hazards limit is 10,000 for proximity
checks. If this limit is passed, Panel Batch DRC stops before completing verification.
Any time a proximity hazard is found, the Review Hazards command is used to locate the
hazard. Once all these hazards have been fixed within the design, Panel Batch DRC should be
run again to make sure no proximity hazards were created while making changes to the design
and a run of the entire panel should be done prior to creating manufacturing data and/or
documentation.
When Panel DRC finishes, you should review the log file using File Viewer. The log files detail
which checks were performed and any violations that were found.
Setup Parameters
Within FabLink XE, only two tabs of Setup Parameters are available:
General - From this tab you can only set the design units and user-defined layers. The specified
design units will be the default assigned to new cells. The defined user-defined layers can be
used when building a cell to store user-defined data within the cell. The maximum number of
user-layers is 250.
When FabLink XE is invoked, the first design that is added within the panel outline is the
default for the panel and its layer data is loaded into the Number of physical layers field.
Before a second design can be loaded within a panel, the system must perform the following
data checks before allowing the design to be placed:
• The design must have the same number of layers as the template (first design).
• If the second design has unique user layers not found within the first design, these layers
are combined into the user-defined layers field.
• If the second design has used the same user layer as the first, questions are asked
because there may be different data created on each of these layers. After you approve
each layer check (or approve them all globally), the design is added into the panel by the
chosen placement method. If you select No to this dialog box, an information statement
is provided asking you to change the data on the second design.

FabLink XE
Library Services
Layer Stackup - This tab displays the conductive and dielectric materials that make up the
design's layer structure and is for review only.
Library Services
Within FabLink XE, Library Services only allows you to copy, move, and delete cells, and
padstacks.
Layout Templates
The following steps show how to create/copy new panel templates using Layout Templates
from Library Manager.
1. Invoke Setup > Library Manager from within FabLink XE and make sure you are
pointing to the correct Central Library .lmc file.
2. Select the Templates icon.

3. Select any existing Template & use the Copy icon to make a copy.
4. A copy of the selected template is created.

FabLink XE
Padstack Editor
5. Click on the copied template and rename it to 6 Layer, then select the Edit Template
icon. This will put you into graphics on the "6 Layer" template design.
6. Select Setup > Setup Parameters from within FabLink XE and in the "Number of
Physical layers" field, type in the number you want, in this case, 6.
7. Select the Apply button on Setup Parameters and a message appears
The number of physical layers have been modified. You must define
how to remap the current physical layers.
8. Select OK and the Remap Layers dialog appears.
9. Select OK and then exit Setup Parameters.
10. Save and exit out of graphics.
11. Exit the Layer Template dialog.
12. Close the Library Manager.
Padstack Editor
Within FabLink XE, the Padstack Editor only allows you to create three types of padstack;
Fiducial, Shearing Hole, Tooling Hole. The table below describes their relationships:
Table B-3. Padstack Types

Fiducial Shearing Hole Tooling Hole
Pads Yes Yes Yes
Hole N/A Yes Yes
Top Must Optional Optional
Internal N/A Optional Optional
Bottom Must Optional Optional
Plane Clearance N/A Optional Optional
Plane Thermal N/A Optional Optional
Soldermask Top Optional Optional Optional
Soldermask Bottom Optional Optional Optional
Solderpaste Top Optional Optional Optional
Solderpaste Bottom Optional Optional Optional
Cell Editor
The following information regards the changes that occur within Cell Editor when you either
acquire a FabLink XE licence from within Expedition PCB or you have accessed FabLink Be

FabLink XE
Cell Editor
stand-alone. Some of the functionality that is available within Cell Editor without a FabLink XE
license is disabled or not available when using FabLink XE. This is not documented within this
Appendix.
The Panelization functionality requires a number of design elements, placing text, draw
functionality, manufacturing fixture location, drilled holes and test coupons that will use the cell
construct in order to fully comply with the manufacturing process. This methodology also
makes it easier for you to create and reuse these elements from panel to panel.
Elements defined within the Cell Editor for panel cells are placed on the layers defined within
the Display Control dialog. Panel Cells are not available at the board level. Panel cells are
available for placement within a panel design.
Panel obstructs are placed as through board obstructs and restrict panel elements from being
placed in theses areas. Dimensional data, silkscreen information etc. will be placed on standard
user defined layers as displayable from within the Display Control dialog.
Panel Cell Types

Panel cells are only available within a Panel. You cannot place a Panel cell within a design
(*.pcb) only within a panel (*.pnl). If you want to create a duplicate of a panel cell to place
within a design you should recreate it as either a drawing cell or a mechanical cell.
Through Library Manager, panel cells without padstacks can be selected as a template and used
to create PCB drawing cells. This allows the Library Manager to select a panel cell and copy it
to a drawing cell within Expedition PCB. Only specified panel type cells can be utilized as
templates for PCB drawing cells. Panel cells which can be used as templates are:
• Electrical Test Identifier

• Panel Identifier
• Bad Board Identifier
There are a number of different panel cell types. Typically panel cell types consist of draw
elements and text that are placed on outside layers.
Table B-4. Panel Cell Types

Cell Type Allowed Elements Description
General (default) Cell Origin, Contour, Fiducial, Used to as a catch all for other type panel
Padstack, Panel Obstruct, cells
Placement Outline,
Soldermask, Solderpaste, Test
Point Obstruct, Tooling Hole,
Trace (draw object), Via

FabLink XE
Cell Editor

Solder palette Cell Origin, Contour, Tooling Physical devices that attaches to the
Hole, Padstack, Placement panel edge to prevent warpage, typically
Outline, Fiducial, Panel using through holes.
Obstruct, Soldermask,
Solderpaste, Test Point
Obstruct, Text
Sky-hook Cell Origin, Contour, Tooling Physical device to prevent panel
Hole, Padstack, Placement warpage, generally attaches close to the
Outline, Fiducial, Panel center of the panel using through holes
Obstruct, Soldermask, and mechanical restraints.
Obstruct, Text
Electrical test Cell Origin, Contour, Generally a box or shape placed in
identifier Placement Outline, Panel unison with each card or as a matrix for
Obstruct, Soldermask, the entire panel.
Solderpaste,
Test Point Obstruct, Text
Panel identifier Cell Origin, Contour, Identifies the entire panel could be text or
Placement Outline, Panel an area to place a label.
Solderpaste,
Bad board identifier Cell Origin, Contour, Generally a box or shape placed in
Placement Outline, Panel unison with each card or as a matrix for
Obstruct,Soldermask, the entire panel.
Solderpaste,
Test Coupon Cell Origin, Contour, Tooling Series of plated holes/pads and traces and
Hole, Padstack, Placement can include other elements, text, draw
Outline,Fiducial, Panel elements.
Obstruct,
Trace (draw object), Via,
Soldermask, Solderpaste, Test
Point Obstruct, Text
Registration pin Cell Origin, Contour, Tooling Registration pins to align artwork on the
grid Hole, Padstack, Placement panel. Generally a three or four pin grid
Outline, Fiducial, Panel system with offsets. Pins are not
Obstruct,Via, Soldermask, symmetrical to prevent artwork
Solderpaste, Test Point misalignment.
Obstruct, Text

FabLink XE
Cell Editor

Break Away Tab Cell Origin, Contour, Tooling Allows the library manager to create a
Hole, Padstack, Placement Break Away Tab cell to be placed at the
Outline, Fiducial, Panel board or panel level.
Obstruct, Via, Soldermask,
Obstruct, Text
Panel Stiffener Cell Origin, Contour, Tooling Physical device that attaches to the panel
Hole, Padstack, Placement edge using through holes or clamp
Outline, Fiducial, Panel technology to prevent warpage.
Obstruct, Text
Test identifiers
Test identifiers are generally placed in the form of silkscreen but could be placed on any layer
mask, silk, or copper layer. There are at least two types of test identifiers; electrical test
identifier, and bad board identifiers. Test operators can identify a specific card within the panel
that did not pass either test. This is typically done using a paint stick, marker or by drilling the
identifier.
Assembly fixtures
Assembly fixtures can come in different forms, shapes and sizes. For instance panel stiffeners
and sky-hooks are typically attached to the panel palette or other supporting platform. These
cells are drawn to match the fixture outline and placed on the panel prior to placing the cards.
Placing these fixture representations in the panel design prior to placing the cards prevents you
from having to modify the cards on the panel to create room for these fixtures.
Solder palette
Solder palettes are mechanical devices that add stability to the panel while it passes over the
solder wave. The solder palette acts as a carrier for the panel reducing panel warpage and
bowing. These mechanical elements can be created in different forms.
• Entire panel (ring)

• Single edged (typically the leading edge)
• Multiple edges (both ends for instance)

FabLink XE
Cell Editor
Sky-hook
A sky-hook is a device that is used to support the panel, usually at its center, as it moves down
the manufacturing conveyor. Typically these support mechanisms mount across the solder
palette and support the panel from a non-populated area of the panel assembly.
Panel stiffeners
Similar to a solder palette a panel stiffener is a mechanical device that adds stability and reduces
warping and bowing. Panel stiffeners aid wave soldering and other process during
manufacturing. These mechanical elements can be created in different forms, surrounding the
entire panel, or may be single strips on the leading edge of the panel.
Board obstructs
Board obstructs can be used on any panel cell to prevent board objects from being placed within
these defined areas. Obstructs can be placed within any panel cell and are used to prevent
placement violations on the panel.
Pin fixtures
Typically manufacturing houses use a pin system to register artwork on the panel. The pins are
spaced differently and can be different shape to aid in artwork registration. These patterns can
be saved as cells and placed in the panel design at any point of the process. Spacing of these
elements is crucial to the panel process and therefore placed as cells or in some cases defined
within panel templates.
Test coupons
Coupons are typically used on the edges of cards but can also be placed between cards to verify
fabrication processes. Typically coupons consist of pads, vias, traces, and drilled / plated holes.
Other elements, which can be included, are registration marks, silkscreen, and solder mask. Test
coupons are set up to span the number of layers defined in the design, if a design/panel has eight
layers the coupon typically consist of eight layers.
With the advancements in high-speed design, tracking and verifying impedances has become
extremely important. Many manufacturers are creating test coupons to verify etching and plated
copper thickness. This is typically done through cross sectioning coupon and conducting exact
measurements on elements within these cross sections.
A test coupon generally consists of trace elements, pads elements, and drilled plated holes but
can contain a number of other elements depending on what tests the designer deems necessary.
Included may be vias, multiple trace widths, registration marks, text, test points, teardrops, and
additional draw elements.

FabLink XE
Cell Editor
Trace elements
Trace elements as defined in test coupons are typically non-intelligent. Therefore you can
utilize the Plow command within the Cell Editor to place trace element on whichever layer is
active. The trace width would follow the parameters defined within Net Classes and Clearances.
Pad elements
Pad elements are selected through the padstack reference list within the Cell Editor. This allows
you to select any pad within the Padstack Editor to be used as a test coupon pad/hole. These
elements will be specified as net 0.
Place via
Vias can only be placed within the create test coupon panel group. This allows you to place any
type via selected through the placement dialog. All placed vias will be net 0. Vias can be
transferred to the panel design library from the layout design through Library Manager.
Draw elements
Any additional elements can be added to a test coupon such as fiducials, text specific names,
bounding areas etc. Any draw element can be added to test point coupons.
Nested panel cell elements

Panel cell nesting is not allowed.
Break Away Tab

Break Away Tabs provides the manufacture the ability to route or mill slots around the extent of
the design leaving bits of material (tabs), which can be easily broken releasing the card from the
panel.
There are two basic styles of break away tabs: a) tabs that will leave a remainder of board
material beyond the board outline, and b) tabs that will not leave a material beyond the board
outline. Most applications for using this second style are based on the card fitting inside a
mechanical enclosure or card guide. The first method will not guarantee an exact break, where
the second method's break within the board outline ensures that card will fit properly where it is
to be used.
There are two important factors in designing these break away tabs: a) provide an easy way to
separate the card from the panel, and b) provide enough mechanical strength to the panel that
will survive both the total weight of all components on the panel and not allow the panel to
excessively bow or twist as it is being soldered. You should be aware of both these factors when
placing breakaway tabs for both the board design and the panel design. Because of these

FabLink XE
Cell Editor
different needs, you may need to use more than one type of breakaway cell on both the board
and/or panel designs to optimize for these factors.
Although there is no industry-defined standard, the break away patterns that are currently being
used (breaking the cards out of the panel) are designed with a combination of milling and drilled
non-plated through holes.
For break away tabs that will not have panel material remaining beyond the board outline, these
are normally designed with a pattern of one to four drill holes (these are referred to as "mouse
bites", where the diameter of these holes are generally smaller than the milling bit) being
symmetrically placed between where the milling path is centered along one axis.
Mouse bites are typically created using a series of three or four holes patterned in a radius and
usually placed within the board outline. This provides the user with the ability to snap the card
at these locations freeing the card from the panel.
Creating a Panel Cell

You can define a logical panel cell name to be stored in the library. In the case of a test coupon
you can manually add padstacks to define not only pads, but also drilled holes. Tooling holes
are also placed in this manner.
Panel groups which allow pads are:
• Sky-Hook
• Solder palette
• Panel Stiffener
• Test Coupon
• Registration Pin Grid
• General
Panel groups which do not allow padstacks to be placed:
• Electrical Test Identifier

• Panel Identifier
• Bad Board Identifier
• Break Away Tabs

FabLink XE
Panel Cell Outline

While building panel cells the library manager will have the option to place a placement outline
surrounding the panel cell data. If the Library Manager does not place a placement outline, upon
exiting the cell editor a placement outline is placed automatically at the extent of the cell
elements. Not all cells require placement outlines, the required cells are:
• Test Coupons
• Panel Identifiers
• Electrical Test Identifiers
• Bad Board Identifiers
The Manufacturing Outline is available from Edit > Place or the Properties dialog within Draw.
There can only be one manufacturing outline associated to a design. If a new manufacturing
outline is created and a manufacturing outline already exists, the original manufacturing outline
is replaced.
The manufacturing outline can be DRC’d against other designs placed within a panel. However,
since the manufacturing outline is only a required object within FabLink XE Pro or FabLink
XE, it is not DRC’d within Expedition PCB. A new layer (Manufacturing Outline) is found in
the Display Control > General > Board Items field.
There are two methodologies for creating manufacturing outlines:
• When you select the File > Open… command on an existing design within Expedition
PCB, a copy of the design's board outline is automatically created as the manufacturing
outline. A Save is required to save the newly created manufacturing outline.
• If you want to modify the manufacturing outline, use the Draw Properties dialog box,
and then either select the Manufacturing Outline type if a manufacturing outline has not
already been selected in the design.
Export IDF
Within FabLink XE, the Intermediate Data Format (IDF) is a format that includes information
such as the shapes of boards and their components, placement of components on boards, and
various layout and mechanical restrictions such as placement or routing keep-ins and keep-out
areas.
Note
Only IDF Version 3.0 can be exported from the Panel environment.

FabLink XE
Export IDF
On invoking IDF export command, the dialog displays the panel, library and the board files that
are to be generated. Since the panel file contains step and repeat information, only one board file
corresponding to a board design is generated even though there are multiple instances of the
same board design.
The association between the board files and panel file is with the board name. The panel file
contains the board name which is also present in the header of individual board files. All the
board designs placed on the panel are exported into a separate board file. All the components
used in the board design are defined in the library file.
A correspondence does not always exist between the elements found in the panel file and the
IDF file. In cases where an IDF record is necessary but the particular attribute is not found in the
panel file, default settings are used.

Appendix C
ICX Pro HSR
ICX Pro™ HSR (High Speed Routing) options allow you to route high-speed nets to specified
rules such as length and time-of-flight delay as well as parallelism and crosstalk rules. The time-
of-flight and crosstalk calculations are estimations and require no simulation capability. These
physical high speed rules can be applied to electrical nets and physical nets.
Note
If your design / database has used CES for physical rules, that design/database will no
longer be allowed to use the Net Classes and Clearances or Net Properties within
Expedition PCB.
High Speed Routing is controlled by constraints defined in the Constraint Editor System™
dialog. The constraints defined in the Constraint Editor System dialog are checked and the
results of that checking is seen in the Review Hazards dialog.
Licensing
The following licensing summary documents the functionality that is available with each
licensing and environment variable configuration.
1. HSR functionality requires an HS license.

2. CES functionality requires a CES license and the MGC_ENABLE_CES=1 environment
variable.
Note
In the case where a user has used CES on a design and then passes it to another user that
doesn't have access to a CES license or doesn't have the MGC_ENABLE_CES
environment variable set, the user is notified of the situation and any modification of net
class and net property data is prevented.
The MGC_ENABLE_CES environment variable enables "Use CES for constraint entry" in the
netlist tab of the Project Integration dialog, which allows you to kick off CES for the first time.
After CES is started, a keyword is set in the job’s .prj file which controls the display and
functionality within Expedition PCB.

ICX Pro HSR
DxDesigner to Expedition Flow
License Scenario 1
If you have a HS License, CES License, and the MGC_ENABLE_CES variable is set you are
enabled to:
• Access CES.
• Net Properties and Net Classes are disabled.
• The router respects the automatic topologies.
• The router tunes nets.
• HSR-related hazards are available.
License Scenario 2
If you have an HS License, CES License and the MGC_ENABLE_CES variable is NOT
enabled, and you have not already created a CES database:
• Access Net Properties and Net Classes and don't access CES
• You cannot set the new automatic topologies in Net Properties
• You cannot set the new automatic topologies in Netline Manipulation.
• Must use parallelrules.txt file to define better parallelism rules
• Get all new HSR-related hazards
DxDesigner to Expedition Flow

CES is enabled in DxDesigner by opening the Expedition PCB configuration and enabling the
"Constraint in CES" property in the Design Configuration dialog.
The "Constraint in CES" option is visible in the Design Configurations, regardless of the
presence of the MGC_ENABLE_CES environment variable. The DxDesigner flow is the only
flow where the CES option's visibility is not controlled by the MGC_ENABLE_CES
environment variable or CES database availability.
When the Constraint in CES option is enabled, the environment variable is checked. If the
variable is not set, then a warning dialog with the following text will be displayed:
Your machine has not been setup to allow access to CES. If you own a CES license and
want to enable this functionality, define an MGC_ENABLE_CES system environment
variable with a value of 1.
If the variable has been set, then a confirmation dialog will be displayed:

ICX Pro HSR
Enabling CES in Expedition PCB
CES has been chosen as the constraint entry tool for this design. CES is a powerful
constraint entry system that allows you to define constraints that have not been available
in the past and therefore are not backward compatible. Once the CES option has been
enabled in this design, you will not be able to change this option.
We recommend that you create a backup copy of this design for use in the pre-2004.1
software, before proceeding.
Selecting the OK button will enable CES. Cancel will disable the CES option and will
allow you to exit and create a backup copy of this design.
Once enabled and the configuration is saved, this option cannot be disabled.
When CES is enabled, DxDesigner automatically checks whether DxDesigner is configured to

use an ePlanner constraint database and tells the user to choose the CES constraint database.
• Constraint database refers to the .cns file used to drive Smart Attribute Editor. This is set
up through the Project->Settings dialog on the Attributes tab.
When CES is launched, it provides the option to import an existing ePlanner database.
• If ePlanner is launched on a design with a CES constraint database, a warning message

is displayed:
CES has been used to edit constraints for this design. ePlanner should no longer be used
for constraint management on this design or constraint data will be lost. You should use
CES to edit constraints for this design. Continue opening ePlanner, anyway?" Yes or
No. No will cancel the invocation of ePlanner.
Enabling CES in Expedition PCB

When the environment variable is found, the "Use CES for constraint entry" option is available
on the Netlist tab of the Setup > Project Integration Editor dialog. This option is only
available for supported front end types (DxDesigner, Design Architect®, Board Architect™), to
avoid CES being used in other Expedition flows. When this option is enabled, a warning dialog
is displayed stating that you cannot go back, once you select this option. Once this option has
been set and the Project Editor dialog has been accepted, the enable CES option within the
Project Editor is grayed (inactive).
If Expedition is launched on a project with CES disabled but contains a CES database, the user
is warned and the Net Properties and Net Class dialogs will not available because the commands
are gray and inactive.
Cross Project Enabling

If the DxDesigner and Expedition projects (proj and pcb files) are synchronized, enabling CES
on one end will enable it on the other end. Cross Probing between DA/BA, CES and Expedition

ICX Pro HSR
Cross Project Enabling
PCB. Select a constraint in CES and nets and components associated with the constraint in
BSRE and Expedition PCB are highlighted. Select a net or component in BSRE or Expedition
PCB and associated nets in CES are highlighted.
If DxDesigner enables CES in the prj file while Expedition is running this case is not detected.
If the DxDesigner and Expedition projects are not synchronized, forward and back annotation
processes checks CES for inconsistent enabled states.
Forward Annotation
On forward annotation, Expedition checks for the presence of the front-end CES database and if
one is found and CES is not enabled, you receive the following warning message:
The DxDesigner constraints have been entered using CES. CES must be enabled in
Expedition before constraints can be viewed or modified. Enable CES in Expedition
and forward annotate now? "No" will forward annotate without enabling CES." Yes, No
or Cancel.
• If yes, forward annotate runs and the menus are reloaded indicating that CES is
available.
• If no, forward annotation runs and Net Properties and Net Classes and Clearances menu
commands are inactive.
• Cancel stops the forward annotation action.
Back Annotation
On back annotation, the flag is checked in the Expedition .pcb file to determine if CES is
enabled on the back end and if it is enabled on the back end but not the front end, the following
warning message displays:
CES has been used to define constraints in Expedition but CES is not enabled in
DxDesigner. CES must be enabled in DxDesigner before constraints can be viewed or
modified. Enable CES in DxDesigner and back annotate now? "No" will back annotate
without enabling CES." Yes, No or Cancel.
• If yes, back annotate runs and the menus are reload indicating that CES is available.
• If no, back annotation runs.
• Cancel stops the back annotation action.
If it is enabled on the front end but not the back end, the following warning message displays:
CES has been used to define constraints in DxDesigner but CES is not enabled in
Expedition. CES must be enabled in Expedition before constraints can be viewed or

ICX Pro HSR
Design Architect / Board Architect > Expedition
modified. Enable CES in Expedition and back annotate now? "No" will back annotate
without enabling CES." Yes, No or Cancel.
• If yes, back annotate runs and the menus are reload indicating that CES is available.
• If no, back annotation runs and Net Properties and Net Classes menu commands are
inactive.
• Cancel stops the back annotation action.
Design Architect / Board Architect > Expedition

Design Architect and Board Architect will check for the existence of the MGC_ENABLE_CES
environment variable or the existence of the CES database to determine whether the Setup >
Constraints command will be available in the menus. Likewise, the commands that are
currently disabled only when the environment variable is found will also be disabled if a CES
database or the environment variable is found.
If a CES database does not exist, and the Setup > Constraints command is selected, a warning
dialog is displayed:
CES has been chosen as the constraint entry tool for this design. CES is a powerful
constraint entry system that allows you to define constraints that have not been available
in the past and therefore are not backward compatible. Once the CES dialog has been
opened in this design, you will not be able to open this design in pre-2004.1 software.
We recommend that you create a backup copy of this design for use in the pre-2004.1
software, before proceeding.
Selecting the OK button will invoke CES. Cancel will not invoke CES and will allow
you to exit and create a backup copy of this design.
Design Architect and Board Architect will only check locally for the existence of the CES
database. They will not check the back-end directories for the CES database.
Expedition
If the environment variable is set and the design is opened in Expedition before CES has been
specified as the constraint editor, CES will be enabled in the Project Editor dialog as specified
in the DxDesigner > Expedition flow above.
Constraints
The constraints available in the CES dialog are a superset of the constraints available in the Net
Classes and Net Properties dialogs. The following CES constraints are not compatible with a
Net Properties-based flow:

ICX Pro HSR
Target Length / TOF Delay
• Automatic Topologies - T, H-Tree, and Star topologies are not supported in the Net
Properties dialog.
• Pair-Based Differential Pair Constraints - Max Convergence Distance, Convergence
Distance Tolerance and Max Separation Distance can be set on individual differential
pairs in CES and can only be set globally without CES.
• Minimum Net Length or TOF Delay - Identical functionality is not available in Net
Properties. This functionality could be mimicked by using Delay Formulas in Net
Properties.
• Minimum / Maximum / Matched Length or TOF for Pin Pairs - Only available by using
Delay Formulas in Net Properties.
• Parallelism Rules - The parallelism rules must be entered with a text file in the Net
Properties flow.

Constraints entered through formulas are converted to equations. The equations are solved, and
constraints are grouped into clusters that are independent (no shared variables) sets of
inequalities. Each cluster has a set of target wire lengths.
Table C-1. Target Length / TOF Delay Definitions

Constraint Set A set of nets that are related because they share wire segments or
(Formula Set) variables, or are matched together or appear together in formulas.
Formula sets are the mathematical outcome of user - defined length and
TOF delay constraints, and are the formula sets determined by
automatically running the solving/tuning software.
Solver The part of the tuning software that solves all formulas in a constraint set,
arriving at target lengths (or TOF delays) for nets or fromtos.
Target Length The length (or TOF delay) of a particular connection, determined by the
solver, that will (if all the target lengths are met) satisfy all formulas in the
given formula set. The set of target lengths do not represent the only
solution that meets the constraints, but merely the current solution derived
by the formula solver.
When the Target Length/TOF Delay dialog displays it is sensitive to the current selection on the
board, as follows:
• If nothing is selected, or if none of the selected items belongs to a net that has
length/TOF delay constraints, the Target Length dialog opens and displays the
constraint set with the worst (largest) total deviation. This is the same as the current
behavior.

ICX Pro HSR
• If one net is selected, the Target Length dialog displays the constraint set with that net
(even if all of the nets/fromtos in that constraint set are fully satisfied and all targets are
shown in green).
• If more than one net is selected, the Target Length dialog displays the constraint set for
one of the selected nets. This may not be the constraint set with the worst deviation, nor
the constraint set containing the net under the mouse pointer.
Current Restrictions
When the Net Properties, Net Classes and Clearances, Netline Manipulation command, Project
Integration, Setup Parameters, Cell Editor, or Import ASCII dialogs are open, the Target Length
dialog is not available. Cross-probing from the dialog into layout is available, but cross-probing
from layout back into the dialog and cross-probing either to or from the hazards is not allowed.
Any conflicts in the formula set are not detected in this release.
When selected, the Target Length dialog opens on the constraint set with the largest total
deviation. Any changes in routing or in the original constraints are dynamically updated in the
dialog, however when moving traces or plowing, the dialog may take a few seconds to update.
Table C-2. Target Length / TOF Delay Options

Constraint Set Each entry represents a cluster and the displayed value is the sum of
Deviation the absolute values of the errors (the total deviation for this cluster).
The value is the total deviation for this set of from/tos. If two clusters
have the same total deviation, they each have their own entry in the
drop down.
Target The desired length (in the design units of the original constraint) to
satisfy the constraints. Red denotes a placement violation, no solution,
or a fixed or locked from-to. Fixed and/or locked from-to(s) do not
have target lengths and because they cannot be tuned, they appear as
FIXED in the dialog.
Current The actual routed length for this from/to. The Current Length is green
if it is not in violation and black if it is open, fixed, and/or locked. Red
text denotes a routed length that is in violation of the target length. If -
-- displays in this column, the from/to is unrouted.
The color coding makes no distinction between routing that is too
short (in need of tuning) and routing that is too long.
Deviation The deviation is the difference between the target length and the
current length. If (Mixed Units), some of the constraints in the
constraint set are length-based, rendering the constraint set unusable.
If FIXED appears in this column (red text), the from/to is fixed and/or
locked when tuning.
Manhattan Length Manhattan Length (the distance between pins). Red text denotes a
placement violation (a tuning derived value that is longer than the
Manhattan distance between the pins in the current placement).

ICX Pro HSR
Routing Features
Table C-2. Target Length / TOF Delay Options

Meander Meander percentage ((current length / Manhattan length) -1)*100%).
If the from/to is unrouted, (Open) is displayed in this column.
Net Name The name of the selected net.
From Displays the source reference designator pin number.
To Displays the target reference designator pin number.
Observe Editor This checkbox is grayed (disabled) when the Editor Control net filter
Control Net Filter is not active.
The Target Length dialog does not show a constraint set if all of the
nets in that constraint set are not in the filter.
Regardless of whether the Enable Filter checkbox on the Filter tab of
Editor Control is active, if this checkbox is not selected it uses the
second-highest level filtering - from-to formula sets.
When the Editor Control net filter is active and this checkbox is
selected, only the constraint sets that contain at least one net in the
filter are displayed.
Toggling this option switches back and forth between the filtering
modes. However, when the check box is initially unchecked, the last
deviation is still displayed.
Example:
1. Start with list of nets based on a deviation.
2. Check the option to filter two nets and the deviation changes.
3. Uncheck the option (switched off) and the last two nets (the subset
of all the nets) are still displayed.
4. To display the original list of nets, exit and repoen.
Note: Pressing Apply or Ok is necessary on the Editor Control dialog,
but not on the Target Length dialog.
Select Selects the objects within your design that compose the current hazard
being displayed. Click the Apply button, or double-click the from/to,
to perform the graphics option on the selected from/to(s).
Highlight Highlights the objects within your design that compose the current
hazard being displayed.
Fit View Fits the graphic view around the objects within your design that
compose the current hazard being displayed.
Apply Click the Apply button to perform the graphics option on the selected
from/to(s).
Recalculate Targets Applies changes, made in the design, to appear in the dialog.
Routing Features
• Interactive Multi-Plow changes
• Topology Support - Virtual pins and Automatic Topologies

ICX Pro HSR
Hazard Features
• Changes to minimum span, daisy chain or SLT , H-Tree and Star

• Route to TOF Delays and Lengths
• Route to Matched TOF Delays and Lengths
• Route to same and adjacent layer Parallelism Rules and Estimated Crosstalk Rules
• Differential Pair Routing
• Formula Support
Hazard Features
All routing features will have an associated hazard so you can verify that the rules have been
satisfied.
• Parallelism and Estimated Crosstalk Hazard

When a parallelism hazard or estimated crosstalk hazard is displayed, an additional button to
resolve parallelism or crosstalk hazards is available at the bottom of the hazard dialog.
Separating the victim and aggressor nets by adding Spacers between them decreases parallelism
and crosstalk values. The spacers are added when the "Resolve" button is pressed.
Changes to the User Interface

The following changes are made in the User Interface when CES is launched:
• Setup > Constraint Editor (Addition)

• Setup > Net Properties (Unavailable)
• Setup > Net Classes and Clearances (Unavailable)
• Setup > Setup Parameters (Read Only when CES is active)
• Analysis > Summary Reports > Longest to Shortest Net
• Analysis > Summary Reports > Nets over Splits
• Analysis > Summary Reports > Strongest to Weakest Coupling > Report By Parallelism
Factor
• Analysis > Summary Reports > Strongest to Weakest Coupling > Report By Spacing
• Analysis > Target Length/TOF Delay

ICX Pro HSR
Changes to the User Interface

Appendix D
Split and Join a PCB Design
TeamPCB™ allows you to split a PCB design into multiple partitions and have different
designers working on those simultaneously. After the work on the partitions is complete, you
may then join the partitions back into the original design.
Access to the Split, Join and Update from other partitions commands are from the File menu.
The Split and Join commands are only available when editing the original design while using a
TeamPCB license. The Update from other Partitions command is available when you are
editing a split design. The options will not appear on the menu when a TeamPCB license is not
available, or has not been selected on the licensing dialog.
Licensing
You will need a TeamPCB license to Split or Join a design, you will also need a TeamPCB
license to edit each of the partitions. The option of accessing a license while entering Expedition
by selecting the check box on the entry splash screen is also available. By default, the TeamPCB
license checkbox will not be pre-selected, however, if a license was checked in the previous
saved session, it will automatically be checked upon the user re-entering Expedition. If a license
is not available, the license option will not appear in the pre-splash screen.
Figure D-1. Expedition PCB Splash Screen

Converting between Team PCB Reserved Areas and Xtreme PCB Protected Areas
License Restrictions
• A TeamPCB license is required to open partitions.
• A TeamPCB session consumes one of the PCB licenses.
Terminology
Original Design - The design before any splitting or merging has occurred. The partitioned
designs will be created as sub-directories to the original design.
Partition - When the original design is split, multiple partitioned designs directories are created
in a directory called "PCBSplit". Each partition may be edited independently.
Reserved Area - A closed polygon on the TeamPCB user layer that defines the area to be
included for editing in the partition.
Unreserved - When the partitions are created through the Split Design function, an additional
partition will be created called "Unreserved". This partition contains all objects not included
within the reserved areas. Even if the reserved areas completely cover the design, an Unreserved
partition will still be created.
Note
You can not open and edit the Unreserved partition.
Converting between Team PCB Reserved Areas

and Xtreme PCB Protected Areas
When in TeamPCB Draw Mode, a protected area can be selected and its properties can be
changed to a TeamPCB Reserved Area. If protected areas are not converted into TeamPCB
Reserved Areas, TeamPCB ignores them.
When in Xtreme Design Client Draw Mode, a TeamPCB Reserved Area can be selected and its
properties can be changed to an Xtreme Protected Area. The following tables provide mapping
options. If TeamPCB Reserved Areas are not converted into protected areas, they are ignored in
Xtreme Design Sessions and by Xtreme Design Clients.
Table D-1. TeamPCB Reserved Area converted to Xtreme PCB Protected Area
TeamPCB Xtreme Protected Area

Reserved Area
Area Name Handle = Handle of Converter
Layer All Layer (All)

Design Flow
Layer Top Layer number 1

Layer Internal Layer (All)
Layer Bottom Layer number which represents the
bottom
Layer Drafting Layer None.
Placement set to Both
Table D-2. XPA converted to TeamPCB Reserved Area
Xtreme Protected Area TeamPCB Reserved Area

Handle(s) Area Name = First Handle
Layer (All) Layer (All)
Layer number 1 Layer Top
Any internal layer Layer (All)
number
Layer number which Layer Bottom
represents the bottom
Placement option N/A
Design Flow
The high-level design flow for TeamPCB is as follows:

Design Flow
1. Define one or more reserved areas that partition the original design using the Draw >
Properties > Reserved Area option to add a name for each reserved area.
a. The reserved area name must consist of legal characters, which are [a-z], [A-Z], [0-
9], '%', '-', '_', '@', '{', '}', and '!'. Spaces are not allowed.
After the reserved area name has been entered and the shape defined, the reserved
area is labeled with the default location for the name being the upper left corner. The
reserved area name may not be enclosed within the reserved area if irregular shapes
are used, but you can move the name to a more appropriate location after the
reserved area has been created.
b. Draw closed polygons on the Reserved Area layer to define the partitions.
c. You must save the original design before splitting.
2. Access File > Split Design to split the design into multiple partitions according to the
names of the reserved areas.
a. The design will be split into PCB sub-directories in the PCBSplit directory. If a
PCBSplit directory is not present, a new one is created.
b. Each PCB sub-directory will be assigned names corresponding the names of the
reserved areas.
c. In addition, an Unreserved sub-directory is created which you cannot open or edit.
3. Open a split design by selecting File > Open and then browsing to the name of the split
partition that you want to edit. Each partition will allow editing inside the reserved areas
that correspond to that partition name.
a. Multiple partitions will be created through File -> Split Design and different
partitions may be edited simultaneously by different designers.
b. Any objects wholly inside the reserved area associated with the partition will be
editable.
c. Objects outside the reserved area will be locked.
d. Objects crossing the reserved area border will be locked. This includes cells which
have graphics that touch or cross the reserved area boundary.
e. Traces that cross reserved areas will be split at the reserved area boundary.
f. The border of the reserved area will have a visible width equal to the largest trace-to-
anything clearance defined in the Default net class. This provides a visible clue as to
the most common clearance rule and is not DRC'd.
g. During routing, you will be allowed to route up to the center of the reserved area
boundary and also be able to place vias at the center of the reserved area boundary. If
the reserved area boundaries of two partitions coincide, a via placed on the reserved
area boundary can be connected to from either partition.

Design Flow
4. Edit partitions and save information local to split designs.

a. Each partition will have a PCB sub-directory that behaves just like a normal PCB
design with the exception of commands that are disabled for a partitioned design.
Please reference the "Command list for Partitioned Designs" section below.
b. Edits to the partitioned design will be saved local to the split design directory until
the next File - Split design occurs.
c. The information in the split designs can be merged into the main design by executing
File - Join design.
5. Editing a partitioned design will have some restrictions.
a. None of the following items may be added:
• Board objects
• Spares
• Reusable Blocks
b. The following items are allowed, but with restrictions:
• Plow
• Circuit Move & Copy - Only allows the selection of items that completely reside in a
split partition (in reserved area).
• Area Fills - you may add, delete and modify area fills wholly inside your reserved
area.
• Test Points - You may add, delete and modify test points within your area.
• Jumpers - You may add and delete but not modify jumpers within your area.
• Teardrops - You may add, delete and modify teardrops within your area.
• Breakouts - You may add, delete and modify breakouts within your area.
• When in draft mode, only objects completely inside your partition will be updated in
the original design, and/or synchronized with your peers.
c. Selections outside your reserved area while in Draft Mode are discarded.
6. Allow peer-to-peer updates by using File - Update From Other Partitions. This option
displays a dialog that allows your updates to be pulled by the other partitions. Within
this dialog, you may choose to update from specific partitions or (All) partitions.
7. Allow edited partitions to be joined back into the original design by using the File - Join
Design pulldown menu, which replaces the original design.

Creating Reserved Areas
Creating Reserved Areas

In Draw mode, place a Reserved Area draw object. This must be a closed polygon. The
Reserved Areas will represent the areas of the design to be split.
• Any Reserved Area draw object is automatically assigned to the Reserved Area layer.
• The closed polygon may have any number of corners and include arcs.
Note
It is highly recommended that you use 90 degree and 45 degree angles when creating the
reserved areas because we have enabled you to snap traces to the edge of an area when
those angles are used. Any reserved area segments that are not 90 or 45 degree angles will
not snap a trace or via to the edge and therefore you won't be able to pick up the trace and
continue routing in other split partitions.
Each reserved area will have a layer attribute.
• All - By default, the reserved area is assigned to apply to (All) layers. Users may edit
any object wholly enclosed within the reserved area.
• Top - allows placement of parts and routing on only the top layer of the design.
• Bottom - allows placement of parts and routing on only the bottom layer of the design.
• Internal - Allows routing on internal layers.
• Draft - Allows manipulation of elements on draft layers wholly enclosed within reserved
area.
Using guide pins on the edge of reserved areas

Every split design could potentially route to a different layer of the guide pins on the edge of the
reserved areas as these connections to the guide pins do not connect through the layers.
Therefore, the routes in each split design meet at the guide pins on different layers.
These connections must be manually controlled to ensure they are made on the same layer.
Layer restricted guide pins will force the connection between the splits to a specific layer.
Polygons
If two polygons overlap, the smaller will cut into the larger, with the edges coincident.
• The resolved overlapping polygons will not be shown in graphics in the original design;
however each partition will see these polygons in their resolved condition.
• If a polygon exists wholly inside another polygon, it will be ignored.

CES with Team PCB
• A polygon does not have to exist wholly inside the board outline. You may create large
polygons that extend outside the board outline. This makes it easy to partition the design
without worrying about following the contours of the board outline.
• The area will be displayed (in the partition) with a width equal to the largest trace
clearance value for the Default net class.
When adding a reserved area, there is a name attribute that must be used. The name will be
automatically added to the upper left corner of the reserved area.
• The text may include any valid character that is used for a directory name. We
recommend using a consistent method to name the areas
o Designer names
o Functional areas of the board
o Simple numbering
CES with Team PCB

The following tabs are read-only when CES is opened in a split Team PCB design:
• Nets
• Differential Pairs
• Parts
• Parallelism Rules
• Topology Templates
The following tabs in CES are editable:
• Traces & Via Properties

• Clearances
Other Requirements
1. All right mouse button commands are disabled when tree view selections are made. The
menu displays but the commands are disabled.
2. All right mouse button commands except the following are disabled when a cell is
selected in the spreadsheet view:
• Cell Info
• Sort > Ascending, Descending

Net Classes and Net Properties with Team PCB
3. The Assign Nets to Classes toolbar button is always disabled.

4. The following menus are disabled:
• Edit > Define Parallelism Rules
• Edit > Variables
• Data > Update Electrical Nets
5. The Edit > Stackup command opens the stackup editor in read-only mode.
6. Within PCB when CES is active in TeamPCB, the new automatic topologies are
supported.
7. When a Save command is issued in CES, a warning dialog is displayed with the
following message:
Changes made in the Traces & Via Properties and Clearances tabs will not be
reflected in the original design after joining. Continue with save? Yes will save the
changes and leave the CES dialog open. No will cancel the save and leave the CES
dialog open.
8. When an Exit command is issued and the Save Project dialog is invoked, and the Save
Selected or Save All option is selected, a warning dialog is displayed with the following
message:
Changes made in the Traces & Via Properties and Clearances tabs will not be
reflected in the original design after joining. Continue with save? Yes will save the
changes and close the CES dialog. No will cancel the save and close the CES dialog.
Net Classes and Net Properties with Team PCB

The Net Classes and Clearances dialog allows changes to all options and these can be saved and
be available when the Split is re-opened; as long as the split has not been joined to the original
design.
This feature allows you to change trace widths and clearances and route them while in your split
design. When you save the Net Classes and Clearances dialog, a warning is displayed and
informs you that all changes done in the Net Class dialog will not be reflected in the original
design after joining. Net Class and Clearance rules are not merged into the master net class
database.
Caution
It is possible to have design rule violations or trace width violations in the master design,
once the join is done. DRC of the master design catches all of these violations.

Split Design
Net Properties Dialog

The Net Properties dialog displays in read-only mode so you can view but not change the net
property constraints. This prevents you from changing things like maximum length on a net that
you may only control part of in your partition. This also prevents you from changing the Net
Class assignments of nets.
Split Design
You will use this when the original design has the reserved areas defined and is ready to be split
into multiple partitions. This function will split the design into multiple partitions under the
../PCBSplit directory.
Note
At least one reserved area must exist (that wholly or partially exist inside the board
outline) on the Reserved Area layer when executing File - Split design... or this function
will not perform.
The PCBSplit directory will be created in the top level PCB directory (same level as the Layout
directory) and must be overwritten by subsequent operations. A PCB directory (and design) will
be created for each unique name used for the reserved areas on the Reserved Area layer.
Currently, users are not allowed to create multiple reserved areas with the same name.
All data wholly inside the reserved area, associated with the partition will be editable. Any data
that resides outside the reserved area associated with a partition, except for traces that exist both
inside and outside, will not be editable. The data will be locked, as will any data wholly outside
the reserved area. This includes data that does not exist on the same layer as the layer restriction
set (Top, Bottom, Internal, Draft) on the reserved areas.
In most cases, the objects will be selectable so the properties can be viewed, but they cannot be
edited and the Unlock function will be insensitive.
• Traces and vias will not be allowed to be created outside the reserved area.
• Parts cannot be placed outside or touching the reserved area.
• Draw objects that exist outside or touch the reserved area are not selectable.
In the case where data is added that exists partially or wholly outside the reserved area, the data
will be discarded when the design is joined back into the original design.
The following graphic is of a reserved area as viewed in a partition (defined by the yellow box).
Objects inside the area are editable while objects outside are locked, and the via that crosses the
reserved area boundary is also locked.

Join Design
Figure D-2. Partition Bounding Box
Join Design
This function will overwrite the original design and reload the design in graphics. All the
partitions are joined together and the original design is updated. All partitions must be closed
before this function will operate.
If any partition is being edited at this time, an error message appears asking you to close all the
partitions. If an attempt to save an original design occurs and there are one or more PCBSplit
partitions with a time stamp later than the unsaved original design, the saved data in this original
design is lost when you execute the Join Design command.
Note
Internal checks are performed to ensure that the latest version of the split design is used.
Usability
After a join:
• You must re-generate any plane data.

• You must re-generate any silkscreen data.
• It is highly recommended that you run DRC.
• Any Net Class changes made within a partition design will NOT be joined into the main
design.
• Any objects added, deleted or modified outside of the reserved area will NOT be joined
into the main design.
A PCBJoin backup directory is created in the Work directory each time you execute the Join
design function. Up to three backups are maintained. For large designs, this may cause an
excessive amount of disk space to be used.

Partitions
Partitions
If an attempt is made to edit the original design and then you execute File - Join design... from
the pulldown menu, the data in the original design will be lost. If the split design has been edited
and a File - Split design is executed, the edits to the split design will be lost.
While editing a partition design, you may change the Net Class rules; however, these rules will
NOT be joined back into the main design and the main design Net Class rules will not change.
This may cause DRC violations.
While editing a partition design, you can execute DRC functionality. This functionality will
check the entire design. The way to properly use DRC is to define a DRC window and then
DRC only within that window while in a partition design.
While editing a partition design, you may figure out ways to add, delete or modify objects (other
than parts and routes) outside your reserved area. If you do this, the changes will be discarded
when the design is joined back into the main design.
Routing in a Partition
When routing in a partition, there will be three types of netlines:
• Netlines that start and end in your area - these can be completely routed.
• Netlines with one end in your area and the other end in another area or on another
layer - you should route these to the edge of the area or to a predefined location such as
a GP or via. It is important to plow the trace all the way to the center of the reserved area
line representing the reserved area boundary. You can do this by click plowing within
the width of the reserved area line. The program will automatically snap the trace and
overlap the reserved area a little. Once you do this, if the reserved area boundaries are
coincident, the person editing the adjacent reserved area can perform the File - Update
From Other Partitions command and receive the updates and complete the routing in
their reserved area. Alternatively, the main design can be joined and split again to send
the updates to all the partition designs.
• Netlines that do not start or end in the reserved area - you cannot route this unless
someone else routes it to the edge of your area and you perform an Update From Other
Partition or Join and then Split.
Save Function in Partitions

Use File -> Save when editing a partition using TeamPCB. This will save the partition in its
own directory and will not affect the original or any other partition. Also, checkpoint files are
created at the interval defined for that partition.

Update from Other Partitions (Split / Join Design)
Update from Other Partitions (Split / Join Design)

This option is only available when editing a partition. Current edits should be saved before
running this command or all current edits will be lost.
All the reserved area names will be displayed in a dialog allowing you to check which partition
or partitions you want to update from. The option to update from '(All)' partitions is available.
Note
If you want to update the original design with your edits, you must close all split designs,
open the main design and execute the File -> Join design command.
Command List for Partitioned Designs

We will make certain commands insensitive while editing partitions. The following information
defines all the commands and how they will appear while editing a partition.
Table D-3. Command Listing for Partition Designs

In Partitioned Design Command
ON Analysis->Acquire Signal Analyzer License
ON Analysis->Batch DRC
ON Analysis->Crosstalk Waveforms
ON Analysis->Design Library Verification
ON Analysis->DRC Window
ON Analysis->IS_Analyzer
ON Analysis->Release Signal Analyzer License
ON Analysis->Reset Simulation Log
ON Analysis->Review Hazards
ON Analysis->Save Electrical Board Description
ON Analysis->Signal Vision
ON Analysis->Simulate Crosstalk
ON Analysis->Simulate Waveforms
ON Analysis->Simulate
ON Analysis->Summary Reports ->Longest to Shortest Nets
ON Analysis->Summary Reports ->Nets over Splits
ON Analysis->Summary Reports ->Strongest to Weakest
Coupling -> Report by Spacing


ON Analysis->Summary Reports ->Strongest to Weakest
Coupling -> Report by Parallelism Factor
ON Analysis->Summary Reports ->Target Length/TOF Delay
ON Analysis->WaveScope
DISABLED DCode to Aperture
DISABLED ECO->Back Annotation
DISABLED ECO->Forward Annotation
DISABLED ECO->Last Ref Des Used
DISABLED ECO->Renumber Ref Des
DISABLED ECO->ReplaceCell
DISABLED ECO->UpdateCellsandPadstacks
ON Edit->Add to Select Set
ON Edit->Copy to Clipboard
LIMITATIONS Edit->Circuit Move and Copy
ON Edit->Delete
ON Edit->Delete All Traces and Vias
ON Edit->Find
ON Edit->Find Next Open Netline
ON Edit->Fix / Lock / Highlight
DISABLED Edit->Modify->Padstack Processor
DISABLED Edit->Modify->Spare Part Number
ON Edit->Place Action Keys
DISABLED Edit->Place->Board Outline
DISABLED Edit->Place->Conductive Shape
DISABLED Edit->Place->Contour
DISABLED Edit->Place->DRC Window
DISABLED Edit->Place->Drill Origin
DISABLED Edit->Place->Fiducial
DISABLED Edit->Place->Mtg Hole
ON Edit->Place->Part


ON Edit->Place->Placement Obstruct
ON Edit->Place->Plane No Connect Area
ON Edit->Place->Plane Obstruct
ON Edit->Place->Plane Shape
DISABLED Edit->Place->Room
DISABLED Edit->Place->Route Border
ON Edit->Place->Route Obstruct
ON Edit->Place->Rule Area
ON Edit->Place->Test Point Obstruct
ON Edit->Place->Test Point
ON Edit->Place->Via
ON Edit->Properties
ON Edit->Review->Design Status
ON Edit->Review->Hazards
ON Edit->Review->MinDistance
ON Edit->Review->Padstack
ON Edit->Select All
ON Edit->Undo / Redo
ON File->Close
DISABLED File->Edif Netlist Reader
ON File->Exit
DISABLED File->Export->General Interfaces
ON File->FileViewer
DISABLED File->IDF Import Export
DISABLED File->Import->Export ASCII
DISABLED File->Import->Export DXF
DISABLED File->JobWizard
ON File->New
ON File->Open
ON File->Print


ON File->Print Preview
ON File->Print Setup
ON File->Recent Design List
ON File->Save
ON File->Save Copy
DISABLED Help->About Discovery PCB
ON Help->About Expedition PCB
ON Help->Contents
ON Help->Expedition PCB Online Support
DISABLED Help->Library Manager Process Guide
ON Help->Product Support
ON Help->Tip of the Day
DISABLED Library Manager
ON Mode->Draw
DISABLED Output->OBDG Interface
DISABLED Output->Variant Manager
ON Output->Design Status
DISABLED Output->Gerber
DISABLED Output->NC Drill
DISABLED Output->Report Writer
DISABLED Output->Silkscreen Generator
DISABLED Output->Synchronize with Enterprise 3000
ON Place->Align Parts
ON Place->Automatic->Swap by Part Number
DISABLED Place->Automatic->Swap Rotate by Cell Name
ON Place->Copy Circuit
DISABLE Place->Fix / Unfix and Lock / Unlock
ON Place->Group_UnGroup
ON Place->Move Circuit
ON Place->Move Part


ON Place->Place Part and Cells
ON Place->Place Action Key
DISABLED Place->PolarPlace
ON Place->Push Part
ON Place->Rotate Part
ON Place->Snap to Grid
ON Place->Swap Parts
DISABLED Place->Unplace Parts
DISABLED Route->Assign Net Name
ON Route->AutoRoute
ON Route->Breakout Traces
ON Route->Change Width
ON Route->Delete All Traces and Vias
DISABLED Route->Delete Plane Data
ON Route->Interactive->Action Keys
ON Route->Interactive->Copy Trace
ON Route->Interactive->Fanout
ON Route->Interactive->Gloss
ON Route->Interactive->Multiplow
ON Route->Interactive->Plow
ON Route->Interactive->Push Trace
ON Route->Interactive->Reroute
ON Route->Interactive->Route
ON Route->Interactive->Toggle Gloss Mode
ON Route->Interactive->Tune
DISABLED Route->Jumpers->Modify Jumpers
ON Route->Jumpers->Place Jumper
ON Route->Modify Corners
DISABLED Route->Netline Manipulation
DISABLED Route->Planes->Delete Plane Data


ON Route->Planes->Dynamic Area Fills
ON Route->Planes->Plane Shape
DISABLED Route->Planes->Planes Processor
DISABLED Route->Planes->Routed Plane Pins
ON Route->Remove Hangers
DISABLED Route->Swap Gates
DISABLED Route->Swap Pins
ON Route->Teardrops
DISABLED Route->Test Points->Auto Assignment
ON Route->Test Points->Place
DISABLED Setup->Cell Editor
DISABLED Setup->Cross Probe
DISABLED Setup->Design Entry
ON Setup->Editor Control
DISABLED Setup->Gerber Machine Format
DISABLED Setup->IBIS Librarian
DISABLED Setup->Library Manager
DISABLED Setup->Library Services
ON Setup->License Modules
ON - USER BEWARE Setup->Net Class and Clearances
While editing a partitioned design, you may change the Net
Class rules; however, these rules will NOT be merged back
into the original design
ON - READ ONLY Setup->Net Properties
DISABLED Setup->Padstack Editor
DISABLED Setup->Part Editor
DISABLED Setup->Project Integration
ON - READ ONLY Setup->Setup Parameters
ON Setup->Simulator Control
ON Setup->Units Display
ON View->Action Key Bar


ON View->Alternate Mouse Mapping
ON View->Customize Toolbar
ON View->Design Path
ON View->Display Control
ON View->Fit All
ON View->Fit Board
ON View->Fit Selected
ON View->Previous / Next View
ON View->Status Bar
ON View->Toolbars
ON View->XY Readout
ON Window->Cascade
ON Window->New
ON Window->Tile Horizontally
ON Window->Tile Vertically
ON (LIMITED USE) Keyins
ON Snapping
YES Licensing
ON Interactive Selection in Route Mode
DISABLED Virtual Pins
DISABLED Electrical Constraint Manager

Appendix E
Xtreme PCB
Read This Before You Begin

This section provides information that you should be aware of before you start designing with
Xtreme PCB™.
Xtreme Design Session

1. A server may host many Xtreme Design Sessions.
2. If VMWare is running on the client machine, the VM network connections on the
machines must be disabled to allow multiple clients to connect to an Xtreme Design
Session.
3. Multiple servers hosting multiple Xtreme Design Sessions can exist on a network.
4. Xtreme PCB uses port number 4000 for communication between an Xtreme Design
Session and an Xtreme Design Client.
5. An Xtreme Design Session only hosts one database at a time.
6. An Xtreme Design Session can be started on the server through an icon on the desktop.
7. An Xtreme Design Session can be started through a command line.
8. The Xtreme Design Session only runs on the machine where it is installed.
9. The Xtreme Design Session detects the database type and starts PCB without full editor
licenses and with no graphics.
10. The Xtreme Design Session does not consume a client license.
11. The maximum number of clients that can join an Xtreme Design Session is fifteen.
12. The last client that leaves the design ends the Xtreme Design Session.
13. An Xtreme Design Session can be stopped only if there are no Xtreme Client
connections.
14. The Xtreme Design Session must have an access path to the database.
15. The Xtreme Design Session assumes the read/write/executable permissions of the login
used when the Xtreme Design Session is started.
16. Xtreme Design Sessions do not support Auto Routing. Only Interactive Routing
commands can be used within an Xtreme Design Session.

Xtreme PCB
Xtreme Design Client

1. Xtreme Design Client requires an Xtreme Design Session connection license.
2. Xtreme Design Client is also dependent upon a stand-alone editor license.
3. If VMWare is running on the client machine, the VM network connections on the
machines must be disabled to allow multiple clients to connect to an Xtreme Design
Session.
4. Xtreme Design Client can only join an active Xtreme Design Session.
5. The Xtreme Design Client respects the read/write privileges of Xtreme Design Session
database.
6. All Xtreme Design Client editor capabilities joining an Xtreme Design Session must
have the exact same product licensing schemes.
7. An Xtreme Design Client can reside on the same machine as an Xtreme Design Session
or on a different machine than the Xtreme Design Session.
8. Only unique Handles are allowed in an Xtreme Design Session.
Editor Control Dialog Warnings

While every client has full control of the Editor Control options (with some minor exceptions
listed below), the major exception is that clients will not be able to locally save any
modifications to the Editor Control dialog: all client Editor Control default settings come from
the Xtreme Design Session. Client Editor Control changes do not modify the Xtreme Design
Session Editor Controls or those of other clients. However, the results of the Editor Control
changes do affect the design that all clients are sharing and may have negative design impacts
on the clients.
Editor Control Exceptions

1. The Interactive Place/Route DRC option is disabled for all clients.
2. The AutoSave intervals to temp work area option is disabled for all clients but is
controlled through the Xtreme Design Session database. The interval can be changed in
the PCB database using single user mode.
3. The Online DRC Off and Warning options are disabled for all clients.
4. The Clusters and Rooms > Rooms section is disabled for all clients. Place > Room is
still supported, providing the rooms are established in the PCB database through single
user mode.
5. The Gridless pad entry for all pads option is disabled for all clients.
6. The Allow via under pad options are disabled for all clients..

Xtreme PCB
Overview of Xtreme PCB
Overview of Xtreme PCB

Xtreme PCB provides the capability to edit a single PCB design simultaneously, by a group of
designers sharing the design environment. This collaboration considerably reduces the design
time for a complex board.
Note
Xtreme Design Sessions do not support Auto Routing. Only Interactive Routing
commands can be used within an Xtreme Design Session.
At the beginning of a design session, all the clients and the server have the same state, defined
by the design database. The server coordinates the clients so that a shared view of the design is
maintained. Certain aspects of the tool are local to the client: the client name and active display
control are examples of local information, and these can be different for multiple clients.
Clients work on a shared design and it is not necessary to have exclusive areas for successful
operation of the system. The whole board can be completely shared as long as the designers
work in a collaborative manner. The server coordinates the shared transactions such that they
are executed in the same order in all the clients.
The exclusive transactions are also executed in all the clients (broadcast by the server), but not
necessarily in the same order. Two transactions, belonging to the same exclusive area, are
executed in the same order in all the clients. But two transactions belonging to two different
areas are not necessarily executed in the same order across the clients.
Multiple Windows within the Editors

Within Expedition PCB it is possible to open multiple windows into the view. When multiple
windows are displayed, the "X" window control closes the window.
In Xtreme Design Client when only one database window is displayed and the "X" window
control is selected it acts as an exit of the Design Client instead of the default, Close.
Xtreme PCB Elements

Xtreme PCB consists of the following elements:
Xtreme Design A design database loaded onto a central machine that allows one or more
Session (XDS) Xtreme Design Clients to interact with the same design database. Only one
database can be represented in an Xtreme Design Session with a maximum
of fifteen Xtreme Design Clients, however, multiple Xtreme Sessions can
occur on a single central machine. An Xtreme Design Session consumes an
Xtreme Design Session license from the license path provided by the server.

Xtreme PCB
Using CES with Xtreme PCB
Xtreme Design Client An editing environment modified for participating in an Xtreme Design
(XDC) Session. This consumes a standard Editor license (Expedition PCB) with any
specific additional editor licensing options and an Xtreme Design Client
license.
Server A generic term to represent the computer hardware where the Xtreme Design
Session is loaded and executed.
Handle A tag an Xtreme Design Client uses to identify themselves to other clients in
the same session. The default handle is the designer's login. If you choose to
modify your handle while joining an Xtreme Design Session, then that
modification becomes your default handle and is saved with the login. A
handle supports a maximum of sixteen characters, a minimum of one and
supports all ASCII characters supported by the PCB software excluding a
space.
Using CES with Xtreme PCB

When CES is opened in an Xtreme PCB design the dialog is read-only. To gain Write access,
select the Request R/W Access tool button.
Note
Write access is only allowed in one client at a time.
To release Write access, select the Relinquish R/W Access tool button, a message appears
asking to confirm the release of Write access. If one client has Write access and another client
tries to gain Write access, the following message appears;
Figure E-1. CES Warning
When am Exit command is issued in CES by a client, an Xtreme interrupt dialog is displayed.
The client has the ability to change the interrupt time and add a message. When an interrupt is
sent, the other client(s) receive an interrupt request dialog and have the option to either Accept
or Reject the changes.
Note
If there is a potential for an interrupt to be Rejected, rather than choosing Exit, select the
Indicator in the status bar to send the interrupt while keeping the CES dialog open. This
will allow another interrupt to be sent without losing any of the CES data changes.

Xtreme PCB
User Analysis of Xtreme PCB
Figure E-2. PCB CES Change Indicator
Caution
If the client(s) receiving the interrupt has CES open, they will need to close CES before
accepting the interrupt. This is to insure that all data changes are updated in each client.
If the interrupt is Accepted, the changes are passed to the server and updated in each client. If
Rejected, a notice is sent back to the client that the interrupt was rejected and the changes are
not passed.
User Analysis of Xtreme PCB

1. Start of a Design Session
A project file is associated with a design and any member of the design team can initiate
a session by invoking XtremePCB Server. XtremePCB Server validates membership,
identifies the server and launches.
2. Designer joining a session
A designer joins a design session by invoking with an Xtreme Design Client license.
Their handle name is added to the XtremePCB Server and the state of the design is
synchronized with the rest of the designers.
3. Designer retiring from a session
When a designer retires from a design session, their handle is dropped from the
XtremePCB Server.
4. Saving a Design
Any designer can initiate a save of the design. All the clients are synchronized as part of
the save operation.
5. End of a design session
A design session ends when the last client retires. When the Save option is selected on
the Xtreme Design Session Status dialog, the Xtreme Design Session is stopped, the
database released and the Xtreme Design Session license is released.
Session and /or Client Design Crash

If the Xtreme Design Server (XDS) hardware loses power, or the network connection is lost
between the server and the clients, any Xtreme Design Clients (XDCs) connected to the server

Xtreme PCB
Undo and Redo Commands
will receive a message "Lost connection with Xtreme Design Session". If this occurs for two
minutes and occurs for all clients, the Xtreme Design Server is not available. At this point one
client should perform a local save, then the machine hosting the session needs to be checked
out. If the server session is still up and running, there is probably a network problem.
The server session will drop all clients after attempting to contact them for a period of two
minutes. After the end of two minutes, all clients should be released from the session. At this
stage, the design in the session can be saved and or the session can be exited. Once the network
is stable, the clients can re-engage.
If the network connection is lost, the database saved on the client can be used as the master
database with the next session starting from this machine. However, this is just a precaution and
may not be necessary depending on when the last save occurred against the session database. In
most cases, if a client crashes, the Xtreme Design Client can rejoin the server as soon as
possible without loss of data. If the work the client was performing when the crash occurred was
posted back to the session, the session database has the data. If not, that data will be lost. If the
client re-connects within two minutes, they need to use a different handle and will temporarily
consume two licenses (for two minutes).
Undo and Redo Commands

Undo and Redo commands issued by a client affect only database changes made by that user.
Changes made by other users are not affected.
Undo and Redo Can Fail

Because other users are constantly changing the database, the Undo and Redo commands could
cause DRC violations or just be not applicable to the current state of the database. In this case,
Undo and Redo commands will fail, and no database changes are done. Status bar message are
provided to inform that this has happened.
Undo and Redo availability

Every time a Save design operation is performed, Undo and Redo data is erased. This does not
apply to Save View operation. On every design modification (excluding view changes) Redo
data is erased.
Rejecting Commands
If a client issues a command that is rejected by the Xtreme Design Session it could be for the
following example: Force Fields are disabled for the editing session and two clients insert vias
of different nets in the same location. The first client that inserts the via keeps their via, the
second is not able to keep their via as this would cause a DRC error; therefore their command
would be rejected.
When this occurs, the client receives a standard error message with "Rejected by Server!" and
their previous command is undone in their client application.

Xtreme PCB
Interrupts
Interrupts
Several design events affect all connected client's data after the Xtreme Design Session is
initiated.
Figure E-3. Interrupt Dialog
Xtreme Design Session Interrupt Requirements

• Any client can initiate an interrupt
• All clients have the ability to accept or reject the interrupt
• Accepted interrupts freeze all client edits until the interrupt is complete
• Rejected interrupts are global to the Design Session and only require one client to reject
• Rejected interrupts take the initiator back to the completed dialog that triggered the
interrupt and display a message to explain why the Interrupt was rejected
The interrupt process starts after the modifications are made to one of the following dialogs and
the OK or Apply button is clicked:
• Setup > Setup Parameters…

• Setup > Net Classes and Clearances…
• Setup > Net Properties
• Setup > CES
• Planes > Plane Classes and Parameters
• Planes > Plane Assignments

Xtreme PCB
Interrupts
The Interrupt Request dialog appears showing the Session database name, and the list of
machine names and handles that represent all the clients connected to the session.
The initiator of the interrupt has the option of selecting the amount of time (1, 5, or 10 minutes)
for the other clients to accept or reject the interrupt. If a client doesn't accept within the time
limit then the interrupt will be automatically accepted. This is helpful in the case of a client
stepping away from their workstation prior to another client sending an interrupt.
Additionally, the initiator can offer an explanation as to why they need to process a
modification. When the initiator clicks "OK" on one of the dialogs, the interrupt request is
processed and immediately broadcasts an interrupt message dialog to all connected clients with
the request for an interruption.
Rejecting an Interrupt
As all clients receive the following dialog, they have the opportunity to accept or reject the
interrupt request. To accept, they either select "Accept" or do nothing and let the time remaining
expire. To reject, all clients have the option of adding a Courtesy message as to why they are
rejecting the interrupt request, then click "Reject" before the time remaining expires.
Figure E-4. Interrupt Message Dialog
While all connected clients have the opportunity to reject an interrupt request, only one
rejection is accepted and processed ñ the first one received. When the rejecter clicks Reject,
their rejection prevents the modifications from being processed and broadcasts the following
dialog to all connected clients.

Xtreme PCB
Interrupts
Figure E-5. Interrupt Cancel Dialog
When all the clients click "OK", they are returned to their design state before the "Interrupt
request" dialog was issued. The Interrupt requester receives the following dialog and is returned
to the original dialog that caused the interrupt, with all of the modifications still present. They
can choose to "Cancel" the dialog or resubmit the Interrupt Request at a later time.
Figure E-6. Interrupt Not Saved Dialog
Accepting the Interrupt

If the clients approve the interrupt request: they are presented with informational message
dialogs; all client editor options are disabled, and the Session does not receive any message
from the clients. Informational messages may include:
• CES modifications are accepted

• Setup Parameter modifications are accepted
• Xtreme Design Session updated with modifications
• Xtreme Design Clients updated with modifications
• Database Reload in progress
• Reloads complete
When the process is complete, all clients are presented with the following dialog. This dialog is
displayed for 30 seconds and then dismissed either automatically or by selecting OK.
Figure E-7. Interrupt Confirmation Dialog

Xtreme PCB
Client Saves in the Design Environment
Client Saves in the Design Environment

A save of the design can occur at any time if one of the clients issue a File > Save or when the
Xtreme Design Session AutoSave interval is reached.
Note
The default AutoSave intervals for every client is controlled through the Xtreme Design
Session database, this can be modified by taking the PCB database into single user mode.
Whenever a client issues a save, the design freezes for all the other clients until the session save
is completed, the option to adjust the "AutoSave" interval is disabled in the individual clients
working environment and is loaded from the XDS database. When a save occurs, in the lower
left corner of each client’s editor window, the message "Saving database" is displayed.
Starting an Xtreme Design Session

With the Xtreme Design Session (XDS) installed on a server, there are several ways to access
the software:
1. From the Windows Start menu

2. From an icon on the desktop.
Once Xtreme Design Session has started, several events occur:
1. Using the local machine's license path, it is determined whether an Xtreme Design
Session license is available. If a license is not available, an error message is displayed
and after you have selected OK on the error dialog, you are returned back to the desktop.
2. If a license is available, it is secured and the XDS "Splash" dialog is displayed allowing
you to type in the desired data source (with path) or browse for the file.
Figure E-8. Xtreme Design Session Splash Screen

Xtreme PCB
Client Licenses
The database can be on the server or another machine; providing the server machine can view
other machines. The access rights of the user login that is starting the Xtreme Design Session is
applied. The Xtreme Design Session must have read/write privileges to the PCB database
selected. Once the database is selected, a check is made to determine whether the database is
engaged by:
• Another Xtreme Design Session - an error message is displayed.

• The Xtreme Design Client count is below fifteen - The maximum amount of clients that
can join a session is fifteen. If the count is fifteen, an error dialog displays and when the
"OK" button is clicked, you are returned to the previous dialog from where you selected
the database.
• A Single User mode client - an error message is displayed and after clicking "OK" in the
error dialog, you are returned to the previous dialog from where you selected the
database.
• TeamPCB - an error message is displayed and after clicking "OK" in the error dialog,
you are returned to the previous dialog from where you selected the database.
If the database is available, a check is made to determine if the database is Expedition PCB.
Client Licenses
After you have selected Xtreme Design Client as the licensing option, you can navigate to the
PCB database that is engaged in an Xtreme Design session. The client respects the read/write
privileges set for them in the database (The database may have only read privileges for some
user logins). If you only have read privilege logins you will not be able to enter the Xtreme
Design Session and an error message displays. The directory where the *.pcb database file is
located is the where the read/write privileges are set.
If a database that is not engaged in an Xtreme Design Session is selected, an error message
displays and you are returned back to the Open dialog allowing you to select another database.
If a database is selected, then several processes occur and a wait dialog appears until the
following process are checked and completed:
• Number of clients attached to the Session. The maximum amount of clients that can join
a Session is fifteen. If the count is below fifteen, the splash screen appears showing the
license options and allows you to select/create a handle. If the count is fifteen an error
dialog displays and you can use the Open dialog to select another database.
• Whether the database is engaged in a TeamPCB or Single user mode design session. If
the database is engaged in either of TeamPCB or Single User mode, an error dialog
displays and you can use the Open dialog to select another database.

Xtreme PCB
Joining an Xtreme Design Session
• Licensing requirements are checked. If licenses are available they are used. If the
licenses are not available an error dialog displays and you can use the Open dialog to
select another database.
If the database selection is successful: the client Splash dialog is presented; you are presented
with the licensing options and you can either keep or modify the default handle. The default
Handle is the last handle used by this login. If the handle is modified, it is saved with the login.
If Cancel is clicked, the licenses are released, the Xtreme Design Session connection count is
decremented by one, and you can use the Open dialog to select another database. If OK is
selected, the handle is checked for uniqueness. If the handle is not unique, an error message is
displayed and after dismissing the error dialog you can enter another handle.
If errors are encountered, the Xtreme Server Status closes and a standard error dialog displays.
When that dialog is dismissed you are returned to the starting location before the entire Xtreme
Design Client process started. Possible error messages/states are:
• Server is not available (perhaps it crashed or fell off the network)

• The Xtreme Session ended before you Joined.
When all is successful, the editor displays with the database loaded. If the database is
Expedition PCB, a dialog appears displaying the specific editor and the licenses. All Xtreme
Design Clients must obtain the same Editor level license with specified options. This routine
does not obtain a license, but establishes the licenses the Xtreme Design Clients must obtain.
Selecting "Cancel" returns you back to the XDS "Splash" dialog. Selecting "OK" accepts the
Client license requirements for the Xtreme Design Session and opens Expedition PCB. An
Expedition License is not required or needed if the Xtreme Design Client is selected when
Expedition PCB is opened. The Xtreme Design Session covers this license requirement.

An Xtreme Design Session must be started in order for a client to join. The process of joining
occurs through a client in one of two ways:
Expedition PCB Editor Centric Joining

You can double-click a PCB database on the local machine, from the network or from the
desktop to start Expedition with the database loaded. The process flow begins with the designer
starting Expedition PCB. At this point, no database is identified. The Expedition PCB splash
dialog is displayed with available product licenses and the designer selects the desired license
options.

Xtreme PCB
Figure E-9. Xtreme Splash Screen for Expedition PCB
If Xtreme Design Client is selected, all other license options are desensitized.
When the OK button is clicked, you can navigate to the PCB database that is engaged in an
Xtreme Design Session. The client respects the read/write privileges set for them in the database
(The database may have only read privileges for some user logins). If you only have read
privilege logins you will not be able to enter the Xtreme Design Session and an error message
displays. The directory where the *.pcb database file is located is the where the read/write
privileges are set.
If a database that is not engaged in an Xtreme Design Session is selected, an error message
displays and you are returned back to the Open dialog allowing you to select another database.
If a database that is running a design for a product different from Expedition PCB is selected an
error message displays and you are returned back to the Open dialog allowing you to select an
appropriate database. If a database is selected, then several processes occur and a wait dialog
appears until the following process are checked and completed:
• Number of clients attached to the Session. The maximum amount of clients that can join
a Session is fifteen. If the count is below fifteen, the splash screen appears showing the
license options and allows you to select/create a handle. If the count is fifteen an error
dialog displays and you can use the Open dialog to select another database.
• Whether the database is engaged in a TeamPCB or Single user mode design session. If
the database is engaged in either of TeamPCB or Single User mode, an error dialog
displays and you can use the Open dialog to select another database.
• Licensing requirements are checked. If licenses are available they are used. If the
licenses are not available an error dialog displays and you can use the Open dialog to
select another database.

Xtreme PCB
If the database selection is successful: the client Splash dialog displays; you are presented with
the licensing options and you can either keep or modify the default handle. The default Handle
is the last handle used by this login. If the handle is modified, it is saved with the login.
Figure E-10. Client Handle Dialog
If Cancel is clicked, the licenses are released, the Xtreme Design Session connection count is
decremented by one, and you can use the Open dialog to select another database.
If OK is selected, the handle is checked for uniqueness. If the handle is not unique, an error
message is displayed and after dismissing the error dialog you can enter another handle.
A progress dialog displays with dynamic status messages showing the states:
• Receiving private design copy

• Initializing design
• Loading initial design view
• Starting design session
The Client joins the Xtreme Design Session.
If errors are encountered, the Xtreme Server Status closes and a standard error dialog displays.
When that dialog is dismissed you are returned to the starting location before the entire Xtreme
Design Client process started. Possible error messages/states are:
• Server is not available (perhaps it crashed or fell off the network)

• The Xtreme Session ended before you Joined.
When all is successful, the Editor displays with the database loaded.

Xtreme PCB
Ending an Xtreme Client Session
Expedition PCB, Data Centric Joining

You can double-click a PCB database on the local machine, from the network or from the
desktop to start Expedition with the database loaded.
Ending an Xtreme Client Session

The following process flow details how to end a client session from Expedition PCB. The last
client in the session ends the XDS.
Xtreme Design Sessions keep the working database on the server. As individual clients leave
and providing they are not the last to leave, they are not required to save the database. Their
work is already included in the Xtreme Design Session database.
If they are not the last to leave, the following steps occur:
1. The editor closes

2. All editor licenses are released
3. The Xtreme Design Session connection count is reduced by one
4. The Xtreme Design Client license is released
5. The designer returns to their original client joining location.
If the client is the last to leave the design session, the following dialog displays.
Figure E-11. Exit Dialog
1. By selecting Continue, the designer's Client operation ends but the Xtreme Design
Session stays engaged and the number count of clients does not decrement.
2. By selecting End, a Save dialog appears and the design can be saved and the Editor and
Xtreme Design Session closes.
3. By selecting Cancel, the client and session remain running.

Xtreme PCB
Adding Clients to the XDS dialog
After the appropriate save choice is indicated, the appropriate save is made and the following
steps are taken:
• The editor closes

• All editor licenses are released
• The Xtreme Design Session license is released
• Xtreme Design Session specific file(s) are renamed (XDS session count, XDS server
locations, XDS database location, etc.…)
• The Xtreme Design Client license is released
• The designer returns to their original Xtreme Design Client joining location
Adding Clients to the XDS dialog

When a Session has just started, the clients list is empty. Once clients join by opening
Expedition PCB and adding a personal handle, their machines names are added to the list.
Figure E-12. Xtreme Design Client Handle Dialog
The dialog displays which baseline client software is used and the database path and name and
can remain open or be minimized.

Xtreme PCB
Stopping an Xtreme Design Session
Figure E-13. Xtreme Design Clients Dialog
The Save and End Session buttons are desensitized when clients are connected to the Session,
however, when the client list is empty these options are available.
Stopping an Xtreme Design Session

If clients have connected to the Xtreme Design Session, the last client to leave ends the session
and the following dialog is displayed allowing you to select the appropriate option for your
design needs.
Figure E-14. Xtreme Design Session End Dialog
By selecting End, the Client is presented with the Expedition PCB Save Dialog. After making
the appropriate selection, the Client operation ends, the Xtreme Design Session is stopped, the
database released and the Xtreme Design Session license is released.

Xtreme PCB
Force Fields
By selecting Continue, the Client is presented with the Expedition PCB Save Dialog. After
making the appropriate selection, the Client operation ends but the Xtreme Design Session stays
engaged.
By selecting Cancel, the dialog closes and all operations continue.
Force Fields
Xtreme PCB Force Fields provide client priorities as multiple clients attempt to work in the
same area of a PCB during an Xtreme Design Session. They can be turned on or off for the
entire session by a client. When turned off, conflicts are resolved by the DRC of the session,
when turned on, conflicts are avoided.
Force Field Rules

The force field maximum size is established for the session through a system environment
variable for this release. The maximum size is entered in 10th on an inch increments, therefore
.4 inches is represented as 4. The default setting, without the variable is .4 inches. The name of
the variable is XDSMaxFFSize.
Force fields are two-dimensional. The force field is always a circle with the center at the user-
cursor position. They cover a circular area through all layers of PCB and they protect areas
against mouse driven commands. They have no protection against key-in commands from other
clients.
The maximum size is entered in 10th on an inch increments, therefore .4 inches is represented as
4. The default setting, with out the variable is .4 inches. The name of the variable is
XDSMaxFFSize. However, if the system environment variable is used on the machine hosting
the session, then the value entered is used throughout the session and is the same for all users in
the session and is stored with the design.
Force Fields are enabled or disabled for an entire Xtreme Design Session. The control to enable
or disable is available for all clients. If one client clicks Force Fields on, then all other clients
experience the affects of Force Fields. If, however, a different client clicks force fields off, then
all clients work with force fields off. Notification of the force field state is displayed to all
clients in the status bar of the application.
Display Control
The controls to enable or disable force fields are found in the General tab of Display Control.
Figure E-15. Force Field Section of Display Control

Xtreme PCB
Force Fields
This XDC Handle - This allows you to set the color and display for your force fields.
Other XDCs - This allows you to set the color and display for other client’s force fields.
Force Field Conflicts - If force fields are enabled, this is selected by default and any conflicts
are displayed as they appear. Force field conflicts are displayed when the client without priority
in an area has their commands and selections prevented.
Force Field Shape and Size

The force field is always a circle with the center at the user cursor position. The force field size
linearly depends on priority up to the maximal force field size.
The default maximum force field size is .4 inches. However, if the system environment variable
is used on the machine hosting the session, then the value entered is used throughout the session
and is the same for all users in the session and is stored with the design.
Force Field Priority calculations

Each user mouse-activated editing operation has an initial weight, which exponentially decays.
A Force Field Priority is a sum of decayed weights in a circle with the center in the current
mouse position and of Maximal Force Field size. Note, even if the Force Field itself is less than
the maximal size, Maximal Force Field size is always used for priority calculations. The priority
will decay over time.
Example
Edit events (mouse clicks) marked as red dots, numbers are time is minutes since the clicks and
weights used to calculate the priority:
Figure E-16. Force Field Example 1
Priority is the sum of the weight inside a circle of max priority size (blue) 100 + 73 + 90 + 66 =
329, and the resulting smaller force field is shown in green on the right.

Xtreme PCB
Xtreme Protected Areas
Force Field Effects and Conflicts

If your mouse pointer is in another client’s force field and this force field has a higher priority,
your mouse editing operations are blocked. Force field has no effect on key-in command,
dialogs, main menu commands or toolbars.
No matter how the display options are set in the Force Field section of Display Control, if Force
Fields are enabled for the session, when a Force Field Conflict occurs it is displayed as shown
below. The handle (VP) displayed in the center is that of the client that has priority in that area.
The display option "Force Field Conflicts" cannot be turned off when Force Fields are enabled.

Xtreme Protected Areas allow handles associated with the protected areas to enter and move
traces, vias and place components within the boundaries.

Xtreme PCB
Unless a protected area is deleted, it appears the next time the PCB database is used in an
Xtreme Design Session. The handles associated with the xtreme design session also remain;
even if they are not part of the new session. In single user mode or TeamPCB, protected areas
are displayed and can be deleted.
Non-associated handles are prevented from:
• Inserting traces and vias inside or along the boundary of the protected areas.
• Moving traces or vias within the protected areas.
• Moving trace segments and vias connected to trace segments that cross the boundary of
the protected areas.
• Placing of components with the center of a pin on or within the protected area
boundaries.
• Moving components with the center of a pin on or within the protected area boundaries.
• Deleting placement of components with the center of a pin on or within the protected
area boundaries.
Non-associated handles are allowed to:
• Delete traces and vias in the protected areas.

• Delete trace segments and vias connected to trace segments that cross the boundary of
the protected areas.
• Add their handle to the protected areas.
• Change the boundary shape.
• Delete the entire protected areas.
Rules of Protected Areas

• There is no limit to the number of protected areas per Xtreme Design Session database.
• There is no limit to the number of Client handles associated with a protected area.
• Protected areas created by a Client are seen by all Clients engaged in the Xtreme Design
Session, if the display layer is turned on.
• Protected areas use a route obstruct method for preventing trace/ via additions in the
protected area by non-associated handles.
• Protected areas use modified placement obstruct for preventing placement additions and
placement manipulations within the protected area by non-associated handles.

Xtreme PCB
• Protected areas existence, layers, shape outline and included handles can be manipulated
by any client handle in the Xtreme Design Session.
• Protected areas use a "real layer" and not a user-defined layer.
• Protected areas are different than TeamPCB's reserved areas.
• Protected areas can be converted to TeamPCB reserved areas.
• TeamPCB reserved areas can be converted into protected areas.
Behavior of Protected Areas

It is possible to overlap protected areas and in this overlap area, handles must have permissions
to edit or add traces or components.
Protected areas prevent handles, not associated with the protected area, from performing edits
within the boundaries of the protected area. As the non-associated handles attempt to route into
an protected area, for example, using Plow, a message "Plow Failed" appears in the lower right
of their main editor window. If they try to move a trace or via in the protected area, it snaps back
to its original location. For trace segments and vias, connected to a trace segment, which crosses
the boundary of an protected area, they snap back to their original location if they are moved. As
non-associated handles attempt to move or place components in the protected area,
component(s) snap to a location outside the protected area.
To Display Protected Areas

You can display protected areas by selecting the Multiple Designers option in the Display
Control - General tab. The display can be turned on or off for individual clients and a color can
be defined. The representation of the protected area shows all associated handles, which are
located in the upper left corner.
Manipulating Protected Areas

Any client can add, delete or modify the shape of a protected area. However, if the handle
performing the edit is not included in the protected area, a warning message displays stating:
"XPA is owned by another handle."
To Create Protected Areas

1. Select Draw Mode and display the Properties dialog.
2. Select Xtreme Protected Area. The default Handle is the creator's Handle.
3. If required, enter a string of handles to this list with a space as a delimiter. These handles
have the privileges to perform edits in the protected area.

Xtreme PCB
4. Select the appropriate layer(s).

5. All is available for traces and vias. The default for Layer is All.
6. Select the placement.
7. The options are Top, Bottom, Both or None. The default is Both.
8. Select a Vertex Type:
Corner - If this setting is selected, you can place multiple lines without any
modification of the intersections of the lines.
Round - If this setting is selected, as lines are placed the intersection of the lines
become an arc. The arc’s radius is determined by the setting on the Properties dialog.
Chamfer - When this setting is selected, as lines are placed the intersection becomes
a chamfered corner. The chamfer length is determined by a user-setting on the
Properties dialog.
9. To add a vertex to the protected area, select the center handle while pressing the Ctrl
key. If a vertex can be added at this location, it stretches into position as you move the
cursor.
10. Select a vertices to define the polygon. All the fields are editable and if edited the
polygon is automatically updated. You can enter a "d" before a location in order to
change the vertices location by delta. If the vertex is at the start of an arc, the entry has
an "a" to the right of the vertex number. Any changes, made in the graphics, causes the
11. Enter a numerical entry to define the X and Y origin of the polygon. The origin is the
first entered point. You can enter a "d" before a location in order to change the vertices
location by delta.
12. Enter a numerical entry to inflate or deflate the polygon by moving the vertices away
from the centroid by the specified distance. If a number is entered in the field, and the
Enter key is pressed, it grows (if no sign or a +) or shrinks (if a – sign).
13. Select whether to display center handles when the object is selected in the design. If
unset, even though the center handles are not displayed they can still be selected.
14. You may complete a polygon by choosing Close Polygon from the popup menu,
accessed by selecting the right mouse button, or you can double-click the last vertex.
The close function inserts a line segment, (line and arc for round corner) from the
previous click point. If the X and Y origin value is the same as one of the placed points,
this terminates the command, completing the polygon.

Xtreme PCB
Converting between Team PCB Reserved Area and Xtreme PCB Protected Areas
Converting between Team PCB Reserved Area

and Xtreme PCB Protected Areas
When in TeamPCB Draw Mode, a protected area can be selected and its properties can be
changed to a TeamPCB Reserved Area.
When in Xtreme Design Client Draw Mode, a TeamPCB Reserved Area can be selected and its
properties can be changed to an Xtreme Protected Area. The following tables provide mapping
options.
If TeamPCB Reserved Areas are not converted into protected areas, they are ignored in Xtreme
Design Sessions and by Xtreme Design Clients.
If protected areas are not converted into TeamPCB Reserved Areas, TeamPCB ignores them.
Table E-1. TeamPCB Reserved Area converted to Xtreme PCB Protected Area
TeamPCB Reserved Area Xtreme Protected Area
Area Name Handle = Handle of Converter
Layer All Layer (All)
Layer Top Layer number 1
Layer Internal Layer (All)
Layer Bottom Layer number which represents the bottom
Layer Drafting Layer None.
Placement set to Both
Table E-2. XPA converted to Temptable Reserved Area

Xtreme Protected Area TeamPCB Reserved Area
Handle(s) Area Name = First Handle
Layer (All) Layer (All)
Layer number 1 Layer Top
Any internal layer number Layer (All)
Layer number which represents the bottom Layer Bottom
Placement option N/A

Xtreme PCB
Command Listing
Command Listing
The following tables list the commands that are either modified, or not included in Xtreme PCB.
Table E-3. Commands not included

Acquire Signal Analyzer License
Batch DRC
Crosstalk Waveforms
Design Lib Verification
Release Signal Analyzer License
Reset Simulation Log
Save Electrical Board Description
Signal Vision
Simulate Crosstalk
WaveScope
Export ICX
Import ICX
Export to HyperLynx
Export to XTK
DRC Window
Simulate Waveforms
Table E-4. Commands included with modification to support Xtreme Design

Client
Command Comments
Review Hazards The options under Batch list the most recent results
from when Batch DRC was run in single user mode.
Table E-5. ECO commands not included

Back Annotation
Forward Annotation
Last Ref Des Used
Renumber Ref Des
Replace Cell
Update Cells and Padstacks

Xtreme PCB
Command Listing
Table E-6. Edit command not included

Modify > Padstack Processor
Modify > Spare Part Number
Place > Drill Origin
Place > Fiducial
Place > Mtg Hole
Place > Route Border
Modify > Edit Selected Cell
Modify > Edit Selected Cell
Place > Board Outline
Place > DRC Window
Place > Board Origin
Table E-7. Edit Commands included with modification to support Xtreme

Design Client
Command Comments
Add to Select Set > Fixed
Parts
Find Next Open Netline The command skips netlines ending on reserved
(selected by others) pins, vias and traces.
Note: As a result, in some rare cases, the command will
not find open netlines even if they exist in the design.
DRC could be used to find all open connections in the
design.
Place > Room Room/component assignments can only be made in
XDS.
Clients can place rooms but not create room areas
(drafting) nor assign components to rooms (Editor
Control).
Table E-8. File commands not included

Command Comments
Export > General Interface

Xtreme PCB
Command Listing
Table E-8. File commands not included

Command Comments
Import > Edif Netlist Reader
IDF Import/Export
Import/Export ASCII
Import/Export IFF
Import/Export DFX
Job Wizard
New
Split Design
Join Design
Update from other Partitions
Open
Recent Design List Not Displayed
Export > General Interface
Table E-9. File Commands included with modification to support Xtreme

Design Client
Command Comments
Close If only one edit window is open, Close becomes Exit.
Exit Check to see if only Xtreme Design Client in Xtreme Design
Session
Save
Table E-10. Help commands not included

Library Manager Process Guide
Table E-11. Library Manager commands not included

Library Manager

Xtreme PCB
Command Listing
Table E-12. Draw commands not included

Command Comment
Associative Dimension Not Available
Properties > Actual Plane Shape Disabled for XDCs
Properties> Board Outline Disabled for XDCs
Properties> DRC Window Disabled for XDCs
Properties> Drill Drawing (Through) Disabled for XDCs
Properties> Generated Silkscreen Data Disabled for XDCs
Properties> Manufacturing Outline Disabled for XDCs
Properties> Room Disabled for XDCs
Properties> Route Border Disabled for XDCs
Properties> Route Fence Disabled for XDCs
Properties > Tie Leg Disabled for XDCs
Table E-13. Output commands not included

Gerber
NC Drill
Report Writer
Silk Screen Generator
Synchronize with Enterprise 3000
Table E-14. Place commands not included

Automatic > Swap by Part Number
Automatic > Swap Rotate by Cell Name
Copy Circuit
Swap Parts

Xtreme PCB
Command Listing
Table E-15. Place Commands included with modification to support Xtreme

Design Client
Command Comments
Place Part and Cells Lists of places and unplaced parts
will be dynamically updated.
Cross Probe option from
Schematic is disabled.
Table E-16. Route commands not included

AutoRoute
Assign Net Name
Delete All Traces and Vias
Delete Plane Data
Netline Order
Parallelism
Planes > Delete Plane Data
Planes > Planes Processor
Planes > Routed Plane Pins
Swap Gates
Swap Pins
Test Points > Auto Assignment
Table E-17. Route commands included with modification to support Xtreme

Design Client
Interactive > Tune
Table E-18. Setup commands not included

Cell Editor
Cross Probe
Design Entry

Xtreme PCB
Command Listing
Table E-18. Setup commands not included

Dimension Parameters
Gerber Machine Format
IBIS Librarian
License Modules
Library Manager
Library Services
Padstack Editor
Part Editor
Project Integration
Simulator Control
Table E-19. Setup Commands included with modification to support Xtreme

Design Client
Command Comments
Editor Control Disable Rooms from Clusters and Rooms tab. Desensitize
AutoSave Interval settings from General tab.
Net Classes and
Clearances
Net Properties
Setup Parameters
Table E-20. View commands included with modification to support Xtreme

Design Client
Command Comments
Design Path Needs to point to session path
Table E-21. Window commands included without modification

Cascade
New
Tile Horizontally

Xtreme PCB
Command Listing
Table E-21. Window commands included without modification

Tile Vertically
Table E-22. Keyins commands not included

Command Comments
pb Place board outline
pf Place fiducial
pr -dist Place Ref. Des. Distribute Distribute parts outside the board
Table E-23. Keyin commands included with modification to support Xtreme

Design Client
Command Comments
Arrow keys Move part Move part using arrow keys. Including the use of
Shift and Ctrl modifiers.
as Array selected
cw Change width
cwm Change width (modal) Undocumented, maybe for debug only
fj Find jumper XtremePCB action only if used with s (select)
fn Find netname XtremePCB action only if used with s (select)
fnl Find next open netline See comments for Edit/Find Next Open Netline
fp Find pin XtremePCB action only if used with s (select)
fr Find Ref. Des. XtremePCB action only if used with s (select)
ft Find test point XtremePCB action only if used with s (select)
m* Move Move various objects (except mx)
pd Place draw object Arc, circle, line, polygon, polyline, rectangle and
text
pj Place jumper Except for "pr dist" distribute parts outside the
board
pr Place Ref. Des.
pt Place Testpoint
pv Place Via
r* Rotate Rotate various objects (including r)

Xtreme PCB
Command Listing
Table E-24. Keyin commands included without modification

Command Comments
? Help Same as help
<coord> - Place coord Same as pc
cl Change Layer
dumpenv Dump Env. Undocumented, maybe for debug only
dx Delete snap point
fa Find all Same as za
fb Find board Same as zb
fc Find coord Same as zc
fh Find highlighted Same as zh
fs Find selected Same as zs
help Help Same as ?
h* Highlight Highlight various objects (except help)
mx Move snap point
of Turn of Turn off display (various modes)
on Turn on Turn on display (various modes)
pc Place coord
px Place snap point
u* Unhighlight Unhighlight various objects
xe Execute Env. Undocumented, maybe for debug only
xf Execute File Execute keyin commands from a file.
Undocumented, maybe for debug only
xe Execute Menu Item Undocumented, maybe for debug only
z* Zoom Zoom to various objects

Appendix F
Xtreme Auto Router
The Appendix provides information on how to distribute the auto routing of a PCB by
connecting multiple machines to a host machine and then using the CPUs on the client machines
to assist in generating faster routing results using existing hardware. Faster results may lead you
to try different routing options in order to find the optimum routing strategy.
XtremeAR works on existing hardware; provided that the hardware meets the baseline
requirements. Without purchasing additional hardware, you can accelerate the routing of a
board using the Xtreme Auto Router.
Environment Variables (Optional)

The following environment variables are optional when using XtremeAR:
1. MGC_CPI_FILE - Displays the available speed of the Client computer on the

XtremeAR Client Manager Dialog under the Performance Info column. The higher the
value, the faster the client machine. For example on a 3.2GHz machine with 2GB RAM
a score of 2784 is displayed.
You need to point to a file where the data is to be stored. For example:
MGC_CPI_FILE=c:\cpi.dat
and then run Cpi.exe (or Cpi on Unix). You only need to run this executable once to
populate the cpi.dat file.
2. E_RecordOn - When entered, it turns on recording for all clients at server startup.
3. MGC_XDC_DESIGN_PATH - The path to the design’s *.pcb file.
Xtreme Design Session License

The Xtreme Design Session™ is a standalone product that must be licensed and installed on a
capable machine. The license name is "xtremedsession" and is included in the mgc.pkginfo
v3.0_7.0v or greater. This is a floating license; node locked licenses are not offered.
Only one Xtreme Design Session can be run per license and host one PCB database. An XDS
license can accommodate up to 15 Xtreme Design Clients. For Xtreme Design Session and
Xtreme Design Client™, one login on a machine will only allow one occurrence of XDS or
XDC instance per applicable license. The Xtreme Design Session can run on a Server machine
or a Client machine, which may also host an Xtreme Design Client.

Xtreme Auto Router
Xtreme Design Clients

The Xtreme Design Client requires its own license to run. The license name is "xtremedclient"
and is available in the mgc.pkginfo v3.0_7.0v or greater. This is offered in both floating license
and node locked licenses. The Xtreme Design Clients requires separately licensed Baseline
Editors. The Xtreme Design Session will indicate which editor licenses and options are required
for the XDC to join the XDS. The XDC must be able to obtain these licenses or it will not be
able to join the session.
Because the Xtreme Design Session has a limit of 15 XDCs per session, as each XDC joins a
session, the XDS will increment the count of total XDCs in a session - limiting it to a maximum
of 15. Once an XDC leaves a session, the connection count will be decremented.
To summarize; the XDC needs the appropriate Baseline Editor license with option(s) and an
Xtreme Design Client License with an available connection to the Xtreme Design Session. The
Xtreme Design Session will offer a maximum of 15 connections.
For XDS and XDC, one login on a machine will only allow one occurrence of XDS or XDC
instance per applicable license.
XtremeAR Editor Licenses

XtremeAR requires one XDS and an XDC license for each client. Additionally, core editor
licenses are needed for each client. The options are Expedition Pinnacle or Board Station RE
AutoRoute - one for each client. If XtremeAR host is started in either Pinnacle or Board Station
RE, those licenses are released as the XtremeAR starts. When XtremeAR is complete, the
Pinnacle or Board Station RE licenses are re-acquired on the XtremeAR host. If the license is
not available, the option to save the database or not is made. Once done, the host exits.
XtremeSvc
A service is installed and can be run on all clients and session hosts to identify and manage
XtremeAR clients. The XtremeSVC service is installed, by default, with Expedition Pinnacle.
Xtreme Design Browser

The Xtreme Design Browser requires an XDC license to run.
Requirements
1. The host requires an Xtreme Design Session License
2. Clients require an Xtreme Design Client License and AutoRoute Product License.
3. Clients do not need to be dedicated machines

Xtreme Auto Router
4. Clients can exist throughout a customers network domain

5. Client Resource allocation occurs, by default, through manual selection of clients
provided in a list created by an administrator.
6. XtremeAR (XAR) runs on existing hardware and is designed to run against server farms
or Blade Servers on 4 way, 8 way and 16 way servers with plug in processor kits. Each
processor must have its own dedicated memory space.
7. Multiple servers hosting multiple XtremeARs can exist on a Network.
8. An XtremeAR can be started through a command line.
9. The same XtremeAR executable works with Expedition and RE databases.
10. The Xtreme Design Clients must have TCP/IP access to the Xtreme Design Session
host.
11. The XtremeAR assumes the read/write/executable permissions of the login used when
the XtremeAR is started.
12. Clients may run other applications while participating as an XtremeAR client.
13. All clients and host must run the same XtremeAR version of software.

Xtreme Auto Router
Terminology
Client Generic term to represent the computer hardware when the
XtremeAR clients are loaded and executed.
Grid Computing Enable the sharing, selection and aggregation of a wide variety of
geographically distributed computational resources and presents
them as a single, unified resource for solving large-scale compute
and data intensive computing applications.
Computer This is installed by default in Expedition PCB and Xtreme Design
Performance Index Session and is run with the install’s configurator. The CPI provides a
(CPI) system performance number used by XtremeAR to understand the
capability of the Client. The value is retained as a system
environment variable: MGC_CPI_FILE.
Host Generic term to represent the computer hardware where the
XtremeAR is started on the PCB design.
MME Multiple Machine Execution. Applied to XtremeAR where one
designer executes an Auto Route on multiple machines.
SME Single Machine Execution for the Auto Router.
SUM Xtreme PCB Single User Mode of Auto Active Editor for Expedition
PCB.
XtremeAR Using Xtreme Technology as a baseline, auto routing can become a
distributed process. The same routing algorithms that exist for Single
User Mode (SUM) and Xtreme Messaging are available for the
design and use one or more Client CPUs on different or same
machines to converge towards 100% routing.
The benefit is faster routing results using existing hardware and
faster results allow you to try different routing options to find the
optimum route strategy.
XtremeAR Agent The XtremeSvc is run on every computer that participates in an
XtremeAR. Its purpose is to monitor client performance, availability,
etc.
Xtreme Design This is a Read-only Xtreme Messaging enabled version of the PCB
Browser Browser. There are no license requirements for the PCB Browser
product but to use it with XtremeAR, an Xtreme Design Client
license is required. Using Xtreme Design Browser allows you to
watch the routing results as they occur from a remote machine.
Xtreme Design Client An editing environment modified for participating in an XDS. Based
(XDC) on the standalone version of the editor with some capability added
and some capabilities removed. This consumes a standard Editor
license with any required options and an Xtreme Design Client
license.

Xtreme Auto Router
Xtreme Design A design database loaded onto a central machine that allows one or
Session (XDS) more Xtreme Design Clients to interact with the same design
database. Multiple Xtreme Sessions can occur on a single central
machine. Only one database can be represented in an XDS and up to
15 Xtreme Design Clients can connect to an XDS. An Xtreme
Design Session consumes an Xtreme Design Session license from
the license path provided by the server.
Xtreme Logging This captures and logs infrastructure performance data for
XtremeAR sessions. This is included, installed and started with the
Xtreme Design Session.
Xtreme Messaging A term used to describe the messaging between hosts and clients.
XtremePCB XtremePCB consists of an Xtreme Design Session (XDS) that
manages the original design and synchronization of all client edits
and one or more Xtreme Design Clients (XDC). Up to 15 Xtreme
Design Clients can connect via a LAN or WAN to an Xtreme Design
Session.
XtremeSvc This is run on every computer that participates in an XtremeAR. Its
purpose is to monitor client status, availability and present this
information back to the XtremeAR host.
Xtreme Design A design database loaded onto a central machine that allows one or
Session (XDS) more Xtreme Design Clients to interact with the same design
database. Multiple Xtreme Sessions can occur on a single central
machine. Only one database can be represented in an XDS and up to
15 Xtreme Design Clients can connect to an XDS. An Xtreme
Design Session consumes an Xtreme Design Session license from
the license path provided by the server.
Xtreme Logging This captures and logs infrastructure performance data for
XtremeAR sessions. This is included, installed and started with the
Xtreme Design Session.
Xtreme Messaging A term used to describe the messaging between hosts and clients.
XtremePCB Xtreme PCB is a revolutionary new technology that enables multiple
PCB designs to work on a single design database simultaneously.
Unlike traditional team design methodologies that employ a split-
and-join approach to design collaboration, Xtreme requires no
physical partitioning and every designer sees all other client edits in
real time. XtremePCB consists of an Xtreme Design Session (XDS)
that manages the original design and synchronization of all client
edits and one or more Xtreme Design Clients (XDC). Up to 15
Xtreme Design Clients can connect via a LAN or WAN to an Xtreme
Design Session.
XtremeSvc This is run on every computer that participates in an XtremeAR. Its
purpose is to monitor client status, availability and present this
information back to the XtremeAR host.

Xtreme Auto Router
Setting up the System Service on Windows
Setting up the System Service on Windows

The machines that are to run XtremeAR can be pre-setup so they run XtremeAR as a system
service. XAR runs in the background on the client machines, suppressing any Expedition
windows or popups; this allows XtremeAR to be automatically run when each machine starts up
or a designated user-account logs in.
Tip: Additional information on the XtremeSvc.exe file displays in the console window, if
you run it without any parameters.
1. The XtremeSVC.exe file is used to setup the system service. It is located in the
%SDD_HOME%\common\<platform>\_bin\ directory. The location of the Expedition
PCB executable is in the %SDD_HOME%\common\<platform>\bin directory.
2. To manually install the system service, you can use a script with the following command
line arguments:
%SDD_HOME%\common\%SDD_PLATFORM%\_bin\XtremeSvc.exe -svcinst
-exe2 %SDD_HOME%\%SDD_WG%\%SDD_PLATFORM%\bin\ExpeditionPCB.exe -exe11
%SDD_HOME%\%SDD_WG%\%SDD_PLATFORM%\bin\ExpeditionPCB.exe
or to specify the master machine:

%SDD_HOME%\common\%SDD_PLATFORM%\_bin\XtremeSvc.exe <master machine name>
-svcinst -exe2 %SDD_HOME%\%SDD_WG%\%SDD_PLATFORM%\bin\ExpeditionPCB.exe
-exe11 %SDD_HOME%\%SDD_WG%\%SDD_PLATFORM%\bin\ExpeditionPCB.exe
3. Select the Control Panel > Administrative Tools > Services and select the service named
XtremeSvc.
4. Click the right mouse button and select Properties.
5. On the Properties > General Tab, select how you want to start the service. Automatic
starts the service at computer startup.
6. On Properties > Log on Tab, select that the service be run as Local System.
Caution
The environment specified should be configured to be able to run Expedition PCB; there
should be a path to all required DLLs. If a network drive is specified, make sure that the
drive exists and is on the network.
7. Restart the computer(s).

8. Start Service.

Xtreme Auto Router
XAR Batch File Start Service
XAR Batch File Start Service

You can create a batch file that can be used to start the Xtreme Service on the Server. For
example, if you named the .bat filename XARServerXtrSVC.bat, it would include the following
path:
%SDDHOME%\common\win32\_bin\XtremeSvc.exe
%SDDHOME%\wg\win32\bin\ExpeditionPCB.exe
To start the sevice on a Client machine, you need to get the hostname for the Server host. To do
this:
1. Open a command window and type at the system prompt:

hostname
2. If the hostname is abcd, modify the XARServerXtrSVC.bat file to include it:

%SDDHOME%\common\win32\_bin\XtremeSvc.exe abcd -exe2
%SDDHOME%\wg\win32\bin\ExpeditionPCB.exe
1. Save the .bat file
To uninstall system service

You must use the following method to remove a system service. Type the following in a
command window:
%SDD_HOME%\common\<platform>\_bin\XtremeSvc.exe -svcrem
Requirement: Make sure the Administrator Tools > Service dialog is not displayed (open)
while performing this task as you can lock the XtremeSvc service and prevent further installs.
XtremeAR Command Line Invocation

To be able to start XtremeDesignSession it is necessary to specify the full path to the
XtremeSvc using the following parameter:
-exe22 <path to XDS>
To be able to start XDS, and XDC for Expedition and Board Station it is necessary to provide
three paths:
XtremeSvc -exe22 <path to XDS exe> -exe2 <path to XDC Expedition> -exe11
<path to XDC BoardStation>
From a command prompt, enter the following command to start XtremeAR Host:

Xtreme Auto Router
Basic Client Allocation
ExpeditionPCB.exe -xar:scheme_name[,save] -xhosts <hosts_filename>

design_path
• scheme_name - Either the name of a local scheme or the full path to user scheme.
• save - Saves the design on exit. If not used, XtremeAR exits without saving.
• hosts_filename - The path to a text file that contain the list of computers used to start the
agents. XtremeSvc.exe is should be started on all those computers.
• design_path is a path to design *.pcb file.
Other parameters that Expedition can accept are allowed.
Example
ExpeditionPCB.exe -xar:debug -xhosts
H:\XtremeAR\borg\Release_Quantify\hosts.txt H:\Designs\burke\template.pcb
The file “H:\XtremeAR\borg\Release_Quantify\hosts.txt” contains the list of the host machines.
Basic Client Allocation

An ASCII file is distributed to each XtremeAR host. This file contains a list of XtremeAR
Clients which have the appropriate system resources and software to perform the duties of an
XtremeAR Client. When a designer "Allocates" clients, the list of clients which populates the
dialog comes from this ASCII file.
XAR Recording & Playback

XAR recording/playback works both for server and client side. Recording can be turned on/off
for server and clients separately.
Server
For the server it is turned on by specifying a command line parameter -xr <filename> or -xr auto
If a filename is specified the recording is created into this file. If "auto" is specified instead of a
filename, the recorded file is created in the Work/XtremeAR subdirectory of design root. If
session name is specified with the parameter -xname <session_name> , recorded filename is put
into the <session_name> subdirectory inside Work/XtremeAR.
To replay a server run ExpeditionPCB.exe with parameter -xp <filename> open design, select
the same scheme used for recording and start XAR as usually with "XtremeAR" button. No
XtremeSvc is required to replay server and client.

Xtreme Auto Router
Process Flow
Client
As the client is managed from the server, the record and playback is slightly different. The
Record On checkbox in the XarClientManager dialog is visible only if the E_RecordOn
environment variable is defined. While this checkbox is turned on, all clients starting with
recording are enabled and the recording file displays on the remote machine from where the
client started.
It is located in the sub-directory of the root directory where the private design copy is created
for client (use the MGC_XDC_DESIGN_PATH environment variable or temp dir if not
defined). Under the XtremeAR sub-directory another directory is created; <session_name> if it
is specified during server startup or with name = session_id (16 bytes hex value) if session
name is not specified. All files created in this directory follow this format, where <pid> is the
process id of client:
cli_<host>_<pid>.rec where <host> - hostname
The difference from server playback is that the client playback does not require the original
design used to start server; everything necessary (including initial design copy) to replay the
client is located in this single file.
To replay the client run:
ExpeditionPCB.exe -xagent -xp <filename>
To automatically turn on recording for all clients at server startup, specify the command line
parameter:
-xar_agentrec
This parameter is useful for command-line startup. and is equivalent to starting XAR manually
and checking the Record On checkbox before starting any client. This recording/playback is
implemented so that it can record all network messages being sent from and to the process
(client or server) and during playback, it can emulate receiving messages but loading them from
the file.
Process Flow
Selecting Client Machines
1. Choose the machine(s) you want to be the client(s).
2. On the client machines, check you have a valid version of the software.
Note
This has to be the same version that the host machine is using.

Xtreme Auto Router
Starting XtremeAR
Starting the Xtreme Service

XtremeSvc can also be started on each individual machine using a shell script or .bat file.
If an XtremeAR route is attempted without an XtremeSvc started, an error message is displayed

with the message: "Failed to connect XtremeSvc service. It should be either started or
restarted.”
Note
The Xtreme Service must be running for the XtremeAR functionality to run.
1. Open a Korn shell and type the following. The XtremeSvc.bat script is located in the
$SDD_HOME\common\<platform>\bin directory. For the host or master machine, you
can simply double-click the .bat file or run it in a Korn Shell. For a client machine, you
must supply the name of the master machine, as shown in the documentation below.
./XtremeSvc.bat master machine name
The korn shell displays, “XtremeSvc service has started. To stop the service, type
‘exit’”, and the Xtreme Design service starts on the client machine.
Accessing the Xtreme Design Session License

1. On the host machine, select Setup > Licensed Modules > Acquire Xtreme Design
session.
Restriction: Only 15 Xtreme Design session license are available. If >15 licenses are in
use, a warning message appears. If > 15 licenses are in use, a license is consumed and
the XAR button on the Route > Auto Route dialog displays.
Starting XtremeAR
1. Display the Route > Auto Route dialog and select the XtremeAR button. If the Xtreme
Design Session license is included, this "XtremeAR" button is active. Without the
Xtreme Design Session license the button is inactive. The Xtreme AR Client Manager
dialog displays.
Note
At least one route pass must be enabled or a warning dialog displays.
The following "Pass Types" are not distributed to XtremeAR clients - they are run only
on the XtremeAR host:
• Smooth
• Expand

Xtreme Auto Router
Dual and Hyperthreaded Processors
• Spread
• Remove Hangers
• Tune Crosstalk
• Fanouts

The ALH-XNXP-DT client (displayed in the figure below) displays as a hyperthreaded
processor [4 x 3198MHz] and since each processor is hyperthreaded, it is interpreted as 4
processors, even though officially it is not. You could still run four clients, but there would be
performance issues. If it were a dual processor, [2 x 3189MHz] would display and you could
safely run two clients from that machine and anticipate equal performance between them.
Figure F-1. XtremeAR Initial Dialog
Table F-1. XtremeAR Client Manager Definition

Sections Description
Database Displays the path and name of the PCB design.
Xtreme Design Clients / TCP port Displays the name of the host machine and a list of the
XtremeAR clients running the Xtreme Service.
OS / Type Displays the operating system of the machine.
Performance info / Activity CPI - Computer Performance Index, CPU Status,
Clock Rate, Total and Available RAM
Actions Log Empty

Xtreme Auto Router
Table F-1. XtremeAR Client Manager Definition

Log Record Details Empty
Start client Starts the selected client(s).
Stop client Disabled
Kill client Disabled
Cancel Cancels the dialog.
OK Disabled
Record This option is visible if the E_RecordOn
environment variable is defined. When checked, it
turns on recording for all clients at server startup. The
file that is produced is stored in the sub-directory of
the root directory on the remote machine from where
the client was started.
1. Select the client(s) by using either Shift +left mouse button and or Ctrl + left mouse
button.
2. Select the Start Client button. On each client, Expedition PCB launches. The client
displays of Expedition PCB should be ignored.
Figure F-2. XtremeAR Client Manager Start Client

Xtreme Auto Router
Table F-2. XtremeAR Start Client Definitions
Database Displays the path and name of the PCB design.
Xtreme Design Displays the name of the host machine and a list of the XtremeAR
Clients / TCP port clients running the Xtreme Service. The sub row for each selected client
displays the process ID and the TCP port.
It is possible for an Xtreme Design Client to host more than one Agent.
An individual Process/TCP port exists for each XtremAR Agent under
the same XtremeAR Client.
OS / Type Displays the operating system of the machine. The sub row for each
selected client displays the Type: XtremeAR Agent.
Performance info / First Column:
Activity CPI - Computer Performance Index
CPU Status
Clock Rate
Total and Available RAM
Activity Sub Row:
Available - Computer is available and ready to run an XtremeAR client.
Starting - XtremeAR client is starting on the selected computer.
Idle - Client computer is ready to start routing.
Active - XtremeAR client is active on the selected computer.
Closing - XtremeAR client is exiting on this computer. XtremeAR client
is switched to this state when the designer has asked to stop the
computer.
Terminating - XtremeAR client is terminating on the computer.
Busy - Computer is busy with another XtremeAR route or Xtreme PCB.
Actions Log Displays different types of messages; informational and errors. You can
click on one of the displayed messages and its details are displayed in
the Log Record Details field.
Events that may produce errors are:
Client machine is not available (either down or too busy to respond).

The client license is not available.
Log Record Details of selected actions display in this field.
Details
Start client Starts the selected client(s).
Stop client Disabled
Kill client Disabled
Cancel Cancels the dialog.

Xtreme Auto Router
Re-displaying XtremeAR
OK When the XtremeAR clients are loaded and ready to route this button
becomes active. When pressed, the XtremeAR route starts and you are
returned to the Auto Route dialog.
Not all XtremeAR clients need to have their data loaded before this
button is active.
Record This option is visible if the E_RecordOn environment variable is
defined. When checked, it turns on recording for all clients at server
startup. The file that is produced is stored in the sub-directory of the root
directory on the remote machine from where the client was started.
Re-displaying XtremeAR
When the OK button is selected on the XtremeAR dialog, it dismisses and you are returned to
the Auto Route dialog. An additional button is displayed that allows you to re-invoke the Client
Manager.
Figure F-3. Re-Display XtremeAR Client Manager Icon
When the XtremeAR Client Manager re-displays, the Performance Info/Activity column for the
selected client machines displays the status of the route.
Figure F-4. XtremeAR Route Status

Xtreme Auto Router
Controlling the XtremeAR Session
Controlling the XtremeAR Session

You can add, stop or kill clients during the XtremeAR during the process.
Adding Clients during a Route Session

1. Redisplay the XtremeAR Client Manager using the icon while the Auto Route is in
session.
2. Select a client that is not participating in the Auto Route and select the Start Client
button.
Result: The Client starts and joins the XtremeAR session.The actions log displays the event
from the selected machine and netlines are sent to the client machine allowing them to be
routed.
Stopping Clients during a Route Session

session.
2. Select a client’s Process/TCP port.
3. Select the Stop Client button.
Results: This action allows the current netline route to complete and be saved back to the
XtremeAR host.
If there is only one client, the Auto Route Dialog stops in mid process and doesn't continue the
routing on the master machine until a client(s) is reselected on the dialog and the Start Client
button is selected.
If one client out of multiple clients is stopped, all remaining clients continue running the route
session.
Killing Clients during a Route Session

session.
2. Select a client’s Process/TCP port.
3. Select the Kill Client button.
Results: This action immediately stops the client machine participation without saving the
active netline route and a termination message displays in the Event column of the Actions log.

Xtreme Auto Router
Completing XtremeAR
Completing XtremeAR
As an XtremeAR completes its route passes and/or assigned routes, it saves the results to the
master database used by the XtremeAR host. The Auto Route dialog displays with the
completion results and all the computing resources and licenses used while participating in the
XtremeAR are released.
The Pinnacle license is automatically re-acquired. If there is not a license available, a warning
message is issued that the license is not available and asks if the database should be saved.
Pausing
If you had selected Pause on a route pass in the Auto Route dialog, the following happens:
1. The route pauses as it finishes the identified pass.

2. The host and clients stay connected and wait for you to continue the route pass or cancel
the route through an interrupt.
3. All running clients are stopped.
Caution
To restart XAR at the next pass, you have to display the Xtreme Client Manager and
restart the attached client.
Interrupting
At any point in the XtremeAR, you may click the Interrupt icon on the Auto Route dialog to
display the Interrupt Auto Route dialog. The ending process of XtremeAR is the same as
described above in the Completing XtremeAR section.
Figure F-5. Interrupt Auto Route Dialog

Xtreme Auto Router
XtremeAR Host or XtremeAR Client Crashes
Table F-3. Interrupt Auto Route Definitions

Autosave, continue routing Forces an autosave. As soon as the autosave is over, the
routing continues.
Skip rest of current effort Stops the current routing effort, and the router begins
routing the next effort.
Stop at end of current effort Allows the router to finish the current effort.
Stop now, keep current results Halts the router at the end of the current connection.
Stop now, discard all routing Halts the Auto Route session and returns your design file
to its state prior to starting the Auto Route session.
XtremeAR Host or XtremeAR Client Crashes

The XtremeAR host can detect connection failures with clients and re-schedule nets to other
clients still connected. In the case of short term network failures logical connection resume and
continue processing after the connection is restored.
If the XtremeAR Client(s) detect a network failure to the host, after a given period of time
(~five minutes), the XtremeAR Clients should save their local databases, end the XtremeAR
Client and release the licenses.
Using Xtreme Design Browser

The Xtreme Design Browser allows you to view (in Read-only mode) an Xtreme Design
Session using the Xtreme Auto Router (XAR) and watch the routing results as they occur from
the remote machine. Even though the design is read-only, updates made within the design
session are displayed in the Browser.
Licensing
Licenses to run PCB Browser are not required, however to participate in an Xtreme design
session an Xtreme Design Client license must be available.
As the PCB Browser joins the Xtreme Design Session, it consumes an XDS connection and an
Xtreme Design Client License. When the Xtreme Design Browser exits from the Xtreme
Design Session, it releases the Xtreme Client license.
Note
Only 15 connections are available per Xtreme Design Session. If >15 licenses are in use,
a warning dialog appears and you cannot participate.

Xtreme Auto Router
Xtreme Logging
Steps To Participate in XtremeAR

You must have access to Xtreme Design Client software licenses.
1. Open a design that is participating in an Xtreme Design Session.

If the database is being used in an Xtreme Design Session and there are already 15 client
licenses in use, a warning message appears and the design does not display in the
Browser.
If the database is being used in an Xtreme Design Session and there are less than 15
client licenses in use, the Xtreme Design Session licenses are decreased by one and an
Xtreme Design Client license is consumed.
The design is loaded into the Xtreme Design Browser in read-only mode but updates are
made to the design by remote clients using the Xtreme Auto Route functionality.
Xtreme Logging
To ensure that XtremeAR is working correctly, a log file format has been established to capture
the performance of the network, each client’s computer and the hardware for the session host
(XDS). The actual data is captured at a defined frequency, which could potentially create a large
report. A summary version of the data is provided in a standard format (for example, ASCII)
with a <TAB> delimiter allowing you to import it into a defined spreadsheet template.
Additionally, graphs and/or charts can be created to show performance bottlenecks in the
computing infrastructure.
Xtreme Logging capabilities are associated with, and included in, Xtreme Design Session. No
additional licensing is required.
The Xtreme logging report can be used by customers administrators to tune their hardware and
infrastructure for XtremeAR use and also provide a baseline session/client performance score
that can be used to predict route performance with a stated tolerance. The report can also be sent
to Mentor Graphics CSD department if poor performance results are seen.
Logging Requirements
1. Runs on all Mentor Graphics supported platforms.
2. Runs on heterogeneous platforms.
3. XAR Route performance report per submitted route. Including network performance,
available resources per client and server node.
4. The Log report is created whenever an Xtreme Design Session is started.
5. The report is stored with the database used to create the session.
6. Previous reports are not overwritten. There is a limit of 10 previous log files.

Xtreme Auto Router
Starting Xtreme Design Session
7. Reports if a client machine becomes unavailable.

8. Xtreme Design Session and Xtreme design Client(s) consolidate their reports and report
to the log file in the defined frequency and a timestamp from the XDS is applied.
9. Raw data format is in a <TAB> delimited ASCII file and a report template is available
to summarize the raw data. This report template can be loaded into a spreadsheet
programme.
Starting Xtreme Design Session

Whenever the Xtreme Design Session is started against an Auto Active database, the
XtremeLogxx.dat file is created, where xx represents a sequential number. This file is saved in
the ..PCB\LogFiles directory.
The logging file for Xtreme Design Session is not application specific. For example, specific
information for XtremeAR “Total Connections” is not included in the XtremeLogxx.dat file.
However, reporting summary mechanisms join the XtremeLogxx.dat and application specific
log files (AutoRouteReport.txt) into a spreadsheet template. If multiple, sequential Xtreme
Design Session are run against the same database, the log filename receives a sequential
number.
Reports
You can generate both a detailed and a summary report file from the XtremeLogxx.dat file by
running the XtremePerfA.exe executable file in a command window:
$SDD_HOME/common/<platform>/_bin/XtremePerfA[.exe]<Job_Directory>/LogFile
s/XtremeLogxx.dat
The XtremeRuntimeLog.txt (detailed report) and XtremeReport.txt (summary report) files are
created in the /LogFiles directory. This information can be imported into a spreadsheet template
and graphs and charts can be created highlighting negative infrastructure information.
Run Time Report

The Run Time Report (XtremeRuntimeLog.txt) captures and reports a summary of message
transactions that occurs in the defined frequency on each node. The Xtreme Design Session
provides a timestamp of when the frequency summary was received. Also included in the
summary is the reporting Node’s specific performance information.
If the Xtreme application uses Handles, it is included in the Nodes column.
sjc:machinename would represent the Node machinename and the Handle sjc.
If the application does not use handles and the same node is used multiple times, the node
reports as above except the handle name is an integer.

Xtreme Auto Router
Reports
If XtremeAR has two clients hosted on the Node machinename, the clients are reported
as 1:machinename and 2:machinename.
The Timestamp column displays the time the message was provided to the Xtreme Design
Session.
The Message Size (bytes), Message Count (bytes) and Message Speed (Milli-seconds) columns
display an average of size that was captured by the defined frequency.
The Queue Length column displays the length of time that the client waited for a transaction to
be completed.
The Rejections column is a complete count of messages rejected by the Xtreme Design Session
in the defined frequency.
The rest of the columns display system performance information at the time of the complete row
of data is provided to Xtreme Design Session.
Message Count
Message Speed
(milli seconds)
Queue Length
Xtreme RAM
Message Size
Xtreme CPU
Fault(#/sec)
Timestamp
RAM Page
Free RAM
Rejections
(bytes)
(bytes)
(bytes)
(bytes)
Node
CPU
(%)
(%)
Summary Report
The Summary Report (XtremeReport.txt) contains job information and database level
information. It also contains an additional logging file; AutoRouteReport.txt. With this
additional information, a complete picture of the XDS and Route results are presented.
The Report is split into sections and contain information for every participating node. The Job
Summary section provides basic session and database information. For the remaining section
headers, Averages, Maximums, Minimums and Percentage of overall session time are
displayed. The last section is called Exit Status and provides information about the exit status of
each client. If there were no errors, it displays “success”. If not successful, a list of network
error messages and client error messages are provided.

Xtreme Auto Router
Reports
Example File
Summary Report
Job Information:Title.
Database:Name and location of job database.
Database Size:Size in MBytes of the database.
XTAR Size:Size in Bytes of the XTAR file. The tarred database delivered from
the XDS to the XDC.
Submit Timestamp:The date and time the job was loaded.
XDS Node Name:Name of the XDS or master XAR server.
Number of Clients:The number of clients that participated in the session.
Session Client Client Client Client Average of

Session Rejections Node Node 1 Node 2 Node 3 Node N All Nodes
Average of All:
At 10% of Time:
At 20% of Time:
~~~~~~~~~~~~~ ~~~~ ~~~~ ~~~~ ~~~~ ~~~~ ~~~~
At 90%% of Time:
At 100% of Time:

System CPU Utilization Node Node 1 Node 2 Node 3 Node N All Nodes
Average of All:
0% Time (startup)
At 10% of Time:
At 20% of Time:
~~~~~~~~~~~~~ ~~~~ ~~~~ ~~~~ ~~~~ ~~~~ ~~~~
At 90%% of Time:
At 100% of Time:
Average:
Max:
Min:

Xtreme Auto Router
Reports

Process CPU Utilization Node Node 1 Node 2 Node 3 Node N All Nodes
Average of All:
0% Time (startup)
At 10% of Time:
At 20% of Time:
~~~~~~~~~~~~~ ~~~~ ~~~~ ~~~~ ~~~~ ~~~~ ~~~~
At 90%% of Time:
At 100% of Time:
Average:
Max:
Min:

Page Fault Count Node Node 1 Node 2 Node 3 Node N All Nodes
Average of All:
0% Time (startup)
At 10% of Time:
At 20% of Time:
~~~~~~~~~~~~~ ~~~~ ~~~~ ~~~~ ~~~~ ~~~~ ~~~~
At 90%% of Time:
At 100% of Time:
Average:
Max:
Min:

Memory Usage Node Node 1 Node 2 Node 3 Node N All Nodes
Average of All:

Xtreme Auto Router
Reports

Memory Usage Node Node 1 Node 2 Node 3 Node N All Nodes
0% Time (startup)
At 10% of Time:
At 20% of Time:
~~~~~~~~~~~~~ ~~~~ ~~~~ ~~~~ ~~~~ ~~~~ ~~~~
At 90%% of Time:
At 100% of Time:
Average:
Max:
Min:

Message Count Node Node 1 Node 2 Node 3 Node N All Nodes
Average of All:
0% Time (startup)
At 10% of Time:
At 20% of Time:
~~~~~~~~~~~~~ ~~~~ ~~~~ ~~~~ ~~~~ ~~~~ ~~~~
At 90%% of Time:
At 100% of Time:
Average:
Max:
Min:

Msg Delivery Time Node Node 1 Node 2 Node 3 Node N All Nodes
Average of All:
0% Time (startup)
At 10% of Time:
At 20% of Time:

Xtreme Auto Router
Third Party Integration

Msg Delivery Time Node Node 1 Node 2 Node 3 Node N All Nodes
~~~~~~~~~~~~~ ~~~~ ~~~~ ~~~~ ~~~~ ~~~~ ~~~~
At 90%% of Time:
At 100% of Time:
Average:
Max:
Min:
Exit Status
Third Party Integration

There can be optionally integration with third part software, specifically Platform LSF and Sun
Gridware. These integrations do not affect Xtreme logging; this occurs as regardless of any
third party integration.

Glossary
active layer
The layer on which you are currently editing. The active layer number must be in the range 1-64.
The active layer is paired with the secondary layer.
accelerators
A keystroke or keystroke combination which immediately starts a command or other function
bypassing menus. Keystroke combinations are usually a modifier key and some other key.
Accelerators are also known as Shortcut keys.
action keys
Keys which map to a menu selection, keystroke combination or macro. Action keys most often
activate a common command. Action keys are also known as Function keys.
alpha characters
The set of ASCII characters that include a-z and A-Z.
alphanumeric pins
A character representation of pin numbers.
ASCII
American Standard Code for Information and Interchange (ASCII)
A character format standard for storing text. An ASCII file can be edited, printed, or typed.
aperture
A precision opening through which light passes to expose film during photoplotting. Apertures
are of varying shapes and sizes. See also photoplotting.
area fill
The polygon shaped area in which to add area fill. Based on interaction with area objects inside
the boundary of the input shape, the input generates one or more actual shapes and islands, which
remain associated with their input shapes. All edits to an area fill are based on selection of the
input shape.
back annotation
A process that updates a schematic file based on changes made to a component design file. Back
Annotation should be run following pin swapping, gate swapping, or renumbering reference
designators.

Glossary
background-selection
A background-selected item is part of a select group, but is not currently selected. Background-
selected items are significant only when you use the ESC key to toggle through a select group.
They have no other functional significance.
backward crosstalk
The coupling of a signal on one conductor with a signal on a nearby conductor such that the
coupling affects the signal on the nearby conductor nearest the source. Backward crosstalk
travels opposite the direction of the signal inducing the crosstalk. The waveform usually has no
resemblance to the coupled signal.
bandwidth
A measure of drill head activity. If the sweep axis is the X-axis, this is the width in mils that the
drill head covers in the Y direction as it moves along the X-axis. If the sweep axis is the Y-axis,
this is the width in mils that the drill head covers in the X direction as it moves along the Y-axis.
bare board test

A test in which the test fixture and its probes are placed on an unpopulated board for the purpose
of checking electrical continuity of routing on the board.
batch process
A process which executes independently of the user's current action. A batch process is
submitted to the batch queue. A message is displayed when the process is completed.
bill of materials (BOM)

Formatted listing of parts used for a particular assembly.
bill of materials report listing

A formatted list of the parts used for a particular job taken from either the schematic or the
component design files.
blind via
A via that originates from either the primary or secondary surface, and does not penetrate
through the entire board.
board outline
The graphical representation defining the shape of a board.
board thickness
The thickness of metal-clad base material including the conductive layer or layers. The board
thickness may include additional platings and coatings, depending upon when the measurement
is made.
bottom layer
On a single-layer board, the first conductive layer on the top/front side of the board. On a double-
sided design, this is the external conductive layer on the bottom/back side of the board.

Glossary
breakout
A metal trace from a part pin on a surface mount device to a routable point.
buried via
A via completely contained within the inner layers of a board. It is not accessible from either of
the surface layers.
cell
A collection of graphical elements grouped together to form a single entity.
Cell Library
A file where definitions of layout components which are to be placed into a layout design are
held. These components include discrete components, via cells, surface-mount parts, etc. A
component might contain things such as component outline, reference designator, pins,
sometimes pads, etc. Cell Libraries are also used to hold font definitions which are later inserted
into font libraries.
Cell Library Index

An index file of the cells included in the Cell Library. The software reads this file to speed up
location of cells in the library.
cell origin
The point to which the cursor attaches when the cell is placed.
chamfer
A beveled edge as shown below.
circuit
The interconnection of a number of electrical elements and/or devices performing a desired
electrical function.
clipboard
A device for storing text or graphics during cut and paste operations.
clustering
The process by which elements within a net are divided into groups of previously connected
elements. This process makes analysis of the net more efficient.
common pins
A logical pin that maps to the same physical pin as one or more other logical pins within the
same part. Common pins occur on separate gates within the part. Common pins share the same
name. For example, you use common pins to tie a pack of resistors to a common ground.
Common pins are defined in Part Database entries.

Glossary
complex components
Components that are not globally gate swapped in swapping routines. They are not swapped
because of the use of a schematic symbol referencing the component being constructed with
more than a single functional subset.
component
A graphical symbol with annotations attached to it. Components are stored in a library and
copied to a design when needed.
component cell
A graphical representation of a physical electronic device. A cell is created by the Cell Editor.
component hole
A hole used for the attachment and electrical connection of component terminations, including
pins and wires, to the printed circuit board.
component lead
The solid or stranded wire or formed conductor that extends from a component and serves as a
mechanical and/or electrical connection.
component netlist
The binary listing of component parts and the connectivity information for the pins, netlines, and
traces used in the component design file.
component outlines
The contours that define the shape and size of a component's body. This outline must be
constructed using shapes, lines, or linestrings, but MUST NOT be a chained element. If the
outline is placed on the package outline level (defined in Job Parameters), and if it is constructed
using linestrings, it may be used as a via keepout area for the routers. Online DRC will also flag
this as a violation when interactively routing.
component pad
A metallized area at the end of a trace where a connection is to be made to another layer. This
area serves as the conductive connect point for component pads or via pads.
component side
The primary side of a printed circuit board.
component text
Informational text associated with a component. Multiple component labels can be associated
with a single component to identify the component type, component geometry name, part
number of the component and the component reference designator.
component outline
The polygon boundary that defines the size and shape of the component.

Glossary
component pin
The PCB term for a component lead, which is the physical pin that provides the metal connection
between a component and the circuit board. Same as pin.
component pin clearance

A value in user units that specifies the allowable distance between the pin padstacks in a
component. This clearance is stored by logical layer with other design rules. The system uses
the value to check that each component pin padstack on specified layers maintains the allowable
distance from other pin padstacks of the component.
component type
Any user-definable name, such as dip, type1, or my_component, for a graphical object
representing a component on a board for which you want to set a placement clearance. See also
type clearance and type-to-type clearance.
composite curve
The individual geometric items such as lines, arcs, or splines that are combined together, end-to-
end, to form a single, geometric object.
compress
To reduce the size of a design file by permanently deleting the elements that have been marked
for deletion in the file.
computer-aided design (CAD)

The use of a computer for automating design processes.
computer-aided engineering (CAE)

The use of a computer for automating engineering tasks.
computer-aided engineering (CAE) netlist

The ASCII file created by the Design Capture software that contains the netlist information
needed to create a schematic netlist.
conductivity
The ability of a material to conduct electricity; the reciprocal of resistivity.
conductor
A substance or body capable of transmitting electricity. In the PCB design tools, conductor
refers to signal trace, ground trace, ground plane, voltage trace, and voltage plane.
connection (1)
1. The means by which components are attached to a conductive pattern.
2. A point where a net connects to a pin, label, or another net.
connection (2)
Netlines, or traces and vias, that connect two component pins together. On signals that have more
than two pins, a connection will be made using a series of paths. On custom nets that have stub

Glossary
lengths set to 0, there can be no series of paths, since all component pins would have to be routed
component-pin to component-pin.
contour
Defines areas to be cut out of a panel, board. The three types of contours are inside cut, board
cut, and slot.
cosmetic trace
A graphical line, with width, drawn in the design file to resemble a normal trace. A cosmetic
trace can be assigned a net, but cannot have netlines attached to it.
custom pad
A pad which displays/plots with a non-standard graphical shape. Tools such as DRC and routing
will have to approximate the pad’s geometry using one of the standard geometries. This
approximate geometry for the custom pad is referred to as the pad’s enclosure, because it
hopefully completely encloses the pad’s custom shape.
crosstalk
The undesirable interference caused by the coupling of energy between signal paths in a circuit.
cutout
A polygon shaped area that is absent of copper. Cutouts are selectable for editing, independent of
an input shape.
D-code
In Gerber data, an entry of the form Dn, where n is a number from 00 to 99. Aperture numbers
are converted to D-Codes in the creation of Gerber data.
D-code/Aperture Correlation
A table used to convert aperture numbers to D-Codes, or vice versa, when Gerber data is created
or read.
daisy chain
A method of routing in which the component pins in a net are connected sequentially in a dot-to-
dot fashion from a source pin to a terminating pin.
database
A collection of data that is related to a particular topic.
dcode
A numerical control language used by Gerber photoplotters. Each aperture position in an
aperture wheel has an equivalent dcode, which is typically an integer between 1 and 256.
default
Any value that is fixed by the system in the absence of user input for that parameter.
delta coordinate system

A two-dimensional Cartesian coordinate system that you can use to enter point locations. The
system allows you to enter two linear distances. The axes of this system are not visible, but are

Glossary
parallel to the axes of the workplane. The basepoint is the origin of the delta coordinate system
and can be moved to any location in space. However, the delta coordinate system maintains the
same orientation as the workplane coordinate system.
design rules checking (DRC)

The process that ensures a design is created to specified design rules by notifying you of design
violations.
design rules checking (DRC) clearances

The minimum distance that elements must be from the other elements in the file. For example, a
trace-to-pad clearance is the minimum distance that any trace edge can be from any pad edge.
device
An individual electrical element, usually in an independent body, that cannot be further reduced
without destroying its stated function.
device parts
The types of parts recognized by PCB. The parts possible are standard, SMD, discrete, edge
connector, chip and wire, and screened resistor.
DI=distance, direction
A precision keyin command which places a data point distance from the last data point or
tentative point place, at an angle of direction. See also precision keyins.
diameter for pins

The representation of the hole created by the drilling of pin locations.
die
An uncased discrete or integrated device obtained from a semiconductor wafer. Also referred to
as a chip.
dielectric
Materials that do not conduct electricity and thus are used to insulate conductors (as in crossover
and multilayer circuits) and for encapsulating circuits.
dielectric constant
The ratio of the charge that would be stored with free space to that stored with the material in
question. Dielectric constant describes a material's ability to store a charge.
digital circuit
A circuit, comprised primarily of integrated circuits, that operates like a switch or operates in a
binary manner, assuming one of two states, for example, either ON or OFF.
directory
A logical structure that contains filenames and subdirectories. Files are organized by grouping
related files together in a common directory. See also job directory.

Glossary
display grid
An array of points with defined horizontal and vertical spacing that displays in the Edit window
as a drawing and alignment aid. The system provides default spacing values for the grid points,
or you can define different spacing values. By default, every grid point displays; you can choose
to display the grid points only at defined intervals or to display no grid points.
double-sided board
A printed circuit board with a conductive pattern on both sides.
drag mode
Drag mode is an interactive editing mode used to move objects. While in drag mode, the object
being placed follows the cursor. When the object is in the desired position, press the data button
to fix the object in position.
draw
In photoplotting, a line produced by shining a light through an aperture and moving the film so
that the line is the width of the aperture. Draws are generally used to represent traces on a
photoplot.
drill format
The description of how drill data is written to files.
drill schedule
A drawing geometry that lists the hole symbol, hole size, count, plating status, and tolerance of
each through-hole in the design. The drill schedule is typically part of a fabrication drawing.
drill table
The mapping of drill bits to the positions in a drill magazine. For each drill position, the drill
table defines a drill size, hole tolerances, and hole plating. Every drill hole in the design must
have a matching drill bit.
dual in-line package (DIP)

1. A component that terminates in two straight rows of pins or lead wires.
2. A package having two rows of leads extending at right angles from the base and having
standard spacings between leads and between rows of leads.
DX=delta_x, delta_y
Precision keyin command which places a data point delta_x and delta_y from the last data point
or tentative point placed. See also precision keyins.
dynaset
A dynamic set of records that answer a query.
edge-board connector
A connector designed specifically for making removable and reliable interconnections between
the edge-board contacts on the edge of a printed board and external wiring.

Glossary
edge-board contacts
A series of contact “fingers” printed on or near any edge of a printed board and intended for
mating with an edge-board connector.
edge connector device type

A device, consisting of etched “fingers” and surface-restricted connect points. The elements are
logically grouped as a component.
edge spacing
The distance of a pattern, components, or both, from the edges of the printed board.
emitter coupled logic

A form of digital logic in which a current source is fed to the emitters of several transistors to
eliminate transistor storage time and allow high speed circuit performance. Also called ECL.
engineering change order

A directive to incorporate a change to the design logic after the design has begun. Also called
ECO.
error messages
A statement that the system generates to report an error condition that prevented the completion
of a requested operation.
etching
A process in which a printed pattern is formed by chemical and/or electrolytic removal of the
unwanted portion of conductive material bonded to a base.
evaluate
The interpretation of a source object, for example a schematic, using the configuration rules of a
design viewpoint.
Euclidean distances
Straight line distances.
fault
Condition within a circuit that could alter its response (for example, a short circuit or an open
circuit).
feed rate
The speed at which the bit will enter the board when drilling or cutting a board.
feed-through
A plated-through hole in a printed circuit board that is used to provide an electrical connection
between a trace on one side of the printed circuit board and a trace on another layer. Since it is
not used to mount component leads, it is generally a small hole and pad diameter.
fiducial
A fiducial is a target screened onto the board which is used by vision or optical correction
machines to orient the board, or device being placed on a board.

Glossary
field
1. A field can be a synonym for a column in a table.
2. A single item of information in a record or a row.
filename
A user-defined name given to an interactively created file.
fill
Display mode in which elements are “colored” within the element boundaries, as opposed to
being displayed as just a shape outline.
fingers
A series of edge-board contacts printed on or near any edge of a printed board and intended for
mating with an edge-board connector.
fix component
The process of preventing parts from being swapped or moved during either the Automatic
Swapping option or Interactive Gate Swapping.
flash
In photoplotting, a brief burst of light that shines through an aperture and exposes the shape of
the aperture on the photographic film.
flat schematic
1. A file containing components/symbols, wires, and labels defining the connections of a group
of electrical parts.
2. A design method where hierarchical components/symbols are not used.
flip chip
A leadless integrated circuit designed to electrically and mechanically interconnect to the hybrid
circuit by means of an appropriate number of bumps located on the circuit side and covered with
a bonding agent.
font
A complete set of characters with the same print style.
form
An object that can be used to enter, change and view records of data. A form can also display
records on the screen or in print.
forward annotation
The process of specifying some aspect of the design in advance and carrying the specified
information forward for use in later stages of the design. Properties carry the specified
information forward in the design process.
Formatted Schematic Netlist

An ASCII file which is optionally created when the netlist is compiled. The Formatted
Schematic Netlist lists netlist information in tabular form.

Glossary
forward crosstalk
The coupling of a signal on one conductor with a signal on a nearby conductor such that the
coupling affects the signal on the receiving end of the nearby conductor. Forward crosstalk
travels in the direction of the signal inducing the crosstalk. See backward crosstalk and
crosstalk.
function keys
Keys which map to a menu selection, keystroke combination or macro. Function keys most often
activate a common command. Function keys are also known as Action keys.
gate
A logic circuit that has at least one input and only one output.
gate swapping
A process that exchanges connections between specified gates. The gates to be swapped must be
defined as gates in the PDB Editor with the pins equivalently defined as a one-to-one
correspondence between the gates to be swapped. Gate swapping may be performed by the
Swapping commands.
geometry
Refers to how the software treats a pad geometrically. The geometry of a pad comes from a fixed
set of standard geometries. The geometry doesn’t necessarily match with the pad’s shape (how it
looks when displayed), although it is best when they do match. For custom pads, the geometry is
often referred to as the enclosure.
GenCAD
A generic, computer-aided design file format that contains physical design information for
electronic circuit boards or hybrids. This format is the standard input for Mitron's CIMBridge.
CIMBridge is Mitron's manufacturing framework of software applications for assembly and
testing of printed circuit boards.
Gerber data
Precisely formatted data which controls a photoplotter to produce flashes and draws. Gerber data
consists of XY coordinates, D-Codes representing aperture numbers, and instruction codes for
light on, light off, and move actions. Gerber data is a form of vector data. See also photoplotting,
D-Code, draw.
graphics
Graphics consist of elements such as lines, shapes, points, and combinations of these.
grid
An orthogonal network of two sets of parallel, equidistant lines used for locating points on a
design.
grid reference (GR)

The number of grid dots between the reference tick marks.

Glossary
grid unit (GU)

Distance between two grid dots in a PCB file; defined in terms of UORs.
ground plane
A conductor layer, or portion of a conductor layer, that serves as a common reference point for
circuit returns, shielding, or heat sinking.
group
Package and/or mechanical cells can be grouped as a single entity. All objects in a group
become selected when you specify the group name. You can then edit all objects as a single
entity. (Groups also let you edit objects in the group individually by simply selecting the object
or objects without specifying the group name.)
head number
A unique number to identify a component insertion head on an insertion machine.
head type
The kind of insertion head that can insert a component. Different types of insertion heads insert
different components. Like machine types, insertion heads can include the following:
auto-insertion axialauto-onsertion
auto-insertion radialauto-onsertion odd-shape
auto-insertion odd componentmanual insertion/mounting
auto-insertion DIP IC
heat sink
An item that has an unlimited or a very large capacity to absorb heat. Examples of heat sinks are
highly conductive metal with multiple fins or the air surrounding a hot component.
hierarchical design
A method of schematic capture that allows the creation of functional blocks, whose functions can
be defined at a later time.
hole density
The quantity of holes-per-unit area in a printed board.
hole diameter
The entry in the pin and pad tables representing the size of the hole to be drilled for a pin code.
The hole diameter should match the hole diameter in the Tool table.
hole location
The dimensional location of the center of a hole.
hole pattern
The arrangement of all holes in a printed board.
icon
A graphical symbol used to represent a command or function. When selected with a data button,
the command it represents is invoked.

Glossary
inert atmosphere
A gas atmosphere, such as helium or nitrogen, that is nonoxidizing or nonreducing of metals.
insertion
The process of attaching or assembling components in plated through-holes on printed circuit
boards using automated machines. The plated through-holes serve as sockets into which a
machine fits the pins of the components.
insertion head
That movable portion of an insertion machine that interfaces directly with the component using
vacuum, mechanical jaws, or both in transferring the component from the feeder to the surface of
the printed circuit board.
insertion head shape

A polygonal region representing the actual shape of an insertion head.
insertion machines
Manufacturing equipment that takes components from a feeding source, orients them, and places
them accurately on the surface of a substrate. Also called pickand-place machines.
insulators
A class of materials with high resistivity that do not conduct electricity.
interactive placement
A placement routine that retrieves the part number names from the compiled netlist, reads the
corresponding cell names from the PDB Editor, and enables you to place a selected cell on the
board. This routine also allows movement or rotation of preplaced parts. Parts are selected from
a scroll list and ordered either by nets on the board or alphabetically by reference.
interconnection
The conductive path required to achieve connection from a circuit element to the rest of the
circuit.
island
A copper area that is not physically connected to a net, or floating metal. An island exists
within the boundary of an area fill input shape and is associated with the input shape. An island
is not selectable; all edits to an area fill are based on selection of the input shape. Options
relating to islands control whether islands are active or inactive.
job
The design project containing all files needed to produce a board. These files include the
configuration file, parameters, schematic netlist, the component design file, and the output files
needed to manufacture the board.
jobname
The specific name given to each job on the workstation network.

Glossary
jumper
Short pieces of conductive wire on a PCB joining one section of etched copper with another
section of etched copper. Jumpers are used to make electrical connections that are otherwise
impossible to complete or require extensive placement and routing modifications. Jumpers are
usually portions of bare or insulated wire mounted on the component side of the board.
keepout area
A defined area that prevents the automatic placement routine from placing components within
that area.
keyin
A command keyed in, rather than selected with an icon.
keyin field
A field on a menu that accepts user data from the keyboard after it has been activated.
keyin netlist
An ASCII file created either with the netlist editor or by a schematic capture package. It is
accessed by the netlist compiler. The keyin netlist, opposed to the CAE netlist, does not have a
%_symbol=> % SYMBOL.
leads
Wires which extend from a physical device, used to attach the device to the printed circuit board.
levels
The design planes that are reserved for graphics design file information. Levels 1-63 are for
design; levels 65-127 contain the cell header information in graphics.
library
A directory containing symbols, geometries, or a catalog file and the mapping files used in the
board design process. Mentor Graphics supplies some libraries with the PCB products; you
create additional libraries of data specific to your company's design requirements.
linear feed
The speed at which the bit will move along the X- or Y-axis when routing or cutting a board.
links
The manipulation lines, with weight, generated by the automatic placement routine. Links
represent the degree of connectivity between parts on the design.
logical tool
A file containing information on each tool used for NC Drill tapes. The information includes:
logical tool number, hole code, hit count, spindle rate, physical tool, use, feed rate, linear feed,
reversed feed, and diameter.

Glossary
Manhattan alignment
Manhattan alignment forces 90-degree adjustment, which causes the most recently placed point
to adjust its position to align either horizontally or vertically, depending upon whether its
placement was closer to the horizontal or vertical axis of the last data point placed.
Manhattan distance
The orthogonal distance created by making a connection between pins using one horizontal and
one vertical segment. The netline is the hypotenuse of the triangle.
mapping file
An ASCII file listing the association between the pins of one or more schematic symbols and the
pins of a component geometry. A mapping file is a generic description that can apply to more
than one component.
master drawing
A document that shows the dimensional limits or grid locations of any or all parts of a printed
board, including the arrangement of conductive and nonconductive patterns or elements and any
other information necessary to describe the product for fabrication.
master pattern
An accurately scaled pattern that is used to produce the printed circuit within the accuracy
specifications of the master drawing.
master unit (MU)

The largest unit that may be referred to when working in the design file. When defining working
units, master units are designated as any one- or two-character abbreviation (such as “IN”, “TH,
or “MN”). See also working units.
maximum insertion height

The maximum allowed distance from the board surface to the head of the insertion machine.
mil (TH)
A unit equal to 0.001" or 0.0254 mm.
Mitron
A company specializing in software for the manufacture of printed circuit boards
mnemonics
A keyboard navigation method, in which a modifier key and the mnemonic letter are pressed.
The mnemonic is indicated by underlining.
mode
A condition or state established for performing a particular type of operation. The current mode
determines how the system interprets and processes data. For example, in a selection mode, the
entry of an x,y coordinate identifies the object to select; in a routing mode, the entry of an x,y
coordinate identifies a vertex of a trace.

Glossary
moire target
A special drill hole specifically defined for alignment of photoplots.
mounting holes
Holes used to mount hardware to a board or to mount a board to another assembly.
mouse
A hand-held, manually moved unit consisting of three buttons: command, data, and reset/reject.
mouse buttons
The three buttons on the hand-held mouse that control the cursor on the display screen. The
command (left), data (middle), and reset/reject (right) buttons specify data points, initiate
commands, and select or move items on the screen. See two-button mouse.
mother board
A circuit board used to interconnect smaller circuit boards called “daughter boards.”
multilayer board
A board containing more than two layers of conductive patterns with dielectric separation.
multilayer design
A design containing more than two layers of conductive patterns with dielectric separation.
multilayer printed circuit board

Completely processed printed circuit or printed wiring configurations consisting of alternate
layers of conductive patterns and insulating materials bonded, with conductive patterns in more
than two layers, and with the conductive patterns interconnected as required. Includes both
flexible and rigid multilayer boards.
neck down a trace

To decrease the width of a trace between two given points. One use of this ability is to shrink
traces going between pins when those traces would cause violations at normal width. Neck down
can be performed through the Change Width command.
negative (noun)
An artwork, artwork master, or production master, in which the intended conductive pattern is
transparent to light, and the areas to be free from conductive material are opaque.
negative data for geometric planes

The Planes Processor option that produces data representing clearances for the planes. This is
shown as hatching in the form of “rings” around pins not connected to the plane.
net
A group of electrically connected pins. Net refers to the connected logical pins shown on a
schematic or the connected physical pins of components on a printed circuit board.
netlist
A record of the nets in a design. For each net, the netlist records net name, pin numbers, and
reference designators.

Glossary
nodename
A name that can be assigned to the network address of a node so that it is easier to remember.
Workstation nodenames can have a maximum of 8 alphanumeric characters.
nonplated hole
A hole within a terminal area containing no conductive material.
notch a trace
The ability to break a trace at two points and stretch the segment created by the break. This
allows you to “notch” around another trace, pin, or via.
Numerically Controlled (NC) Drill

Software used to produce numerical control data for drill machines.
numerically controlled (NC) drilling

A highly accurate method of drilling printed circuit boards on a quantity basis. A paper tape
containing a tabulation of hole coordinates and diameters is fed into an automatic multihead
drilling machine that then drills the printed circuit board.
object
A unit such as a table, form, and report that can be selected and manipulated as a unit.
objects
Graphical entities that reside on the board layers and graphical data that provides information for
use in board layout. Examples of graphical entities are area fills, drill holes, pin pads, traces, and
vias. Examples of graphical data are errors, grids, guides, density, and geometry attributes, such
as the board outline and component placement outlines. You can set object types to visible or
invisible. Visible object types display on visible layers.
offset, for pads

The displacement of the origin of the pad from the center of the pin. The offset is defined within
the Pad Table.
online
A process which runs continuously. Online DRC and Help are two examples of online processes.
onsertion
A process for mounting, affixing, and sometimes (flow) soldering a (surfacemounted)
component or device on a substrate, such as a printed circuit board.
orientation
The rotational offset of a custom pad’s enclosure to its custom shape. This is used only for
custom pads, and only affects how the enclosure is treated by software, it does not affect how the
pad is displayed. By default, the enclosure of a pad has the same ‘rotation angle’ as the shape
(text element). If the enclosure does not properly match the shape given the same rotation angle,
the user can use the orientation to add to the enclosure’s rotation angle the amount specified as
the orientation (0, 90, 180 or 270 degrees).

Glossary
origin offset for head shapes

A user-definable distance that an insertion head shape can be offset from the origin of a
component geometry. If you do not define an offset for head shapes, the system maps the origin
of the head shape to the associated component's origin.
orthogonal
The descriptor that defines the placement of two lines or elements at right angles to each other,
making a perpendicular connection.
package pins
The pins defined in the PDB Editor, but not shown in the schematic or keyin netlist. Package
pins can be referenced by the supply file when the netlist is augmented. The pins connected to
net ground or power, or no connects are package pins.
package type
The form of a physical package. For integrated circuits, common package types include DIP,
SOIC, PLCC, CDIP, and flatpack.
packaging density
Quantity of parts (components, interconnection devices, mechanical devices) per unit volume,
usually expressed in qualitative terms, such as high, medium, or low.
pad
A metal shape on a board layer at every point where a component pin connects to the board layer.
Solder ties the component pin to the board at the pad location. Pads of through-pin components
have plated-through holes in the middle. Pads of surface mount components have no drilled
holes.
pad clearance
The minimum space between a pin padstack or via padstack and any other conductive element.
The optional board attribute Default_padstack_clearance sets the pad clearance value. The
autorouter honors the clearance value when routing near pads or vias.
pad code
A number from 1 to 9999 referencing an entry in the pad table.
pad types
The number representing the different geometries used to define pads.
padstack
The set of associated pads with this pin. This allows different pads to be associated with this pin.
This includes pads to be used for different layers of the board. The goal of the pad stack is to
encourage the user to build pins, but not pads, into components. When the components are
placed into the design file, they will have pins but not pads (it is allowed to build pads into
components, but isn’t recommended). This saves a lot of memory since the design file will not
have explicit instances of all pads inside the design file, but will instead contain references to
them. The user can run a tool called Pads Processor that explicitly places requested pads into the
design file so that they can be viewed properly. Therefore, the pad stack allows the software to

Glossary
‘pretend’ a pad is on a pin, even if it isn’t physically placed yet. Tools such as DRC, Routing, etc.
will use the appropriate pads in the pad stack depending on the situation. See pin padstack and
via padstack.
pan
A dynamic scrolling of the view in a horizontal, vertical, or diagonal direction. As you move the
cursor, two reference lines follow. The dotted line connects the current cursor position to the
initial cursor position. If you need to return to the pan's point of origin this line can be used as a
guide. The solid line is a velocity and direction vector. Its length shows the relative speed of the
pan, and its path shows the direction of the pan. To stop panning, release the right mouse button.
panel
A sheet of board material in a specified size used for manufacturing one or more printed circuit
boards or one or more layers of a printed circuit board. A step and repeat panel contains multiple
copies of a printed circuit board. A multi-layer panel contains copies of two or more different
groups of layers of the same board. Panels are typically used for efficiency and economy in
board manufacturing.
parallelism
The degree to which two nets run parallel to one another.
part
A physical device (such as a resistor, capacitor, or integrated circuit) used in the board design to
perform an electrical function. In PCB, a part consists of a part number for identification, the
logic symbol or symbols packaged in the part, a component geometry, an associated mapping
file, and any properties you assign to the part.
Part Editor
The Parts Database (PDB) Editor provides tools to create and modify the PDB entries which
exist in the Central Library partition.
part number
The field used to identify components according to their functionality and value. The part
number is used as a reference for most PCB processes.
path
A sequence of directories leading to a file.
pattern
The outline of a collection of circuit conductors and resistors that defines the area to be covered
by the material on a board.
photographic master
A 1:1 photoreproduction or precision duplicate of the master pattern that is sent to a
manufacturer to produce the printed circuit board.

Glossary
photoplotting
The process by which board artwork is generated by plotters that expose the film to light,
therefore making a “photograph” of what is being plotted. This film or artwork is then used in the
manufacturing process.
pin
An intelligent element that is part of a component or symbol. It allows components/symbols to
be connected while providing a reference point for creating a netlist. A pin’s main purpose in life
is to serve as a connect point for non-intrusion routers and to serve as the focal point for
padstacks. It is also commonly used to define the size of drilled-holes for through pins.
pin code
A number from 1 to 9999, referencing an entry in the pin table.
pin padstack
A pin padstack is the graphical representation of the size and shape of a pad or a series of pads
occurring, vertically aligned, on different board layers. A padstack can also include information
on the finished hole size and the whether the hole is plated or non-plated to define the hole for
inserting a component pin. The pin padstack geometry represents a component pin connection
and consists of a geometry name, the pad graphics, and padstack attributes. There are three types
of pin padstacks:
blind - provides for a pin connection on one or more board layers from a surface layer to an
internal layer. A blind pin padstack lets you define optional pin rules.
surface - represents a pad for a surface-mount device and appears on either the top or bottom
physical layer of the board, depending on the placement of a surface-mount device.
through-pin - spans all physical layers of the board to provide connection to a component pin on
all board layers.
pin swapping
The process that exchanges connections from one pin to another pin to improve routing,
provided the pins are in the same gate and in the same swap group. The purpose of swapping is to
decrease congestion and reduce net length.
plane
An area of conductive material placed on a layer of a design to connect the termination points of
nets (for example, all power nets can be tied to plane 1 and all ground nets tied to plane 2.) For
shielding purposes, planes can also be placed on layers without being tied to a net.
plane layer
A design layer which contains solid or patterned conductors tied to a supply or ground net.
plated hole
A hole in which conductive material is deposited on the wall. Can be produced with terminal
areas on one or both sides of a pc board.

Glossary
plated-through hole
A hole in which electrical connection is made between internal or external conductive patterns,
or both, by the deposition of metal on the wall of the hole.
plating
A uniform coating of conductive material placed upon the base metal of the design.
plotting
1. The practice of mechanically converting X-Y positional information into a visual pattern, such
as a schematic.
2. The production of a hard-copy plot, such as a schematic, from a graphical package.
plowing
Within an area fill input shape, the removal of copper around a net object to maintain design rule
clearances.
polar angle
An angle that is measured from the X axis and is specified in degrees or radians.
polar coordinate system

A coordinate system that you use to enter coordinates as an angle measured from the positive X
axis of the delta coordinate system. The positive X is parallel with the X axis of the workplane
and is a linear distance measured from the basepoint. The orientation of the polar coordinate
system is set by the workplane coordinate system. The origin of the polar coordinate system is
indicated by the basepoint.
positional unit (PU)

The smallest unit that may be addressed in the design file. One unit of resolution equals one
subunit. When defining working units, the number of positional units per subunit is designated.
See also unit of resolution, working units.
positive (noun)
An artwork, artwork master, or production master in which the intended conductive pattern is
opaque to light, and the areas intended to be free from conductive material are transparent.
power plane
A layer of the board reserved for power nets.
precision keyins
Commands used to place data points at precise locations by keying in the absolute coordinates or
relative values. See also XY=x_value, y_value, DX= delta_x, delta_y and DI=distance,
direction.
prepreg
Sheet material (for example, glass fabric) impregnated with a resin cured to an intermediate stage
(B-stage resin).

Glossary
pressing a button
To push down a mouse button.
primary class
The default display class used for the creation and placement of graphics.
Primary Key
The Primary key of a table consists of one or more fields that uniquely identify every record
stored in the table. A Primary key is often an ID number or code, since this type of value is often
different for each record.
primary levels
The levels defined for the etch (trace) layers of the component design file, as opposed to the
secondary or pad layers of the board. Positive plane data is also placed on the primary levels.
printed circuit
A conductive pattern comprised of printed components, printed wiring, or a combination thereof,
all formed in a predetermined design and intended to be attached to a common base. In addition,
this is a generic term used to describe a printed board produced by any of a number of
techniques.
printed circuit board (PCB)

A part manufactured from rigid base material on which a completely processed printed circuit
has been formed.
propagation delay
The time required for a signal to travel to the end of a conductor, or the time required for a logic
device to perform its function and present a signal at its output.
property
An informational tag that you or the system assigns to a symbol instance, a net, a pin, or a
component. Like attributes, properties convey important characteristics and data that influence
how the PCB applications handle the object.
query
A query defines a set of criteria about how data is selected from table(s).
radial lead
A lead extending out of the side of a component, rather than from the end.
README files
ASCII files which are downloaded with each product, and placed in the product directory.
record
A record can be a synonym for a row in a table.
reference designator
The field in a component cell used to identify a unique name for each physical device in the
design. It is often referred to as an instance indicator. A reference designator consists of a text

Glossary
prefix plus a sequence number, such as U32 or R17. The prefix typically represents the type of
function.
register mark
A symbol used as a reference point to maintain registration.
registration
The alignment of a pad on one side of the printed circuit board (or layers of a multilayer board)
to its mating pad on the opposite side.
registration marks
A symbol used as a reference point to visually check the alignment of multiple artwork layers.
report
An object that can be used to print records in a custom layout. A report can also be used to group
records and show totals for groups and grand totals for the entire report.
reusable block
This defines all of the reusable block data stored in the Central Library represented by the
Expedition PCB Design, Design Capture Schematic, and saved reusable block cell. The reusable
block is referenced by a unique user-defined name.
reusable block design

An Expedition PCB layout and schematic database that represents a repeatable circuit. This
defines the data that is used to create the reusable block cell which is the object placed within
other Expedition PCB designs.
reusable block cell

This defines the cell created from a verified reusable block design while in Expedition PCB.
This cell is used in other Expedition PCB designs that reference the reusable block from its
attached Central Library.
reusable block schematic

This defines the schematic referenced within the reusable block design that contains the logic
required by the reusable block.
reverse feed
The speed at which the bit will be removed from the board as it drills the holes.
route border
The area defining the routeable portion of the board. It contains all traces. If used by the
Automatic Routers as a boundary, any traces that exist outside this area will be flagged by DRC.
route channel
A path along the X- or Y-axis where a trace is allowed when routing.
route obstructs
Lines or shapes placed by one of the route obstruct commands, restricting routing in areas
defined by these elements.

Glossary
rubberbanding
The stretching of an element, such as an SLI or trace, with one or both ends of the element
stationary and the other end or the element between the two endpoints moving with the cursor.
schematic
A drawing that shows, by means of graphic symbols, the electrical connections, symbols, and
functions of a specific circuit arrangement.
schematic capture
The process of using Design Capture to assist in the creation and modification of electronic
circuits.
schematic diagram
A drawing that shows, by means of graphic symbols, the electrical connections, components, and
functions of a specific circuit arrangement.
schematic file
In Design Capture, a file that contains a software representation of a circuit under design.
schematic netlist
A binary listing of parts and net connections derived from a schematic.
scheme
Nine customized schemes are delivered with PCB of which only four can be modified or deleted.
These schemes represent an organized framework of specific design processes.
secondary layer
The layer which, if you insert a via, will be the destination of the via. The secondary layer
number must be in the range 1-64. If you insert a via, the secondary layer becomes the active
layer, and the active layer becomes the secondary layer.
secondary levels
The layers defined to contain pad information for each primary etch level and/or for negative
planes data if generated.
seed file
A customized template file that is referenced when a new schematic file is created. The new file
assumes the characteristics of the seed file, thus preventing repetitive file “set up” procedures.
segment
The section of a trace between two vertices. Both vertices must be on the same layer.
shortcut keys
A keystroke or keystroke combination which immediately starts a command or other function
bypassing menus. Keystroke combinations are usually a modifier key and some other key.
Shortcut keys are also known as Accelerators.

Glossary
signal
An electrical impulse of a predetermined voltage, current, polarity, and pulse width. Signals pass
information from one point to another in a circuit. Signals are conveyed by nets between ports,
pins, and connectors.
signal layer
A conductor layer intended to carry signals rather than serve as a ground or other fixed voltage
function. A signal layer can be a surface layer or an internal layer of the printed circuit board.
single point nets

Nets that have only one connection point. This condition occurs when a label is assigned to a pin
that lacks another connection.
silk screen (verb)

A process for transferring an image to a surface by forcing suitable media through a stencil
screen.
silkscreen (noun)
A graphical representation of a component showing reference designators, outlines, and
orientations.
single point nets

Nets that have only one connection point. This condition is caused by assigning a label to a pin
without the pin having another connection.
single-sided board
A printed board with a conductive pattern on one side only.
snap
Property that moves the cursor to the nearest element if it is not on an element when a data point
is placed.
soldering
The process of joining metallic surfaces with solder, without the melting of the base material.
soldermask
A screened or laminated coating on the surface layer(s) of a printed circuit board. The coating
prevents solder from adhering to selected areas and forming bridges (unwanted conductive
paths) between traces and pads during soldering.
stripline
A controlled impedance configuration in which conductors are centered in a dielectric medium
between two reference planes. If the thickness and width of the conductor, the dielectric constant
of the medium, and the distance between the reference planes are controlled, the conductor
exhibits a characteristic impedance that can be held constant.

Glossary
stub
A branch of the main line of a signal net usually used to reach a load that is not on the direct
signal path.
stylus
A sharp-pointed probe used in making an electrical contact on the pad of a leadless device or a
film circuit.
subunit (SU)
A portion of the master unit. When defining working units, subunits are designated as any one-
or two-character abbreviation, and the number of subunits per master unit is indicated. Most PCB
commands express distances in subunits. See also working units.
supply file
An ASCII file containing part number name, package pin and net, such as GND or VCC,
associated with that pin.
surface-mounted device (SMD)

A component with pins that attach to the surface of the board. You can place two surface-mount
components at the same x,y location on the board*one on the top surface and one on the bottom
surface.
surface-mounted pin
The attach point of a surface mounted device to the printed circuit board.
surface mounting
The electrical connection of components to the surface of a conductive pattern without utilizing
component holes. A device which mounts to the surface of a board.
swap groups
The type of a part number definition in the Parts Database denoting all pins that are functionally
equivalent with each other. A single pin in a swap group means that no pins may be swapped
with that pin.
swapping
The ability to switch connections for components/symbols, gates, or pins having electrical
equivalence. The “swappability” of elements depends on the part number definition in the Parts
Database.
sweep axis
The primary direction the drill head will move across the board as it drills the holes.
symbology
Characteristics of an element, such as: color, line, weight, and text height.
t-junction
A trace that perpendicularly joins another trace.

Glossary
teardrop
A deposit of copper in a specified shape and size at the entry point of a trace to a pin or via pad
for the purpose of reinforcing the connection. Available teardrop shapes are triangular and
snowball (round).
terminating a trace
The ability to complete the routing of a trace from the last vertex to the center of the pin, trace, or
via.
test board
A printed board suitable for determining acceptability of the board or of a batch of boards
produced with the same process so as to be representative of the production board.
test point
A special point of access to an electrical circuit for testing purposes. A pin or via on the board
that has been designated for testing. A point on a board, usually a pin or via, at which a probe
makes electrical contact to apply or sense a test signal.
through connection
An electrical connection between conductive patterns on opposite sides of an insulating base (for
example, plated-through hole or clinched jumper wire).
through-hole component
A component with pins that extend through holes in the board. Each pin of a through-pin
component requires a pad with a plated through hole.
through-mounted pin
A pin which is inserted into a hole in the printed circuit board.
toggle
The name for any software switch that allows you to change between two settings of a variable,
typically between ON and OFF.
tooling/datum holes
A minimum of two holes placed within the finished board profile, to assist in the accurate
location of the master pattern to the blank profile of the printed circuit board during the
manufacturing stage. Also called “indexing holes,” they are used in locating jigs and other tools
at the assembly stage.
thru pad
A pad which goes through all the layers of the design.
trace
A copper track on a printed circuit board which serves as a path for electrical conduction
between points.

Glossary
transmission line
Any form of conductor that carries a signal from a source to a load. The transmission time is
usually long compared to the speed or rise time of the signals, so that coupling, impedance, and
terminators are important to preserving signal integrity.
two-button mouse
The two buttons on the hand-held mouse that control the cursor on the display screen. The select
(left) and custom (right) buttons specify data points, initiate commands, and select or move items
on the screen. In the Advanced Editor, the Shift+Right mouse button combination replaces any
action of the middle button. See three-button mouse
UNC format
UNC stands for Uniform Naming Convention. The following is an example of UNC format,
\\node_name\share_point.
unit of resolution (UOR)

The smallest unit that may be addressed in the design file. One unit of resolution equals one
subunit. See also working units, positional units.
variant
A collection of multiple features of the design of a circuit, based on assigning specific instances
in the schematic to the collection (variant). One assembly of a multiple-assembly design. For
example, variant_a might contain the functions memory, clock, audio, and mono while variant_b
might contain memory, clock, audio, and stereo.
venting
A pattern placed on a panel that allows a uniform flow of prepreg. When the board layers are
compressed, venting controls the flow of prepreg, maintaining an even distribution.
vertex
A point on a trace. A component pin is a starting vertex of a trace. Vertices other than component
pins are bend points or vias in the path of the trace.
via
A plated hole connecting one etch (trace) layer to another. A via allows a net connection to
transfer and continue routing on another layer of the board.
via hole
A plated-through hole used as a through connection, but in which there is no intention to insert a
component lead or other reinforcing material.
via name
The cellname given to the via cell.
via padstack
A via padstack is the graphical representation of the size and shape of a pad or a series of pads
occurring, vertically aligned, on different board layers. The via padstack geometry represents

Glossary
the movement of a trace through board layers and consists of a geometry (via) name, the pad
graphics, and padstack attributes. There are two types of via padstacks:
buried - provides for via connections on one or more board layers from a internal layer to
another internal layer. You can also define, using via rules, that a buried via is a blind via, that is,
a via connecting a surface layer to an internal layer.
through-via - provides via connections to all routing layers of the board, from the top surface
layer to the bottom surface layer.
via rule
A rule that defines the physical layers that a via padstack spans. A buried via padstack is the
only type of via padstack for which you can define via rules. With via rules, you can define
whether a buried via padstack appears as a buried via, blind via, or through-pin via. You must
assign via rules to a buried via to make the buried via available for use in routing.
voltage plane
A conductor or portion of a conductor layer on or in a printed board that is maintained at other
than ground potential.
voltage-plane clearance
The etched portion of a voltage plane around a plated-through or nonplated- through hole that
isolates the voltage plane from the hole.
wildcard
A special character that provides compact notation for several characters or character strings.
working units
The design file units that define the reference points used in setting up the grid. Values for the
working units are in MU:SU:PU or master units: subunits: positional units. The design plane is
composed of units of resolution (UOR). When these UORs are divided into a grouping where a
quantity of the UORs has a value, that is, the design plane area has been defined, a working unit
definition is in effect. See also master unit, subunit, positional unit.
XY= x_value, y_value

Precision keyin command which places a data point at the coordinate (x_value, y_value). See
also precision keyins.
X & Y dimension for pads

The value representing the dimension of the pad used for checking processes (DRC & automatic
routing).
yield
The ratio of usable components at the end of a manufacturing process to the number of
components initially submitted for processing. Since yield can be applied to any input-output
stage in processing it must be carefully defined.

Glossary
Zoom
A rapid enlarging or reducing of the viewing area. Zooming in focuses the view on a smaller area
of the board. Zooming out expands the view to show a larger area of the board.

A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Index
—A— Running, 182

Accelerator Keys, 28 Specific Nets Example, 180
Action-Object Commands, 29 Straight Line Interconnects Pass, 171
Adding Vias, 162 Usage, 176
Additive Resistors, 333 Automatic
Advantages/Disadvantages of Negative and Routing, 133
Positive Planes, 195 Swap by Cell Name, 131
Allowed Via Padstacks, 79 Swap by Part Number, 132
Alt Key, 348 Test Point Assignment, 193
Alternate Mouse Mappings, 20 Automatic Placement Modification
Angle Lock, 349 Polar Placement, 132
Handle, 349
Angle Plow, 156 —B—
Back Annotation, 256, 262
Arc, 364
Batch DFF, 200, 201
Add, 364
Board Origin, 114
Alt Move, 366
Board Outline, 113
Center X,Y, 364
Board Setup, 112
Ctrl Add, 365
Bring Forward in Draw, 355
Ctrl Move, 366
Buildup Designs for Microvias, 296
Drag & Release and One Click, 365
Buried Resistors and Rise Time, 87
Line Width, 364
Bus, 165
Move, 365
Recalculation, 166
Operation, 364
Routing, 166
Radius, 364
Routing Rules, 167
Selection, 365
Routing Steps, 167
Shift Move, 366
Tune, 168
Shift Stretch on the Diamond, 367, 382
Stretch, 366 —C—
Stretch Endpoint, 366 CAE Netlist, 269
Stretching on the Diamond, 367, 381 Cell Editor, 67
Sweep Angle, 364 Draw Mode, 67
Three Click Events, 364 Drawing Cells, 67
Vertices, 364 Mechanical Cells, 67
Arced Corners, 184 Package Cells, 67
Archive Plots, 214 Partitions, 67
Auto Route, 182 Place Mode, 67
Auto Save, 46 Route Mode, 67
Layer Pairs, 135 Cell Editor in Fablink XE, 418
Routing with Fences, 180 Assembly fixtures, 421
Routing Costs, 135

Creating a Panel Cell, 424 Deleting Objects, 217

Panel Cell Outline, 425 Design Reference Objects, 226
Panel Cell Types, 419 Dimension Objects, 227
Test identifiers, 421 DRC Violations after Mirroring, 238
Cells Dynamic Mirror, 238
Editing, 125 Embedded Passives, 243
centlib.prp Default File, 64 Examples of cells with an axis of
Central Library, 57 symmetry, 239
Explanation, 57 Find with Circuit Move and Copy, 221
Packaging Parts (Expedition), 64 General Methodology for Copy & Paste,
Partitions, 59 216
Property Verification Settings, 71 Incompatible Via Spans, 236, 242
User Access to a Central Library, 59 Instantation Wizard, 229
CES Usage with Xtreme PCB, 458 Instantiation Wizard Physical Layers, 232,
Chained Net, 118 233
Chained Order Nets, 186 Instantiation Wizard Ref Des, 230
Algorithm, 120 Instantiation Wizard User Layers, 234
Change Layers in Circuit Move and Copy, 235 Jumpers, 221
Changing a Trace Width, 175 Limitations, 225
Changing Layers and Adding Vias, 162 Mirror, 237
Characteristic Impedance, 161 Mounting Holes, 220
Circle Moving Circuits, 216
Add, 368 Mulitiple Mapping, 233
Alt Move, 369 Multiple Equivalent Circuit Instances, 219
Alt Stretch, 370 Multiple Selected Objects Priority, 228
Center X, Y, 368 Multiple Via Objects, 219
Ctrl Move, 369 Multiple Via Objects Usage, 225
Diameter, 368 Part Placement Criteria, 219
Drag & Release, 368 Part Selection, 227
Fill, 368 Plane Shapes and Net Assignments, 220
Line Width, 368 Push, 241
Move, 369 Retrieving a Circuit, 222
Operation, 368 Reusable Blocks, 236
Selection, 369 RF Shapes and Groups, 242
Shift Move, 369 Rooms and Clusters, 220
Stretch, 370 Rule Area Scheme Assignments, 220
Two Click Events, 368 Save Schemes in Push and Change Layer,
Circuit Clipboard, 221 236
Circuit Move and Copy, 215 Selection Filter Layers, 225
Alternate Cells, 218 Selection Filter Objects, 226
Cell Name Mismatches, 219 Selection Filter Outside RF Toolkit, 228
Change Layers, 235 Selection List, 222
Circuit Clipboard, 221 SelectionFilterPriority.hkp File, 228
Circuit Layers, 233 Static Mirror, 238
Copy to Layout Clipboard, 228 Table Associations, 223

Test Points, 220 Cases and exceptions, 155

Transformation of cell instances on Mirror Curve center point modification, 155
command, 240 Example, 154
Via Span Definitions, 219 Moving trace segments with arcs, 154
Virtual Pins and Guide Pins, 220 Trace push and modification, 155
Cleanup, 184 Custom Net, 118
C-Link, 212 Customizing the Interface, 29
Command Listing for Xteme PCB, 479 Buttons, 29
Common Properties, 64 Dockable Toolbars, 29
Comparisons between Fix and Permanent, 125 System Default, 29
Contour Placement, 115 Toolbars, 29
Copper Balancing, 404
DRC, 410 —D—
Terminology, 405 D-Codes, 209
Copper Balancing Processor, 407 Default Mouse Mappings, 20
Copy Circuit, 129 Definitions of Reusable Block Terminaology,
Suggested process of designing your 318
schematic, 129 Delete
Copy to Layout Clipboard, 228 Unused Test Points, 193
Copy Trace and Fanout, 174 Delete Copper Balance Data, 409
Copying and Pasting Circuits, 217 Delete End Point Handle, 353
Create Delete Plane Data, 194
Polygon, 352 Deleting Objects in Circuit Move and Copy,
Polyline, 352 217
Creating Special Properties for ODB++, 289 Design Architect, 272
Critical Nets, 180, 186 Design Architect Commands for Cross
Control Crosstalk, 191 Probing, 281
Example, 179 Design Architect Flow, 276
Group Length Control, 187 Design Capture
Impedance Control, 187 CAE Netlist, 269
Length / Delay Control, 187 Foreign CDB, 267
Pin Ordering Control, 186 Schematic CDB, 266
Routing Differential Pairs, 190 Design for Fabrication, 42
Critical Part Placement, 115 Hazards Display, 43
Cross Probe, 278 Design Grid, 137
Between Design Views, 278 Design Placement, 397
Design Architect Commands, 281 Design Reference Objects, 226
DXDesigner, 279 Design Review, 184
Xplore, 280 Design Status, 185
Cross Probe Select, 184 Hazards, 185
Crosshatch Patterns, 195 Signal Integrity Attributes, 185
Crosstalk, 177 Design Status, 185
Crosstalk Control, 191 Design Verification, 200
Ctrl Key, 347 Detail Views, 402
Curved Traces, 153 Detailed Views, 212
Annotation Mode, 213

Example, 214 Copying Objects with the Mouse and Ctrl

Modification and Annotation Modes, 403 key, 347
Modification Mode, 213 Create Polygon, 352
Device data mapping (DxD to Expedition), 65 Create Polyline, 352
DFF, 42, 201 Ctrl Key, 347
Hazards Display, 43 Dimension, 360
Dialog Boxes, 26 Dissolve Polygon, 353
Modeless Dialogs, 27 Dissolve Polyline, 353
Differences between Copy Circuit and Circuit Esc Key, 348
Move and Copy, 218 Graphics, 362
Differential Pair Routing, 190 Line, 370
Dimension, 347, 360 Line Widths, 349
Angle from X-Axis of Linear Element, 362 Moving an Object, 355
Angular Dimension Between Two Linear Objects, 363
Elements, 362 Pen Widths, 349
Icons, 360 Polygon, 382
Layer, 362 Polyline, 375
Non-stacked, 360 Properties, 362
Options, 361 Properties Dialog, 362
Place a Radius or Diameter Dimension, 362 Rectangle, 385
Place an ordinate dimension, 361 Redo, 349
Place Dimension along a linear dimension, Selecting Locations, 348
361 Selecting Objects, 348
Place dimension between two elements, Send Back, 355
361 Shift Key, 347
Place stacked dimension, 361 Snap Grid, 348
Stacked, 360 Tab Key, 347
Discard Plane Areas, 196 Text, 390
Display Control, 33, 163 Text Modification, 204
General Tab, 38 Toolbars, 349
Layer and Type Table, 35 Undo, 349
Layers Tab, 35 Units, 349
Parts Tab, 40 DRC, 200
Spacers, 37 Batch, 132
Virtual Pins, 40 Post Processing, 200
Dissolve Polygon, 353 Review DRC Hazards, 201
Dissolve Polyline, 353 Verifying Part Placement, 132
Dock, 46 DRC Violations after Mirroring, 238
Draw, 347 Drill Symbols and Charts, 207
Alt Key, 348 Dual Proecessor, 497
Angle Lock, 349 DXDesigner, 270, 273
Arc, 364 Cross Probe, 279
Bring Forward, 355 Steps for using Cross Probing, 279
Cancel, 349 DxDesigner to Expedition device data
Circle, 368 mapping, 65

DXF, 250 Partition Editor, 72

Character String Limitation, 252 PDB Editor, 64
Export, 250 Property Definition Editor, 64
Import, 250 Symbol Editor, 66
Microstation, 253 Visual IBIS Editor, 63
Dyna Plow, 157 Electrical Board Description, 69
Hockey Stick, 156 Electrical Board Description (EBD) Files, 64
Dynamic Teardrops and Breakout Traces, 183 Embedded Capacitors, 324
Embedded Components, 319
—E— Embedded Passives, 330
EBD files, 64, 69 DxDesigner, 319
ECO Report, 193 Integration with FabLink XE and
Editing Expedition PCB, 325
Selected Cells, 125 Parametric Components Capacitor, 332
Spare Part Numbers, 125 Parametric Components Resistor, 331
Editor Control, 89 Place Command Enhancements, 340
Auto Save, 46 Support in a DxDesigner and Design
Cells Tab, 94 Capture Flow, 319
Clusters and Rooms Tab, 94 Supported Embedded Technologies, 331
Design Grid, 137 Embedded Passives in Circuit Move and Copy,
Fanout Unused Single Pin Nets, 136 243
Filter Tab, 99 Instantiating Embedded Passive Devices,
General Setup Rules, 89 244
Gloss Tab, 96 Embedded Passives Technologies, 323
Grids Tab, 98 Embedded Resistors, 323
Jumpers Tab, 100 Enterprise 3000, 290
Net Selection Filter, 137 Esc Key, 348
Pad Entry Tab, 97 Etch Text, 118
Parts Tab, 92 Expedition PCB
Placement Checking, 136 Accelerator Keys, 28
Router Tuning Patterns, 136 Customizing the Interface, 29
Routes Tab, 95 Design Process, 75
Routing Costs, 135 Dialog Boxes, 26
Routing Rules, 136 Display Control, 33
Tuning Tab, 99 Draw, 347
Editors Function Keys, 28
Cell Editor, 67 Getting the most from graphics, 29
Common Properties, 64 Keyboard Entry, 27
IBIS Model Editor, 69 Keyins, 23
Import Symbols, 63 Mnemonics, 27
Library Manager Editors, 61 Modeless Dialogs, 27
Library Services, 62 Mouse Mappings, 19
Material and Process Editor, 68 Mouse Strokes, 21
Modify Cells and Symbols, 63 Net Classes and Clearances, 101
Padstack Editor, 70 Net Properties, 104
Part Manager, 69

Printing, 48 Fix
Reserved Areas, 111 Parts, 125
Saving Files, 45 Fixed Hanger, 175
Setup Procedure, 76 Fixing Parts, 125
Shortcut Keys, 28 Flip Horizontal, 354
Snap, 24 Flip Vertical, 354
Team PCB Split / Join Design, 437 Flow
Time Zone Constraints, 55 Design Architect, 276
Expedition to DxDesigner device data DXDesigner, 273
mapping, 65 Forced Order Nets, 186
Export Forced Plow, 155
DXF, 250 Hangers, 153
IDF, 247 Hockey Stick, 155
Foreign iCDB, 267
—F— Forward Annotation, 264
Fablink XE, 393 Database Load, 264
Cell Editor, 418 Netload, 264
Copper Balancing, 404 Function Keys, 28
Copper Balancing DRC, 410
Copper Balancing Processor, 407 —G—
Delete Copper Balance Data, 409 General Clearances for Via Rules, 83
Detailed Views, 402 General Comments on High Speed Nets, 186
Export IDF, 425 General Interfaces, 211
Import Gerber, 397 C-Link, 212
Import NCDrill, 399 FabMaster, 212
Layout Templates, 417 Generic AIS, 212
Library Services, 417 Generic ATE, 212
Licensing, 393 Hyperlynx Thermal, 212
Manufacturing Outline, 113, 425 Mitron GenCad, 212
Manufacturing Output Validation, 412 General Tab in Setup Parameters, 76
Neutral File, 412 Generating Reports, 185
Padstack Editor, 418 Generating Silkscreens, 204
Panel DRC, 416 Generic AIS, 212
Panel Wizard, 396 Generic ATE, 212
Placing Copper Balancing Shapes, 406 Gerber, 191
Setup Parameters, 416 274D, 210
Fabmaster, 212 274X, 209
FabMaster Panelization, 401 Custom Pads, 210
Fanout Unused Single Pin Nets, 136 D-Codes, 209
Fanout Vias, 177 Defining Screen Contents, 209
Cover Layers Example, 178 Gerber Machine Format, 211
Fences, 180 Header and Trailer Text, 209
File Viewer, 71 Polygon Fill Method, 211
Find Next Open Netline, 32 Gerber Import from Fablink XE, 397
Find with Circuit Move and Copy, 221 Gerber Machine Format, 211
Finishing Remaining Opens, 183 Polygon Fill Method, 211

Getting the most from graphics, 29 Enabling CES in Expedition PCB, 429
Dynamic Panning, 29 Licensing, 427
Next View, 29 IDF, 247
Previous View, 29 Buried Cells, 249
Gloss Export, 247
Fix States, 149 Import, 247
Glossing Principles, 149 Properties for Electrical Parts, 249
Guiding Principles, 150 XY Locations, 249
Modes, 149 IFF, 254
Semi-Fixed Traces, 149 Impedance Control, 187
Table of Posssibilities, 150 Import
Glossary, 511 DXF, 250
Graphics IDF, 247
Getting the Most From, 29 Import NCDrill for Fablink XE, 399
Object-Selection, 29 Import Symbols, 63
Zoom, 31 Incompatible Via Spans in Circuit Move and
Graphics in Draw Copy, 236
Cursors, 349 Instantation Wizard, 229
Handles, 349 Instantiation Wizard, 233
Origin Markers, 349 Physical Layers, 232
Selection Appearance, 349 Ref Des, 230
Group Length Control, 187 User Layers, 234
Guide Pins, 123 Integration
Back Annotation, 262
—H— CAE Netlist, 269
Hazards, 185 Cross Probe, 278
Header and Trailer Text, 209 Design Capture, 256
High Speed Nets, 186 DXDesigner, 279
Control Crosstalk, 191 DXF, 250
General Comments, 186 Enterprise 3000, 290
Group Length Control, 187 Foreign CDB, 267
Impedance Control, 187 Forward Annotation, 264
Length / Delay Control, 187 HyperLynx, 291
Pin Ordering Control, 186 ICX, 256
Routing Differential Pairs, 190 IDF, 247
hockey stick, 155 IFF, 254
Hug Traces, 148 Keyin Netlist, 268
HyperLynx, 291 Netlist Types, 266
Hyperthreaded Proecessor, 497 OBD++, 284
—I— OBDG Interface, 282
IBIS Model Editor, 69 OrCAD, 290
IBIS ver. 3.2, 69 Project Integration, 257
ICX, 256 Scepter, 290
ICX Pro HSR, 427 Schematic CDB, 266
DxDesigner to Expedition Flow, 428 Variant Manager, 282

Xplore, 280 —L—

XTK, 292 Laminate Designs for MicroVias, 295
Interactive Layer Directional Bias, 135
Routing, 137 Layer Pairs, 135
Interactive Placement, 117 Layer Stackup, 176, 187
Interactive Placement Modification Layout Template Cell Definition, 321
Copy Circuit, 129 Layout Templates, 70
Place Mode, 113 Length / Delay Control, 187
Rotate Parts, 128 Library Manager, 57
Snap to Grid, 127 Cell Editor, 67
Interactive Routing, 133 Editors, 61
Route, 161 File Viewer, 71
Route Mode, 134 IBIS Model Editor, 69
Interconnect Modification, 164 Layout Templates, 70
Interdigitated capacitors, 339 Library Services, 62
Invoking FabLink XE from within Expedition Material and Process Editor, 68
PCB, 395 Padstack Editor, 70
IPC-D-356B, 401 Part Manager, 69
Partition Editor, 72
—J— Partition Search Paths, 72
Join Design, 437, 446
PDB Editor, 64
Creating Reserved Areas, 442
PDF Documenter, 70
Design Flow, 439
Property Definition Editor, 64
License
Property Verification, 71
Restrictions, 438
Reusable Blocks, 69
Licensing, 437
Setup Parameters, 73
Partitions, 447
Symbol Editor, 66
Terminology, 438
Units Display, 73
—K— Unreserve Partitions, 72
Key Utilities, 61
Alt, 348 Library Navigation Tree viewer (DxD-
Ctrl, 347 Expedition Library Manager), 60
Esc, 348 Library Services, 62
Shift, 347 Importing Parts and Cells, 62
Tab, 347 Licensing Assistance, 56
Keyboard Entry, 27 Licensing for Fablink XE, 393
Function Keys, 28 Acquiring, 393
Mnemonics, 27 Standalone, 393
Keyin Netlist, 268 Through Expedition PCB License Option,
Keyins, 23 395
Moving Parts by File, 23 Through Expedition PCB Splash Screen,
keyins 394
Moving Parts with the Arrow Keys, 24 Licensing for ICX Pro HSR, 427
keyword Auto, 180 Licensing for Split / Join Design, 437
Line, 370

Add, 371 Buildup Rule 3, 297

Alt Add, 371 Buildup Rule2, 297
Alt Move, 374 Example 1, 298
Alt Stretch, 374 Example 2, 299
Angle, 371 Example 3, 299
Ctrl Move, 374 Example 4, 301
Ctrl Stretch a Center Point Handle, 374 Examples of Laminate and Buildup
Drag & Release Events, 371, 377 Fanouts, 298
Length, 370 Fanout with Micro and Blind/Buried Vias,
Line Width, 370 295
Move, 373 Laminate, 295
Operation, 371 Laminate Designs, 295
Selection, 371 Laminate Rule 1, 295
Shift Add, 371 Laminate Rule 2, 296
Shift Move, 373 Laminate Rule 3, 296
Shift Stretch an End Point Handle, 374 Middle Button Strokes, 21
Stretch a Center Point Handle, 374 Migrating Existing Plane Data, 197
Stretch an End Point Handle, 374 Minimum Distance, 25
Two Click Events, 371, 377 Mirror in Circuit Move and Copy, 237
Vertices, 371 Mitron GenCad, 212
LocalPartsDB.pdb File, 64 Modeless Dialogs, 27
Modify Cells and Symbols, 63
—M— Modify Corners, 184
MainWin Control Panel, 49 Mounting Holes, 114
Manufacturing Cleanup, 184 Mouse Mappings, 19
Manufacturing Outline, 113, 425 Alternate Mouse Mappings, 20
Manufacturing Output Validation, 412 Default Mouse Mappings, 20
Error Processing, 415 Middle Button Strokes, 21
Package Creation, 414 Mouse Strokes, 21
Pre-Validation Checks, 413 Move
Validation Process, 414 Circuit, 127
Mapping DxDesigner device data to PDB, 65 Grouped parts, 113, 126
Mapping Expedition to DxDesigner device Part, 125
data, 65 Reusable blocks, 113, 126
Matched Length Group, 188 Move Circuit
Material Process Editor, 68, 329 BGA, 127
Embedded Capacitors, 330 Plane Net Fanouts, 127
Embedded Resistors, 330 Moving an object in Draw, 355
Measure, 32 Moving Circuits, 216
Mechanical Verification, 133 Moving Parts by File, 23
Mezzanine Capacitors, 324 File Syntax, 24
Mezzanine capacitors, 337 Moving Parts with the Arrow Keys, 24
Microvia Routing Strategy, 295 Moving Traces and Vias in Route Mode, 138
Buildup, 295 MST Net, 118
Buildup Designs, 296 Multi Plow, 157
Buildup Rule 1, 296

Multiple Equivalent Circuit Instances, 219 —O—

Multiple Via Objects, 85, 139 OBD++, 284
Affected Commands, 141 Compress Output, 288
ASCII File Format, 146 Creating Special Properties, 289
Principles, 140 Defining the Additional Parameters, 286
Unsupported Items, 145 Defining the Basic Export Options, 285
Defining the Output Options, 285
—N— Defining the Pins, Pads, Via and Package
NC Drill, 205
Options, 286
Symbols and Charts, 207
Defining User Layer Mapping, 288
Negative Planes
OBDG Interface, 282
Advantages and Disadvantages, 195
Object-Action Commands, 30
Nested Cells, 116
Adding to Selected Items, 31
Rules within IDF Import and Export, 117
Selecting a Surface Mounted Device
Rules within PCB, 117
(SMD), 30
Rules within the Cell Editor, 68
ODBG ++
Net Classes and Clearances, 101
DRC Features, 288
Net Maniuplation
Optimizer, 332
Custom, 118
OrCAD Interface, 290
Net Properties, 104
Origin
Net Selection Filter, 137
Board, 114
Netline Manipulation, 118
Origin Markers in Draw, 349
Cell Types, 121
Outline
Chained, 118
Board, 113
Chained Order Algorithm, 120
Manufacturing, 113
Design Capture Properties and Symbols,
121 —P—
Guide Pins, 123 Packaging
MST, 118 Parts in Expedition Central Library, 64
Parts Database Attributes, 120 Padstack Editor, 70
Unrecognized Pins Become Loads, 121 Padstack Processor, 194
Virtual Pin Characteristics, 121 Pan, 32
Netlist Panel DRC, 416
Design Architect, 272 Panel Wizard, 396
DXDesigner, 270 Parametric Cell Creation, 321
Netlist Types, 266 Parametric Pad Definition, 322
CAE, 269 Part Numbers
Design Architect, 272 Editing, 125
DXDesigner, 270 Part Placement, 115
Foreign CDB, 267 Critical Parts, 115
Keyin, 268 Interactive Placement, 117
Schematic CDB, 266 Location Fields, 116
Nets, 180 Nested Cells, 116
Neutral File, 412 Push Back Parts, 116
Notation Settings, 73 Rotation Fields, 116

Partition Editor, 72 Swap Pins, 131

Partition Search Paths, 72 Placement Improvement Process, 124
Permissions, 72 Placement Modification
Partitions, 59 Automatic, 131
Cell Editor, 67 Placement Verification, 132
Partition Editor, 72 Plane Assignments, 197
Search Paths, 72 Plane Classes and Parameters, 194
Symbol Editor, 67 Plane Clearances and Parameters
Unreserve Partitions, 72 Positive Planes, 194
Partitions in Split / Join Design, 447 Plane Data Migration of Existing Data, 197
Command List, 448 Plane Shapes, 109
Routing in a Partition, 447 Planes
Save Function, 447 Signal Flooded, 197
Parts Planes Handling, 161
Pushing Parts with Traces, 128 Characteristic Impedance, 161
Rotation, 128 Plane Nets, 161
Parts Manager, 69 Velocity of Propagation, 161
Pasting Circuits, 217 Planes Processor
PDB Editor, 64 Crosshatch Patterns, 195
EBD Files, 64 Discard Plane Areas, 196
LocalPartsDB.pdb File, 64 Heat Dissipation, 194
PDF Documenter, 70 Plane Data, 194
Physical Layers, 233 Shielding Sensitive Signals, 194
Pin Ordering Control, 186 Split Planes, 196
Pin Package Length, 189 Plotting Archive Plots, 214
Place Plow
Contour, 115 Angle, 156
DRC Window, 200 Curved Traces, 153
Etch Text, 118 Dyna, 156
Part, 115 Forced, 155
Test Point, 192 Multi, 157
Test Points from File, 193 Route, 156
Place Copper Balancing Shapes, 406 Polar Placement, 132
Place Mode, 113 Polygon, 382
Placement and Routing of Target Areas, 168 Chamfer, 383
Placement Improvement Corner, 382
Automatic Swap by Cell Name, 131 Display center handles, 384
Automatic Swap by Part Number, 132 Ending the polygon, 385
Back Annotation, 124 Fill, 384
Fixing Parts, 125 Grow/Shrink, 384
Move Circuit, 127 Origin X, Y, 384
Move Part, 125 Round, 382
Push Part, 128 Vertex Type, 382
Swap Gates, 130 Vertices, 384
Swap Parts, 130 Polyline, 375

A Diamond on an Arc, 382 Renumber Reference Designators, 203

A Line Segment Attached to An Arc, 381 Running Batch DFF, 201
A Line Segment Attached to Another Line Running Batch DRC, 200
Segment, 380 Test Points, 192
Add, 377 Text Modification using Draw, 204
Additional Segments, 378 Principles of Multiple Via Objects, 140
Chamfer, 376 Printing, 48
Corner, 376 Setting Up, 50
Cursors at vertex and center handles, 379 Sun Solaris, HP-UX, Linux, 48
Display center handles, 377 Using the Visual MainWin Control Panel to
Ending the Polyline, 378 configure Printers, 49
Ending the polyline, 382 Windows, 48
Intersection between lines, 378 Process, 180
Line Segment and an Arc(s), 380 Process Flow
Line Segment Attached to an Arc, 382 Board Setup, 112
Line Width, 375 Project Indicator Light in Layout, 258
Operation, 377 Project Integration, 257
Origin X,Y, 377 Back Annotation Options, 262
Overlapping Segments, 378 CES Integration, 265
Round, 376 Design Architect, 272
Selection, 378 Disabled Forward Annotation / Back
Shift Add While Adding a Line, 378 Annotation - DC Flow, 261
Shift Stretch an End Point Handle, 382 Disabled Forward Annotation / Back
Starting With a Line, 377 Annotation - DxDesigner Flow, 260
Starting With an Arc, 377 DXDesigner, 270
Stretch a Center Point Handle, 380 Forward and Back Annotation Order, 260
Stretch an End Point Handle, 380 Library Extraction, 261
Two Line Segments, 380 Library Extraction Options, 261
Vertex Type, 376 Load pending schematic CES changes into
Vertices, 377 PCB, 260
Positive Planes, 194 Loading PCB CES Data, 260
Advantages and Disadvantages, 195 Roll Back Constraint Changes Warning,
Post Processing, 191 266
CAM Files, 191 Schematic Connectivity and Constraint
Design Verification, 200 Status Section, 259
Documentation, 191 Synchronization Options, 260
General Interfaces, 211 Trace Removal Options, 262
Generating Silkscreen, 204 Properties Dialog
Gerber, 191 Confirming Text Fields, 363
Gerber 274D, 210 Multiple Selections, 363
Gerber 274X, 209 Property List, 363
Gerber Custom Pads, 210 Type, 363
NC Drill, 205 Properties in Draw, 362
Padstack Processor, 194 Property Definition Editor, 64
Plane Classes and Parameters, 194 centlib.prp Default File, 64

Property Verification, 71 Definitions, 318

Push, 126 Reusable Blocks in Circuit Move and Copy,
Part, 128 236
Parts with Traces, 128 Review Design, 183, 184
Push in Circuit Move and Copy, 241 Review DRC Violations, 201
File Viewer, 201
—R— RF Shapes and Groups in Circuit Move and
Recalculation of Buses, 166 Copy, 242
Rectangle, 385 Copy Selection, 243
Add, 386 Instantiating RF Shapes, 243
Alt Move, 388 Move and Rotate Selection, 242
Alt Stretch, 390 RF Elements in the Instantiation Wizard,
Convert to Polygon, 385 243
Ctrl Move, 388 Roll Back Constraint Changes Warning, 266
Display center handles, 386 Rotate, 355
Drag & Release Events, 386 Rotate 180, 126
Fill, 385 Rotate 90, 126
Grow/Shrink, 386 Rotate Parts, 128
Height, 386 Route, 161
Key in, 386 Changing a Trace Width, 175
Line Width, 385 Critical Nets, 178
Move, 387 Display Control, 112
Operation, 386 Interconnect Modification, 164
Origin X, Y, 386 Layer Stackup, 176
Rotate, 388 Modify Corners, 184
Selection, 387 Moving Traces and Vias, 138
Selection Handles, 387 Netline Manipulation, 118
Shift Move, 388 Planes Handling, 161
Shift Stretch, 389 Remove Hanger, 175
Stretch, 388 Routing Process Flow, 177
Two Click Events, 386 Rules, 136
Vertices, 386 Route Border, 114
Width, 386 Route Mode, 155
Reference Designators Route Obstruct, 111
Renumbering, 203 Route Plow, 156
Remap Layers, 77 Router, 180
Remove Hanger, 175 Routing, 133
Renumbering Reference Designators, 203 Automatic, 133
Replace Cell, 176 Bus, 166
Reports Generating, 185 Interactive, 133
Reroute, 175 Saving, 134
Reserved Areas, 111, 442 Semi-Automatic, 152
Creating, 442 Routing Costs, 135
Reserved Layer Names, 88 Routing Process Flow, 177
Retrieving a Circuit, 222 Fanout Vias, 177
Reusable Blocks, 69, 309

Finishing Remaining Opens, 183 Selection Filter Objects, 226

Manufacturing Cleanup, 184 Semi-Automatic Routing, 152
Move Parts, 182 Send Back in Draw, 355
Review Design, 183 Setting up Expedition PCB, 76
Routing Critical Nets, 178 Editor Control, 89
Running the Auto Router, 182 Setting up printers, 50
Routing Rules for Buses, 167 Setting up the System Service on Windows,
Routing Steps for Bus Route, 167 492
Rule Areas, 303, 455, 487 Setup Parameters, 73, 76
Rule for adding the cursor images at shared end Buried Resistors and Rise Time, 87
points Default Via Padstack, 78
Alt Move, 380 Multiple Via Objects, 85
Ctrl Move, 380 Remap Layers, 77
Move, 379 Reserved Layer Names, 88
Shift Move, 379 Same Net Via Span to Via Span
Rules within IDF Import and Export for Nested Clearances, 84
Cells, 117 Skip Vias, 80
Rules within PCB for Nested Cells, 117 Trace to Via Clearance, 84
Rules within the Cell Editor for Nested Cells, Via Clearances Tab, 83
68 Via Definitions Tab, 78
Running Batch DRC, 200 Setup Rules for Editor Control, 89
Shielding Sensitive Signals, 194
—S— Shortcut Keys, 28
Save Schemes in Push and Change Layer, 236 Signal Flooded Planes, 197
Saving Signal Integrity Attributes, 185
Auto Save in the Auto Router, 46 Skip Vias, 80
AutoSave Option in Editor Control, 46 SMD Pads, 186
Save Copy, 45 Snap, 24
Saving Your Work Process, 134 Snap Grid, 348
Scepter, 290 Add, 348
Schematic CDB, 266 Appearance, 351
Schematic Integration, 256 Key in, 348
Back Annotation, 256 Move, 348
Forward Annotation, 256 Stretch, 348
Schematic Parametric Symbol Definition, 320 Snap to Grid, 126, 127
Screen Contents Definition, 209 Spacers
Screen Printed Capacitors, 325 Display Control, 37
Screen printed capacitors, 338 Specific, 180
Search Paths, 59 Specific Nets Example, 180
Select Split Design, 437, 445
Adding to Selected Items, 31 Creating Reserved Areas, 442
Area, 31 Design Flow, 439
Surface Mounted Device, 30 License
Selecting Locations in Draw, 348 Restrictions, 438
Selecting Objects in Draw, 348 Licensing, 437
Selection Filter Layers, 225

Partitions, 447 ECO Report

Terminology, 438 test_eco.txt, 193
Update from Other Partitions, 448 Floating, 193
Split Planes, 195 Place from File, 193
Straight Line Interconnects Auto Route Pass, Report Generator, 193
171 Test Summary Report, 193
Stub Length, 187 test_eco.txt, 193
Subtractive Resistors, 335 testptsum##.txt File, 193
Sun Solaris, HP-UX and Linux Printing, 48 Text, 390
Support Add, 392
Licensing Assistance, 56 Alt Move, 392
Swap Display only Gerber-compatible fonts, 391
Crossing Netlines, 131 Height, 391
Gates, 130 Location X, Y, 392
Parts, 130 Mirror, 391
Pins, 131 Move, 392
Symbol Editor, 66 Operation, 392
Partitions, 67 Pen width, 391
Rotation, 391
—T— Selection, 392
Tab Key, 347 String, 392
Target Areas Text, 391
Automatic Placement, 173 Text origin, 391
Guidelines, 169 Text Draw Toolbar, 360
Input and Formula Parameters for Text Modification using Draw, 204
Automatic Calculation of Target Time Zone Constraints, 55
Areas, 173 Toggle Button in Draw
Interactive Moving of Routed/Partially Default, 350
Routed Target Areas, 172 Selection Methodology, 350
PCB Design Flow, 170 Toggle Parametric, 341
Placement and Routing, 168 Toolbars in Draw
Route and Auto Routing, 171 Angle Lock, 351
Straight Line Interconnects Auto Route Create Polyline or Polygon, 352
Pass, 171 Delete End Point Handle, 353
Supported Functionality, 170 Dissolve Polyline or Polygon, 353
Unsupported Functionality, 170 Flip Horizontal, 354
Target Length TOF Delay, 432 Flip Vertical, 354
Team PCB in Circuit Move and Copy, 244 Join, 352
Move, 245 Multi-State, 350
Paste and Instantiation, 245 Polygon Select, 350
Rotate, 245 Push Button, 350
Selection, 244 Rotate, 355
Technology Setup, 177 Snap to Grid, 351
Test Points, 192 Text, 360
Cell Editor, 192 Toggle Button, 350
Delete, 193

Trim, 354 Same Net Via Span to Via Span

Tooling Holes, 114 Clearances, 84
Trace Width Virtual Pins
Changing, 175 Characteristics, 121
Trim, 354 Visual IBIS Editor, 63
Tune, 188
Tuned Nets, 179 —W—
Tuning Ellipse, 187 Working with High Speed and Critical Nets,
Tuning Meter, 136 186
Crosstalk Control, 191
—U— Differential Pair Routing, 190
Undock, 47 Group Length Control, 187
Units Display, 73 Impedance Control, 187
Precision and Format, 73 Length/Delay Control, 187
Working Units, 73 Pin Ordering Control, 186
Unreserve Partitions, 72
Update from Other Partitions, 448 —X—
Using the Visual MainWin Control Panel to Xplore
configure Printers, 49 Cross Probe, 280
Utilities Design Architect Commands, 281
Library Manager Utilities, 61 Invoking from Design Architect, 281
Invoking from Expedition, 280
—V— XTK, 292
Variant Manager, 282 Xtreme PCB, 455, 487
vb_ais.tx, 212 Accepting the Interrupt, 463
vb_ate.txt, 212 Adding Clients to the XDS dialog, 470
Velocity of Propagation, 161 Client Design Crashes, 459
Verify Client Licenses, 465
Mechanical, 133 Client Saves in the Design Environment,
Placement, 132 464
Via Clearances Command Listing, 479
Setup Parameters, 83 Ending an Xtreme Client Session, 469
Via Definitions Force Field Effects and Conflicts, 474
Setup Parameters, 78 Force Field Priority calculations, 473
Via Obstruct, 111 Force Fields, 472
Vias Interrupt Acceptance, 463
Adding Vias Using the Display Control Joining and Ending and Xtreme Design
Menu, 163 Session, 469
Adding Vias with the Space Bar, 162 Multiple Windows within the Editors, 457
Allowed Padstacks, 78 Network Crash, 459
Clearances, 85 Overview, 457
Connected by a Single Trace, 84 Protected Areas, 474
General Via Span to Via Span Clearances, Rules of Protected Areas, 475
83 Read this before you begin, 455
Padstack, 78 Rejecting an Interrupt, 462
Saving in the Design Environment, 464

Session Crash, 459

Starting an Interrupt, 461
Starting an Xtreme Design Session, 464
Stopping an Xtreme Design Session, 471
Undo and Redo Commands, 460
User Analysis, 459
Using CES with Xtreme PCB, 458
Xtreme Design Client, 456
Xtreme Design Client End Session, 469
Xtreme Design Session, 455
Xtreme Design Session Rejecting
Commands, 460
—Z—
Zoom
Graphics, 31


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and assigns. The provisions of this section 4 shall survive the termination or expiration of this Agreement.
5. LIMITED WARRANTY.
5.1. Mentor Graphics warrants that during the warranty period Software, when properly installed, will substantially
conform to the functional specifications set forth in the applicable user manual. Mentor Graphics does not warrant
that Software will meet your requirements or that operation of Software will be uninterrupted or error free. The
warranty period is 90 days starting on the 15th day after delivery or upon installation, whichever first occurs. You
must notify Mentor Graphics in writing of any nonconformity within the warranty period. This warranty shall not be
valid if Software has been subject to misuse, unauthorized modification or improper installation. MENTOR
GRAPHICS' ENTIRE LIABILITY AND YOUR EXCLUSIVE REMEDY SHALL BE, AT MENTOR GRAPHICS'
OPTION, EITHER (A) REFUND OF THE PRICE PAID UPON RETURN OF SOFTWARE TO MENTOR
GRAPHICS OR (B) MODIFICATION OR REPLACEMENT OF SOFTWARE THAT DOES NOT MEET THIS
LIMITED WARRANTY, PROVIDED YOU HAVE OTHERWISE COMPLIED WITH THIS AGREEMENT.
MENTOR GRAPHICS MAKES NO WARRANTIES WITH RESPECT TO: (A) SERVICES; (B) SOFTWARE
WHICH IS LICENSED TO YOU FOR A LIMITED TERM OR LICENSED AT NO COST; OR
(C) EXPERIMENTAL BETA CODE; ALL OF WHICH ARE PROVIDED “AS IS.”
5.2. THE WARRANTIES SET FORTH IN THIS SECTION 5 ARE EXCLUSIVE. NEITHER MENTOR GRAPHICS
NOR ITS LICENSORS MAKE ANY OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, WITH
RESPECT TO SOFTWARE OR OTHER MATERIAL PROVIDED UNDER THIS AGREEMENT. MENTOR
GRAPHICS AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT OF
INTELLECTUAL PROPERTY.
6. LIMITATION OF LIABILITY. EXCEPT WHERE THIS EXCLUSION OR RESTRICTION OF LIABILITY

WOULD BE VOID OR INEFFECTIVE UNDER APPLICABLE LAW, IN NO EVENT SHALL MENTOR GRAPHICS
OR ITS LICENSORS BE LIABLE FOR INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES
(INCLUDING LOST PROFITS OR SAVINGS) WHETHER BASED ON CONTRACT, TORT OR ANY OTHER
LEGAL THEORY, EVEN IF MENTOR GRAPHICS OR ITS LICENSORS HAVE BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES. IN NO EVENT SHALL MENTOR GRAPHICS' OR ITS LICENSORS'
LIABILITY UNDER THIS AGREEMENT EXCEED THE AMOUNT PAID BY YOU FOR THE SOFTWARE OR
SERVICE GIVING RISE TO THE CLAIM. IN THE CASE WHERE NO AMOUNT WAS PAID, MENTOR
GRAPHICS AND ITS LICENSORS SHALL HAVE NO LIABILITY FOR ANY DAMAGES WHATSOEVER. THE
PROVISIONS OF THIS SECTION 6 SHALL SURVIVE THE EXPIRATION OR TERMINATION OF THIS
AGREEMENT.
7. LIFE ENDANGERING ACTIVITIES. NEITHER MENTOR GRAPHICS NOR ITS LICENSORS SHALL BE
LIABLE FOR ANY DAMAGES RESULTING FROM OR IN CONNECTION WITH THE USE OF SOFTWARE IN
ANY APPLICATION WHERE THE FAILURE OR INACCURACY OF THE SOFTWARE MIGHT RESULT IN
DEATH OR PERSONAL INJURY. THE PROVISIONS OF THIS SECTION 7 SHALL SURVIVE THE
EXPIRATION OR TERMINATION OF THIS AGREEMENT.
8. INDEMNIFICATION. YOU AGREE TO INDEMNIFY AND HOLD HARMLESS MENTOR GRAPHICS AND ITS
LICENSORS FROM ANY CLAIMS, LOSS, COST, DAMAGE, EXPENSE, OR LIABILITY, INCLUDING
ATTORNEYS' FEES, ARISING OUT OF OR IN CONNECTION WITH YOUR USE OF SOFTWARE AS
DESCRIBED IN SECTION 7. THE PROVISIONS OF THIS SECTION 8 SHALL SURVIVE THE EXPIRATION OR
TERMINATION OF THIS AGREEMENT.
9. INFRINGEMENT.
9.1. Mentor Graphics will defend or settle, at its option and expense, any action brought against you alleging that
Software infringes a patent or copyright or misappropriates a trade secret in the United States, Canada, Japan, or
member state of the European Patent Office. Mentor Graphics will pay any costs and damages finally awarded
against you that are attributable to the infringement action. You understand and agree that as conditions to Mentor
Graphics' obligations under this section you must: (a) notify Mentor Graphics promptly in writing of the action;
(b) provide Mentor Graphics all reasonable information and assistance to defend or settle the action; and (c) grant
Mentor Graphics sole authority and control of the defense or settlement of the action.
9.2. If an infringement claim is made, Mentor Graphics may, at its option and expense: (a) replace or modify Software so
that it becomes noninfringing; (b) procure for you the right to continue using Software; or (c) require the return of
Software and refund to you any license fee paid, less a reasonable allowance for use.
9.3. Mentor Graphics has no liability to you if infringement is based upon: (a) the combination of Software with any
product not furnished by Mentor Graphics; (b) the modification of Software other than by Mentor Graphics; (c) the
use of other than a current unaltered release of Software; (d) the use of Software as part of an infringing process; (e) a
product that you make, use or sell; (f) any Beta Code contained in Software; (g) any Software provided by Mentor
Graphics’ licensors who do not provide such indemnification to Mentor Graphics’ customers; or (h) infringement by
you that is deemed willful. In the case of (h) you shall reimburse Mentor Graphics for its attorney fees and other costs
related to the action upon a final judgment.
9.4. THIS SECTION IS SUBJECT TO SECTION 6 ABOVE AND STATES THE ENTIRE LIABILITY OF MENTOR
GRAPHICS AND ITS LICENSORS AND YOUR SOLE AND EXCLUSIVE REMEDY WITH RESPECT TO
ANY ALLEGED PATENT OR COPYRIGHT INFRINGEMENT OR TRADE SECRET MISAPPROPRIATION
BY ANY SOFTWARE LICENSED UNDER THIS AGREEMENT.
10. TERM. This Agreement remains effective until expiration or termination. This Agreement will immediately terminate
upon notice if you exceed the scope of license granted or otherwise fail to comply with the provisions of Sections 1, 2, or
4. For any other material breach under this Agreement, Mentor Graphics may terminate this Agreement upon 30 days
written notice if you are in material breach and fail to cure such breach within the 30 day notice period. If Software was
provided for limited term use, this Agreement will automatically expire at the end of the authorized term. Upon any
termination or expiration, you agree to cease all use of Software and return it to Mentor Graphics or certify deletion and
destruction of Software, including all copies, to Mentor Graphics’ reasonable satisfaction.
11. EXPORT. Software is subject to regulation by local laws and United States government agencies, which prohibit export
or diversion of certain products, information about the products, and direct products of the products to certain countries
and certain persons. You agree that you will not export any Software or direct product of Software in any manner without
first obtaining all necessary approval from appropriate local and United States government agencies.
12. RESTRICTED RIGHTS NOTICE. Software was developed entirely at private expense and is commercial computer
software provided with RESTRICTED RIGHTS. Use, duplication or disclosure by the U.S. Government or a U.S.
Government subcontractor is subject to the restrictions set forth in the license agreement under which Software was
obtained pursuant to DFARS 227.7202-3(a) or as set forth in subparagraphs (c)(1) and (2) of the Commercial Computer
Software - Restricted Rights clause at FAR 52.227-19, as applicable. Contractor/manufacturer is Mentor Graphics
Corporation, 8005 SW Boeckman Road, Wilsonville, Oregon 97070-7777 USA.
13. THIRD PARTY BENEFICIARY. For any Software under this Agreement licensed by Mentor Graphics from Microsoft
or other licensors, Microsoft or the applicable licensor is a third party beneficiary of this Agreement with the right to
enforce the obligations set forth herein.
14. AUDIT RIGHTS. You will monitor access to, location and use of Software. With reasonable prior notice and during
your normal business hours, Mentor Graphics shall have the right to review your software monitoring system and
reasonably relevant records to confirm your compliance with the terms of this Agreement, an addendum to this
Agreement or U.S. or other local export laws. Such review may include FLEXlm or FLEXnet report log files that you
shall capture and provide at Mentor Graphics’ request. Mentor Graphics shall treat as confidential information all of your
information gained as a result of any request or review and shall only use or disclose such information as required by law
or to enforce its rights under this Agreement or addendum to this Agreement. The provisions of this section 14 shall
survive the expiration or termination of this Agreement.
15. CONTROLLING LAW, JURISDICTION AND DISPUTE RESOLUTION. THIS AGREEMENT SHALL BE
GOVERNED BY AND CONSTRUED UNDER THE LAWS OF THE STATE OF OREGON, USA, IF YOU ARE
LOCATED IN NORTH OR SOUTH AMERICA, AND THE LAWS OF IRELAND IF YOU ARE LOCATED
OUTSIDE OF NORTH OR SOUTH AMERICA. All disputes arising out of or in relation to this Agreement shall be
submitted to the exclusive jurisdiction of Portland, Oregon when the laws of Oregon apply, or Dublin, Ireland when the
laws of Ireland apply. Notwithstanding the foregoing, all disputes in Asia (except for Japan) arising out of or in relation to
this Agreement shall be resolved by arbitration in Singapore before a single arbitrator to be appointed by the Chairman of
the Singapore International Arbitration Centre (“SIAC”) to be conducted in the English language, in accordance with the
Arbitration Rules of the SIAC in effect at the time of the dispute, which rules are deemed to be incorporated by reference
in this section 15. This section shall not restrict Mentor Graphics’ right to bring an action against you in the jurisdiction
where your place of business is located. The United Nations Convention on Contracts for the International Sale of Goods
does not apply to this Agreement.
16. SEVERABILITY. If any provision of this Agreement is held by a court of competent jurisdiction to be void, invalid,
unenforceable or illegal, such provision shall be severed from this Agreement and the remaining provisions will remain in
full force and effect.
17. PAYMENT TERMS AND MISCELLANEOUS. You will pay amounts invoiced, in the currency specified on the
applicable invoice, within 30 days from the date of such invoice. Any past due invoices will be subject to the imposition
of interest charges in the amount of one and one-half percent per month or the applicable legal rate currently in effect,
whichever is lower. Some Software may contain code distributed under a third party license agreement that may provide
additional rights to you. Please see the applicable Software documentation for details. This Agreement may only be
modified in writing by authorized representatives of the parties. Waiver of terms or excuse of breach must be in writing
and shall not constitute subsequent consent, waiver or excuse.
Rev. 060210, Part No. 227900

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Expedition™ PCB User’s Guide

Software Release EE2007.1

© 1998-2007 Mentor Graphics Corporation

RESTRICTED RIGHTS LEGEND 03/97

Expedition PCB User’s Guide, EE2007.1 3

4 Expedition PCB User’s Guide, EE2007.1

General Tab in Setup Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Expedition PCB User’s Guide, EE2007.1 5

Nested Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

6 Expedition PCB User’s Guide, EE2007.1

Expedition PCB User’s Guide, EE2007.1 7

Finish Remaining Opens. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

8 Expedition PCB User’s Guide, EE2007.1

Hyperlynx Thermal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Expedition PCB User’s Guide, EE2007.1 9

Instantiation Wizard User Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

10 Expedition PCB User’s Guide, EE2007.1

Steps to translate a DA schematic to Expedition PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

Expedition PCB User’s Guide, EE2007.1 11

12 Expedition PCB User’s Guide, EE2007.1

Expedition PCB User’s Guide, EE2007.1 13

Rendered Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399

14 Expedition PCB User’s Guide, EE2007.1

Panel Cell Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425

Expedition PCB User’s Guide, EE2007.1 15

Xtreme PCB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455

16 Expedition PCB User’s Guide, EE2007.1

Expedition PCB User’s Guide, EE2007.1 17

18 Expedition PCB User’s Guide, EE2007.1

If you want to:

Expedition PCB User’s Guide, EE2007.1 19

Default Mouse Mappings

Alternate Mouse Mappings

20 Expedition PCB User’s Guide, EE2007.1

Table 1-2. Alternate Mouse Mappings

Middle Button Strokes

Expedition PCB User’s Guide, EE2007.1 21

Table 1-4. Stroke Recognition Grid

Stroke Action Grid

Report Selected 1474123

View Area 159

View All 951

Zoom Out 753

Turns On / Off Netlines 321478965

22 Expedition PCB User’s Guide, EE2007.1

Stroke Action Grid

Display Control 1478

Editor Control 14569

Auto Finish (Plow) 258

Move (Place Mode) 74159

Moving Parts by File

Expedition PCB User’s Guide, EE2007.1 23

{.units <in> | <mm> | <th> |<um> }

.ref <ref_des> {cellname=<cellname>} <xy> <rot> <top|bottom> { fix |

Moving Parts with the Arrow Keys

• Select a point and start a drawing element

24 Expedition PCB User’s Guide, EE2007.1

• Align two elements

Snap placement in space (no element attached)

With grid lock on the snap point is placed on the grid.

Select Place Tentative or Static snap.

Measure > Minimum Distance

Expedition PCB User’s Guide, EE2007.1 25