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15mm
elements and the feed-network can be realized using currently
available multi-layered printed circuit board fabrication
techniques.
I. INTRODUCTION
Since the launch of SIR-C/X-SAR in 1994, space-borne
polarimetric SAR with quadrature-polarimetric (quad-pol) or
dual-polarimetric (dual-pol) modes of operations has captured
great interest and enabled a wide range of remote sensing
applications [1]. In this paper, we present the design of a dual-
ii. Bottom View showing asymmetric stripline to
polarized active antenna sub-array and T/R modules that can be microstrip line transition)
used in a full-polarimetric X-band SAR system. The array
element is based on an aperture-coupled stacked patch (a) Unit cell with 2 array elements
operating at 9.65GHz. Aperture-coupled stacked patch Layer 1
antennas had been used in several SAR applications [2]-[4]. 5880 [20]
Layer 2
The unique feature in our proposed array element design is the 2929 [4]
broad bandwidth that is achieved without using foam layer, and Layer 3 Parasitic Patch
5880 [30]
its realization using existing multilayer printed circuit board Layer 4
(PCB) fabrication process. Further, the feed network for each 2929 [4]
Layer 5 Active Patch
sub-array is implemented with an optimal number of layers in a 5880 [20]
element design, the feed network for each sub-array with 1×16
Layer 9 Asymmetric
s-via Stripline
5880 [20] g-via1
elements and the corresponding T/R module architecture will Layer 10
Feed Line Ground
be discussed. 2929 [4]
Layer 11 Feed Line Ground
5880 [10]
Layer 12 CPWG
II. ARRAY ELEMENT DESIGN g-via2
978-1-4673-7297-8/15/$31.00 2015
c IEEE 139
A parasitic patch is added to the top surface of the
superstrate to increase the impedance bandwidth, and is
covered by another substrate on top. Further, an offset-
slot feed to obtain higher bandwidth [3] and the feed
lines for both polarizations are located on the same
substrate layer. In the current design, broad bandwidth is
achieved without using foam layer, typically used in such
antenna design [4]. The parasitic patch is printed on the
bottom surface of the top-most substrate. Thus the top
substrate serves as a radome for the array. The array is
designed for an elevation (across-track) scan of ±20° and
an azimuth (along-track) scan of ±1°. The limited scan
range in azimuth and wide scan range in elevation leads
to a sub-array of 1×16 elements with dimensions of (a) Vertical Polarization
240mm×15mm. Each tile of dimensions 240mm ×
120mm contains 8 such linear sub-arrays aligned
vertically, and is realized as a multilayered PCB, based
on low loss Rogers Duroid 5880 substrate as core and
Rogers 2929 bondply as the pre-preg. The design takes
into account existing limitations and capabilities of
multilayer printed circuit board fabrication processes for
signal and ground vias required in the 16-way corporate
feed network. A 12-layered PCB configuration with
standard thickness for substrate and bondply is adopted.
The feedline for each of the patch element is based on an
asymmetric stripline which provides efficient aperture
coupling to the radiating patch. H-shaped slots (one for
each polarization) are used in the ground plane for wide- (b) Horizontal Polarization
band aperture coupling. Individual array element is
designed to be matched to an impedance of 100Ω. This
enables the first level of the feed network, i.e., the
combining of 2 adjacent elements in the asymmetric
stripline layer, to be matched to 50Ω. After the first level
of combining in the asymmetric stripline, subsequent
feed network is realized in a lower layer as a coplanar
waveguide. The transition from coplanar waveguide to
the inner asymmetric stripline is realized using a blind-
via (signal-via) with additional horse-shoe shaped ground
vias. The geometry of two adjacent unit elements and the
2-way reactive power divider and via transition is shown
in Figure 1a. The 12-layered PCB stack-up and the (c) Isolation between Horizontal and Vertical
corresponding copper layers are shown in the Figure 1b. Polarization
A unit-cell with two array elements and two 2-way
Fig. 2. Simulated active 2-port s-parameters of the dual-polarized unit
reactive power dividers (one for each polarization) is element in an infinite array.
simulated in an infinite array environment using periodic
boundary conditions. Thus the unit-cell has 2 ports, one
for each polarization. The active reflection coefficient for -25dB over the band of interest.
both polarizations across the elevation scan range of ±20° The realized gain pattern for a uniformly-fed array of
is shown in Figure 2. In Figure 2c, it is observed that the 4×2 tiles, i.e., 32×2 sub-arrays or 32x32 elements,
isolation between the two ports is better than obtained using pattern multiplication is shown in Figure
Fig. 3. Realized Gain (Co-pol: Solid line and Cross-pol: Dashed line) in the
elevation plane for a 32x32 element array based on pattern Fig. 4. Functional block diagram of T/R Module.
multiplication.