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4 3 2 1

VCU110 EVALUATION PLATFORM HW-U1-VCU110


D D

XCVU190-FLGC2104
DISCLAIMER:
XILINX IS DISCLOSING THIS USER GUIDE, MANUAL, RELEASE NOTE, SCHEMATIC,
AND/OR SPECIFICATION (THE “DOCUMENTATION”) TO YOU SOLELY FOR USE IN
THE DEVELOPMENT OF DESIGNS TO OPERATE WITH XILINX HARDWARE DEVICES.
YOU MAY NOT REPRODUCE, DISTRIBUTE, REPUBLISH, DOWNLOAD, DISPLAY, POST,
OR TRANSMIT THE DOCUMENTATION IN ANY FORM OR BY ANY MEANS INCLUDING,
BUT NOT LIMITED TO, ELECTRONIC, MECHANICAL, PHOTOCOPYING, RECORDING,
OR OTHERWISE, WITHOUT THE PRIOR WRITTEN CONSENT OF XILINX.
XILINX EXPRESSLY DISCLAIMS ANY LIABILITY ARISING OUT OF YOUR USE OF
C THE DOCUMENTATION. XILINX RESERVES THE RIGHT, AT ITS SOLE DISCRETION, C
TO CHANGE THE DOCUMENTATION WITHOUT NOTICE AT ANY TIME. XILINX ASSUMES
NO OBLIGATION TO CORRECT ANY ERRORS CONTAINED IN THE DOCUMENTATION, OR
TO ADVISE YOU OF ANY CORRECTIONS OR UPDATES. XILINX EXPRESSLY
DISCLAIMS ANY LIABILITY IN CONNECTION WITH TECHNICAL SUPPORT OR
ASSISTANCE THAT MAY BE PROVIDED TO YOU IN CONNECTION WITH THE
DOCUMENTATION.
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CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES,
INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF
B THE DOCUMENTATION. B

THE XILINX HARDWARE, FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS")
ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH
CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY
DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT
IS NOT WITHIN THE SPECIFICATIONS STATED ON THE XILINX DATA SHEET.
ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.

PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY


APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY
DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL
RISKS OF DEATH, PERSONAL INJURY OR PROPERTY OR ENVIRONMENTAL DAMAGE
TITLE: Title Page ASSY P/N: 0431880
A SCHEM, ROHS COMPLIANT PCB P/N: 1280790
("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT HW-U1-VCU110_REV1_0 SCH P/N: 0381622
TEST P/N: TSS0174
THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. ALL A
DATE: 09/21/2015:13:57 VER: 1.0
SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
SHEET SIZE: B REV: 01

SHEET OF DRAWN BY:


1 92 BF

4 3 2 1
4 3 2 1

12VDC
Page 71

VCCINT Regulator @ 80A


also VCCINT_IO and VCCBRAM
Page 75
D
GPIO DIP QDR2+ 36-bit DUAL QSPI Pg. 65 FMC FMC
ETHERNET PHY Pg. 64 HPC1 LA HPC0 LA FMC HPC0 DP[0:7]
D

SW. 4-POLE(18-bit SIO) DUAL USB UART Pg.66 PBSW E,SPBSW W,N VCC_1V8 Regulator @ 10A
CY7C2663KV18-550BZXC IIC MAIN Pg. 72 Page 76
also VCCAUX and VCCAUX_IO
Page 67 Page 27-28 Page 43,67 Page 39,67 Page 39

EXAMAX J116 User SMA Clock CLK_125MHZ USER_SI570 VADJ_1V8 Regulator @ 10A
Page 77

GTH220
Page 59 GTY121 GTH221

GTY120
VCC1V2 Regulator @ 10A
Page 78
HR
BULLSEYE2 J122 GTY GTY122 HP HP HP GTH222 VCC1V5 Regulator @ 6A
94 FMC HPC1 DP[0:7] Page 79
Page 63 67 66 65 Page 43
GTY124 HP GTH224 HMC1V2 Regulator @ 20A
HR Page 80
CFP4 MODULES 0-3 68
GTY125 84 GTH225
J107-J110 MGTAVCC Regulator @ 45A
Page 81
Page 54-55

VCCAUX, VCCAUX_IO
VCCINT, VCCINT_IO
GTY126 XCVU190FLGC2104
GTH226 MGTAVTT Regulator @ 45A
C Page 82 C
BULLSEYE1 J87 GTY

VCCBRAM
GTY127 U1 0 GTH227 MGTVCCAUX Regulator @ 1A
Page 63
HYBRID MEM. CUBE Page 83

GTY128 GTH228 UTIL_0V9 Regulator @ 15A


VCCINT Page 32-37
Page 84

GTY129 GTH229 UTIL_1V35 Regulator @ 10A


Page 85
INTERLAKEN J121
GTY130 GTH230 SI5328C and UTIL_3V3 Regulator @ 20A
Page 60
HP HP HP Page 86
SI53340
70 71 72 Clock Buffer
GTY133

GTH233
GTY131 GTH231
Page 38
SYS_1V0 Regulator @ 2A
Page 88
GTY132 GTH232
BULLSEYE3 J111 PCIe SYS_1V8 Regulator @ 1A
Page 88
PBSW C
PB CPU_RESET SYSCLK_300 Page 63
B B
SI5328B and SYS_2V5 Regulator @ 2A
RLD3 36-bit PMOD HDR. RLD3 18-bit Page 88
SI53301, SI53340 (36-bit CIO) Page 71 (18-bit CIO)
Clock Buffers MT44K16M36RB-093E GPIO LEDs MT44K32M18RB-093E
Page 57, 62 Page 29-31 Page 67 Page 29,30

SYS_5V0 Regulator @ 1A
Page 87

SYSMON OP AMPs
DIGILENT USB JTAG BANK# PAGE# BANK# PAGE# PAGE# SYSMON MUX
14-pin JTAG CONN. INTERFACE TO
& Buffers BANK 0 3 BANK 84 9 MGTH228-231 16 BANK 67

Page 26 BANK 65 4 BANK 94 9 MGTH232-233 17 Pages 69-70


BANK 66 5 MGTY120-122 10 PWR/GND BANKS 18-23 TITLE: Block Diagram ASSY P/N: 0431880
A SCHEM, ROHS COMPLIANT PCB P/N: 1280790
System Controller BANK 67 5 MGTY124-127 11 DECOUP. CAPS 24-25 HW-U1-VCU110_REV1_0 SCH P/N: 0381622
IIC, JTAG, SD J83
MECHANICALS TEST P/N: TSS0174
BANK 68 6 MGTY128-131 12 A
DATE: 09/21/2015:13:57 VER: 1.0
Page 50-53,58 BANK 70 7 MGTY132-133 13 Page 91
SHEET SIZE: B REV: 01
BANK 71 7 MGTH220-222 14
SHEET OF DRAWN BY:
BANK 72 8 MGTH224-227 15 2 92 BF

4 3 2 1
4 3 2 1

POR_OVERRIDE select
Default: 2-3 GND VCC1V8
PCIe Test Header
VCCINT_FPGA 1 R547
SYS_1V8 UTIL_3V3
DNP

J5

J78
DNP

HDR_1X3

HDR_1X4
C542 1 SN74AVC1T45 1 C541 2 DNP J80

4
D SYSMON_VP_R_I2C 2 1 SYSMON_VP D
0.1UF 0.1UF
HDR_1X2
Bank 0 HR 25V 2
1
VCCA VCCB
6
2 25V R548 1
GND 20.5K
COMBINED_PGOOD_LS 3 A B 4 COMBINED_PGOOD 1/10W
SOC_VU190_FLGC2104_IRONWOOD GND 1% 2
VCC1V8_FPGA
R554 11 R553 2 5
GND DIR
200 200 1 R1665
1/10W 1/10W
22 1.00K GND
1% 1% SC70_6 U84 J81
1/16W
2 GND 2
1% GND SYSMON_VN_R_I2C 1 SYSMON_VN
HDR_1X2
BANK 0 1 R418
XCVU190FLGC2104 DNP
DNP R560 1
PUDC_B_0_K14 K14 2 DNP 20.5K
POR_OVERRIDE_AB14 AB14 POR_OVERRIDE_PIN
1/10W
RDWR_FCS_B_0_AF14 AF14 QSPI0_CS_B VCC1V8_FPGA 2
1%
DXP_AE20 AE20
AE19 FERRITE-600
DXN_AE19 GND
VCCADC_AB20 AB20 FPGA_SYSMON_VCC
AB19

2
GNDADC_AB19 GND
VREFN_AC19 AC19
AD20
L13
VREFP_AD20
VP_AC20 AC20
AD19
SYSMON_VP
SYSMON_VN
1 C2 1 C2055 SYSMON I2C Address jumpers
VN_AD19 0.1UF 0.47UF
VBATT_AN13 AN13 FPGA_VBATT
C 2 25V 2 10V C
CCLK_0_AB16 AB16 FPGA_CCLK
X5R
TCK_0_AD16 AD16 JTAG_TCK
AB15 JTAG_TMS FERRITE-600
TMS_0_AB15
TDO_0_AD15 AD15 FPGA_TDO_FMC_TDI
AF15 JTAG_TDI

2
TDI_0_AF15
INIT_B_0_P14 P14
AE14
FPGA_INIT_B
FPGA_PROG_B
L87
PROGRAM_B_0_AE14
CFGBVS_0_M14 M14 GND
SYSMON_AGND
DONE_0_AC14 AC14 FPGA_DONE VCC1V8
D03_0_AH14 AH14 QSPI0_IO3
D02_0_AF16 AF16 QSPI0_IO2
SDA03H1SBD
D01_DIN_0_AK14 AK14 QSPI0_IO1
VCC1V8_FPGA FPGA_M2 1 6
D00_MOSI_0_AM14 AM14 QSPI0_IO0
FPGA_M1 2 5
M2_0_T14 T14 FPGA_M2
FPGA_M0 3 4
AE15 VCCO_0_AE15 M1_0_V14 V14 FPGA_M1
AC15 VCCO_0_AC15 M0_0_Y14 Y14 FPGA_M0 1 R1084
1.21K
SW16
1/10W
1 R339 1 R1085
2 1% 1 R1083
DNP 1.21K 1.21K
1 R116 DNP 1/10W 1/10W
GND 2 2 2
U1 DNP 1% 1%
SOC_FLGC2104_IRON 4.70K
1/16W C357
2 1
1%
DNP
2 DNP VCC1V8 GND
VCC1V8 UTIL_3V3
DNP
B B

SYS_1V8 GND GND 1 R236C642 1 1 C643


NC

4.70K 0.1UF 0.1UF


SN74AVC1T45
1 1/16W 25V 2 2 25V
D15 LAYOUT: Place CCLK termination pads 2 1%
200MW 3 6 1
VCCB VCCA
40V
BAS40-04 after last QSPI device FPGA_DONE 4 B A 3
R598
2
2 1

2
5 2 261 DS34
LED-GRN-SMT
DIR GND
1 R115 1/10W
1% GND
4.70K
U90 SC70_6
1/16W
2 1% GND GND

FPGA_VBATT
VCC1V8 UTIL_3V3
VCC1V8

TS518FE_FL35E
1
R473 FPGA Bank 0
261
R6 1 C540 1 1 C633 1/10W
0.1UF 0.1UF 1%
4.70K SN74AVC1T45
25V 2 2 25V
1/16W
1% 2 DS2 UTIL_3V3

2
6 1
VCCB VCCA RED
TITLE: FPGA Bank 0 ASSY P/N: 0431880
4 3
A 2 FPGA_INIT_B 4 B A 3 SCHEM, ROHS COMPLIANT PCB P/N: 1280790
B1 BAT_TS518_TS621_DUAL
1 2
HW-U1-VCU110_REV1_0 SCH P/N: 0381622
5 2 TEST P/N: TSS0174
DIR GND R472 GRN A
LED-GRN-RED DATE: 09/21/2015:13:57 VER: 1.0

2
GND
U53 SC70_6 261 GND
SHEET SIZE: B REV: 01
GND GND 1/10W
1% SHEET OF DRAWN BY:
3 92 BF

4 3 2 1
4 3 2 1

Bank 65 HP
SOC_VU190_FLGC2104_IRONWOOD
D D

BANK 65
XCVU190FLGC2104
IO_L24P_T3U_N10_EMCCLK_65_BE20 BE20 FPGA_EMCCLK
IO_L24N_T3U_N11_DOUT_CSO_B_65_BF20 BF20 FMC_HPC0_PRSNT_M2C_B_LS
IO_T3U_N12_PERSTN0_65_BD20 BD20 FMC_HPC0_PG_M2C_LS
SGMII_RX_P
IO_L23P_T3U_N8_I2C_SCLK_65_BE16 BE16 SYSMON_SCL_LS
IO_L23N_T3U_N9_I2C_SDA_65_BF16 BF16 SYSMON_SDA_LS 1 R1178
IO_L22P_T3U_N6_DBC_AD0P_D04_65_BE19 BE19 QSPI1_IO0
100
IO_L22N_T3U_N7_DBC_AD0N_D05_65_BF19 BF19 QSPI1_IO1
1/10W
IO_L21P_T3L_N4_AD8P_D06_65_BD18 BD18 QSPI1_IO2 2 1%
IO_L21N_T3L_N5_AD8N_D07_65_BE18 BE18 QSPI1_IO3
SGMII_RX_N
IO_L20P_T3L_N2_AD1P_D08_65_BE17 BE17 MOD_RSTN_CFP4_LS
IO_L20N_T3L_N3_AD1N_D09_65_BF17 BF17 GLB_ALRMN_CFP4_LS
SGMIICLK_P
IO_L19P_T3L_N0_DBC_AD9P_D10_65_BD17 BD17 CFP4_REC_CLOCK_C_P
IO_L19N_T3L_N1_DBC_AD9N_D11_65_BD16 BD16 CFP4_REC_CLOCK_C_N 1 R865
BC20 SGMII_RX_P
IO_L18P_T2U_N10_AD2P_D12_65_BC20 SGMII_RX_N 100
C IO_L18N_T2U_N11_AD2N_D13_65_BC19 BC19 C
SGMII_TX_P 1/10W
IO_L17P_T2U_N8_AD10P_D14_65_BA19 BA19 2
SGMII_TX_N 1%
IO_L17N_T2U_N9_AD10N_D15_65_BB19 BB19
SGMIICLK_N
IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65_BA21 BA21 FMC_HPC1_PG_M2C_LS
IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65_BB21 BB21 PHY_MDIO_LS
IO_L15P_T2L_N4_AD11P_A02_D18_65_BB18 BB18 PHY_RESET_LS
IO_L15N_T2L_N5_AD11N_A03_D19_65_BC18 BC18 PHY_MDC_LS
USER_SI570_CLOCK_P
IO_L14P_T2L_N2_GC_A04_D20_65_AY20 AY20 USER_SI570_CLOCK_P
IO_L14N_T2L_N3_GC_A05_D21_65_BA20 BA20 USER_SI570_CLOCK_N 1 R866
IO_T2U_N12_CSI_ADV_B_65_BC21 BC21 PHY_INT_LS
100
IO_L13P_T2L_N0_GC_QBC_A06_D22_65_AY19 AY19 SGMIICLK_P
1/10W
IO_L13N_T2L_N1_GC_QBC_A07_D23_65_AY18 AY18 SGMIICLK_N 2 1%
IO_L12P_T1U_N10_GC_A08_D24_65_AV20 AV20 CLK_125MHZ_P
IO_L12N_T1U_N11_GC_A09_D25_65_AW20 AW20 CLK_125MHZ_N USER_SI570_CLOCK_N
IO_T1U_N12_PERSTN1_65_AV19 AV19 IIC_MAIN_SCL_LS
IO_L11P_T1U_N8_GC_A10_D26_65_AW18 AW18 ILKN_FC_RX_CLK_LS
IO_L11N_T1U_N9_GC_A11_D27_65_AW17 AW17 ILKN_FC_TX_CLK_LS
IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65_AV21 AV21 IIC_MAIN_SDA_LS
IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65_AW21 AW21 SI5328_RST_LS
IO_L9P_T1L_N4_AD12P_A14_D30_65_AU18 AU18 SYSCTLR_GPIO_5 CLK_125MHZ_P
IO_L9N_T1L_N5_AD12N_A15_D31_65_AV18 AV18 SYSCTLR_GPIO_7
IO_L8P_T1L_N2_AD5P_A16_65_AT21 AT21 SM_FAN_PWM 1 R150
IO_L8N_T1L_N3_AD5N_A17_65_AU21 AU21 PMBUS_ALERT_FPGA 100
IO_L7P_T1L_N0_QBC_AD13P_A18_65_AT19 AT19 SM_FAN_TACH 1/10W
AU19 USB_UART_RTS 2 1%
IO_L7N_T1L_N1_QBC_AD13N_A19_65_AU19
IO_L6P_T0U_N10_AD6P_A20_65_AR20 AR20 USB_UART_TX CLK_125MHZ_N
IO_L6N_T0U_N11_AD6N_A21_65_AT20 AT20 USB_UART_RX
IO_L5P_T0U_N8_AD14P_A22_65_AR19 AR19 USB_UART_CTS
B B
IO_L5N_T0U_N9_AD14N_A23_65_AR18 AR18 IIC_MUX_RESET_B_LS
IO_L4P_T0U_N6_DBC_AD7P_A24_65_AM21 AM21 SYSCTLR_GPIO_6
VCC1V8_FPGA
IO_L4N_T0U_N7_DBC_AD7N_A25_65_AN21 AN21 ILKN_FC_TX_DATA_LS
IO_L3P_T0L_N4_AD15P_A26_65_AM19 AM19 ILKN_FC_TX_SYNC_LS
IO_L3N_T0L_N5_AD15N_A27_65_AN19 AN19 ILKN_FC_RX_DATA_LS
AM20 VCCO_65_AM20 IO_L2P_T0L_N2_FOE_B_65_AN20 AN20 ILKN_FC_RX_SYNC_LS
AR21 VCCO_65_AR21 IO_L2N_T0L_N3_FWE_FCS2_B_65_AP20 AP20 QSPI1_CS_B
AT18 VCCO_65_AT18 IO_T0U_N12_VRP_A28_65_AP21 AP21 FMC_HPC1_PRSNT_M2C_B_LS
AW19 VCCO_65_AW19 IO_L1P_T0L_N0_DBC_RS0_65_AN18 AN18 FMC_VADJ_ON_LS
BB20 VCCO_65_BB20 IO_L1N_T0L_N1_DBC_RS1_65_AP18 AP18 VADJ_1V8_PGOOD_LS
BF18 VCCO_65_BF18 VREF_65_AM18 AM18 NC

U1 SOC_FLGC2104_IRON
FPGA Banks 65

TITLE: FPGA Banks 65 ASSY P/N: 0431880


A SCHEM, ROHS COMPLIANT PCB P/N: 1280790
HW-U1-VCU110_REV1_0 SCH P/N: 0381622
TEST P/N: TSS0174
A
DATE: 09/21/2015:13:57 VER: 1.0

SHEET SIZE: B REV: 01

SHEET OF DRAWN BY:


4 92 BF

4 3 2 1
4 3 2 1

Layout: Place resistor and capacitor for VREF


Underneath the FPGA via array
right next to the via Bank 67 HP
SOC_VU190_FLGC2104_IRONWOOD
Bank 66 HP
SOC_VU190_FLGC2104_IRONWOOD
D D

BANK 67
BANK 66 XCVU190FLGC2104
BC28 GPIO_DIP_SW1
XCVU190FLGC2104 IO_L24P_T3U_N10_67_BC28
IO_L24N_T3U_N11_67_BD28 BD28 GPIO_DIP_SW0
IO_L24P_T3U_N10_66_BE24 BE24 QDR2_18B_A9 IO_T3U_N12_67_BD27 BD27 NC
IO_L24N_T3U_N11_66_BF24 BF24 QDR2_18B_RPS_B IO_L23P_T3U_N8_67_BE25 BE25 GPIO_DIP_SW2
IO_T3U_N12_66_BD21 BD21 NC IO_L23N_T3U_N9_67_BF25 BF25 GPIO_DIP_SW3
IO_L23P_T3U_N8_66_BD23 BD23 QDR2_18B_A7 IO_L22P_T3U_N6_DBC_AD0P_67_BE27 BE27 SYSMON_AD0_R_P
IO_L23N_T3U_N9_66_BE23 BE23 QDR2_18B_A6 IO_L22N_T3U_N7_DBC_AD0N_67_BE28 BE28 SYSMON_AD0_R_N
IO_L22P_T3U_N6_DBC_AD0P_66_BF21 BF21 QDR2_18B_A11 IO_L21P_T3L_N4_AD8P_67_BC26 BC26 SYSMON_AD8_R_P
IO_L22N_T3U_N7_DBC_AD0N_66_BF22 BF22 QDR2_18B_A10 IO_L21N_T3L_N5_AD8N_67_BD26 BD26 SYSMON_AD8_R_N
IO_L21P_T3L_N4_AD8P_66_BB24 BB24 QDR2_18B_A5 IO_L20P_T3L_N2_AD1P_67_BF26 BF26 TX_DIS_MOD0_CFP4_LS
IO_L21N_T3L_N5_AD8N_66_BC24 BC24 QDR2_18B_A12 IO_L20N_T3L_N3_AD1N_67_BF27 BF27 TX_DIS_MOD1_CFP4_LS
IO_L20P_T3L_N2_AD1P_66_BD22 BD22 QDR2_18B_A15 IO_L19P_T3L_N0_DBC_AD9P_67_BC25 BC25 TX_DIS_MOD2_CFP4_LS
IO_L20N_T3L_N3_AD1N_66_BE22 BE22 QDR2_18B_A14 IO_L19N_T3L_N1_DBC_AD9N_67_BD25 BD25 TX_DIS_MOD3_CFP4_LS
IO_L19P_T3L_N0_DBC_AD9P_66_BB23 BB23 QDR2_18B_A13 IO_L18P_T2U_N10_AD2P_67_BA29 BA29 SYSMON_AD2_R_P
IO_L19N_T3L_N1_DBC_AD9N_66_BC23 BC23 QDR2_18B_A8 IO_L18N_T2U_N11_AD2N_67_BB29 BB29 SYSMON_AD2_R_N
C C
IO_L18P_T2U_N10_AD2P_66_AY25 AY25 QDR2_18B_A20 IO_L17P_T2U_N8_AD10P_67_BA26 BA26 HMC_REFCLK_BOOT_0
IO_L18N_T2U_N11_AD2N_66_BA25 BA25 QDR2_18B_A18 IO_L17N_T2U_N9_AD10N_67_BB26 BB26 HMC_REFCLK_BOOT_1
IO_L17P_T2U_N8_AD10P_66_BA22 BA22 QDR2_18B_A0 IO_L16P_T2U_N6_QBC_AD3P_67_BA27 BA27 MOD_LOPWR_MOD0_CFP4_LS
USER_SMA_CLOCK_P
IO_L17N_T2U_N9_AD10N_66_BB22 BB22 QDR2_18B_A16 IO_L16N_T2U_N7_QBC_AD3N_67_BB27 BB27 HMC_L1RXPS
IO_L16P_T2U_N6_QBC_AD3P_66_AY24 AY24 QDR2_18B_A1 IO_L15P_T2L_N4_AD11P_67_AY29 AY29 HMC_L1TXPS 1 R1448
IO_L16N_T2U_N7_QBC_AD3N_66_BA24 BA24 QDR2_18B_A17 IO_L15N_T2L_N5_AD11N_67_AY30 AY30 HMC_L0RXPS
100
IO_L15P_T2L_N4_AD11P_66_AY22 AY22 QDR2_18B_A21 IO_L14P_T2L_N2_GC_67_AW27 AW27 HMC_L0TXPS
1/10W
IO_L15N_T2L_N5_AD11N_66_AY23 AY23 QDR2_18B_WPS_B IO_L14N_T2L_N3_GC_67_AW28 AW28 HMC_P_RST_B 2 1%
IO_L14P_T2L_N2_GC_66_AW22 AW22 QDR2_18B_A4 IO_T2U_N12_67_BB28 BB28 MOD_LOPWR_MOD1_CFP4_LS
USER_SMA_CLOCK_N
IO_L14N_T2L_N3_GC_66_AW23 AW23 QDR2_18B_A2 IO_L13P_T2L_N0_GC_QBC_67_AY27 AY27 USER_SMA_CLOCK_P
IO_T2U_N12_66_AW25 AW25 QDR2_18B_DOFF_B IO_L13N_T2L_N1_GC_QBC_67_AY28 AY28 USER_SMA_CLOCK_N
IO_L13P_T2L_N0_GC_QBC_66_AV23 AV23 QDR2_18B_A19 IO_L12P_T1U_N10_GC_67_AV29 AV29 QDR2_18B_Q9
IO_L13N_T2L_N1_GC_QBC_66_AV24 AV24 QDR2_18B_A3 IO_L12N_T1U_N11_GC_67_AV30 AV30 HMC_REFCLK_SEL
IO_L12P_T1U_N10_GC_66_AT24 AT24 QDR2_18B_D12 IO_T1U_N12_67_AW30 AW30 HMC_FERR_B
IO_L12N_T1U_N11_GC_66_AT25 AT25 QDR2_18B_BWS1_B IO_L11P_T1U_N8_GC_67_AU28 AU28 QDR2_18B_Q13
IO_T1U_N12_66_AV25 AV25 MOD_ABS_MOD1_CFP4_LS IO_L11N_T1U_N9_GC_67_AV28 AV28 QDR2_18B_Q10
IO_L11P_T1U_N8_GC_66_AU23 AU23 QDR2_18B_K_P IO_L10P_T1U_N6_QBC_AD4P_67_AT30 AT30 QDR2_18B_CQ
IO_L11N_T1U_N9_GC_66_AU24 AU24 QDR2_18B_K_N IO_L10N_T1U_N7_QBC_AD4N_67_AT31 AT31 QDR2_18B_Q17
IO_L10P_T1U_N6_QBC_AD4P_66_AT26 AT26 QDR2_18B_D10 IO_L9P_T1L_N4_AD12P_67_AT29 AT29 QDR2_18B_Q15
IO_L10N_T1U_N7_QBC_AD4N_66_AU26 AU26 QDR2_18B_D9 IO_L9N_T1L_N5_AD12N_67_AU29 AU29 QDR2_18B_Q11
IO_L9P_T1L_N4_AD12P_66_AT22 AT22 QDR2_18B_D15 IO_L8P_T1L_N2_AD5P_67_AT27 AT27 QDR2_18B_Q16
IO_L9N_T1L_N5_AD12N_66_AU22 AU22 QDR2_18B_D14 IO_L8N_T1L_N3_AD5N_67_AU27 AU27 QDR2_18B_Q14
IO_L8P_T1L_N2_AD5P_66_AR24 AR24 QDR2_18B_D13 IO_L7P_T1L_N0_QBC_AD13P_67_AV26 AV26 QDR2_18B_CQ_B
IO_L8N_T1L_N3_AD5N_66_AR25 AR25 QDR2_18B_D11 IO_L7N_T1L_N1_QBC_AD13N_67_AW26 AW26 QDR2_18B_Q12
IO_L7P_T1L_N0_QBC_AD13P_66_AR22 AR22 QDR2_18B_D16 IO_L6P_T0U_N10_AD6P_67_AN30 AN30 MOD_LOPWR_MOD2_CFP4_LS
IO_L7N_T1L_N1_QBC_AD13N_66_AR23 AR23 QDR2_18B_D17 IO_L6N_T0U_N11_AD6N_67_AP30 AP30 MOD_LOPWR_MOD3_CFP4_LS
IO_L6P_T0U_N10_AD6P_66_AP26 AP26 MOD_ABS_MOD2_CFP4_LS IO_L5P_T0U_N8_AD14P_67_AR27 AR27 QDR2_18B_Q6
B IO_L6N_T0U_N11_AD6N_66_AP27 AP27 MOD_ABS_MOD3_CFP4_LS IO_L5N_T0U_N9_AD14N_67_AR28 AR28 MOD_ABS_MOD0_CFP4_LS B
IO_L5P_T0U_N8_AD14P_66_AM24 AM24 QDR2_18B_D1 IO_L4P_T0U_N6_DBC_AD7P_67_AR29 AR29 QDR2_18B_Q7
IO_L5N_T0U_N9_AD14N_66_AN24 AN24 QDR2_18B_BWS0_B VCC1V5_FPGA IO_L4N_T0U_N7_DBC_AD7N_67_AR30 AR30 QDR2_18B_Q8
IO_L4P_T0U_N6_DBC_AD7P_66_AN25 AN25 QDR2_18B_D5 IO_L3P_T0L_N4_AD15P_67_AM29 AM29 QDR2_18B_Q1
VCC1V5_FPGA IO_L4N_T0U_N7_DBC_AD7N_66_AP25 AP25 QDR2_18B_D7 AM30 VCCO_67_AM30 IO_L3N_T0L_N5_AD15N_67_AN29 AN29 QDR2_18B_Q2
IO_L3P_T0L_N4_AD15P_66_AP22 AP22 QDR2_18B_D3 AR31 VCCO_67_AR31 IO_L2P_T0L_N2_67_AM31 AM31 QDR2_18B_Q3
AN27 VCCO_66_AN27 IO_L3N_T0L_N5_AD15N_66_AP23 AP23 QDR2_18B_D8 AT28 VCCO_67_AT28 IO_L2N_T0L_N3_67_AN31 AN31 QDR2_18B_Q5
AP24 VCCO_66_AP24 IO_L2P_T0L_N2_66_AM26 AM26 QDR2_18B_D4 AW29 VCCO_67_AW29 IO_T0U_N12_VRP_67_AP31 AP31 VRP_67
AU25 VCCO_66_AU25 IO_L2N_T0L_N3_66_AN26 AN26 QDR2_18B_D6 AY26 VCCO_67_AY26 IO_L1P_T0L_N0_DBC_67_AN28 AN28 QDR2_18B_Q0
AV22 VCCO_66_AV22 IO_T0U_N12_VRP_66_AM27 AM27 VRP_66 BC27 VCCO_67_BC27 IO_L1N_T0L_N1_DBC_67_AP28 AP28 QDR2_18B_Q4
BA23 VCCO_66_BA23 IO_L1P_T0L_N0_DBC_66_AM23 AM23 QDR2_18B_D0 BF28 VCCO_67_BF28 VREF_67_AM28 AM28 VREF_67
BD24 VCCO_66_BD24 IO_L1N_T0L_N1_DBC_66_AN23 AN23 QDR2_18B_D2
BE21 VCCO_66_BE21 VREF_66_AM22 AM22 VREF_66
1 R1353
1 R1351 1.00K
1/16W
1.00K 2
U1 1%
1/16W SOC_FLGC2104_IRON
2 1%
U1 SOC_FLGC2104_IRON
GND
FPGA Banks 66 67
GND

VRP_67
VRP_66

A 1 R700 36-bit QDR2+: 1x18-bit SIO 1 R382


240
TITLE: FPGA Banks 66 67
SCHEM, ROHS COMPLIANT
HW-U1-VCU110_REV1_0
ASSY P/N:
PCB P/N:
SCH P/N:
0431880
1280790
0381622
240 1/10W
2
1/10W
1% D,Q[17:0]/ADDR/CTRL 2 1%
DATE: 09/21/2015:13:57 VER:
TEST P/N:

1.0
TSS0174
A

GND
QDR2+ MEM_IF GND
SHEET SIZE: B REV: 01

SHEET OF DRAWN BY:


5 92 BF

4 3 2 1
4 3 2 1

D D

SOC_VU190_FLGC2104_IRONWOOD

FMC_HPC0_VREF_A_M2C

R1674 1
DNP 1 C2667
DNP DNP
DNP 2 2 DNP
DNP
BANK 68
XCVU190FLGC2104 GND
IO_L24P_T3U_N10_68_BF30 BF30 FMC_HPC0_LA10_P
IO_L24N_T3U_N11_68_BF31 BF31 FMC_HPC0_LA10_N
IO_T3U_N12_68_BA30 BA30 NC
IO_L23P_T3U_N8_68_BC31 BC31 FMC_HPC0_LA09_P
IO_L23N_T3U_N9_68_BD31 BD31 FMC_HPC0_LA09_N
IO_L22P_T3U_N6_DBC_AD0P_68_BE29 BE29 FMC_HPC0_LA08_P
IO_L22N_T3U_N7_DBC_AD0N_68_BF29 BF29 FMC_HPC0_LA08_N
IO_L21P_T3L_N4_AD8P_68_BA31 BA31 FMC_HPC0_LA07_P
C IO_L21N_T3L_N5_AD8N_68_BB31 BB31 FMC_HPC0_LA07_N C
IO_L20P_T3L_N2_AD1P_68_BD30 BD30 FMC_HPC0_LA06_P
IO_L20N_T3L_N3_AD1N_68_BE30 BE30 FMC_HPC0_LA06_N
IO_L19P_T3L_N0_DBC_AD9P_68_BC29 BC29 FMC_HPC0_LA05_P
IO_L19N_T3L_N1_DBC_AD9N_68_BC30 BC30 FMC_HPC0_LA05_N
IO_L18P_T2U_N10_AD2P_68_BA36 BA36 FMC_HPC0_LA02_P
IO_L18N_T2U_N11_AD2N_68_BB36 BB36 FMC_HPC0_LA02_N
IO_L17P_T2U_N8_AD10P_68_BB32 BB32 FMC_HPC0_LA04_P
IO_L17N_T2U_N9_AD10N_68_BB33 BB33 FMC_HPC0_LA04_N
IO_L16P_T2U_N6_QBC_AD3P_68_BA34 BA34 FMC_HPC0_LA03_P
IO_L16N_T2U_N7_QBC_AD3N_68_BB34 BB34 FMC_HPC0_LA03_N
IO_L15P_T2L_N4_AD11P_68_AY32 AY32 FMC_HPC0_LA01_CC_P
IO_L15N_T2L_N5_AD11N_68_BA32 BA32 FMC_HPC0_LA01_CC_N
IO_L14P_T2L_N2_GC_68_AW33 AW33 FMC_HPC0_CLK0_M2C_P
IO_L14N_T2L_N3_GC_68_AY33 AY33 FMC_HPC0_CLK0_M2C_N
IO_T2U_N12_68_BA35 BA35 NC
IO_L13P_T2L_N0_GC_QBC_68_AY34 AY34 FMC_HPC0_LA00_CC_P
IO_L13N_T2L_N1_GC_QBC_68_AY35 AY35 FMC_HPC0_LA00_CC_N
IO_L12P_T1U_N10_GC_68_AU33 AU33 FMC_HPC1_CLK0_M2C_P
IO_L12N_T1U_N11_GC_68_AU34 AU34 FMC_HPC1_CLK0_M2C_N
IO_T1U_N12_68_AW32 AW32 NC
IO_L11P_T1U_N8_GC_68_AV33 AV33 FMC_HPC1_LA00_CC_P
IO_L11N_T1U_N9_GC_68_AV34 AV34 FMC_HPC1_LA00_CC_N
IO_L10P_T1U_N6_QBC_AD4P_68_AV36 AV36 FMC_HPC1_LA03_P
IO_L10N_T1U_N7_QBC_AD4N_68_AW36 AW36 FMC_HPC1_LA03_N
IO_L9P_T1L_N4_AD12P_68_AV35 AV35 FMC_HPC1_LA07_P
IO_L9N_T1L_N5_AD12N_68_AW35 AW35 FMC_HPC1_LA07_N
IO_L8P_T1L_N2_AD5P_68_AU31 AU31 FMC_HPC1_LA05_P
B B
IO_L8N_T1L_N3_AD5N_68_AU32 AU32 FMC_HPC1_LA05_N
IO_L7P_T1L_N0_QBC_AD13P_68_AV31 AV31 FMC_HPC1_LA09_P
IO_L7N_T1L_N1_QBC_AD13N_68_AW31 AW31 FMC_HPC1_LA09_N
IO_L6P_T0U_N10_AD6P_68_AR36 AR36 FMC_HPC1_LA06_P
IO_L6N_T0U_N11_AD6N_68_AT36 AT36 FMC_HPC1_LA06_N
IO_L5P_T0U_N8_AD14P_68_AP33 AP33 FMC_HPC1_LA04_P
VADJ_1V8_FPGA IO_L5N_T0U_N9_AD14N_68_AR33 AR33 FMC_HPC1_LA04_N
IO_L4P_T0U_N6_DBC_AD7P_68_AR35 AR35 FMC_HPC1_LA01_CC_P
IO_L4N_T0U_N7_DBC_AD7N_68_AT35 AT35 FMC_HPC1_LA01_CC_N
IO_L3P_T0L_N4_AD15P_68_AR32 AR32 FMC_HPC1_LA10_P
AP34 VCCO_68_AP34 IO_L3N_T0L_N5_AD15N_68_AT32 AT32 FMC_HPC1_LA10_N
AU35 VCCO_68_AU35 IO_L2P_T0L_N2_68_AR34 AR34 FMC_HPC1_LA02_P
AV32 VCCO_68_AV32 IO_L2N_T0L_N3_68_AT34 AT34 FMC_HPC1_LA02_N
AY36 VCCO_68_AY36 IO_T0U_N12_VRP_68_AU36 AU36 VRP_68
BA33 VCCO_68_BA33 IO_L1P_T0L_N0_DBC_68_AN32 AN32 FMC_HPC1_LA08_P
BB30 VCCO_68_BB30 IO_L1N_T0L_N1_DBC_68_AP32 AP32 FMC_HPC1_LA08_N
BE31 VCCO_68_BE31 VREF_68_AM32 AM32 VREF_68

U1 SOC_FLGC2104_IRON

TITLE: FPGA Bank 68 ASSY P/N: 0431880


VRP_68
A SCHEM, ROHS COMPLIANT PCB P/N: 1280790
HW-U1-VCU110_REV1_0 SCH P/N: 0381622
1 R1676 TEST P/N: TSS0174
240 A
1/10W DATE: 09/21/2015:13:58 VER: 1.0
2 1%
SHEET SIZE: B REV: 01

SHEET OF DRAWN BY:


GND 6 92 BF

4 3 2 1
4 3 2 1

SOC_VU190_FLGC2104_IRONWOOD
SOC_VU190_FLGC2104_IRONWOOD

D BANK 71 D
BANK 70
XCVU190FLGC2104
XCVU190FLGC2104 BANK MIGRATION:
VU160 = BANK 71
BANK MIGRATION: VU125 = BANK 71
VU160 = BANK 70 VU095 = BANK 70
VU125 = BANK 70
VU095 = BANK 69

IO_L24P_T3U_N10_71_C22 C22 RLD3_36B_BA3


IO_L24N_T3U_N11_71_B22 B22 RLD3_36B_A9
IO_L24P_T3U_N10_70_B26 B26 RLD3_36B_DQ4 IO_T3U_N12_71_D22 D22 NC
IO_L24N_T3U_N11_70_A26 A26 RLD3_36B_QVLD0 IO_L23P_T3U_N8_71_B25 B25 RLD3_36B_BA2
IO_T3U_N12_70_E26 E26 NC IO_L23N_T3U_N9_71_A25 A25 RLD3_36B_WE_B
IO_L23P_T3U_N8_70_D29 D29 RLD3_36B_DQ1 IO_L22P_T3U_N6_DBC_AD0P_71_C23 C23 RLD3_36B_A10
IO_L23N_T3U_N9_70_C29 C29 RLD3_36B_DQ7 IO_L22N_T3U_N7_DBC_AD0N_71_B23 B23 RLD3_36B_A18
IO_L22P_T3U_N6_DBC_AD0P_70_B27 B27 RLD3_36B_DQ3 IO_L21P_T3L_N4_AD8P_71_D25 D25 RLD3_36B_A0
IO_L22N_T3U_N7_DBC_AD0N_70_B28 B28 RLD3_36B_DQ8 IO_L21N_T3L_N5_AD8N_71_C25 C25 RLD3_36B_BA0
IO_L21P_T3L_N4_AD8P_70_C27 C27 RLD3_36B_DQ0 IO_L20P_T3L_N2_AD1P_71_A24 A24 RLD3_36B_REF_B
IO_L21N_T3L_N5_AD8N_70_C28 C28 RLD3_36B_DQ6 IO_L20N_T3L_N3_AD1N_71_A23 A23 RLD3_36B_A17
IO_L20P_T3L_N2_AD1P_70_A28 A28 RLD3_36B_DQ5 IO_L19P_T3L_N0_DBC_AD9P_71_D24 D24 RLD3_36B_A4
IO_L20N_T3L_N3_AD1N_70_A29 A29 RLD3_36B_DQ2 IO_L19N_T3L_N1_DBC_AD9N_71_C24 C24 RLD3_36B_A3
IO_L19P_T3L_N0_DBC_AD9P_70_D26 D26 RLD3_36B_QK0_P IO_L18P_T2U_N10_AD2P_71_G21 G21 RLD3_36B_A13
IO_L19N_T3L_N1_DBC_AD9N_70_D27 D27 RLD3_36B_QK0_N IO_L18N_T2U_N11_AD2N_71_F21 F21 RLD3_36B_RESET_B
IO_L18P_T2U_N10_AD2P_70_E27 E27 RLD3_36B_DQ23 IO_L17P_T2U_N8_AD10P_71_F24 F24 RLD3_36B_A14
IO_L18N_T2U_N11_AD2N_70_E28 E28 RLD3_36B_DM0 IO_L17N_T2U_N9_AD10N_71_E24 E24 RLD3_36B_BA1
C IO_L17P_T2U_N8_AD10P_70_F29 F29 RLD3_36B_DQ21 IO_L16P_T2U_N6_QBC_AD3P_71_F23 F23 RLD3_36B_A5 C
IO_L17N_T2U_N9_AD10N_70_E29 E29 RLD3_36B_DQ24 IO_L16N_T2U_N7_QBC_AD3N_71_E23 E23 RLD3_36B_A8
IO_L16P_T2U_N6_QBC_AD3P_70_G26 G26 RLD3_36B_DQ20 IO_L15P_T2L_N4_AD11P_71_G25 G25 RLD3_36B_CK_P
IO_L16N_T2U_N7_QBC_AD3N_70_F26 F26 RLD3_36B_DQ25 IO_L15N_T2L_N5_AD11N_71_F25 F25 RLD3_36B_CK_N
IO_L15P_T2L_N4_AD11P_70_G28 G28 RLD3_36B_DQ22 IO_L14P_T2L_N2_GC_71_H23 H23 RLD3_36B_DK0_P
IO_L15N_T2L_N5_AD11N_70_F28 F28 RLD3_36B_DQ26 IO_L14N_T2L_N3_GC_71_G23 G23 RLD3_36B_DK0_N
IO_L14P_T2L_N2_GC_70_J27 J27 RLD3_36B_DQ19 IO_T2U_N12_71_E22 E22 RLD3_36B_CS_B
IO_L14N_T2L_N3_GC_70_H27 H27 RLD3_36B_DQ18 IO_L13P_T2L_N0_GC_QBC_71_H22 H22 RLD3_36B_DK1_P
IO_T2U_N12_70_G27 G27 RLD3_36B_QVLD1 IO_L13N_T2L_N1_GC_QBC_71_G22 G22 RLD3_36B_DK1_N
IO_L13P_T2L_N0_GC_QBC_70_H28 H28 RLD3_36B_QK2_P IO_L12P_T1U_N10_GC_71_J24 J24 SYSCLK_300_P
IO_L13N_T2L_N1_GC_QBC_70_H29 H29 RLD3_36B_QK2_N IO_L12N_T1U_N11_GC_71_H24 H24 SYSCLK_300_N SYSCLK_300_P
IO_L12P_T1U_N10_GC_70_K29 K29 RLD3_36B_DQ9 IO_T1U_N12_71_L25 L25 MDC_CFP4
IO_L12N_T1U_N11_GC_70_J29 J29 CPU_RESET IO_L11P_T1U_N8_GC_71_K22 K22 MDIO_CFP4 R1355 1
IO_T1U_N12_70_L26 L26 GPIO_SW_C IO_L11N_T1U_N9_GC_71_J22 J22 PMOD0_1_LS
100
IO_L11P_T1U_N8_GC_70_K27 K27 RLD3_36B_DQ16 IO_L10P_T1U_N6_QBC_AD4P_71_K21 K21 PMOD0_5_LS
1/10W
IO_L11N_T1U_N9_GC_70_K28 K28 RLD3_36B_DQ11 IO_L10N_T1U_N7_QBC_AD4N_71_J21 J21 PMOD0_2_LS 2
1%
IO_L10P_T1U_N6_QBC_AD4P_70_K26 K26 RLD3_36B_DQ14 IO_L9P_T1L_N4_AD12P_71_J25 J25 PMOD0_3_LS
SYSCLK_300_N
IO_L10N_T1U_N7_QBC_AD4N_70_J26 J26 RLD3_36B_DQ10 IO_L9N_T1L_N5_AD12N_71_H25 H25 PMOD0_7_LS
IO_L9P_T1L_N4_AD12P_70_L28 L28 RLD3_36B_DQ13 IO_L8P_T1L_N2_AD5P_71_L23 L23 PMOD0_0_LS
IO_L9N_T1L_N5_AD12N_70_L29 L29 RLD3_36B_DQ17 IO_L8N_T1L_N3_AD5N_71_K23 K23 PMOD0_4_LS
IO_L8P_T1L_N2_AD5P_70_N27 N27 RLD3_36B_DQ12 IO_L7P_T1L_N0_QBC_AD13P_71_L24 L24 PMOD0_6_LS
IO_L8N_T1L_N3_AD5N_70_M27 M27 RLD3_36B_DQ15 IO_L7N_T1L_N1_QBC_AD13N_71_K24 K24 MAXIM_CABLE_B_FPGA
IO_L7P_T1L_N0_QBC_AD13P_70_N28 N28 RLD3_36B_QK1_P IO_L6P_T0U_N10_AD6P_71_M21 M21 SYSMON_MUX_ADDR0_LS
IO_L7N_T1L_N1_QBC_AD13N_70_M28 M28 RLD3_36B_QK1_N IO_L6N_T0U_N11_AD6N_71_L21 L21 SYSMON_MUX_ADDR1_LS
IO_L6P_T0U_N10_AD6P_70_M30 M30 RLD3_36B_DQ29 IO_L5P_T0U_N8_AD14P_71_P25 P25 SYSMON_MUX_ADDR2_LS
IO_L6N_T0U_N11_AD6N_70_L30 L30 RLD3_36B_DM1 IO_L5N_T0U_N9_AD14N_71_N25 N25 GPIO_LED_0_LS
IO_L5P_T0U_N8_AD14P_70_K31 K31 RLD3_36B_DQ31 VCC1V2_FPGA IO_L4P_T0U_N6_DBC_AD7P_71_N22 N22 GPIO_LED_1_LS
IO_L5N_T0U_N9_AD14N_70_J31 J31 RLD3_36B_DQ34 IO_L4N_T0U_N7_DBC_AD7N_71_M22 M22 GPIO_LED_2_LS
B B
IO_L4P_T0U_N6_DBC_AD7P_70_N29 N29 RLD3_36B_DQ27 IO_L3P_T0L_N4_AD15P_71_M26 M26 GPIO_LED_3_LS
VCC1V2_FPGA IO_L4N_T0U_N7_DBC_AD7N_70_N30 N30 RLD3_36B_DQ30 IO_L3N_T0L_N5_AD15N_71_M25 M25 GPIO_LED_4_LS
IO_L3P_T0L_N4_AD15P_70_K32 K32 RLD3_36B_DQ35 B24 VCCO_71_B24 IO_L2P_T0L_N2_71_P24 P24 GPIO_LED_5_LS
A27 VCCO_70_A27 IO_L3N_T0L_N5_AD15N_70_J32 J32 RLD3_36B_DQ33 E25 VCCO_71_E25 IO_L2N_T0L_N3_71_N24 N24 GPIO_LED_6_LS
D28 VCCO_70_D28 IO_L2P_T0L_N2_70_N32 N32 RLD3_36B_DQ28 F22 VCCO_71_F22 IO_T0U_N12_VRP_71_P22 P22 VRP_71
G29 VCCO_70_G29 IO_L2N_T0L_N3_70_M32 M32 RLD3_36B_DQ32 J23 VCCO_71_J23 IO_L1P_T0L_N0_DBC_71_N23 N23 GPIO_LED_7_LS
H26 VCCO_70_H26 IO_T0U_N12_VRP_70_J30 J30 VRP_70 M24 VCCO_71_M24 IO_L1N_T0L_N1_DBC_71_M23 M23 SI5328_INT_ALM_LS
K30 VCCO_70_K30 IO_L1P_T0L_N0_DBC_70_M31 M31 RLD3_36B_QK3_P N21 VCCO_71_N21 VREF_71_P21 P21 VREF_71
L27 VCCO_70_L27 IO_L1N_T0L_N1_DBC_70_L31 L31 RLD3_36B_QK3_N
N31 VCCO_70_N31 VREF_70_P27 P27 VREF_70
1 R1050
1.00K
1 R1048 1/16W
1.00K 2 1%
1/16W
U1 SOC_FLGC2104_IRON
2 1%
U1 SOC_FLGC2104_IRON
GND

GND FPGA Banks 70 71

VRP_70 VRP_71
1 R1072
240
36-bit RLD3: 1x36-bit 1 R1073
240
TITLE: FPGA Banks 70 71 ASSY P/N: 0431880
A SCHEM, ROHS COMPLIANT PCB P/N: 1280790
2
1/10W
1% DATA[35:0], Multiplexed ADDR 2
1/10W
1%
HW-U1-VCU110_REV1_0 SCH P/N:
TEST P/N:
0381622
TSS0174
A
DATE: 09/21/2015:13:58 VER: 1.0
GND
RLD3 MEM_IF GND
SHEET SIZE: B REV: 01

SHEET OF DRAWN BY:


7 92 BF

4 3 2 1
4 3 2 1

SOC_VU190_FLGC2104_IRONWOOD

D D

BANK 72
XCVU190FLGC2104
BANK MIGRATION:
VU160 = BANK 72
VU125 = BANK 72
VU095 = BANK 71

IO_L24P_T3U_N10_72_B18 B18 RLD3_18B_WE_B


IO_L24N_T3U_N11_72_A18 A18 RLD3_18B_BA1
IO_T3U_N12_72_D21 D21 NC
IO_L23P_T3U_N8_72_A20 A20 RLD3_18B_A0
IO_L23N_T3U_N9_72_A19 A19 RLD3_18B_A14
IO_L22P_T3U_N6_DBC_AD0P_72_C19 C19 RLD3_18B_DK1_P
IO_L22N_T3U_N7_DBC_AD0N_72_C18 C18 RLD3_18B_DK1_N
IO_L21P_T3L_N4_AD8P_72_B21 B21 RLD3_18B_DK0_P
IO_L21N_T3L_N5_AD8N_72_A21 A21 RLD3_18B_DK0_N
IO_L20P_T3L_N2_AD1P_72_D20 D20 RLD3_18B_CK_P
IO_L20N_T3L_N3_AD1N_72_D19 D19 RLD3_18B_CK_N
IO_L19P_T3L_N0_DBC_AD9P_72_C20 C20 RLD3_18B_REF_B
IO_L19N_T3L_N1_DBC_AD9N_72_B20 B20 RLD3_18B_BA2
IO_L18P_T2U_N10_AD2P_72_E19 E19 RLD3_18B_BA0
IO_L18N_T2U_N11_AD2N_72_E18 E18 RLD3_18B_A4
C C
IO_L17P_T2U_N8_AD10P_72_G20 G20 RLD3_18B_BA3
IO_L17N_T2U_N9_AD10N_72_F20 F20 RLD3_18B_A3
IO_L16P_T2U_N6_QBC_AD3P_72_H18 H18 RLD3_18B_A5
IO_L16N_T2U_N7_QBC_AD3N_72_G18 G18 RLD3_18B_A8
IO_L15P_T2L_N4_AD11P_72_F19 F19 RLD3_18B_CS_B
IO_L15N_T2L_N5_AD11N_72_F18 F18 RLD3_18B_A13
IO_L14P_T2L_N2_GC_72_H20 H20 RLD3_18B_A17
IO_L14N_T2L_N3_GC_72_H19 H19 RLD3_18B_A9
IO_T2U_N12_72_E21 E21 RLD3_18B_RESET_B
IO_L13P_T2L_N0_GC_QBC_72_J20 J20 RLD3_18B_A18
IO_L13N_T2L_N1_GC_QBC_72_J19 J19 RLD3_18B_A10
IO_L12P_T1U_N10_GC_72_K19 K19 RLD3_18B_DQ8
IO_L12N_T1U_N11_GC_72_K18 K18 RLD3_18B_DQ6
IO_T1U_N12_72_J15 J15 RLD3_18B_QVLD0
IO_L11P_T1U_N8_GC_72_L19 L19 RLD3_18B_DQ5
IO_L11N_T1U_N9_GC_72_L18 L18 RLD3_18B_DQ3
IO_L10P_T1U_N6_QBC_AD4P_72_K16 K16 RLD3_18B_DQ0
IO_L10N_T1U_N7_QBC_AD4N_72_J16 J16 RLD3_18B_DQ4
IO_L9P_T1L_N4_AD12P_72_M20 M20 RLD3_18B_DQ7
IO_L9N_T1L_N5_AD12N_72_L20 L20 RLD3_18B_DQ2
IO_L8P_T1L_N2_AD5P_72_L16 L16 RLD3_18B_DM0
IO_L8N_T1L_N3_AD5N_72_L15 L15 RLD3_18B_DQ1
IO_L7P_T1L_N0_QBC_AD13P_72_K17 K17 RLD3_18B_QK0_P
IO_L7N_T1L_N1_QBC_AD13N_72_J17 J17 RLD3_18B_QK0_N
IO_L6P_T0U_N10_AD6P_72_P17 P17 RLD3_18B_DQ15
IO_L6N_T0U_N11_AD6N_72_P16 P16 RLD3_18B_DQ13
IO_L5P_T0U_N8_AD14P_72_P20 P20 RLD3_18B_DQ16
B IO_L5N_T0U_N9_AD14N_72_N20 N20 RLD3_18B_DQ12 B
VCC1V2_FPGA IO_L4P_T0U_N6_DBC_AD7P_72_M16 M16 RLD3_18B_DQ10
IO_L4N_T0U_N7_DBC_AD7N_72_M15 M15 RLD3_18B_DQ14
IO_L3P_T0L_N4_AD15P_72_P19 P19 RLD3_18B_DQ17
IO_L3N_T0L_N5_AD15N_72_N19 N19 RLD3_18B_DQ9
C21 VCCO_72_C21 IO_L2P_T0L_N2_72_N17 N17 RLD3_18B_DM1
D18 VCCO_72_D18 IO_L2N_T0L_N3_72_M17 M17 RLD3_18B_DQ11
G19 VCCO_72_G19 IO_T0U_N12_VRP_72_N15 N15 VRP_72
K20 VCCO_72_K20 IO_L1P_T0L_N0_DBC_72_N18 N18 RLD3_18B_QK1_P
L17 VCCO_72_L17 IO_L1N_T0L_N1_DBC_72_M18 M18 RLD3_18B_QK1_N
P18 VCCO_72_P18 VREF_72_P15 P15 VREF_72

1 R1030
1.00K
1/16W
2 1%
U1 SOC_FLGC2104_IRON

GND
FPGA Bank 72

VRP_72
18-bit RLD3: 1x18-bit TITLE: FPGA Bank 72 ASSY P/N: 0431880
A
1
240
DATA[17:0], Multiplexed ADDR
R1371
SCHEM, ROHS COMPLIANT
HW-U1-VCU110_REV1_0
PCB P/N:
SCH P/N:
TEST P/N:
1280790
0381622
TSS0174
1/10W A
2 1% DATE: 09/21/2015:13:57 VER: 1.0
RLD3 MEM_IF SHEET SIZE: B REV: 01

SHEET OF DRAWN BY:


GND 8 92 BF

4 3 2 1
4 3 2 1

D D

SOC_VU190_FLGC2104_IRONWOOD
SOC_VU190_FLGC2104_IRONWOOD

C BANK 84 C
BANK 94
XCVU190FLGC2104
IO_L24P_T3U_N10_84_AP17 AP17 NC XCVU190FLGC2104
IO_L24N_T3U_N11_84_AR17 AR17 NC IO_L12P_T1U_N10_GC_94_AW13 AW13 NC
IO_T3U_N12_84_AM16 AM16 GPIO_SW_W IO_L12N_T1U_N11_GC_94_AW12 AW12 NC
IO_L23P_T3U_N8_84_AN15 AN15 RX_LOS_MOD0_CFP4_LS IO_T1U_N12_94_AY13 AY13 GPIO_SW_E
IO_L23N_T3U_N9_84_AP15 AP15 RX_LOS_MOD1_CFP4_LS IO_L11P_T1U_N8_GC_94_AV14 AV14 NC
IO_L22P_T3U_N6_DBC_AD0P_84_AV16 AV16 RX_LOS_MOD2_CFP4_LS IO_L11N_T1U_N9_GC_94_AV13 AV13 NC
IO_L22N_T3U_N7_DBC_AD0N_84_AV15 AV15 RX_LOS_MOD3_CFP4_LS IO_L10P_T1U_N6_QBC_AD4P_94_BA11 BA11 NC
IO_L21P_T3L_N4_AD8P_84_AN16 AN16 PCIE_CABLE_FPGA_CPERST_B IO_L10N_T1U_N7_QBC_AD4N_94_BB11 BB11 NC
IO_L21N_T3L_N5_AD8N_84_AP16 AP16 NC IO_L9P_T1L_N4_AD12P_94_AY12 AY12 NC
IO_L20P_T3L_N2_AD1P_84_AT17 AT17 NC IO_L9N_T1L_N5_AD12N_94_BA12 BA12 NC
IO_L20N_T3L_N3_AD1N_84_AU17 AU17 NC IO_L8P_T1L_N2_AD5P_94_BB13 BB13 NC
IO_L19P_T3L_N0_DBC_AD9P_84_AT16 AT16 NC IO_L8N_T1L_N3_AD5N_94_BB12 BB12 NC
IO_L19N_T3L_N1_DBC_AD9N_84_AU16 AU16 NC IO_L7P_T1L_N0_QBC_AD13P_94_AV11 AV11 NC
IO_L18P_T2U_N10_AD2P_84_AP13 AP13 NC IO_L7N_T1L_N1_QBC_AD13N_94_AW11 AW11 NC
IO_L18N_T2U_N11_AD2N_84_AR13 AR13 NC IO_L6P_T0U_N10_AD6P_94_AY17 AY17 NC
IO_L17P_T2U_N8_AD10P_84_AU12 AU12 NC IO_L6N_T0U_N11_AD6N_94_BA17 BA17 NC
IO_L17N_T2U_N9_AD10N_84_AU11 AU11 NC IO_L5P_T0U_N8_AD14P_94_BA14 BA14 NC
IO_L16P_T2U_N6_QBC_AD3P_84_AR15 AR15 NC IO_L5N_T0U_N9_AD14N_94_BB14 BB14 NC
IO_L16N_T2U_N7_QBC_AD3N_84_AR14 AR14 NC IO_L4P_T0U_N6_DBC_AD7P_94_BB17 BB17 NC
IO_L15P_T2L_N4_AD11P_84_AR12 AR12 NC IO_L4N_T0U_N7_DBC_AD7N_94_BB16 BB16 NC
IO_L15N_T2L_N5_AD11N_84_AT12 AT12 NC IO_L3P_T0L_N4_AD15P_94_BA16 BA16 NC
VCC1V8_FPGA
IO_L14P_T2L_N2_GC_84_AT15 AT15 NC IO_L3N_T0L_N5_AD15N_94_BB15 BB15 NC
VCC1V8_FPGA
IO_L14N_T2L_N3_GC_84_AT14 AT14 NC IO_L2P_T0L_N2_94_AW15 AW15 NC
AN17 VCCO_84_AN17 IO_T2U_N12_84_AT11 AT11 GPIO_SW_N IO_L2N_T0L_N3_94_AY14 AY14 NC
B AP14 VCCO_84_AP14 IO_L13P_T2L_N0_GC_QBC_84_AU14 AU14 NC AV12 VCCO_94_AV12 IO_T0U_N12_94_BC16 BC16 GPIO_SW_S B
AR11 VCCO_84_AR11 IO_L13N_T2L_N1_GC_QBC_84_AU13 AU13 NC AY16 VCCO_94_AY16 IO_L1P_T0L_N0_DBC_94_AY15 AY15 NC
AU15 VCCO_84_AU15 VREF_84_AM17 AM17 NC BA13 VCCO_94_BA13 IO_L1N_T0L_N1_DBC_94_BA15 BA15 NC
BC17 VCCO_94_BC17 VREF_94_AW16 AW16 NC

U1 SOC_FLGC2104_IRON
U1 SOC_FLGC2104_IRON

FPGA Banks 84 94

TITLE: FPGA Banks 84 94 ASSY P/N: 0431880


A SCHEM, ROHS COMPLIANT PCB P/N: 1280790
HW-U1-VCU110_REV1_0 SCH P/N: 0381622
TEST P/N: TSS0174
A
DATE: 09/21/2015:13:58 VER: 1.0

SHEET SIZE: B REV: 01

SHEET OF DRAWN BY:


9 92 BF

4 3 2 1
4 3 2 1

SOC_VU190_FLGC2104_IRONWOOD SOC_VU190_FLGC2104_IRONWOOD

BANK 120 BANK 121


D D
XCVU190FLGC2104 XCVU190FLGC2104
MGTYTXP0_120_BF38 BF38 EXAMAX_TX8_P MGTYTXP0_121_BC40 BC40 EXAMAX_TX4_P
BANK MIGRATION: MGTYTXN0_120_BF39 BF39 EXAMAX_TX8_N BANK MIGRATION: MGTYTXN0_121_BC41 BC41 EXAMAX_TX4_N
VU160 = BANK 120 MGTYRXP0_120_BF33 BF33 EXAMAX_RX8_P VU160 = BANK 121 MGTYRXP0_121_BC45 BC45 EXAMAX_RX4_P
VU125 = NC MGTYRXN0_120_BF34 BF34 EXAMAX_RX8_N VU125 = NC MGTYRXN0_121_BC46 BC46 EXAMAX_RX4_N
VU095 = NC MGTYTXP1_120_BE36 BE36 EXAMAX_TX7_P VU095 = NC MGTYTXP1_121_BB38 BB38 EXAMAX_TX3_P
MGTYTXN1_120_BE37 BE37 EXAMAX_TX7_N MGTYTXN1_121_BB39 BB39 EXAMAX_TX3_N
MGTYRXP1_120_BD33 BD33 EXAMAX_RX7_P MGTYRXP1_121_BB43 BB43 EXAMAX_RX3_P
MGTYRXN1_120_BD34 BD34 EXAMAX_RX7_N MGTYRXN1_121_BB44 BB44 EXAMAX_RX3_N
MGTYTXP2_120_BE40 BE40 EXAMAX_TX6_P MGTYTXP2_121_BA40 BA40 EXAMAX_TX2_P
MGTYTXN2_120_BE41 BE41 EXAMAX_TX6_N MGTYTXN2_121_BA41 BA41 EXAMAX_TX2_N
MGTYRXP2_120_BF43 BF43 EXAMAX_RX6_P MGTYRXP2_121_BA45 BA45 EXAMAX_RX2_P
MGTYRXN2_120_BF44 BF44 EXAMAX_RX6_N MGTYRXN2_121_BA46 BA46 EXAMAX_RX2_N
MGTYTXP3_120_BD38 BD38 EXAMAX_TX5_P MGTYTXP3_121_AY38 AY38 EXAMAX_TX1_P
MGTYTXN3_120_BD39 BD39 EXAMAX_TX5_N MGTYTXN3_121_AY39 AY39 EXAMAX_TX1_N
MGTYRXP3_120_BD43 BD43 EXAMAX_RX5_P MGTYRXP3_121_AY43 AY43 EXAMAX_RX1_P
MGTYRXN3_120_BD44 BD44 EXAMAX_RX5_N MGTYRXN3_121_AY44 AY44 EXAMAX_RX1_N
MGTREFCLK0P_120_AN36 AN36 EXAMAX_SI5328_OUT1_BUF1_C_P MGTREFCLK0P_121_AL36 AL36 EXAMAX_SI5328_OUT1_BUF2_C_P
MGTREFCLK0N_120_AN37 AN37 EXAMAX_SI5328_OUT1_BUF1_C_N MGTREFCLK0N_121_AL37 AL37 EXAMAX_SI5328_OUT1_BUF2_C_N
AM34 NC AK34 NC

R1231
MGTREFCLK1P_120_AM34 MGTREFCLK1P_121_AK34
MGTREFCLK1N_120_AM35 AM35 NC MGTREFCLK1N_121_AK35 AK35 NC

1/10W
MGTRREF_LS_BD37 BD37
MGTAVTT_FPGA
BD36

100
MGTAVTTRCAL_LS_BD36

1%
MGTRREF_120

2
C U1 C
SOC_FLGC2104_IRON
U1 SOC_FLGC2104_IRON

SOC_VU190_FLGC2104_IRONWOOD

BANK 122
XCVU190FLGC2104
MGTYTXP0_122_AW40 AW40 CFP4_MOD0_TX3_P
BANK MIGRATION: MGTYTXN0_122_AW41 AW41 CFP4_MOD0_TX3_N
VU160 = BANK 122 MGTYRXP0_122_AW45 AW45 CFP4_MOD0_RX3_P
B VU125 = NC MGTYRXN0_122_AW46 AW46 CFP4_MOD0_RX3_N B
VU095 = NC MGTYTXP1_122_AV38 AV38 CFP4_MOD0_TX2_P
MGTYTXN1_122_AV39 AV39 CFP4_MOD0_TX2_N
MGTYRXP1_122_AV43 AV43 CFP4_MOD0_RX2_P
MGTYRXN1_122_AV44 AV44 CFP4_MOD0_RX2_N
MGTYTXP2_122_AU40 AU40 CFP4_MOD0_TX1_P
MGTYTXN2_122_AU41 AU41 CFP4_MOD0_TX1_N
MGTYRXP2_122_AU45 AU45 CFP4_MOD0_RX1_P
MGTYRXN2_122_AU46 AU46 CFP4_MOD0_RX1_N
MGTYTXP3_122_AT38 AT38 CFP4_MOD0_TX0_P
MGTYTXN3_122_AT39 AT39 CFP4_MOD0_TX0_N
MGTYRXP3_122_AT43 AT43 CFP4_MOD0_RX0_P
MGTYRXN3_122_AT44 AT44 CFP4_MOD0_RX0_N
MGTREFCLK0P_122_AJ36 AJ36 CFP4_SI5328_OUT1_BUF1_C_P
MGTREFCLK0N_122_AJ37 AJ37 CFP4_SI5328_OUT1_BUF1_C_N
MGTREFCLK1P_122_AH34 AH34 NC
MGTREFCLK1N_122_AH35 AH35 NC

FPGA Banks 120 121 122


U1 SOC_FLGC2104_IRON

TITLE: FPGA Banks 120 121 122 ASSY P/N: 0431880


A SCHEM, ROHS COMPLIANT PCB P/N: 1280790
HW-U1-VCU110_REV1_0 SCH P/N: 0381622
TEST P/N: TSS0174
A
DATE: 09/21/2015:13:58 VER: 1.0

SHEET SIZE: B REV: 01

SHEET OF DRAWN BY:


10 92 BF

4 3 2 1
4 3 2 1

SOC_VU190_FLGC2104_IRONWOOD SOC_VU190_FLGC2104_IRONWOOD

BANK 124 BANK 125


D XCVU190FLGC2104 XCVU190FLGC2104 D

MGTYTXP0_124_AR40 AR40 BULLSEYE2_GTY_TX0_P MGTYTXP0_125_AL40 AL40 CFP4_MOD1_TX3_P


MGTYTXN0_124_AR41 AR41 BULLSEYE2_GTY_TX0_N MGTYTXN0_125_AL41 AL41 CFP4_MOD1_TX3_N
MGTYRXP0_124_AR45 AR45 BULLSEYE2_GTY_RX0_P MGTYRXP0_125_AL45 AL45 CFP4_MOD1_RX3_P
MGTYRXN0_124_AR46 AR46 BULLSEYE2_GTY_RX0_N MGTYRXN0_125_AL46 AL46 CFP4_MOD1_RX3_N
MGTYTXP1_124_AP38 AP38 BULLSEYE2_GTY_TX1_P MGTYTXP1_125_AK38 AK38 CFP4_MOD1_TX2_P
MGTYTXN1_124_AP39 AP39 BULLSEYE2_GTY_TX1_N MGTYTXN1_125_AK39 AK39 CFP4_MOD1_TX2_N
MGTYRXP1_124_AP43 AP43 BULLSEYE2_GTY_RX1_P MGTYRXP1_125_AK43 AK43 CFP4_MOD1_RX2_P
MGTYRXN1_124_AP44 AP44 BULLSEYE2_GTY_RX1_N MGTYRXN1_125_AK44 AK44 CFP4_MOD1_RX2_N
MGTYTXP2_124_AN40 AN40 BULLSEYE2_GTY_TX2_P MGTYTXP2_125_AJ40 AJ40 CFP4_MOD1_TX1_P
MGTYTXN2_124_AN41 AN41 BULLSEYE2_GTY_TX2_N MGTYTXN2_125_AJ41 AJ41 CFP4_MOD1_TX1_N
MGTYRXP2_124_AN45 AN45 BULLSEYE2_GTY_RX2_P MGTYRXP2_125_AJ45 AJ45 CFP4_MOD1_RX1_P
MGTYRXN2_124_AN46 AN46 BULLSEYE2_GTY_RX2_N MGTYRXN2_125_AJ46 AJ46 CFP4_MOD1_RX1_N
MGTYTXP3_124_AM38 AM38 BULLSEYE2_GTY_TX3_P MGTYTXP3_125_AH38 AH38 CFP4_MOD1_TX0_P
MGTYTXN3_124_AM39 AM39 BULLSEYE2_GTY_TX3_N MGTYTXN3_125_AH39 AH39 CFP4_MOD1_TX0_N
MGTYRXP3_124_AM43 AM43 BULLSEYE2_GTY_RX3_P MGTYRXP3_125_AH43 AH43 CFP4_MOD1_RX0_P
MGTYRXN3_124_AM44 AM44 BULLSEYE2_GTY_RX3_N MGTYRXN3_125_AH44 AH44 CFP4_MOD1_RX0_N
MGTREFCLK0P_124_AG36 AG36 BULLSEYE2_GTY_REFCLK0_C_P MGTREFCLK0P_125_AE36 AE36 CFP4_SI5328_OUT1_BUF2_C_P
MGTREFCLK0N_124_AG37 AG37 BULLSEYE2_GTY_REFCLK0_C_N MGTREFCLK0N_125_AE37 AE37 CFP4_SI5328_OUT1_BUF2_C_N
MGTREFCLK1P_124_AF34 AF34 BULLSEYE2_GTY_REFCLK1_C_P MGTREFCLK1P_125_AD34 AD34 NC
MGTREFCLK1N_124_AF35 AF35 BULLSEYE2_GTY_REFCLK1_C_N MGTREFCLK1N_125_AD35 AD35 NC
MGTRREF_LC_AH41 AH41 MGTRREF_125

R1098
MGTAVTTRCAL_LC_AH40 AH40

1/10W
MGTAVTT_FPGA

100

1%
U1
C2542

C SOC_FLGC2104_IRON C

2
0.1UF

U1 SOC_FLGC2104_IRON
C2543
25V

0.1UF

C2544
25V

BULLSEYE2_GTY_REFCLK0_C_P BULLSEYE2_GTY_REFCLK0_P
0.1UF
1

C2545
25V

BULLSEYE2_GTY_REFCLK0_C_N BULLSEYE2_GTY_REFCLK0_N
0.1UF
1

25V

BULLSEYE2_GTY_REFCLK1_C_P BULLSEYE2_GTY_REFCLK1_P
1

BULLSEYE2_GTY_REFCLK1_C_N BULLSEYE2_GTY_REFCLK1_N
1

SOC_VU190_FLGC2104_IRONWOOD SOC_VU190_FLGC2104_IRONWOOD

BANK 126 BANK 127


XCVU190FLGC2104 XCVU190FLGC2104
MGTYTXP0_126_AG40 AG40 BULLSEYE1_GTY_TX0_P MGTYTXP0_127_AC40 AC40 CFP4_MOD2_TX3_P
MGTYTXN0_126_AG41 AG41 BULLSEYE1_GTY_TX0_N MGTYTXN0_127_AC41 AC41 CFP4_MOD2_TX3_N
MGTYRXP0_126_AG45 AG45 BULLSEYE1_GTY_RX0_P MGTYRXP0_127_AC45 AC45 CFP4_MOD2_RX3_P
B MGTYRXN0_126_AG46 AG46 BULLSEYE1_GTY_RX0_N MGTYRXN0_127_AC46 AC46 CFP4_MOD2_RX3_N B
MGTYTXP1_126_AF38 AF38 BULLSEYE1_GTY_TX1_P MGTYTXP1_127_AB38 AB38 CFP4_MOD2_TX2_P
MGTYTXN1_126_AF39 AF39 BULLSEYE1_GTY_TX1_N MGTYTXN1_127_AB39 AB39 CFP4_MOD2_TX2_N
MGTYRXP1_126_AF43 AF43 BULLSEYE1_GTY_RX1_P MGTYRXP1_127_AB43 AB43 CFP4_MOD2_RX2_P
MGTYRXN1_126_AF44 AF44 BULLSEYE1_GTY_RX1_N MGTYRXN1_127_AB44 AB44 CFP4_MOD2_RX2_N
MGTYTXP2_126_AE40 AE40 BULLSEYE1_GTY_TX2_P MGTYTXP2_127_AA40 AA40 CFP4_MOD2_TX1_P
MGTYTXN2_126_AE41 AE41 BULLSEYE1_GTY_TX2_N MGTYTXN2_127_AA41 AA41 CFP4_MOD2_TX1_N
MGTYRXP2_126_AE45 AE45 BULLSEYE1_GTY_RX2_P MGTYRXP2_127_AA45 AA45 CFP4_MOD2_RX1_P
MGTYRXN2_126_AE46 AE46 BULLSEYE1_GTY_RX2_N MGTYRXN2_127_AA46 AA46 CFP4_MOD2_RX1_N
MGTYTXP3_126_AD38 AD38 BULLSEYE1_GTY_TX3_P MGTYTXP3_127_Y38 Y38 CFP4_MOD2_TX0_P
MGTYTXN3_126_AD39 AD39 BULLSEYE1_GTY_TX3_N MGTYTXN3_127_Y39 Y39 CFP4_MOD2_TX0_N
MGTYRXP3_126_AD43 AD43 BULLSEYE1_GTY_RX3_P MGTYRXP3_127_Y43 Y43 CFP4_MOD2_RX0_P
MGTYRXN3_126_AD44 AD44 BULLSEYE1_GTY_RX3_N MGTYRXN3_127_Y44 Y44 CFP4_MOD2_RX0_N
MGTREFCLK0P_126_AC36 AC36 BULLSEYE1_GTY_REFCLK0_C_P MGTREFCLK0P_127_AA36 AA36 CFP4_SI5328_OUT1_BUF3_C_P
MGTREFCLK0N_126_AC37 AC37 BULLSEYE1_GTY_REFCLK0_C_N MGTREFCLK0N_127_AA37 AA37 CFP4_SI5328_OUT1_BUF3_C_N
MGTREFCLK1P_126_AB34 AB34 BULLSEYE1_GTY_REFCLK1_C_P MGTREFCLK1P_127_Y34 Y34 NC
MGTREFCLK1N_126_AB35 AB35 BULLSEYE1_GTY_REFCLK1_C_N MGTREFCLK1N_127_Y35 Y35 NC

FPGA Banks 124 125 126 127


C2538

U1 SOC_FLGC2104_IRON U1 SOC_FLGC2104_IRON
0.1UF

C2539
25V

0.1UF

TITLE: FPGA Banks 124 125 126 127 ASSY P/N: 0431880
C2540
25V

A BULLSEYE1_GTY_REFCLK0_C_P BULLSEYE1_GTY_REFCLK0_P SCHEM, ROHS COMPLIANT PCB P/N: 1280790


0.1UF

HW-U1-VCU110_REV1_0 SCH P/N: 0381622


1

C2541

TEST P/N: TSS0174


25V

BULLSEYE1_GTY_REFCLK0_C_N BULLSEYE1_GTY_REFCLK0_N
A
0.1UF
1

DATE: 09/21/2015:13:58 VER: 1.0


25V

BULLSEYE1_GTY_REFCLK1_C_P BULLSEYE1_GTY_REFCLK1_P
SHEET SIZE: B REV: 01
1

BULLSEYE1_GTY_REFCLK1_C_N BULLSEYE1_GTY_REFCLK1_N
SHEET OF DRAWN BY:
11 92
1

BF

4 3 2 1
4 3 2 1

SOC_VU190_FLGC2104_IRONWOOD
SOC_VU190_FLGC2104_IRONWOOD

BANK 129
BANK 128
XCVU190FLGC2104
XCVU190FLGC2104 MGTYTXP0_129_R40 R40 ILKN_TX0_P
MGTYTXP0_128_W40 W40 CFP4_MOD3_TX3_P MGTYTXN0_129_R41 R41 ILKN_TX0_N
D D
MGTYTXN0_128_W41 W41 CFP4_MOD3_TX3_N MGTYRXP0_129_R45 R45 ILKN_RX0_C_P
MGTYRXP0_128_W45 W45 CFP4_MOD3_RX3_P MGTYRXN0_129_R46 R46 ILKN_RX0_C_N
MGTYRXN0_128_W46 W46 CFP4_MOD3_RX3_N MGTYTXP1_129_P38 P38 ILKN_TX1_P
MGTYTXP1_128_V38 V38 CFP4_MOD3_TX2_P MGTYTXN1_129_P39 P39 ILKN_TX1_N
MGTYTXN1_128_V39 V39 CFP4_MOD3_TX2_N MGTYRXP1_129_P43 P43 ILKN_RX1_C_P
MGTYRXP1_128_V43 V43 CFP4_MOD3_RX2_P MGTYRXN1_129_P44 P44 ILKN_RX1_C_N
MGTYRXN1_128_V44 V44 CFP4_MOD3_RX2_N MGTYTXP2_129_N40 N40 ILKN_TX2_P
MGTYTXP2_128_U40 U40 CFP4_MOD3_TX1_P MGTYTXN2_129_N41 N41 ILKN_TX2_N
MGTYTXN2_128_U41 U41 CFP4_MOD3_TX1_N MGTYRXP2_129_N45 N45 ILKN_RX2_C_P
MGTYRXP2_128_U45 U45 CFP4_MOD3_RX1_P MGTYRXN2_129_N46 N46 ILKN_RX2_C_N
MGTYRXN2_128_U46 U46 CFP4_MOD3_RX1_N MGTYTXP3_129_M38 M38 ILKN_TX3_P
MGTYTXP3_128_T38 T38 CFP4_MOD3_TX0_P MGTYTXN3_129_M39 M39 ILKN_TX3_N
MGTYTXN3_128_T39 T39 CFP4_MOD3_TX0_N MGTYRXP3_129_M43 M43 ILKN_RX3_C_P
MGTYRXP3_128_T43 T43 CFP4_MOD3_RX0_P MGTYRXN3_129_M44 M44 ILKN_RX3_C_N
MGTYRXN3_128_T44 T44 CFP4_MOD3_RX0_N MGTREFCLK0P_129_U36 U36 ILKN_SI5328_OUT2_BUF1_C_P
MGTREFCLK0P_128_W36 W36 CFP4_SI5328_OUT1_BUF4_C_P MGTREFCLK0N_129_U37 U37 ILKN_SI5328_OUT2_BUF1_C_N
MGTREFCLK0N_128_W37 W37 CFP4_SI5328_OUT1_BUF4_C_N MGTREFCLK1P_129_T34 T34 NC
MGTREFCLK1P_128_V34 V34 CFP4_REC_CLOCK2_C_P MGTREFCLK1N_129_T35 T35 NC
MGTREFCLK1N_128_V35 V35 CFP4_REC_CLOCK2_C_N

U1 SOC_FLGC2104_IRON
U1 SOC_FLGC2104_IRON

C C

SOC_VU190_FLGC2104_IRONWOOD SOC_VU190_FLGC2104_IRONWOOD

BANK 130 BANK 131


XCVU190FLGC2104 XCVU190FLGC2104
MGTYTXP0_130_L40 L40 ILKN_TX4_P MGTYTXP0_131_G40 G40 ILKN_TX8_P
MGTYTXN0_130_L41 L41 ILKN_TX4_N MGTYTXN0_131_G41 G41 ILKN_TX8_N
B B
MGTYRXP0_130_L45 L45 ILKN_RX4_C_P MGTYRXP0_131_G45 G45 ILKN_RX8_C_P
MGTYRXN0_130_L46 L46 ILKN_RX4_C_N MGTYRXN0_131_G46 G46 ILKN_RX8_C_N
MGTYTXP1_130_K38 K38 ILKN_TX5_P MGTYTXP1_131_F38 F38 ILKN_TX9_P
MGTYTXN1_130_K39 K39 ILKN_TX5_N MGTYTXN1_131_F39 F39 ILKN_TX9_N
MGTYRXP1_130_K43 K43 ILKN_RX5_C_P MGTYRXP1_131_F43 F43 ILKN_RX9_C_P
MGTYRXN1_130_K44 K44 ILKN_RX5_C_N MGTYRXN1_131_F44 F44 ILKN_RX9_C_N
MGTYTXP2_130_J40 J40 ILKN_TX6_P MGTYTXP2_131_G36 G36 ILKN_TX10_P
MGTYTXN2_130_J41 J41 ILKN_TX6_N MGTYTXN2_131_G37 G37 ILKN_TX10_N
MGTYRXP2_130_J45 J45 ILKN_RX6_C_P MGTYRXP2_131_G31 G31 ILKN_RX10_C_P
MGTYRXN2_130_J46 J46 ILKN_RX6_C_N MGTYRXN2_131_G32 G32 ILKN_RX10_C_N
MGTYTXP3_130_H38 H38 ILKN_TX7_P MGTYTXP3_131_F34 F34 ILKN_TX11_P
MGTYTXN3_130_H39 H39 ILKN_TX7_N MGTYTXN3_131_F35 F35 ILKN_TX11_N
MGTYRXP3_130_H43 H43 ILKN_RX7_C_P MGTYRXP3_131_E31 E31 ILKN_RX11_C_P
MGTYRXN3_130_H44 H44 ILKN_RX7_C_N MGTYRXN3_131_E32 E32 ILKN_RX11_C_N
MGTREFCLK0P_130_R36 R36 ILKN_SI5328_OUT2_BUF2_C_P MGTREFCLK0P_131_N36 N36 ILKN_SI5328_OUT2_BUF3_C_P
MGTREFCLK0N_130_R37 R37 ILKN_SI5328_OUT2_BUF2_C_N MGTREFCLK0N_131_N37 N37 ILKN_SI5328_OUT2_BUF3_C_N
MGTREFCLK1P_130_P34 P34 NC MGTREFCLK1P_131_M34 M34 NC
MGTREFCLK1N_130_P35 P35 NC MGTREFCLK1N_131_M35 M35 NC
D41 MGTRREF_130
MGTRREF_LN_D41
MGTAVTTRCAL_LN_D40 D40 FPGA Banks 128 129 130 131
R1099
1/10W

MGTAVTT_FPGA
100

1%

U1 SOC_FLGC2104_IRON
U1
1

SOC_FLGC2104_IRON TITLE: FPGA Banks 128 129 130 131 ASSY P/N: 0431880
A SCHEM, ROHS COMPLIANT PCB P/N: 1280790
HW-U1-VCU110_REV1_0 SCH P/N: 0381622
TEST P/N: TSS0174
A
DATE: 09/21/2015:13:58 VER: 1.0

SHEET SIZE: B REV: 01

SHEET OF DRAWN BY:


12 92 BF

4 3 2 1
4 3 2 1

D D

SOC_VU190_FLGC2104_IRONWOOD
SOC_VU190_FLGC2104_IRONWOOD

BANK 132
XCVU190FLGC2104 BANK 133
BANK MIGRATION: MGTYTXP0_132_E40 E40
E41
ILKN_TX12_P
ILKN_TX12_N
XCVU190FLGC2104
MGTYTXN0_132_E41 D38 ILKN_TX16_P
VU160 = BANK 132 E45 ILKN_RX12_C_P MGTYTXP0_133_D38
VU125 = BANK 132
MGTYRXP0_132_E45
E46 ILKN_RX12_C_N
BANK MIGRATION: MGTYTXN0_133_D39 D39 ILKN_TX16_N
MGTYRXN0_132_E46 VU160 = BANK 133 D33 ILKN_RX16_C_P
VU095 = NC E36 ILKN_TX13_P MGTYRXP0_133_D33
MGTYTXP1_132_E36 VU125 = BANK 133 D34 ILKN_RX16_C_N
E37 ILKN_TX13_N MGTYRXN0_133_D34
MGTYTXN1_132_E37 VU095 = NC C36 ILKN_TX17_P
D43 ILKN_RX13_C_P MGTYTXP1_133_C36
MGTYRXP1_132_D43 C37 ILKN_TX17_N
D44 ILKN_RX13_C_N MGTYTXN1_133_C37
MGTYRXN1_132_D44 C31 ILKN_RX17_C_P
C40 ILKN_TX14_P MGTYRXP1_133_C31
MGTYTXP2_132_C40 C32 ILKN_RX17_C_N
C41 ILKN_TX14_N MGTYRXN1_133_C32
MGTYTXN2_132_C41 B38 ILKN_TX18_P
C45 ILKN_RX14_C_P MGTYTXP2_133_B38
MGTYRXP2_132_C45 B39 ILKN_TX18_N
C46 ILKN_RX14_C_N MGTYTXN2_133_B39
MGTYRXN2_132_C46 B33 ILKN_RX18_C_P
A40 ILKN_TX15_P MGTYRXP2_133_B33
MGTYTXP3_132_A40 B34 ILKN_RX18_C_N
C A41 ILKN_TX15_N MGTYRXN2_133_B34 C
MGTYTXN3_132_A41 A36 ILKN_TX19_P
B43 ILKN_RX15_C_P MGTYTXP3_133_A36
MGTYRXP3_132_B43 A37 ILKN_TX19_N
B44 ILKN_RX15_C_N MGTYTXN3_133_A37
MGTYRXN3_132_B44 A31 ILKN_RX19_C_P
L36 ILKN_SI5328_OUT2_BUF4_C_P MGTYRXP3_133_A31
MGTREFCLK0P_132_L36 A32 ILKN_RX19_C_N
L37 ILKN_SI5328_OUT2_BUF4_C_N MGTYRXN3_133_A32
MGTREFCLK0N_132_L37 J36 ILKN_SI5328_OUT2_BUF5_C_P
K34 NC MGTREFCLK0P_133_J36
MGTREFCLK1P_132_K34 J37 ILKN_SI5328_OUT2_BUF5_C_N
K35 NC MGTREFCLK0N_133_J37
MGTREFCLK1N_132_K35 H34 NC
MGTREFCLK1P_133_H34
MGTREFCLK1N_133_H35 H35 NC

U1 SOC_FLGC2104_IRON
U1 SOC_FLGC2104_IRON

B B

FPGA Banks 132 133

TITLE: FPGA Banks 132 133 ASSY P/N: 0431880


A SCHEM, ROHS COMPLIANT PCB P/N: 1280790
HW-U1-VCU110_REV1_0 SCH P/N: 0381622
TEST P/N: TSS0174
A
DATE: 09/21/2015:13:58 VER: 1.0

SHEET SIZE: B REV: 01

SHEET OF DRAWN BY:


13 92 BF

4 3 2 1
4 3 2 1

SOC_VU190_FLGC2104_IRONWOOD SOC_VU190_FLGC2104_IRONWOOD

D BANK 220 BANK 221 D


XCVU190FLGC2104 XCVU190FLGC2104
MGTHTXP0_220_BF9 BF9 FMC_HPC0_DP0_C2M_P MGTHTXP0_221_BC7 BC7 FMC_HPC0_DP4_C2M_P
BANK MIGRATION: MGTHTXN0_220_BF8 BF8 FMC_HPC0_DP0_C2M_N BANK MIGRATION: MGTHTXN0_221_BC6 BC6 FMC_HPC0_DP4_C2M_N
VU160 = BANK 220 MGTHRXP0_220_BF14 BF14 FMC_HPC0_DP0_M2C_P VU160 = BANK 221 MGTHRXP0_221_BC2 BC2 FMC_HPC0_DP4_M2C_P
VU125 = NC MGTHRXN0_220_BF13 BF13 FMC_HPC0_DP0_M2C_N VU125 = NC MGTHRXN0_221_BC1 BC1 FMC_HPC0_DP4_M2C_N
VU095 = NC MGTHTXP1_220_BE11 BE11 FMC_HPC0_DP1_C2M_P VU095 = NC MGTHTXP1_221_BB9 BB9 FMC_HPC0_DP5_C2M_P
MGTHTXN1_220_BE10 BE10 FMC_HPC0_DP1_C2M_N MGTHTXN1_221_BB8 BB8 FMC_HPC0_DP5_C2M_N
MGTHRXP1_220_BD14 BD14 FMC_HPC0_DP1_M2C_P MGTHRXP1_221_BB4 BB4 FMC_HPC0_DP5_M2C_P
MGTHRXN1_220_BD13 BD13 FMC_HPC0_DP1_M2C_N MGTHRXN1_221_BB3 BB3 FMC_HPC0_DP5_M2C_N
MGTHTXP2_220_BE7 BE7 FMC_HPC0_DP2_C2M_P MGTHTXP2_221_BA7 BA7 FMC_HPC0_DP6_C2M_P
MGTHTXN2_220_BE6 BE6 FMC_HPC0_DP2_C2M_N MGTHTXN2_221_BA6 BA6 FMC_HPC0_DP6_C2M_N
MGTHRXP2_220_BF4 BF4 FMC_HPC0_DP2_M2C_P MGTHRXP2_221_BA2 BA2 FMC_HPC0_DP6_M2C_P
MGTHRXN2_220_BF3 BF3 FMC_HPC0_DP2_M2C_N MGTHRXN2_221_BA1 BA1 FMC_HPC0_DP6_M2C_N
MGTHTXP3_220_BD9 BD9 FMC_HPC0_DP3_C2M_P MGTHTXP3_221_AY9 AY9 FMC_HPC0_DP7_C2M_P
MGTHTXN3_220_BD8 BD8 FMC_HPC0_DP3_C2M_N MGTHTXN3_221_AY8 AY8 FMC_HPC0_DP7_C2M_N
MGTHRXP3_220_BD4 BD4 FMC_HPC0_DP3_M2C_P MGTHRXP3_221_AY4 AY4 FMC_HPC0_DP7_M2C_P
MGTHRXN3_220_BD3 BD3 FMC_HPC0_DP3_M2C_N MGTHRXN3_221_AY3 AY3 FMC_HPC0_DP7_M2C_N
MGTREFCLK0P_220_AN11 AN11 NC MGTREFCLK0P_221_AL11 AL11 FMC_HPC0_GBTCLK0_M2C_C_P
MGTREFCLK0N_220_AN10 AN10 NC MGTREFCLK0N_221_AL10 AL10 FMC_HPC0_GBTCLK0_M2C_C_N
MGTREFCLK1P_220_AM13 AM13 NC MGTREFCLK1P_221_AK13 AK13 FMC_HPC0_GBTCLK1_M2C_C_P
MGTREFCLK1N_220_AM12 AM12 NC MGTREFCLK1N_221_AK12 AK12 FMC_HPC0_GBTCLK1_M2C_C_N

R1232
MGTRREF_RS_BD10 BD10 MGTRREF_221
BD11

1/10W
MGTAVTTRCAL_RS_BD11
MGTAVTT_FPGA

100

1%

C1576
C C
U1

0.1UF
SOC_FLGC2104_IRON

C1577
25V
U1 SOC_FLGC2104_IRON

0.1UF

C1578
25V
FMC_HPC0_GBTCLK0_M2C_C_P FMC_HPC0_GBTCLK0_M2C_P

0.1UF
1

C1579
25V
FMC_HPC0_GBTCLK0_M2C_C_N FMC_HPC0_GBTCLK0_M2C_N

0.1UF
1

25V
FMC_HPC0_GBTCLK1_M2C_C_P FMC_HPC0_GBTCLK1_M2C_P

2
FMC_HPC0_GBTCLK1_M2C_C_N FMC_HPC0_GBTCLK1_M2C_N

2
SOC_VU190_FLGC2104_IRONWOOD

BANK 222
XCVU190FLGC2104
MGTHTXP0_222_AW7 AW7 FMC_HPC1_DP4_C2M_P
B
BANK MIGRATION: MGTHTXN0_222_AW6 AW6 FMC_HPC1_DP4_C2M_N
B
VU160 = BANK 222 MGTHRXP0_222_AW2 AW2 FMC_HPC1_DP4_M2C_P
VU125 = NC MGTHRXN0_222_AW1 AW1 FMC_HPC1_DP4_M2C_N
VU095 = NC MGTHTXP1_222_AV9 AV9 FMC_HPC1_DP5_C2M_P
MGTHTXN1_222_AV8 AV8 FMC_HPC1_DP5_C2M_N
MGTHRXP1_222_AV4 AV4 FMC_HPC1_DP5_M2C_P
MGTHRXN1_222_AV3 AV3 FMC_HPC1_DP5_M2C_N
MGTHTXP2_222_AU7 AU7 FMC_HPC1_DP6_C2M_P
MGTHTXN2_222_AU6 AU6 FMC_HPC1_DP6_C2M_N
MGTHRXP2_222_AU2 AU2 FMC_HPC1_DP6_M2C_P
MGTHRXN2_222_AU1 AU1 FMC_HPC1_DP6_M2C_N
MGTHTXP3_222_AT9 AT9 FMC_HPC1_DP7_C2M_P
MGTHTXN3_222_AT8 AT8 FMC_HPC1_DP7_C2M_N
MGTHRXP3_222_AT4 AT4 FMC_HPC1_DP7_M2C_P
MGTHRXN3_222_AT3 AT3 FMC_HPC1_DP7_M2C_N
MGTREFCLK0P_222_AJ11 AJ11 FMC_HPC1_GBTCLK0_M2C_BUF1_C_P
MGTREFCLK0N_222_AJ10 AJ10 FMC_HPC1_GBTCLK0_M2C_BUF1_C_N
MGTREFCLK1P_222_AH13 AH13 FMC_HPC1_GBTCLK1_M2C_BUF1_C_P
MGTREFCLK1N_222_AH12 AH12 FMC_HPC1_GBTCLK1_M2C_BUF1_C_N
FPGA Banks 220 221 222
C1572
0.1UF

U1
C1573

SOC_FLGC2104_IRON
25V

0.1UF

TITLE: FPGA Banks 220 221 222 ASSY P/N: 0431880


C1574
25V

A FMC_HPC1_GBTCLK0_M2C_BUF1_C_P FMC_HPC1_GBTCLK0_M2C_BUF1_P SCHEM, ROHS COMPLIANT PCB P/N: 1280790


0.1UF

HW-U1-VCU110_REV1_0 SCH P/N: 0381622


1

C1575

TEST P/N: TSS0174


25V

FMC_HPC1_GBTCLK0_M2C_BUF1_C_N FMC_HPC1_GBTCLK0_M2C_BUF1_N
A
0.1UF
1

DATE: 09/21/2015:16:07 VER: 1.0


25V

FMC_HPC1_GBTCLK1_M2C_BUF1_C_P FMC_HPC1_GBTCLK1_M2C_BUF1_P
SHEET SIZE: B REV: 01
1

FMC_HPC1_GBTCLK1_M2C_BUF1_C_N FMC_HPC1_GBTCLK1_M2C_BUF1_N
SHEET OF DRAWN BY:
14 92
1

BF

4 3 2 1
4 3 2 1

SOC_VU190_FLGC2104_IRONWOOD SOC_VU190_FLGC2104_IRONWOOD

D D
BANK 224 BANK 225
XCVU190FLGC2104 XCVU190FLGC2104
MGTHTXP0_224_AR7 AR7 FMC_HPC1_DP0_C2M_P MGTHTXP0_225_AL7 AL7 HMC_L1TX_0_P
MGTHTXN0_224_AR6 AR6 FMC_HPC1_DP0_C2M_N MGTHTXN0_225_AL6 AL6 HMC_L1TX_0_N
MGTHRXP0_224_AR2 AR2 FMC_HPC1_DP0_M2C_P MGTHRXP0_225_AL2 AL2 HMC_L1RX_0_C_P
MGTHRXN0_224_AR1 AR1 FMC_HPC1_DP0_M2C_N MGTHRXN0_225_AL1 AL1 HMC_L1RX_0_C_N
MGTHTXP1_224_AP9 AP9 FMC_HPC1_DP1_C2M_P MGTHTXP1_225_AK9 AK9 HMC_L1TX_2_P
MGTHTXN1_224_AP8 AP8 FMC_HPC1_DP1_C2M_N MGTHTXN1_225_AK8 AK8 HMC_L1TX_2_N
MGTHRXP1_224_AP4 AP4 FMC_HPC1_DP1_M2C_P MGTHRXP1_225_AK4 AK4 HMC_L1RX_2_C_P
MGTHRXN1_224_AP3 AP3 FMC_HPC1_DP1_M2C_N MGTHRXN1_225_AK3 AK3 HMC_L1RX_2_C_N
MGTHTXP2_224_AN7 AN7 FMC_HPC1_DP2_C2M_P MGTHTXP2_225_AJ7 AJ7 HMC_L1TX_1_P
MGTHTXN2_224_AN6 AN6 FMC_HPC1_DP2_C2M_N MGTHTXN2_225_AJ6 AJ6 HMC_L1TX_1_N
MGTHRXP2_224_AN2 AN2 FMC_HPC1_DP2_M2C_P MGTHRXP2_225_AJ2 AJ2 HMC_L1RX_1_C_P
MGTHRXN2_224_AN1 AN1 FMC_HPC1_DP2_M2C_N MGTHRXN2_225_AJ1 AJ1 HMC_L1RX_1_C_N
MGTHTXP3_224_AM9 AM9 FMC_HPC1_DP3_C2M_P MGTHTXP3_225_AH9 AH9 HMC_L1TX_6_P
MGTHTXN3_224_AM8 AM8 FMC_HPC1_DP3_C2M_N MGTHTXN3_225_AH8 AH8 HMC_L1TX_6_N
MGTHRXP3_224_AM4 AM4 FMC_HPC1_DP3_M2C_P MGTHRXP3_225_AH4 AH4 HMC_L1RX_6_C_P
MGTHRXN3_224_AM3 AM3 FMC_HPC1_DP3_M2C_N MGTHRXN3_225_AH3 AH3 HMC_L1RX_6_C_N
MGTREFCLK0P_224_AG11 AG11 FMC_HPC1_GBTCLK0_M2C_BUF2_C_P MGTREFCLK0P_225_AE11 AE11 NC
MGTREFCLK0N_224_AG10 AG10 FMC_HPC1_GBTCLK0_M2C_BUF2_C_N MGTREFCLK0N_225_AE10 AE10 NC
MGTREFCLK1P_224_AF13 AF13 FMC_HPC1_GBTCLK1_M2C_BUF2_C_P MGTREFCLK1P_225_AD13 AD13 NC
MGTREFCLK1N_224_AF12 AF12 FMC_HPC1_GBTCLK1_M2C_BUF2_C_N MGTREFCLK1N_225_AD12 AD12 NC

C C
C2657

U1 SOC_FLGC2104_IRON U1 SOC_FLGC2104_IRON
0.1UF

C2658
25V

0.1UF

C2659
25V

FMC_HPC1_GBTCLK0_M2C_BUF2_C_P FMC_HPC1_GBTCLK0_M2C_BUF2_P
0.1UF
1

C2660
25V

FMC_HPC1_GBTCLK0_M2C_BUF2_C_N FMC_HPC1_GBTCLK0_M2C_BUF2_N
0.1UF
1

25V

FMC_HPC1_GBTCLK1_M2C_BUF2_C_P FMC_HPC1_GBTCLK1_M2C_BUF2_P
1

FMC_HPC1_GBTCLK1_M2C_BUF2_C_N FMC_HPC1_GBTCLK1_M2C_BUF2_N
1

SOC_VU190_FLGC2104_IRONWOOD SOC_VU190_FLGC2104_IRONWOOD

BANK 226 BANK 227


B B
XCVU190FLGC2104 XCVU190FLGC2104
MGTHTXP0_226_AG7 AG7 HMC_L1TX_4_P MGTHTXP0_227_AC7 AC7 HMC_L1TX_11_P
MGTHTXN0_226_AG6 AG6 HMC_L1TX_4_N MGTHTXN0_227_AC6 AC6 HMC_L1TX_11_N
MGTHRXP0_226_AG2 AG2 HMC_L1RX_4_C_P MGTHRXP0_227_AC2 AC2 HMC_L1RX_11_C_P
MGTHRXN0_226_AG1 AG1 HMC_L1RX_4_C_N MGTHRXN0_227_AC1 AC1 HMC_L1RX_11_C_N
MGTHTXP1_226_AF9 AF9 HMC_L1TX_3_P MGTHTXP1_227_AB9 AB9 HMC_L1TX_14_P
MGTHTXN1_226_AF8 AF8 HMC_L1TX_3_N MGTHTXN1_227_AB8 AB8 HMC_L1TX_14_N
MGTHRXP1_226_AF4 AF4 HMC_L1RX_3_C_P MGTHRXP1_227_AB4 AB4 HMC_L1RX_14_C_P
MGTHRXN1_226_AF3 AF3 HMC_L1RX_3_C_N MGTHRXN1_227_AB3 AB3 HMC_L1RX_14_C_N
MGTHTXP2_226_AE7 AE7 HMC_L1TX_7_P MGTHTXP2_227_AA7 AA7 HMC_L1TX_15_P
MGTHTXN2_226_AE6 AE6 HMC_L1TX_7_N MGTHTXN2_227_AA6 AA6 HMC_L1TX_15_N
MGTHRXP2_226_AE2 AE2 HMC_L1RX_7_C_P MGTHRXP2_227_AA2 AA2 HMC_L1RX_15_C_P
MGTHRXN2_226_AE1 AE1 HMC_L1RX_7_C_N MGTHRXN2_227_AA1 AA1 HMC_L1RX_15_C_N
MGTHTXP3_226_AD9 AD9 HMC_L1TX_5_P MGTHTXP3_227_Y9 Y9 HMC_L1TX_13_P
MGTHTXN3_226_AD8 AD8 HMC_L1TX_5_N MGTHTXN3_227_Y8 Y8 HMC_L1TX_13_N
MGTHRXP3_226_AD4 AD4 HMC_L1RX_5_C_P MGTHRXP3_227_Y4 Y4 HMC_L1RX_13_C_P
MGTHRXN3_226_AD3 AD3 HMC_L1RX_5_C_N MGTHRXN3_227_Y3 Y3 HMC_L1RX_13_C_N
MGTREFCLK0P_226_AC11 AC11 HMC_SI5328_OUT2_BUF2_C_P MGTREFCLK0P_227_AA11 AA11 NC
MGTREFCLK0N_226_AC10 AC10
AB13
HMC_SI5328_OUT2_BUF2_C_N
NC
MGTREFCLK0N_227_AA10 AA10
Y13
NC
NC
FPGA Banks 224 225 226 227
MGTREFCLK1P_226_AB13 MGTREFCLK1P_227_Y13
R1088

MGTREFCLK1N_226_AB12 AB12 NC MGTREFCLK1N_227_Y12 Y12 NC


AH6 MGTRREF_226
1/10W

MGTRREF_RC_AH6
MGTAVTTRCAL_RC_AH7 AH7 MGTAVTT_FPGA
100

1%

TITLE: FPGA Banks 224 225 226 227 ASSY P/N: 0431880
1

A U1 SCHEM, ROHS COMPLIANT PCB P/N: 1280790


SOC_FLGC2104_IRON
HW-U1-VCU110_REV1_0 SCH P/N: 0381622
U1 TEST P/N: TSS0174
SOC_FLGC2104_IRON
A
DATE: 09/21/2015:13:57 VER: 1.0

SHEET SIZE: B REV: 01

SHEET OF DRAWN BY:


15 92 BF

4 3 2 1
4 3 2 1

SOC_VU190_FLGC2104_IRONWOOD
SOC_VU190_FLGC2104_IRONWOOD

D D
BANK 228 BANK 229
XCVU190FLGC2104 XCVU190FLGC2104
MGTHTXP0_229_R7 R7 HMC_L0TX_12_P
MGTHTXP0_228_W7 W7 HMC_L1TX_12_P
MGTHTXN0_229_R6 R6 HMC_L0TX_12_N
MGTHTXN0_228_W6 W6 HMC_L1TX_12_N
MGTHRXP0_229_R2 R2 HMC_L0RX_12_C_P
MGTHRXP0_228_W2 W2 HMC_L1RX_12_C_P
MGTHRXN0_229_R1 R1 HMC_L0RX_12_C_N
MGTHRXN0_228_W1 W1 HMC_L1RX_12_C_N
MGTHTXP1_229_P9 P9 HMC_L0TX_9_P
MGTHTXP1_228_V9 V9 HMC_L1TX_10_P
MGTHTXN1_229_P8 P8 HMC_L0TX_9_N
MGTHTXN1_228_V8 V8 HMC_L1TX_10_N
MGTHRXP1_229_P4 P4 HMC_L0RX_9_C_P
MGTHRXP1_228_V4 V4 HMC_L1RX_10_C_P
MGTHRXN1_229_P3 P3 HMC_L0RX_9_C_N
MGTHRXN1_228_V3 V3 HMC_L1RX_10_C_N
MGTHTXP2_229_N7 N7 HMC_L0TX_13_P
MGTHTXP2_228_U7 U7 HMC_L1TX_9_P
MGTHTXN2_229_N6 N6 HMC_L0TX_13_N
MGTHTXN2_228_U6 U6 HMC_L1TX_9_N
MGTHRXP2_229_N2 N2 HMC_L0RX_13_C_P
MGTHRXP2_228_U2 U2 HMC_L1RX_9_C_P
MGTHRXN2_229_N1 N1 HMC_L0RX_13_C_N
MGTHRXN2_228_U1 U1 HMC_L1RX_9_C_N
MGTHTXP3_229_M9 M9 HMC_L0TX_8_P
MGTHTXP3_228_T9 T9 HMC_L1TX_8_P
MGTHTXN3_229_M8 M8 HMC_L0TX_8_N
MGTHTXN3_228_T8 T8 HMC_L1TX_8_N
MGTHRXP3_229_M4 M4 HMC_L0RX_8_C_P
MGTHRXP3_228_T4 T4 HMC_L1RX_8_C_P
MGTHRXN3_229_M3 M3 HMC_L0RX_8_C_N
MGTHRXN3_228_T3 T3 HMC_L1RX_8_C_N
MGTREFCLK0P_229_U11 U11 NC
MGTREFCLK0P_228_W11 W11 NC
MGTREFCLK0N_229_U10 U10 NC
MGTREFCLK0N_228_W10 W10 NC
MGTREFCLK1P_229_T13 T13 NC
MGTREFCLK1P_228_V13 V13 NC
MGTREFCLK1N_229_T12 T12 NC
MGTREFCLK1N_228_V12 V12 NC

C C

U1 SOC_FLGC2104_IRON
U1 SOC_FLGC2104_IRON

SOC_VU190_FLGC2104_IRONWOOD SOC_VU190_FLGC2104_IRONWOOD

B B

BANK 230 BANK 231


XCVU190FLGC2104 XCVU190FLGC2104
MGTHTXP0_230_L7 L7 HMC_L0TX_10_P MGTHTXP0_231_G7 G7 HMC_L0TX_4_P
MGTHTXN0_230_L6 L6 HMC_L0TX_10_N MGTHTXN0_231_G6 G6 HMC_L0TX_4_N
MGTHRXP0_230_L2 L2 HMC_L0RX_10_C_P MGTHRXP0_231_G2 G2 HMC_L0RX_4_C_P
MGTHRXN0_230_L1 L1 HMC_L0RX_10_C_N MGTHRXN0_231_G1 G1 HMC_L0RX_4_C_N
MGTHTXP1_230_K9 K9 HMC_L0TX_14_P MGTHTXP1_231_F9 F9 HMC_L0TX_11_P
MGTHTXN1_230_K8 K8 HMC_L0TX_14_N MGTHTXN1_231_F8 F8 HMC_L0TX_11_N
MGTHRXP1_230_K4 K4 HMC_L0RX_14_C_P MGTHRXP1_231_F4 F4 HMC_L0RX_11_C_P
MGTHRXN1_230_K3 K3 HMC_L0RX_14_C_N MGTHRXN1_231_F3 F3 HMC_L0RX_11_C_N
MGTHTXP2_230_J7 J7 HMC_L0TX_0_P MGTHTXP2_231_G11 G11 HMC_L0TX_6_P
MGTHTXN2_230_J6 J6 HMC_L0TX_0_N MGTHTXN2_231_G10 G10 HMC_L0TX_6_N
MGTHRXP2_230_J2 J2 HMC_L0RX_0_C_P MGTHRXP2_231_G16 G16 HMC_L0RX_6_C_P
MGTHRXN2_230_J1 J1 HMC_L0RX_0_C_N MGTHRXN2_231_G15 G15 HMC_L0RX_6_C_N
MGTHTXP3_230_H9 H9 HMC_L0TX_1_P MGTHTXP3_231_F13 F13 HMC_L0TX_2_P
H8 HMC_L0TX_1_N F12 HMC_L0TX_2_N
MGTHTXN3_230_H8
MGTHRXP3_230_H4 H4 HMC_L0RX_1_C_P
MGTHTXN3_231_F12
MGTHRXP3_231_E16 E16 HMC_L0RX_2_C_P FPGA Banks 228 229 230 231
MGTHRXN3_230_H3 H3 HMC_L0RX_1_C_N MGTHRXN3_231_E15 E15 HMC_L0RX_2_C_N
MGTREFCLK0P_230_R11 R11 HMC_SI5328_OUT2_BUF1_C_P MGTREFCLK0P_231_N11 N11 NC
MGTREFCLK0N_230_R10 R10 HMC_SI5328_OUT2_BUF1_C_N MGTREFCLK0N_231_N10 N10 NC

R1089
MGTREFCLK1P_230_P13 P13 NC MGTREFCLK1P_231_M13 M13 NC
P12 NC M12 NC

1/10W
MGTREFCLK1N_230_P12 MGTREFCLK1N_231_M12
MGTRREF_RN_D6 D6 MGTRREF_231 MGTAVTT_FPGA

100
D7 TITLE: FPGA Banks 228 229 230 231 ASSY P/N: 0431880

1%
MGTAVTTRCAL_RN_D7
A SCHEM, ROHS COMPLIANT PCB P/N: 1280790
HW-U1-VCU110_REV1_0 SCH P/N: 0381622

2
TEST P/N: TSS0174
A
U1 SOC_FLGC2104_IRON DATE: 09/21/2015:13:58 VER: 1.0
U1 SOC_FLGC2104_IRON SHEET SIZE: B REV: 01

SHEET OF DRAWN BY:


16 92 BF

4 3 2 1
4 3 2 1

D D

SOC_VU190_FLGC2104_IRONWOOD
SOC_VU190_FLGC2104_IRONWOOD

BANK 232
BANK 233
XCVU190FLGC2104
MGTHTXP0_232_E7 E7 HMC_L0TX_3_P XCVU190FLGC2104
BANK MIGRATION: MGTHTXN0_232_E6 E6 HMC_L0TX_3_N MGTHTXP0_233_D9 D9 PCIE_CABLE_TX3_C_P
VU160 = BANK 232 MGTHRXP0_232_E2 E2 HMC_L0RX_3_C_P BANK MIGRATION: MGTHTXN0_233_D8 D8 PCIE_CABLE_TX3_C_N
VU125 = BANK 232 MGTHRXN0_232_E1 E1 HMC_L0RX_3_C_N VU160 = BANK 233 MGTHRXP0_233_D14 D14 PCIE_CABLE_RX3_P
C C
VU095 = NC MGTHTXP1_232_E11 E11 HMC_L0TX_15_P VU125 = BANK 233 MGTHRXN0_233_D13 D13 PCIE_CABLE_RX3_N
MGTHTXN1_232_E10 E10 HMC_L0TX_15_N VU095 = NC MGTHTXP1_233_C11 C11 PCIE_CABLE_TX2_C_P
MGTHRXP1_232_D4 D4 HMC_L0RX_15_C_P MGTHTXN1_233_C10 C10 PCIE_CABLE_TX2_C_N
MGTHRXN1_232_D3 D3 HMC_L0RX_15_C_N MGTHRXP1_233_C16 C16 PCIE_CABLE_RX2_P
MGTHTXP2_232_C7 C7 HMC_L0TX_5_P MGTHRXN1_233_C15 C15 PCIE_CABLE_RX2_N
MGTHTXN2_232_C6 C6 HMC_L0TX_5_N MGTHTXP2_233_B9 B9 PCIE_CABLE_TX1_C_P
MGTHRXP2_232_C2 C2 HMC_L0RX_5_C_P MGTHTXN2_233_B8 B8 PCIE_CABLE_TX1_C_N
MGTHRXN2_232_C1 C1 HMC_L0RX_5_C_N MGTHRXP2_233_B14 B14 PCIE_CABLE_RX1_P
MGTHTXP3_232_A7 A7 HMC_L0TX_7_P MGTHRXN2_233_B13 B13 PCIE_CABLE_RX1_N
MGTHTXN3_232_A6 A6 HMC_L0TX_7_N MGTHTXP3_233_A11 A11 PCIE_CABLE_TX0_C_P
MGTHRXP3_232_B4 B4 HMC_L0RX_7_C_P MGTHTXN3_233_A10 A10 PCIE_CABLE_TX0_C_N
MGTHRXN3_232_B3 B3 HMC_L0RX_7_C_N MGTHRXP3_233_A16 A16 PCIE_CABLE_RX0_P
MGTREFCLK0P_232_L11 L11 NC MGTHRXN3_233_A15 A15 PCIE_CABLE_RX0_N
MGTREFCLK0N_232_L10 L10 NC MGTREFCLK0P_233_J11 J11 PCIE_CABLE_CLK_C_P
MGTREFCLK1P_232_K13 K13 NC MGTREFCLK0N_233_J10 J10 PCIE_CABLE_CLK_C_N
MGTREFCLK1N_232_K12 K12 NC MGTREFCLK1P_233_H13 H13 NC
MGTREFCLK1N_233_H12 H12 NC

U1 SOC_FLGC2104_IRON
U1 SOC_FLGC2104_IRON

C2669
0.1UF

C2670
25V
B B

0.1UF
25V
PCIE_CABLE_TX0_C_P PCIE_CABLE_TX0_P

C26711
2
PCIE_CABLE_TX0_C_N PCIE_CABLE_TX0_N

0.1UF

C26721
2
25V

0.1UF
25V
PCIE_CABLE_TX1_C_P PCIE_CABLE_TX1_P

C26731
2
PCIE_CABLE_TX1_C_N PCIE_CABLE_TX1_N

0.1UF

C26741
2
25V

0.1UF
25V
PCIE_CABLE_TX2_C_P PCIE_CABLE_TX2_P
C2675 1 FPGA Bank 232 233
2
PCIE_CABLE_TX2_C_N PCIE_CABLE_TX2_N

C2676 1
2
0.1UF
25V

0.1UF
25V
PCIE_CABLE_TX3_C_P PCIE_CABLE_TX3_P
TITLE: FPGA Bank 232 233 ASSY P/N: 0431880
C2677 1
2

A SCHEM, ROHS COMPLIANT PCB P/N: 1280790


PCIE_CABLE_TX3_C_N PCIE_CABLE_TX3_N
HW-U1-VCU110_REV1_0 SCH P/N: 0381622
C2678 1
2
0.1UF

TEST P/N: TSS0174


A
25V

DATE: 09/21/2015:13:58 VER: 1.0


0.1UF
25V

PCIE_CABLE_CLK_C_P PCIE_CABLE_CLK_P SHEET SIZE: B REV: 01


1

SHEET OF DRAWN BY:


PCIE_CABLE_CLK_C_N PCIE_CABLE_CLK_N
17 92 BF
1

4 3 2 1
4 3 2 1

SOC_VU190_FLGC2104_IRONWOOD SOC_VU190_FLGC2104_IRONWOOD SOC_VU190_FLGC2104_IRONWOOD

D BANK MGTAVCC_LC MGTAVCC_FPGA BANK MGTAVCC_LN MGTAVCC_FPGA BANK MGTAVCC_LS MGTAVCC_FPGA


D

XCVU190FLGC2104 XCVU190FLGC2104 XCVU190FLGC2104


MGTAVCC_LC_AF36 AF36 MGTAVCC_LN_T37 T37 MGTAVCC_LS_AL38 AL38
MGTAVCC_LC_AE35 AE35 MGTAVCC_LN_R34 R34 MGTAVCC_LS_AL34 AL34
MGTAVCC_LC_AD37 AD37 MGTAVCC_LN_P36 P36 MGTAVCC_LS_AJ35 AJ35
MGTAVCC_LC_AC34 AC34 MGTAVCC_LN_N35 N35 MGTAVCC_LS_AH37 AH37
MGTAVCC_LC_AA35 AA35 MGTAVCC_LN_M37 M37 MGTAVCC_LS_AG34 AG34
MGTAVCC_LC_W38 W38 MGTAVCC_LN_K36 K36
MGTAVCC_LC_W34 W34 MGTAVCC_LN_H37 H37
MGTAVCC_LC_V36 V36 MGTAVCC_LN_G34 G34
MGTAVCC_LC_U35 U35 MGTAVCC_LN_F36 F36

U1 SOC_FLGC2104_IRON

U1 SOC_FLGC2104_IRON U1 SOC_FLGC2104_IRON

C C

SOC_VU190_FLGC2104_IRONWOOD SOC_VU190_FLGC2104_IRONWOOD SOC_VU190_FLGC2104_IRONWOOD

BANK MGTAVCC_RC MGTAVCC_FPGA BANK MGTAVCC_RN MGTAVCC_FPGA BANK MGTAVCC_RS MGTAVCC_FPGA


XCVU190FLGC2104 XCVU190FLGC2104 XCVU190FLGC2104
MGTAVCC_RC_AF11 AF11 MGTAVCC_RN_T10 T10 MGTAVCC_RS_AL13 AL13
MGTAVCC_RC_AE12 AE12 MGTAVCC_RN_R13 R13 MGTAVCC_RS_AL9 AL9
MGTAVCC_RC_AD10 AD10 MGTAVCC_RN_P11 P11 MGTAVCC_RS_AJ12 AJ12
MGTAVCC_RC_AC13 AC13 MGTAVCC_RN_N12 N12 MGTAVCC_RS_AH10 AH10
MGTAVCC_RC_AA12 AA12 MGTAVCC_RN_M10 M10 MGTAVCC_RS_AG13 AG13
MGTAVCC_RC_W13 W13 MGTAVCC_RN_K11 K11
MGTAVCC_RC_W9 W9 MGTAVCC_RN_H10 H10
B B
MGTAVCC_RC_V11 V11 MGTAVCC_RN_G13 G13
MGTAVCC_RC_U12 U12 MGTAVCC_RN_F11 F11

U1 SOC_FLGC2104_IRON

U1 SOC_FLGC2104_IRON U1 SOC_FLGC2104_IRON

FPGA Power 1

TITLE: FPGA Power 1 ASSY P/N: 0431880


A SCHEM, ROHS COMPLIANT PCB P/N: 1280790
HW-U1-VCU110_REV1_0 SCH P/N: 0381622
TEST P/N: TSS0174
A
DATE: 09/21/2015:13:57 VER: 1.0

SHEET SIZE: B REV: 01

SHEET OF DRAWN BY:


18 92 BF

4 3 2 1
4 3 2 1

SOC_VU190_FLGC2104_IRONWOOD SOC_VU190_FLGC2104_IRONWOOD SOC_VU190_FLGC2104_IRONWOOD

BANK MGTAVTT_LC MGTAVTT_FPGA


BANK MGTAVTT_LN MGTAVTT_FPGA
BANK MGTAVTT_LS MGTAVTT_FPGA

D
XCVU190FLGC2104 XCVU190FLGC2104 XCVU190FLGC2104 D
MGTAVTT_LC_AT41 AT41 MGTAVTT_LN_T41 T41 MGTAVTT_LS_BF40 BF40
MGTAVTT_LC_AR38 AR38 MGTAVTT_LN_R38 R38 MGTAVTT_LS_BF37 BF37
MGTAVTT_LC_AP40 AP40 MGTAVTT_LN_P40 P40 MGTAVTT_LS_BE39 BE39
MGTAVTT_LC_AN39 AN39 MGTAVTT_LN_N39 N39 MGTAVTT_LS_BD41 BD41
MGTAVTT_LC_AM41 AM41 MGTAVTT_LN_M41 M41 MGTAVTT_LS_BC38 BC38
MGTAVTT_LC_AK40 AK40 MGTAVTT_LN_L38 L38 MGTAVTT_LS_BB40 BB40
MGTAVTT_LC_AJ39 AJ39 MGTAVTT_LN_K40 K40 MGTAVTT_LS_BA39 BA39
MGTAVTT_LC_AG38 AG38 MGTAVTT_LN_J39 J39 MGTAVTT_LS_AY41 AY41
MGTAVTT_LC_AF40 AF40 MGTAVTT_LN_H41 H41 MGTAVTT_LS_AW38 AW38
MGTAVTT_LC_AE39 AE39 MGTAVTT_LN_G38 G38 MGTAVTT_LS_AV40 AV40
MGTAVTT_LC_AD41 AD41 MGTAVTT_LN_F40 F40 MGTAVTT_LS_AU39 AU39
MGTAVTT_LC_AC38 AC38 MGTAVTT_LN_E39 E39
MGTAVTT_LC_AB40 AB40 MGTAVTT_LN_D37 D37
MGTAVTT_LC_AA39 AA39 MGTAVTT_LN_C38 C38
MGTAVTT_LC_Y41 Y41 MGTAVTT_LN_B40 B40
MGTAVTT_LC_V40 V40 MGTAVTT_LN_B36 B36
MGTAVTT_LC_U39 U39 MGTAVTT_LN_A43 A43
U1 SOC_FLGC2104_IRON

U1 SOC_FLGC2104_IRON U1 SOC_FLGC2104_IRON

C C

SOC_VU190_FLGC2104_IRONWOOD SOC_VU190_FLGC2104_IRONWOOD SOC_VU190_FLGC2104_IRONWOOD

BANK MGTAVTT_RC MGTAVTT_FPGA


BANK MGTAVTT_RN MGTAVTT_FPGA
BANK MGTAVTT_RS MGTAVTT_FPGA
XCVU190FLGC2104 XCVU190FLGC2104 XCVU190FLGC2104
MGTAVTT_RC_AT6 AT6 MGTAVTT_RN_T6 T6 MGTAVTT_RS_BF10 BF10
MGTAVTT_RC_AR9 AR9 MGTAVTT_RN_R9 R9 MGTAVTT_RS_BF7 BF7
MGTAVTT_RC_AP7 AP7 MGTAVTT_RN_P7 P7 MGTAVTT_RS_BE8 BE8
MGTAVTT_RC_AN8 AN8 MGTAVTT_RN_N8 N8 MGTAVTT_RS_BD6 BD6
MGTAVTT_RC_AM6 AM6 MGTAVTT_RN_M6 M6 MGTAVTT_RS_BC9 BC9
MGTAVTT_RC_AK7 AK7 MGTAVTT_RN_L9 L9 MGTAVTT_RS_BB7 BB7
MGTAVTT_RC_AJ8 AJ8 MGTAVTT_RN_K7 K7 MGTAVTT_RS_BA8 BA8
MGTAVTT_RC_AG9 AG9 MGTAVTT_RN_J8 J8 MGTAVTT_RS_AY6 AY6
MGTAVTT_RC_AF7 AF7 MGTAVTT_RN_H6 H6 MGTAVTT_RS_AW9 AW9
MGTAVTT_RC_AE8 AE8 MGTAVTT_RN_G9 G9 MGTAVTT_RS_AV7 AV7
B MGTAVTT_RC_AD6 AD6 MGTAVTT_RN_F7 F7 MGTAVTT_RS_AU8 AU8 B
MGTAVTT_RC_AC9 AC9 MGTAVTT_RN_E8 E8
MGTAVTT_RC_AB7 AB7 MGTAVTT_RN_D10 D10
MGTAVTT_RC_AA8 AA8 MGTAVTT_RN_C9 C9
MGTAVTT_RC_Y6 Y6 MGTAVTT_RN_B11 B11
MGTAVTT_RC_V7 V7 MGTAVTT_RN_B7 B7
MGTAVTT_RC_U8 U8 MGTAVTT_RN_A4 A4
U1 SOC_FLGC2104_IRON

U1 SOC_FLGC2104_IRON U1 SOC_FLGC2104_IRON

FPGA Power 2

TITLE: FPGA Power 2 ASSY P/N: 0431880


A SCHEM, ROHS COMPLIANT PCB P/N: 1280790
HW-U1-VCU110_REV1_0 SCH P/N: 0381622
TEST P/N: TSS0174
A
DATE: 09/21/2015:13:58 VER: 1.0

SHEET SIZE: B REV: 01

SHEET OF DRAWN BY:


19 92 BF

4 3 2 1
4 3 2 1

SOC_VU190_FLGC2104_IRONWOOD SOC_VU190_FLGC2104_IRONWOOD SOC_VU190_FLGC2104_IRONWOOD

D BANK MGTVCCAUX_LC MGTVCCAUX BANK MGTVCCAUX_LN MGTVCCAUX BANK MGTVCCAUX_LS MGTVCCAUX


D

XCVU190FLGC2104 XCVU190FLGC2104 XCVU190FLGC2104


MGTVCCAUX_LC_AB36 AB36 MGTVCCAUX_LN_L34 L34 MGTVCCAUX_LS_AM37 AM37
MGTVCCAUX_LC_Y37 Y37 MGTVCCAUX_LN_J35 J35 MGTVCCAUX_LS_AK36 AK36

U1 SOC_FLGC2104_IRON U1 SOC_FLGC2104_IRON U1 SOC_FLGC2104_IRON

SOC_VU190_FLGC2104_IRONWOOD
SOC_VU190_FLGC2104_IRONWOOD SOC_VU190_FLGC2104_IRONWOOD

C C
BANK MGTVCCAUX_RC MGTVCCAUX
BANK MGTVCCAUX_RN MGTVCCAUX BANK MGTVCCAUX_RS MGTVCCAUX
XCVU190FLGC2104
MGTVCCAUX_RC_AB11 AB11 XCVU190FLGC2104 XCVU190FLGC2104
MGTVCCAUX_RC_Y10 Y10 MGTVCCAUX_RN_L13 L13 MGTVCCAUX_RS_AM10 AM10
MGTVCCAUX_RN_J12 J12 MGTVCCAUX_RS_AK11 AK11

U1 SOC_FLGC2104_IRON
U1 SOC_FLGC2104_IRON U1 SOC_FLGC2104_IRON

B B

FPGA Power 3

TITLE: FPGA Power 3 ASSY P/N: 0431880


A SCHEM, ROHS COMPLIANT PCB P/N: 1280790
HW-U1-VCU110_REV1_0 SCH P/N: 0381622
TEST P/N: TSS0174
A
DATE: 09/21/2015:13:58 VER: 1.0

SHEET SIZE: B REV: 01

SHEET OF DRAWN BY:


20 92 BF

4 3 2 1
4 3 2 1

SOC_VU190_FLGC2104_IRONWOOD SOC_VU190_FLGC2104_IRONWOOD
VCC1V8_FPGA
SOC_VU190_FLGC2104_IRONWOOD
VCCINT_FPGA

BANK VCCINT_IO BANK VCCAUX


D
VCCINT_FPGA BANK VCCINT VCCINT_FPGA XCVU190FLGC2104 XCVU190FLGC2104 D
XCVU190FLGC2104 VCCINT_IO_AL29 AL29
AJ29
VCCAUX_AK32 AK32
AH32
AL27 AB28 VCCINT_IO_AJ29 VCCAUX_AH32
VCCINT_AL27 VCCINT_AB28 AG29 AF32
AL25 AB26 VCCINT_IO_AG29 VCCAUX_AF32
VCCINT_AL25 VCCINT_AB26 AE29 AE31
AL23 AB24 VCCINT_IO_AE29 VCCAUX_AE31
VCCINT_AL23 VCCINT_AB24 AC29 AD32
AL21 AB22 VCCINT_IO_AC29 VCCAUX_AD32
VCCINT_AL21 VCCINT_AB22 AA29 AC31
AL19 AB18 VCCINT_IO_AA29 VCCAUX_AC31
VCCINT_AL19 VCCINT_AB18 V30 AB32
AL17 AA27 VCCINT_IO_V30 VCCAUX_AB32
VCCINT_AL17 VCCINT_AA27 T30 Y32
AL15 AA25 VCCINT_IO_T30 VCCAUX_Y32
VCCINT_AL15 VCCINT_AA25 P30 V32
AK28 AA23 VCCINT_IO_P30 VCCAUX_V32
VCCINT_AK28 VCCINT_AA23 T32
AK26 AA21 VCCAUX_T32
VCCINT_AK26 VCCINT_AA21 P32
AK24 AA19 VCCAUX_P32
VCCINT_AK24 VCCINT_AA19
AK22 VCCINT_AK22 VCCINT_Y28 Y28
AK20 VCCINT_AK20 VCCINT_Y26 Y26
AK18 VCCINT_AK18 VCCINT_Y24 Y24
AK16 VCCINT_AK16 VCCINT_Y22 Y22 U1 SOC_FLGC2104_IRON
AJ27 VCCINT_AJ27 VCCINT_Y20 Y20
AJ25 VCCINT_AJ25 VCCINT_Y18 Y18 U1 SOC_FLGC2104_IRON
AJ23 VCCINT_AJ23 VCCINT_W29 W29
AJ21 VCCINT_AJ21 VCCINT_W27 W27
AJ19 VCCINT_AJ19 VCCINT_W25 W25
AJ17 VCCINT_AJ17 VCCINT_W23 W23
SOC_VU190_FLGC2104_IRONWOOD SOC_VU190_FLGC2104_IRONWOOD
AJ15 VCCINT_AJ15 VCCINT_W21 W21
AH28 VCCINT_AH28 VCCINT_W19 W19 VCC1V8_FPGA
AH26 VCCINT_AH26 VCCINT_V28 V28
AH24 VCCINT_AH24 VCCINT_V26 V26 VCCINT_FPGA
AH22 VCCINT_AH22 VCCINT_V24 V24
C AH20
AH18
VCCINT_AH20 VCCINT_V22 V22
V20
BANK VCCBRAM BANK VCCAUX_IO C
VCCINT_AH18 VCCINT_V20
AH16
AG27
VCCINT_AH16 VCCINT_V18 V18
U29
XCVU190FLGC2104 XCVU190FLGC2104
VCCINT_AG27 VCCINT_U29 AG17 AL31
AG25 U27 VCCBRAM_AG17 VCCAUX_IO_AL31
VCCINT_AG25 VCCINT_U27 AE17 AK30
AG23 U25 VCCBRAM_AE17 VCCAUX_IO_AK30
VCCINT_AG23 VCCINT_U25 AC17 AJ31
AG21 U23 VCCBRAM_AC17 VCCAUX_IO_AJ31
VCCINT_AG21 VCCINT_U23 AA17 AH30
AG19 U21 VCCBRAM_AA17 VCCAUX_IO_AH30
VCCINT_AG19 VCCINT_U21 Y16 AG31
AF28 U19 VCCBRAM_Y16 VCCAUX_IO_AG31
VCCINT_AF28 VCCINT_U19 W17 AF30
AF26 U17 VCCBRAM_W17 VCCAUX_IO_AF30
VCCINT_AF26 VCCINT_U17 W15 AD30
AF24 U15 VCCBRAM_W15 VCCAUX_IO_AD30
VCCINT_AF24 VCCINT_U15 V16 AB30
AF22 T28 VCCBRAM_V16 VCCAUX_IO_AB30
VCCINT_AF22 VCCINT_T28 AA31
AF20 T26 VCCAUX_IO_AA31
VCCINT_AF20 VCCINT_T26 Y30
AF18 T24 VCCAUX_IO_Y30
VCCINT_AF18 VCCINT_T24 W31
AE27 T22 VCCAUX_IO_W31
VCCINT_AE27 VCCINT_T22 U31
AE25 T20 VCCAUX_IO_U31
VCCINT_AE25 VCCINT_T20 R31
AE23 T18 VCCAUX_IO_R31
VCCINT_AE23 VCCINT_T18
AE21 VCCINT_AE21 VCCINT_T16 T16 U1 SOC_FLGC2104_IRON
AD28 VCCINT_AD28 VCCINT_R29 R29
AD26 VCCINT_AD26 VCCINT_R27 R27
AD24 VCCINT_AD24 VCCINT_R25 R25
AD22 VCCINT_AD22 VCCINT_R23 R23
AD18 VCCINT_AD18 VCCINT_R21 R21 U1 SOC_FLGC2104_IRON
AC27 VCCINT_AC27 VCCINT_R19 R19
AC25 VCCINT_AC25 VCCINT_R17 R17
AC23 VCCINT_AC23 VCCINT_R15 R15
AC21 VCCINT_AC21 VCCINT_P28 P28
VCCINT_P26 P26
B SOC_VU190_FLGC2104_IRONWOOD B

U1 SOC_FLGC2104_IRON
NO CONNECTS
XCVU190FLGC2104
NC_A39 A39 NC
NC_A38 A38 NC
NC_A9 A9 NC
NC_A8 A8 NC

U1 SOC_FLGC2104_IRON FPGA Power 4

TITLE: FPGA Power 4 ASSY P/N: 0431880


A SCHEM, ROHS COMPLIANT PCB P/N: 1280790
HW-U1-VCU110_REV1_0 SCH P/N: 0381622
TEST P/N: TSS0174
A
DATE: 09/21/2015:13:57 VER: 1.0

SHEET SIZE: B REV: 01

SHEET OF DRAWN BY:


21 92 BF

4 3 2 1
A
B
C
D
SOC_VU190_FLGC2104_IRONWOOD
SOC_VU190_FLGC2104_IRONWOOD

BANK GND2 BANK GND1


XCVU190FLGC2104 XCVU190FLGC2104GND_F37 F37
AC5 GND_AC5 GND_V21 V21 N5 GND_N5 GND_F33 F33
AC4 GND_AC4 GND_V19 V19 N4 GND_N4 GND_F32 F32
AC3 GND_AC3 GND_V17 V17 N3 GND_N3 GND_F31 F31
AB46 V15 M46 F30

4
4

GND_AB46 GND_V15 GND_M46 GND_F30


AB45 GND_AB45 GND_V10 V10 M45 GND_M45 GND_F27 F27
AB42 GND_AB42 GND_V6 V6 M42 GND_M42 GND_F17 F17
AB41 GND_AB41 GND_V5 V5 M40 GND_M40 GND_F16 F16
AB37 GND_AB37 GND_V2 V2 M36 GND_M36 GND_F15 F15
AB33 GND_AB33 GND_V1 V1 M33 GND_M33 GND_F14 F14
AB31 GND_AB31 GND_U44 U44 M29 GND_M29 GND_F10 F10
AB29 GND_AB29 GND_U43 U43 M19 GND_M19 GND_F6 F6
AB27 GND_AB27 GND_U42 U42 M11 GND_M11 GND_F5 F5
AB25 GND_AB25 GND_U38 U38 M7 GND_M7 GND_F2 F2
AB23 GND_AB23 GND_U34 U34 M5 GND_M5 GND_F1 F1
AB21 GND_AB21 GND_U33 U33 M2 GND_M2 GND_E44 E44
AB17 GND_AB17 GND_U32 U32 M1 GND_M1 GND_E43 E43
AB10 GND_AB10 GND_U30 U30 L44 GND_L44 GND_E42 E42
AB6 GND_AB6 GND_U28 U28 L43 GND_L43 GND_E38 E38
AB5 GND_AB5 GND_U26 U26 L42 GND_L42 GND_E35 E35
AB2 GND_AB2 GND_U24 U24 L39 GND_L39 GND_E34 E34
AB1 GND_AB1 GND_U22 U22 L35 GND_L35 GND_E33 E33
AA44 GND_AA44 GND_U20 U20 L33 GND_L33 GND_E30 E30
AA43 GND_AA43 GND_U18 U18 L32 GND_L32 GND_E20 E20
AA42 GND_AA42 GND_U16 U16 L22 GND_L22 GND_E17 E17
AA38 GND_AA38 GND_U14 U14 L14 GND_L14 GND_E14 E14
AA34 GND_AA34 GND_U13 U13 L12 GND_L12 GND_E13 E13
AA33 GND_AA33 GND_U9 U9 L8 GND_L8 GND_E12 E12
AA32 GND_AA32 GND_U5 U5 L5 GND_L5 GND_E9 E9
AA30 GND_AA30 GND_U4 U4 L4 GND_L4 GND_E5 E5
AA28 GND_AA28 GND_U3 U3 L3 GND_L3 GND_E4 E4
AA26 GND_AA26 GND_T46 T46 K46 GND_K46 GND_E3 E3
AA24 GND_AA24 GND_T45 T45 K45 GND_K45 GND_D46 D46
AA22 GND_AA22 GND_T42 T42 K42 GND_K42 GND_D45 D45
AA20 GND_AA20 GND_T40 T40 K41 GND_K41 GND_D42 D42
AA18 GND_AA18 GND_T36 T36 K37 GND_K37 GND_D36 D36
AA16 GND_AA16 GND_T33 T33 K33 GND_K33 GND_D35 D35
AA15 GND_AA15 GND_T31 T31 K25 GND_K25 GND_D32 D32
AA14 GND_AA14 GND_T29 T29 K15 GND_K15 GND_D31 D31
AA13 GND_AA13 GND_T27 T27 K10 GND_K10 GND_D30 D30
AA9 GND_AA9 GND_T25 T25 K6 GND_K6 GND_D23 D23
AA5 GND_AA5 GND_T23 T23 K5 GND_K5 GND_D17 D17
AA4 GND_AA4 GND_T21 T21 K2 GND_K2 GND_D16 D16
AA3 GND_AA3 GND_T19 T19 K1 GND_K1 GND_D15 D15
Y46 GND_Y46 GND_T17 T17 J44 GND_J44 GND_D12 D12
Y45 GND_Y45 GND_T15 T15 J43 GND_J43 GND_D11 D11
Y42 GND_Y42 GND_T11 T11 J42 GND_J42 GND_D5 D5

3
3

Y40 GND_Y40 GND_T7 T7 J38 GND_J38 GND_D2 D2


Y36 GND_Y36 GND_T5 T5 J34 GND_J34 GND_D1 D1
Y33 GND_Y33 GND_T2 T2 J33 GND_J33 GND_C44 C44
Y31 GND_Y31 GND_T1 T1 J28 GND_J28 GND_C43 C43
Y29 GND_Y29 GND_R44 R44 J18 GND_J18 GND_C42 C42
Y27 GND_Y27 GND_R43 R43 J14 GND_J14 GND_C39 C39
Y25 GND_Y25 GND_R42 R42 J13 GND_J13 GND_C35 C35
Y23 GND_Y23 GND_R39 R39 J9 GND_J9 GND_C34 C34
Y21 GND_Y21 GND_R35 R35 J5 GND_J5 GND_C33 C33
Y19 GND_Y19 GND_R33 R33 J4 GND_J4 GND_C30 C30
Y17 GND_Y17 GND_R32 R32 J3 GND_J3 GND_C26 C26
Y15 GND_Y15 GND_R30 R30 H46 GND_H46 GND_C17 C17
Y11 GND_Y11 GND_R28 R28 H45 GND_H45 GND_C14 C14
Y7 GND_Y7 GND_R26 R26 H42 GND_H42 GND_C13 C13
Y5 GND_Y5 GND_R24 R24 H40 GND_H40 GND_C12 C12
Y2 GND_Y2 GND_R22 R22 H36 GND_H36 GND_C8 C8
Y1 GND_Y1 GND_R20 R20 H33 GND_H33 GND_C5 C5
W44 GND_W44 GND_R18 R18 H32 GND_H32 GND_C4 C4
W43 GND_W43 GND_R16 R16 H31 GND_H31 GND_C3 C3
W42 GND_W42 GND_R14 R14 H30 GND_H30 GND_B45 B45
W39 GND_W39 GND_R12 R12 H21 GND_H21 GND_B42 B42
W35 GND_W35 GND_R8 R8 H17 GND_H17 GND_B41 B41
W33 GND_W33 GND_R5 R5 H16 GND_H16 GND_B37 B37
W32 GND_W32 GND_R4 R4 H15 GND_H15 GND_B35 B35
W30 GND_W30 GND_R3 R3 H14 GND_H14 GND_B32 B32
W28 GND_W28 GND_P46 P46 H11 GND_H11 GND_B31 B31
W26 GND_W26 GND_P45 P45 H7 GND_H7 GND_B30 B30
W24 GND_W24 GND_P42 P42 H5 GND_H5 GND_B29 B29
W22 GND_W22 GND_P41 P41 H2 GND_H2 GND_B19 B19
W20 GND_W20 GND_P37 P37 H1 GND_H1 GND_B17 B17
W18 GND_W18 GND_P33 P33 G44 GND_G44 GND_B16 B16
W16 GND_W16 GND_P31 P31 G43 GND_G43 GND_B15 B15
W14 GND_W14 GND_P29 P29 G42 GND_G42 GND_B12 B12
W12 GND_W12 GND_P23 P23 G39 GND_G39 GND_B10 B10
W8 GND_W8 GND_P10 P10 G35 GND_G35 GND_B6 B6
W5 GND_W5 GND_P6 P6 G33 GND_G33 GND_B5 B5
W4 GND_W4 GND_P5 P5 G30 GND_G30 GND_B2 B2
W3 GND_W3 GND_P2 P2 G24 GND_G24 GND_A44 A44
V46 GND_V46 GND_P1 P1 G17 GND_G17 GND_A42 A42
V45 GND_V45 GND_N44 N44 G14 GND_G14 GND_A35 A35
V42 GND_V42 GND_N43 N43 G12 GND_G12 GND_A34 A34
V41 GND_V41 GND_N42 N42 G8 GND_G8 GND_A33 A33
V37 N38 G5 A30

2
2

GND_V37 GND_N38 GND_G5 GND_A30


V33 GND_V33 GND_N34 N34 G4 GND_G4 GND_A22 A22
V31 GND_V31 GND_N33 N33 G3 GND_G3 GND_A17 A17
V29 GND_V29 GND_N26 N26 F46 GND_F46 GND_A14 A14
V27 GND_V27 GND_N16 N16 F45 GND_F45 GND_A13 A13
V25 GND_V25 GND_N14 N14 F42 GND_F42 GND_A12 A12
V23 GND_V23 GND_N13 N13 F41 GND_F41 GND_A5 A5
GND_N9 N9 GND_A3 A3

GND U1 U1
SOC_FLGC2104_IRON SOC_FLGC2104_IRON

GND
GND GND
SHEET
SHEET SIZE: B
TITLE: FPGA GND1

22
FPGA GND1

DATE: 09/21/2015:13:57

OF
HW-U1-VCU110_REV1_0
SCHEM, ROHS COMPLIANT

92
1
1

REV:
VER:

DRAWN BY:
BF
01
1.0
SCH P/N:
PCB P/N:

TEST P/N:
ASSY P/N:

TSS0174
0381622
1280790
0431880

A
B
C
D
A
B
C
D
SOC_VU190_FLGC2104_IRONWOOD SOC_VU190_FLGC2104_IRONWOOD

BANK GND4 BANK GND3


XCVU190FLGC2104 XCVU190FLGC2104
BF42 GND_BF42 GND_AY21 AY21 AN5 GND_AN5 GND_AH1 AH1
BF41 GND_BF41 GND_AY11 AY11 AN4 GND_AN4 GND_AG44 AG44
BF36 GND_BF36 GND_AY10 AY10 AN3 GND_AN3 GND_AG43 AG43
BF35 GND_BF35 GND_AY7 AY7 AM46 GND_AM46 GND_AG42 AG42
BF32 GND_BF32 GND_AY5 AY5 AM45 GND_AM45 GND_AG39 AG39
BF23 GND_BF23 GND_AY2 AY2 AM42 GND_AM42 GND_AG35 AG35

4
4

BF15 GND_BF15 GND_AY1 AY1 AM40 GND_AM40 GND_AG33 AG33


BF12 GND_BF12 GND_AW44 AW44 AM36 GND_AM36 GND_AG32 AG32
BF11 GND_BF11 GND_AW43 AW43 AM33 GND_AM33 GND_AG30 AG30
BF6 GND_BF6 GND_AW42 AW42 AM25 GND_AM25 GND_AG28 AG28
BF5 GND_BF5 GND_AW39 AW39 AM15 GND_AM15 GND_AG26 AG26
BE45 GND_BE45 GND_AW37 AW37 AM11 GND_AM11 GND_AG24 AG24
BE44 GND_BE44 GND_AW34 AW34 AM7 GND_AM7 GND_AG22 AG22
BE43 GND_BE43 GND_AW24 AW24 AM5 GND_AM5 GND_AG20 AG20
BE42 GND_BE42 GND_AW14 AW14 AM2 GND_AM2 GND_AG18 AG18
BE38 GND_BE38 GND_AW10 AW10 AM1 GND_AM1 GND_AG16 AG16
BE35 GND_BE35 GND_AW8 AW8 AL44 GND_AL44 GND_AG15 AG15
BE34 GND_BE34 GND_AW5 AW5 AL43 GND_AL43 GND_AG14 AG14
BE33 GND_BE33 GND_AW4 AW4 AL42 GND_AL42 GND_AG12 AG12
BE32 GND_BE32 GND_AW3 AW3 AL39 GND_AL39 GND_AG8 AG8
BE26 GND_BE26 GND_AV46 AV46 AL35 GND_AL35 GND_AG5 AG5
BE15 GND_BE15 GND_AV45 AV45 AL33 GND_AL33 GND_AG4 AG4
BE14 GND_BE14 GND_AV42 AV42 AL32 GND_AL32 GND_AG3 AG3
BE13 GND_BE13 GND_AV41 AV41 AL30 GND_AL30 GND_AF46 AF46
BE12 GND_BE12 GND_AV37 AV37 AL28 GND_AL28 GND_AF45 AF45
BE9 GND_BE9 GND_AV27 AV27 AL26 GND_AL26 GND_AF42 AF42
BE5 GND_BE5 GND_AV17 AV17 AL24 GND_AL24 GND_AF41 AF41
BE4 GND_BE4 GND_AV10 AV10 AL22 GND_AL22 GND_AF37 AF37
BE3 GND_BE3 GND_AV6 AV6 AL20 GND_AL20 GND_AF33 AF33
BE2 GND_BE2 GND_AV5 AV5 AL18 GND_AL18 GND_AF31 AF31
BD46 GND_BD46 GND_AV2 AV2 AL16 GND_AL16 GND_AF29 AF29
BD45 GND_BD45 GND_AV1 AV1 AL14 GND_AL14 GND_AF27 AF27
BD42 GND_BD42 GND_AU44 AU44 AL12 GND_AL12 GND_AF25 AF25
BD40 GND_BD40 GND_AU43 AU43 AL8 GND_AL8 GND_AF23 AF23
BD35 GND_BD35 GND_AU42 AU42 AL5 GND_AL5 GND_AF21 AF21
BD32 GND_BD32 GND_AU38 AU38 AL4 GND_AL4 GND_AF19 AF19
BD29 GND_BD29 GND_AU37 AU37 AL3 GND_AL3 GND_AF17 AF17
BD19 GND_BD19 GND_AU30 AU30 AK46 GND_AK46 GND_AF10 AF10
BD15 GND_BD15 GND_AU20 AU20 AK45 GND_AK45 GND_AF6 AF6
BD12 GND_BD12 GND_AU10 AU10 AK42 GND_AK42 GND_AF5 AF5
BD7 GND_BD7 GND_AU9 AU9 AK41 GND_AK41 GND_AF2 AF2
BD5 GND_BD5 GND_AU5 AU5 AK37 GND_AK37 GND_AF1 AF1
BD2 GND_BD2 GND_AU4 AU4 AK33 GND_AK33 GND_AE44 AE44
BD1 GND_BD1 GND_AU3 AU3 AK31 GND_AK31 GND_AE43 AE43
BC44 GND_BC44 GND_AT46 AT46 AK29 GND_AK29 GND_AE42 AE42
BC43 GND_BC43 GND_AT45 AT45 AK27 GND_AK27 GND_AE38 AE38
BC42 GND_BC42 GND_AT42 AT42 AK25 GND_AK25 GND_AE34 AE34
BC39 GND_BC39 GND_AT40 AT40 AK23 GND_AK23 GND_AE33 AE33
BC37 AT37 AK21 AE32

3
3

GND_BC37 GND_AT37 GND_AK21 GND_AE32


BC36 GND_BC36 GND_AT33 AT33 AK19 GND_AK19 GND_AE30 AE30
BC35 GND_BC35 GND_AT23 AT23 AK17 GND_AK17 GND_AE28 AE28
BC34 GND_BC34 GND_AT13 AT13 AK15 GND_AK15 GND_AE26 AE26
BC33 GND_BC33 GND_AT10 AT10 AK10 GND_AK10 GND_AE24 AE24
BC32 GND_BC32 GND_AT7 AT7 AK6 GND_AK6 GND_AE22 AE22
BC22 GND_BC22 GND_AT5 AT5 AK5 GND_AK5 GND_AE18 AE18
BC15 GND_BC15 GND_AT2 AT2 AK2 GND_AK2 GND_AE16 AE16
BC14 GND_BC14 GND_AT1 AT1 AK1 GND_AK1 GND_AE13 AE13
BC13 GND_BC13 GND_AR44 AR44 AJ44 GND_AJ44 GND_AE9 AE9
BC12 GND_BC12 GND_AR43 AR43 AJ43 GND_AJ43 GND_AE5 AE5
BC11 GND_BC11 GND_AR42 AR42 AJ42 GND_AJ42 GND_AE4 AE4
BC10 GND_BC10 GND_AR39 AR39 AJ38 GND_AJ38 GND_AE3 AE3
BC8 GND_BC8 GND_AR37 AR37 AJ34 GND_AJ34 GND_AD46 AD46
BC5 GND_BC5 GND_AR26 AR26 AJ33 GND_AJ33 GND_AD45 AD45
BC4 GND_BC4 GND_AR16 AR16 AJ32 GND_AJ32 GND_AD42 AD42
BC3 GND_BC3 GND_AR10 AR10 AJ30 GND_AJ30 GND_AD40 AD40
BB46 GND_BB46 GND_AR8 AR8 AJ28 GND_AJ28 GND_AD36 AD36
BB45 GND_BB45 GND_AR5 AR5 AJ26 GND_AJ26 GND_AD33 AD33
BB42 GND_BB42 GND_AR4 AR4 AJ24 GND_AJ24 GND_AD31 AD31
BB41 GND_BB41 GND_AR3 AR3 AJ22 GND_AJ22 GND_AD29 AD29
BB37 GND_BB37 GND_AP46 AP46 AJ20 GND_AJ20 GND_AD27 AD27
BB35 GND_BB35 GND_AP45 AP45 AJ18 GND_AJ18 GND_AD25 AD25
BB25 GND_BB25 GND_AP42 AP42 AJ16 GND_AJ16 GND_AD23 AD23
BB10 GND_BB10 GND_AP41 AP41 AJ14 GND_AJ14 GND_AD21 AD21
BB6 GND_BB6 GND_AP37 AP37 AJ13 GND_AJ13 GND_AD17 AD17
BB5 GND_BB5 GND_AP36 AP36 AJ9 GND_AJ9 GND_AD14 AD14
BB2 GND_BB2 GND_AP35 AP35 AJ5 GND_AJ5 GND_AD11 AD11
BB1 GND_BB1 GND_AP29 AP29 AJ4 GND_AJ4 GND_AD7 AD7
BA44 GND_BA44 GND_AP19 AP19 AJ3 GND_AJ3 GND_AD5 AD5
BA43 GND_BA43 GND_AP12 AP12 AH46 GND_AH46 GND_AD2 AD2
BA42 GND_BA42 GND_AP11 AP11 AH45 GND_AH45 GND_AD1 AD1
BA38 GND_BA38 GND_AP10 AP10 AH42 GND_AH42 GND_AC44 AC44
BA37 GND_BA37 GND_AP6 AP6 AH36 GND_AH36 GND_AC43 AC43
BA28 GND_BA28 GND_AP5 AP5 AH33 GND_AH33 GND_AC42 AC42
BA18 GND_BA18 GND_AP2 AP2 AH31 GND_AH31 GND_AC39 AC39
BA10 GND_BA10 GND_AP1 AP1 AH29 GND_AH29 GND_AC35 AC35
BA9 GND_BA9 GND_AN44 AN44 AH27 GND_AH27 GND_AC33 AC33
BA5 GND_BA5 GND_AN43 AN43 AH25 GND_AH25 GND_AC32 AC32
BA4 GND_BA4 GND_AN42 AN42 AH23 GND_AH23 GND_AC30 AC30
BA3 GND_BA3 GND_AN38 AN38 AH21 GND_AH21 GND_AC28 AC28
AY46 GND_AY46 GND_AN35 AN35 AH19 GND_AH19 GND_AC26 AC26
AY45 GND_AY45 GND_AN34 AN34 AH17 GND_AH17 GND_AC24 AC24

2
2

AY42 GND_AY42 GND_AN33 AN33 AH15 GND_AH15 GND_AC22 AC22


AY40 GND_AY40 GND_AN22 AN22 AH11 GND_AH11 GND_AC18 AC18
AY37 GND_AY37 GND_AN14 AN14 AH5 GND_AH5 GND_AC16 AC16
AY31 GND_AY31 GND_AN12 AN12 AH2 GND_AH2 GND_AC12 AC12
GND_AN9 AN9 GND_AC8 AC8

GND U1 U1
SOC_FLGC2104_IRON SOC_FLGC2104_IRON

GND
GND GND
SHEET
SHEET SIZE: B
TITLE: FPGA GND2

23
FPGA GND2

DATE: 09/21/2015:13:58

OF
HW-U1-VCU110_REV1_0
SCHEM, ROHS COMPLIANT

92
1
1

REV:
VER:

DRAWN BY:
BF
01
1.0
SCH P/N:
PCB P/N:

TEST P/N:
ASSY P/N:

TSS0174
0381622
1280790
0431880

A
B
C
D
4 3 2 1

C2716 C2383 C2388


C2717 C2384 C2389 C657 C1557 C1782 C1784 C1786 C1790
C2721 C2723 C2718 C2386 C2390 C658 C1558 C1781 C1785 C1788 C1791
VCCINT_FPGA
C2800 VCCINT_FPGA VCCINT_FPGA C2719 C2392 C2391 VCCINT_FPGA
C2801 C2722 C2720 C659 C1559 C1783 C1787 C1789
VCCINT 1 1 1 1
VCCINT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
D XILINX 470UF
2V
1 1
470UF
100UF 100UF 100UF 100UF
4V
X6S
2 2 2 2
Maxim, 100UF 100UF 100UF 100UF 100UF 100UF 100UF 100UF 100UF 100UF 100UF 100UF
4V
X6S
2 2 2 2 2 2 2 2 2 2 2 2
4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF
6.3V 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
D

UG583 SP 2 2
Other X5R

V1.3 GND
GND
GND GND

(2x more C2745 C2748 C2752 C2753 C2756 C2760 C2762 C2764 C2768 C2770 C2773 C2777
470UF shown C2747 C2749 C2751 C2755 C2757 C2759 C2763 C2766 C2769 C2772 C2774 C2776
on regulator VCCINT_FPGA VCCINT_FPGA VCCINT_FPGA
page) C2746 C2750 C2754 C2758 C2761 C2765 C2767 C2771 C2775 C2778

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 47UF 47UF 47UF 47UF 47UF 47UF 47UF 47UF 47UF 47UF 47UF 47UF 47UF 47UF 47UF 47UF 47UF 47UF 47UF 47UF 47UF 47UF 47UF 47UF 47UF 47UF
6.3V 2 2 2 2 2 2 2 2 6.3V 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 6.3V 2 2 2 2 2 2 2 2 2
X5R X6S X6S

GND GND GND

C C
VCCBRAM VCCAUX/VCCAUX_IO VCCO_65 84/94 VCCO_68 VCCO_0
VCC1V8_FPGA C919 C921
VCCINT_FPGA VCCINT_FPGA VCC1V8_FPGA VCC1V8_FPGA C920 C1792 VCC1V8_FPGA VADJ_1V8_FPGA VCC1V8_FPGA

XILINX C1486 1
47UF
C330 1
C23041
100UF
C2351
47UF
1 1 1 1
C1828
47UF
1
C1827
47UF
1
C1826
47UF
1
UG583 6.3V
X6S
2
4.7UF
6.3V
X5R
2
4V
X6S
2
6.3V
X6S
2
4.7UF 4.7UF 4.7UF 4.7UF
6.3V
X5R
2 2 2 2
6.3V
X6S
2
6.3V
X6S
2
6.3V
X6S
2

V1.3 GND GND GND GND GND GND


GND
GND

C2301 C2305 C2308


VCCINT_FPGA
VCC1V8_FPGAC2302 VCC1V8_FPGA
C1793 VADJ_1V8_FPGA
VADJ_1V8_FPGA C2306 C2307
C2303 C2665 C1794
C2666 C1795
C331
Maxim, C334 4.7UF1
4.7UF
1
100UF
4V
1 1 1
100UF 100UF
1 1
4.7UF 4.7UF 4.7UF
1 1
4.7UF 4.7UF
1
100UF
4V
1

2
1

2
1 1
100UF 100UF 100UF
2 2
Other 6.3V
X5R
2 2
X6S
2 2 2 6.3V
X5R
2 2 2 6.3V
X5R
2 2
X6S

B B
GND
GND GND GND GND

VCCO_66 / VCCO_67 VCCO_70 / VCCO_71 / VCCO_72


VCC1V5_FPGA VCC1V2_FPGA
XILINX C1829
1
C153
1
UG583 47UF
6.3V
X6S
2
47UF
6.3V
X6S
2
V1.3
GND GND FPGA Decoupling 1
C1452 C1460 C1458 C2310 C2312
C2298 VCC1V5_FPGA C1453 C1461 C1459 C2309 C2313
VCC1V5_FPGA C1450 VCC1V2_FPGA C1456 VCC1V2_FPGA C2311
Maxim, C2299
C2300
C1451 C1457
TITLE: FPGA Decoupling 1 ASSY P/N: 0431880
A
Other 100UF
4V
1

2
1

2
1
100UF 100UF
2 6.3V
1

2
1

2
1
4.7UF 4.7UF 4.7UF 4.7UF
2
1

2 6.3V
1

2
1

2
1

2
1

2
1
4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF
2
1

2
100UF
4V
1

2
1

2
1 1 1
100UF100UF 100UF 100UF
2 2 2
SCHEM, ROHS COMPLIANT
HW-U1-VCU110_REV1_0
PCB P/N:
SCH P/N:
TEST P/N:
1280790
0381622
TSS0174
X6S
X5R X5R X6S A
DATE: 09/21/2015:13:57 VER: 1.0

SHEET SIZE: B REV: 01


GND GND GND GND
SHEET OF DRAWN BY:
24 92 BF

4 3 2 1
4 3 2 1

MGTAVCC MGTAVTT MGTVCCAUX


XILINX C1816 C1812 C1480
C1477 C1813
C1522 C1481
C711 C1804
C1807 C924
C713 C1801
D
UG576 MGTAVCC_FPGA C1482 C1478 C1809
MGTAVTT_FPGA
C1479 C1810 MGTVCCAUX
D
V1.1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1
4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF
UG578 6.3V
X5R
2 2 2 2 2 2
4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF
6.3V
X5R
2 2 2 2 2 2
4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF
6.3V
X5R
2 2 2 2 2 2

V1.10
GND
GND GND

C1513 C2593
C2432 C2404 C2408 C2406 C2412 C1733 C1728 C1729 C2327 C2329 C2315 C2317 C2320 C2323
MGTAVCC_FPGA
MGTAVCC_FPGA C2405 C2410 C2407 C2411 MGTAVTT_FPGA
C2595 MGTAVTT_FPGA MGTVCCAUX C2316 C2318 C2321 C2322
C2433 C2596 C1732 C2331 C2326 C2328 C2330
1 1 1 1 1 1 1 1 100UF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
470UF 470UF 470UF 100UF 100UF 100UF 100UF 100UF 100UF 100UF 100UF 470UF 470UF 470UF 100UF 100UF 100UF 100UF 100UF 100UF 100UF4V
100UF
100UF 100UF 100UF 100UF 100UF 100UF 100UF 100UF 100UF
2V 4V 2V 4V 2 2 2 2 2 2 2 2 X6S
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

C
Maxim, SP 2 2 2 X6S SP 2 2 2 X6S

C
Other GND C2611 C2613 GND
C1808 C596 C1474 GND
GND
GND
C2612 C2615 C1805 C1799 C1796 C2621 C2623 C2625
MGTAVCC_FPGA
MGTAVCC_FPGA C1802 C590 C2619 C2616 C601 C1803 C1475 MGTVCCAUX
C2614 C2617 C2618 MGTAVTT_FPGA
C2622 C2624
MGTAVTT_FPGA C1806 C589 C1797
C2620 C595 C1800
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
10UF
10UF 10UF 10UF 10UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 10UF 10UF 10UF 10UF 10UF
6.3V 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 6.3V 2 2 2 2 2 2 2 2 6.3V 2 2 2 2 2
X5R 10UF 10UF 10UF 10UF 10UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF
X5R X5R
6.3V 2 2 2 2 2 6.3V 2 2 2 2 2 2 2 2
X5R X5R

GND GND
GND
GND
GND
C622 C1521 C1842 C1834 C1846 C1485 C1814 C1811 C1476
C1838 C1520 C614 C1517 C1848 C1518 C1849 C1837 C1519 C1835 MGTVCCAUXC1484 C1483 C1798 C1815
MGTAVCC_FPGA MGTAVTT_FPGA C623 C1839 C1845 C1843 C1515
C1516 C1844 C1836 C1840
C1841 C1847 C615 C1833
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF 0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
6.3V 2 2 2 2 2 2 2 2
6.3V 2 2 2 2 2 2 2 2 2 2 2 2 2 2 6.3V 2 2 2 2 2 2 2 2 2 2 2 2 2 2
X5R
B X6S X6S B

GND
GND GND

C632 C2003 C1547 C2007 C1549


MGTAVCC_FPGA C2004 C628 C2001 C1548 C2005
C630 C2002 C1550 C2006
1 1 1 1 1 1 1 1 1 1 1 1 1 1
0.47UF
0.47UF
0.47UF
0.47UF
0.47UF
0.47UF
0.47UF
0.47UF
0.47UF
0.47UF
0.47UF
0.47UF
0.47UF
0.47UF
10V 2 2 2 2 2 2 2 2 2 2 2 2 2 2
X5R

FPGA Decoupling 2
GND

TITLE: FPGA Decoupling 2 ASSY P/N: 0431880


A SCHEM, ROHS COMPLIANT PCB P/N: 1280790
HW-U1-VCU110_REV1_0 SCH P/N: 0381622
TEST P/N: TSS0174
A
DATE: 09/21/2015:13:57 VER: 1.0

SHEET SIZE: B REV: 01

SHEET OF DRAWN BY:


25 92 BF

4 3 2 1
4 3 2 1

VCC1V8

VCC1V8 R211

R573
1 VCC1V8

1/10W
DIGILENT_USB_JTAG_2_NC
10.0K
87832-1420 1GND1GPIO2_SRST7 NC

R574
1/10W

15

1%

1/10W
2 UTIL_3V3
1%
1 JTAG_TCK 2TCK GPIO16 NC

R575
VSENSE R212

15

1%
1

1/10W
D D

2
2 10.0K JTAG_TDI 3TDI GPIO05 NC
VREF

15

1%
1/10W

2
12 NC 2 1% JTAG_TMS 4TMS
VPRG USB_JTAG_FLTR USB_JTAG_VBUS 3V311
MUSBK15230

2
FERRITE-220
6 JTAG_TCK GND210
TCK 1
VBUS

2
4 JTAG_TMS 6 12DM VREF9
TMS L139 7
SHLD1
SHLD2
10 JTAG_TDI C26091 1 C2608 1 C2607 3 USB_JTAG_DATA_P 13DP TDO8 FMC_HPC1_TDO_LS
TDI D_P
1UF 0.1UF 0.1UF 2 USB_JTAG_DATA_N
D_N
14 NC 25V 2 2 25V 2 25V U115 DIGILENT_USB_JTAG_2_NC
INIT
X5R FERRITE-220 4 USB_JTAG_VBUS
ID TPD4S012
8 FMC_HPC1_TDO_LS
TDO USB_JTAG_GND 5
GND
1 6

2
13 C2802 D_P VBUS GND
PGND L140 1 2
D_N NC
5 NC
GND
3
680PF J135 3
ID GND
4
GND GND 50V 2
C0G, NP0
GND 5
X9
GND
GND 7
GND

GND 9

GND 11

C J3 C

GND
UTIL_3V3 VCC1V8

UTIL_3V3
1 C40 1 C39
0.1UF SN74AVC2T245 0.1UF
2 25V 2 25V
7 6
VCCA VCCB

GND GND
FMC_HPC1_TDO 8 A1 B1 5 FMC_HPC1_TDO_LS

2 10
OE_B DIR1

NC 9 A2 B2 4 NC

B B
3 1
GND DIR2

U13 QFN_RSW_10
UTIL_3V3 GND
VCC1V8

C41 1 R861 1
0.1UF 10.0K C893 C894
1 1
25V 2 1/10W
2 0.1UF 0.1UF
1%
SN74AVC8T245 25V 2 25V 2

1 24
GND VCCA VCCB1
2 23
DIR VCCB2
GND
FPGA_TDO_FMC_TDI
JTAG_TMS
3
4
A1 B1
21
20
FPGA_TDO_FMC_TDI_BUF
FMC_HPC0_TMS_BUF
JTAG Buffer - USB Module - JTAG Header
A2 B2
5 19 FMC_HPC1_TMS_BUF
NC A3 B3
6 18 NC
A4 B4
JTAG_TCK 7 17 FMC_HPC0_TCK_BUF
A5 B5
8 16 FMC_HPC1_TCK_BUF
NC A6 B6
9 15 NC
NC A7 B7
10 14 NC
A8 B8 TITLE: JTAG Buffer - USB Module - JTAG Header ASSY P/N: 0431880
A SCHEM, ROHS COMPLIANT PCB P/N: 1280790
11
GND1 HW-U1-VCU110_REV1_0 SCH P/N: 0381622
12
GND2 TEST P/N: TSS0174
22 13
OE_B GND3 A
DATE: 09/21/2015:13:57 VER: 1.0
TSSOP_24
U19 SHEET SIZE: B REV: 01
GND GND
SHEET OF DRAWN BY:
26 92 BF

4 3 2 1
4 3 2 1

VCC1V5_FPGA VCC1V8
ODT SELECTION HEADER
Pull Up = High Range ZQ/1.66 VCC1V5_FPGA
QDR2_VREF
PCB LAYOUT DIRECTIVE:
Pull Down = Low Range ZQ/3.33
Place 0.1UF adjacent

VREF1 H10
U168 VCC1V5_FPGA 1 R1361

H2

E4
VDDQ1 E8
VDDQ2 F4
VDDQ3 F8
VDDQ4 G4
VDDQ5 G8
VDDQ6 H3
VDDQ7 H4
VDDQ8 H8
VDDQ9 H9
VDDQ10 J4
VDDQ11 J8
VDDQ12 K4
VDDQ13 K8
VDDQ14 L4
VDDQ15 L8

F5
VDD1 F7
VDD2 G5
VDD3 G7
VDD4 H5
VDD5 H7
VDD6 J5
VDD7 J7
VDD8 K5
VDD9 K7
to memory component 100

VREF2

VDD10
VDDQ16
1/10W
D 1 R1386 pins H2 and H10 2 1% D
QDR2_18B_D0 P10
2.21K 1 C1702
D0 Q0P11 QDR2_18B_Q0
1/10W
QDR2_VREF
0.1UF
QDR2_18B_D1 N11 Q1M10 QDR2_18B_Q1 2
D1 1% 2 25V
QDR2_18B_D2 M11 Q2L11 QDR2_18B_Q2 C17011 C17031 R1360
D2 1 X5R
QDR2_18B_D3 K10 Q3K11 QDR2_18B_Q3
D3 0.1UF 0.1UF 100
QDR2_18B_D4 J11 Q4J10 QDR2_18B_Q4
D4 2 25V 2 25V 1/10W
QDR2_18B_D5 G11 Q5F11 QDR2_18B_Q5 2
D5 X5R X5R 1%
QDR2_18B_D6 E10 Q6E11 QDR2_18B_Q6
D6
QDR2_18B_D7 D11 Q7C10 QDR2_18B_Q7 1 R1380
D7
QDR2_18B_D8 C11 Q8B11 QDR2_18B_Q8
D8 0
QDR2_18B_D9 B3 Q9B2 QDR2_18B_Q9
D9 1/10W
QDR2_18B_D10 C3 Q10D3 QDR2_18B_Q10 2
D10 5% GND
QDR2_18B_D11 D2 Q11E3 QDR2_18B_Q11
D11
QDR2_18B_D12 F3 Q12F2 QDR2_18B_Q12
D12
QDR2_18B_D13 G2 Q13G3 QDR2_18B_Q13
D13
QDR2_18B_D14 J3 Q14K3 QDR2_18B_Q14
D14 GND
QDR2_18B_D15 L3 Q15L2 QDR2_18B_Q15
D15
QDR2_18B_D16 M3 Q16N3 QDR2_18B_Q16
D16
QDR2_18B_D17 N2 Q17P3 QDR2_18B_Q17
D17
QDR2_18B_A0 A3A0 ODTR6 ODT_SELECT_C2
QDR2_18B_A1 A9A1 QVLDP6 NC
QDR2_18B_A2 B4A2
QDR2_18B_A3 B8A3 CQA11 QDR2_18B_CQ
QDR2_18B_A4 C5A4 CQ_BA1 QDR2_18B_CQ_B
QDR2_18B_A19 C6A5--Pin C6 = BL=2/BL=4 Address Support
QDR2_18B_A6 C7A6 TDOR1 QDR2_18B_TDO
C QDR2_18B_A7 N5A7 TDIR11 QDR2_18B_TDI C
QDR2_18B_A8 N6A8 TMSR10 QDR2_18B_TMS
QDR2_18B_A9 N7A9 TCKR2 QDR2_18B_TCK
QDR2_18B_A10 P4A10
QDR2_18B_A11 P5A11
QDRII+ SRAM 2Mx18 SIO with ODT, BL=2 VCC1V8
QDR2_18B_A12 P7A12
QDR2_18B_A13 P8A13
QDR2_18B_A14 R3A14 NC1B1 NC 1
QDR2_18B_A15 R4A15 CY7C2663KV18_550BZXC NC2B5 NC R1614
B9 NC
QDR2_18B_A16 R5A16 NC3 1/10W
QDR2_18B_A17 R7A17 NC4B10 NC 2 10.0K
BGA165N39P11X15_594X673X23 C1 NC
QDR2_18B_A18 R8A18 NC5 1%
QDR2_18B_A5 R9A19 NC6C2 NC 1 1 VCC1V8
C9 NC R1616 R1615
NC7
D1 NC 1/10W 1/10W
NC8
QDR2_18B_BWS0_B B7BWS0_B NC9D9 NC 2 10.0K 2 10.0K
QDR2_18B_BWS1_B A5BWS1_B D10 NC 1% 1%
NC10 VCC1V8
NC11E1 NC J129 1 C1820 1 C2008 1 C2009 1 C1983 1 C1982
QDR2_18B_WPS_B A4WPS_B E2 NC
NC12 4.7UF 0.47UF 0.47UF 0.068UF 0.068UF
QDR2_18B_RPS_B A8RPS_B NC13E9 NC 1
2 6.3V 2 10V 2 10V 2 16V 2 16V
NC14F1 NC X5R X5R X5R X7R X7R
QDR2_18B_K_P B6K F9 NC QDR2_18B_TDO 2
NC15
QDR2_18B_K_N A6K_B NC16F10 NC
G1 NC QDR2_18B_TDI 3
NC17
QDR2_18B_A20 A10NC_72M NC18G9 NC GND
QDR2_18B_A21 A2NC_144M G10 NC QDR2_18B_TMS 4
NC19
QDR2_18B_A22 A7NC_288M J1 NC
NC20
NC21J2 NC QDR2_18B_TCK 5
VCC1V5_FPGA
B QDR2_18B_DOFF_B H1DOFF_B J9 NC B
NC22
NC23K1 NC 6
VCC1V5_FPGA K2 NC
NC24
NC25K9 NC HDR_1X6
R1257 1 1 R1256 NC26L1 NC C1821 C2010 C2011 C1985 C1984
L9 NC 1 1 1 1 1
NC27 GND
DNP 4.70K NC28L10 NC 4.7UF 0.47UF 0.47UF 0.068UF 0.068UF
DNP 1/16W M1 NC 2 6.3V 2 10V 2 10V 2 16V 2 16V
2 2 NC29
DNP 1% NC30M2 NC X5R X5R X5R X7R X7R
M9 NC
NC31
N1 NC VCC1V5_FPGA
NC32
NC33N9 NC
GND N10 NC GND
NC34 R1385 1
NC35P1 NC
P2 NC DNP
NC36
NC37P9 NC DNP
2
DNP
E7VSS10
F6VSS11
G6VSS12
H6VSS13
J6VSS14
K6VSS15
L5VSS16
L6VSS17
L7VSS18
M4VSS19
M5VSS20
M6VSS21
M7VSS22
M8VSS23
N4VSS24
N8VSS25

ZQH11 QDR2_18B_ZQ0
QDR2 MEMORY D Q[17-0]
C4VSS1
C8VSS2
D4VSS3
D5VSS4
D6VSS5
D7VSS6
D8VSS7
E5VSS8
E6VSS9

1 R1276
249
1/10W
ZQ 2 1%
TITLE: QDR2 MEMORY D Q[17-0] ASSY P/N: 0431880
A GND SCHEM, ROHS COMPLIANT PCB P/N: 1280790
HW-U1-VCU110_REV1_0 SCH P/N: 0381622
TEST P/N: TSS0174
A
GND DATE: 09/21/2015:13:58 VER: 1.0
ALTERNATE COMPONENT:
QDR2+ MEMORY D,Q[17:0]
SHEET SIZE: B REV: 01

SHEET OF DRAWN BY:


CY7C2263XV18-633BZXC (BL=4) 27 92 BF

4 3 2 1
4 3 2 1

QDR2_VTERM_0V75

1%

1%

1%

1%

1%

1%

1%

1%

1%

1%

1%

1%
1 1 1 1 1 1 1 1 1 1 1 1

R1278

R1280

R1297

R1282

R1283

R1287

R1295

R1292

R1293

R1291

R1289

R1301
D 2 2 2 2 2 2 2 2 2 2 2 2 D

39.2

39.2

39.2

39.2

39.2

39.2

39.2

39.2

39.2

39.2

39.2

39.2
1%

1%

1%

1%

1%

1%

1%

1%

1%

1%

1%

1%
GND 1 1 1 1 1 1 1 1 1 1 1 1

1%

R1279

R1299

R1284

R1281

R1285

R1286

R1294

R1288

R1296

R1290

R1298

R1300
1

R1277
2 2 2 2 2 2 2 2 2 2 2 2
PLACE TERM RESISTORS

39.2

39.2

39.2

39.2

39.2

39.2

39.2

39.2

39.2

39.2

39.2

39.2
2

39.2
CLOSE TO MEMORY
COMPONENT INPUTS

QDR2_18B_WPS_B
QDR2_18B_RPS_B

QDR2_18B_A0
QDR2_18B_A1
QDR2_18B_A2
QDR2_18B_A3
QDR2_18B_A4
QDR2_18B_A5
QDR2_18B_A6
C C
QDR2_18B_A7
QDR2_18B_A8
QDR2_18B_A9
QDR2_18B_A10
QDR2_18B_A11
QDR2_18B_A12
QDR2_18B_A13
QDR2_18B_A14
QDR2_18B_A15
QDR2_18B_A16
QDR2_18B_A17
QDR2_18B_A18
QDR2_18B_A19
QDR2_18B_A20
QDR2_18B_A21
QDR2_18B_A22

B B

QDR2_VTERM_0V75 QDR2_VTERM_0V75
QDR2 TERMINATION

1 C1713 1 C1711 1 C1710 1 C1709 1 C1712 1 C1707 1 C1706 1 C1705 1 C1704 1 C1708
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V
X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R TITLE: QDR2 TERMINATION ASSY P/N: 0431880
A SCHEM, ROHS COMPLIANT PCB P/N: 1280790
HW-U1-VCU110_REV1_0 SCH P/N: 0381622
TEST P/N: TSS0174
GND GND A
DATE: 09/21/2015:13:58 VER: 1.0

QDR2+ 36-BIT RTERM DECOUPLING SHEET SIZE: B REV: 01

SHEET OF DRAWN BY:


28 92 BF

4 3 2 1
4 3 2 1

SYS_2V5 VCC1V2_FPGA UTIL_1V35


UTIL_1V35
RLD3_36B_VREF

VEXT1 B13

VEXT3 M13

VDDQ5 C11

VDDQ7 D10

VDDQ13 J13

VDDQ15 K10

VDDQ17 L11

VDD1 A11

VDD3 C13

VDD5 F11

VDD9 H12

VDD11 L13

VDD13 N11
U141 1 C1424 1 C1425

A7
VREF1 N7

B1
VEXT2 M1

A5
VDDQ1 A9
VDDQ2 B6
VDDQ3 B8
VDDQ4 C3

VDDQ6 D4

VDDQ8 E5
VDDQ9 E9
VDDQ10 J1
VDDQ11 J5
VDDQ12 J9

VDDQ14 K4

VDDQ16 L3

VDDQ18 M6
VDDQ19 M8
VDDQ20 N5
VDDQ21 N9

A3
VDD2 C1

VDD4 F3

VDD6 H2
VDD7 H5
VDD8 H9

VDD10 L1

VDD12 N3
100UF 100UF

VREF2

VEXT4

VDDQ22

VDD14
2 4V 2 4V
X6S X6S

VCC1V2_FPGA
D D
RLD3_36B_DQ0 D11 GND
DQ0 DK0D7 RLD3_36B_DK0_P
RLD3_36B_DQ1 E10
DQ1 DK0_BC7 RLD3_36B_DK0_N
RLD3_36B_DQ2 C8
DQ2
RLD3_36B_DQ3 C10
DQ3 DK1K7 RLD3_36B_DK1_P
RLD3_36B_DQ4 C12 1 R989 C1232
DQ4 DK1_BL7 RLD3_36B_DK1_N 1
RLD3_36B_DQ5 B9
DQ5 100 0.1UF
RLD3_36B_DQ6 B11
DQ6 QK0D9 RLD3_36B_QK0_P 1/10W 2 25V
RLD3_36B_DQ7 A8 2
DQ7 QK0_BE8 RLD3_36B_QK0_N 1%
RLD3_36B_DQ8 A10
DQ8
RLD3_36B_DQ9 J10
DQ9 QK1K9 RLD3_36B_QK1_P RLD3_36B_VREF
RLD3_36B_DQ10 K11
DQ10 QK1_BJ8 RLD3_36B_QK1_N
RLD3_36B_DQ11 K13
DQ11
RLD3_36B_DQ12
RLD3_36B_DQ13
L8
L10
DQ12 QK2D5 RLD3_36B_QK2_P 1 C16581 C12331 R988
100
DQ13 QK2_BE6 RLD3_36B_QK2_N 0.1UF 0.1UF
RLD3_36B_DQ14 L12 VCC1V2_FPGA 1/10W
DQ14 2 25V 2 25V 2
RLD3_36B_DQ15 M9 1%
DQ15 QK3K5 RLD3_36B_QK3_P X5R
RLD3_36B_DQ16 M11
DQ16 QK3_BJ6 RLD3_36B_QK3_N 1
RLD3_36B_DQ17 N8
DQ17 R1608
RLD3_36B_DQ18 D3
DQ18 1/10W
RLD3_36B_DQ19 E4 GND
DQ19 2 10.0K
RLD3_36B_DQ20 C6
DQ20 QVLD0J12 RLD3_36B_QVLD0 1%
RLD3_36B_DQ21 C4 1 1
DQ21 QVLD1J2 RLD3_36B_QVLD1
RLD3_36B_DQ22 C2 R1610 R1609
DQ22
RLD3_36B_DQ23 B5 1/10W 1/10W UTIL_1V35
DQ23
RLD3_36B_DQ24 B3 2 10.0K 2 10.0K
DQ24
RLD3_36B_DQ25 A6 1% 1%
DQ25 VCC1V2_FPGA
RLD3_36B_DQ26 A4
C RLD3_36B_DQ27 J4
DQ26 J127 C
DQ27
RLD3_36B_DQ28 K3 1
DQ28 C1269 C1290 C1291 C1277 C1282
RLD3_36B_DQ29 K1 1 1 1 1 1
DQ29
RLD3_36B_DQ30 L6 RLD3_36B_0_TDO 2 4.7UF 0.47UF 0.47UF 0.068UF 0.068UF
DQ30
RLD3_36B_DQ31 L4 2 6.3V 2 10V 2 10V 2 16V 2 16V
DQ31
RLD3_36B_DQ32 L2 RLD3_36B_0_TDI 3 X5R X5R X5R X7R X7R
DQ32
RLD3_36B_DQ33 M5
DQ33
RLD3_36B_DQ34 M3 RLD3_36B_0_TMS 4
DQ34
RLD3_36B_DQ35 N6
DQ35
RLD3_36B_0_TCK 5 GND
RLD3_36B_DM0 B7DM0
RLD3_36B_DM1 M7DM1 6
MT44K16M36RB_093E VCC1V2_FPGA
RLD3_36B_A0 E2A0 TDON4 RLD3_36B_0_TDO HDR_1X6
RLD3_36B_MUX_ADDR_PD F5A1 TDIN10 RLD3_36B_0_TDI
F4A2 FBGA168_13_5X13_5MM TMSN12 RLD3_36B_0_TMS
GND
RLD3_36B_A3 F9A3 TCKN2 RLD3_36B_0_TCK
RLD3_36B_A4 F10A4 C1270 C1292 C1293 C1279 C1298
1 1 1 1 1
RLD3_36B_A5 F12A5
4.7UF 0.47UF 0.47UF 0.068UF 0.068UF
G3A6
2 6.3V 2 10V 2 10V 2 16V 2 16V
F1A7
X5R X5R X5R X7R X7R
RLD3_36B_A8 G11A8
RLD3_36B_A9 F13A9
RLD3_36B_A10 H13A10
D1A11
GND
H11A12
RLD3_36B_A13 D13A13
RLD3_36B_A14 H3A14
B B
G2A15
H4A16
RLD3_36B_A17 H10A17
RLD3_36B_A18 G12A18
H1NF_A19 SYS_2V5
F2NF_A20
RLD3_36B_BA0 G9BA0
RLD3_36B_BA1 G5BA1
RLD3_36B_BA2 H8BA2
RLD3_36B_BA3 H6BA3 ZQF7 RLD3_36B_0_ZQ C1294 C1295 C1281 C1280
1 1 1 1
0.47UF 0.47UF 0.068UF 0.068UF
2 10V 2 10V 2 16V 2 16V
X5R X5R X7R X7R
RLD3_36B_WE_B F6WE_B 1 R1145
RLD3_36B_REF_B F8REF_B
240
RLD3_36B_CK_P H7CK
1/10W
RLD3_36B_CK_N G7CK_B 2 1%
GND 40 OHM INTERFACE
RLD3_36B_RESET_B A13RESET_B
RLD3_36B_CS_B E12CS_B RLD3 36B Data [35-0]
RLD3_36B_MF E7MF
GND
E11VSSQ10
J3VSSQ11
J11VSSQ12
K2VSSQ13
K6VSSQ14
K8VSSQ15
K12VSSQ16
L5VSSQ17
L9VSSQ18
M4VSSQ19
M10VSSQ20

VCC1V2_FPGA
G8VSS10
G10VSS11
G13VSS12
J7VSS13
M2VSS14
M12VSS15
N1VSS16
N13VSS17

B4VSSQ1
B10VSSQ2
C5VSSQ3
C9VSSQ4
D2VSSQ5
D6VSSQ6
D8VSSQ7
D12VSSQ8
E3VSSQ9
A2VSS1
A12VSS2
B2VSS3
B12VSS4
E1VSS5
E13VSS6
G1VSS7
G4VSS8
G6VSS9

R1356 1 1 R1374
1 C2661 100 0
0.1UF 1/10W 1/10W TITLE: RLD3 36B Data [35-0] ASSY P/N: 0431880
A 2 25V 1% 2 2 5% SCHEM, ROHS COMPLIANT PCB P/N: 1280790
HW-U1-VCU110_REV1_0 SCH P/N: 0381622
1 R1668
1 R1669 TEST P/N: TSS0174
36 36 A
1/10W 1/10W GND GND DATE: 09/21/2015:13:58 VER: 1.0
2 1% 2 1%
SHEET SIZE: B REV: 01
RLD3_36B_CK_P GND GND
An NOT USED
RLD3_36B_CK_N
RLD3 C1 MEMORY DATA[35:0] SHEET
29
OF
92
DRAWN BY:
BF

4 3 2 1
4 3 2 1

SYS_2V5 VCC1V2_FPGA UTIL_1V35


UTIL_1V35
RLD3_18B_VREF
VCC1V2_FPGA

VEXT1 B13

VEXT3 M13

VDDQ5 C11

VDDQ7 D10

VDDQ13 J13

VDDQ15 K10

VDDQ17 L11

VDD1 A11

VDD3 C13

VDD5 F11

VDD9 H12

VDD11 L13

VDD13 N11
U173 1 C1426 1 C1427

A7
VREF1 N7

B1
VEXT2 M1

A5
VDDQ1 A9
VDDQ2 B6
VDDQ3 B8
VDDQ4 C3

VDDQ6 D4

VDDQ8 E5
VDDQ9 E9
VDDQ10 J1
VDDQ11 J5
VDDQ12 J9

VDDQ14 K4

VDDQ16 L3

VDDQ18 M6
VDDQ19 M8
VDDQ20 N5
VDDQ21 N9

A3
VDD2 C1

VDD4 F3

VDD6 H2
VDD7 H5
VDD8 H9

VDD10 L1

VDD12 N3
100UF 100UF

VREF2

VEXT4

VDDQ22

VDD14
2 4V 2 4V
X6S X6S 1 R1142
100
1/10W
D 2 D
GND 1% C1235
1
RLD3_18B_DQ0 D11 DK0 D7 RLD3_18B_DK0_P
DQ0 0.1UF
RLD3_18B_DQ1 E10 DK0_B C7 RLD3_18B_DK0_N RLD3_18B_VREF
DQ1 2 25V
RLD3_18B_DQ2 C8
DQ2
RLD3_18B_DQ3 C10 K7 RLD3_18B_DK1_P
RLD3_18B_DQ4 C12
DQ3
DQ4
DK1
DK1_B L7 RLD3_18B_DK1_N 1 C1659
1 C12361 R1141
100
RLD3_18B_DQ5 B9 0.1UF 0.1UF
DQ5 1/10W
RLD3_18B_DQ6 B11 QK0 D9 RLD3_18B_QK0_P 2 25V 2 25V 2
DQ6 1%
RLD3_18B_DQ7 A8 QK0_B E8 RLD3_18B_QK0_N X5R
DQ7
RLD3_18B_DQ8 A10
DQ8
RLD3_18B_DQ9 J10 QK1 K9 RLD3_18B_QK1_P UTIL_1V35
DQ9
RLD3_18B_DQ10 K11 QK1_B J8 RLD3_18B_QK1_N
DQ10 GND
RLD3_18B_DQ11 K13
DQ11
RLD3_18B_DQ12 L8 QVLD J12 RLD3_18B_QVLD0
DQ12
RLD3_18B_DQ13 L10
DQ13
RLD3_18B_DQ14 L12
DQ14 C1271 C1392 C1296 C1284 C1283
RLD3_18B_DQ15 M9 1 1 1 1 1
DQ15
RLD3_18B_DQ16 M11 4.7UF 0.47UF 0.47UF 0.068UF 0.068UF
DQ16
RLD3_18B_DQ17 N8 TDO N4 RLD3_18B_1_TDO 2 6.3V 2 10V 2 10V 2 16V 2 16V
DQ17
TDI N10 RLD3_18B_1_TDI X5R X5R X5R X7R X7R
RLD3_18B_DM0 B7 DM0
MT44K32M18RB_093E TMS N12 RLD3_18B_1_TMS
RLD3_18B_DM1 M7 DM1 TCK N2 RLD3_18B_1_TCK
VCC1V2_FPGA
RLD3_18B_A0 E2 A0 FBGA168_13_5X13_5MM NF1 A4 NC GND
RLD3_18B_MUX_ADDR_PD F5 A1 NF2 A6 NC 1
F4 A2 NF3 B3 NC R1611
RLD3_18B_A3 F9 A3 NF4 B5 NC 1/10W VCC1V2_FPGA
C RLD3_18B_A4 F10 A4 NF5 C2 NC 2 10.0K C
RLD3_18B_A5 F12 A5 NF6 C4 NC 1%
G3 C6 NC 1 1
A6 NF7 R1613 R1612
F1 A7 NF8 D3 NC
1/10W 1/10W
RLD3_18B_A8 G11 A8 NF9 D5 NC C1272 C1391 C1299 C1286 C1285
RLD3_18B_A9 F13 E4 NC 2 10.0K 2 10.0K 1 1 1 1 1
A9 NF10 1% 1% 4.7UF 0.47UF 0.47UF 0.068UF 0.068UF
RLD3_18B_A10 H13 A10 NF11 E6 NC VCC1V2_FPGA
2 6.3V 2 10V 2 10V 2 16V 2 16V
D1 A11 NF12 J2 NC J128 X5R X5R X5R X7R X7R
H11 A12 NF13 J4 NC
1
RLD3_18B_A13 D13 A13 NF14 J6 NC
RLD3_18B_A14 H3 A14 NF15 K1 NC
RLD3_18B_1_TDO 2
G2 A15 NF16 K3 NC
GND
H4 A16 NF17 K5 NC
RLD3_18B_1_TDI 3
RLD3_18B_A17 H10 A17 NF18 L2 NC
RLD3_18B_A18 G12 A18 NF19 L4 NC
RLD3_18B_1_TMS 4
H1 A19 NF20 L6 NC SYS_2V5
F2 NF_A20 NF21 M3 NC
RLD3_18B_1_TCK 5
RLD3_18B_BA0 G9 BA0 NF22 M5 NC
RLD3_18B_BA1 G5 BA1 NF23 N6 NC
6
RLD3_18B_BA2 H8 BA2
RLD3_18B_BA3 H6 BA3 C1300 C1301 C1288 C1287
HDR_1X6 1 1 1 1
ZQ F7 RLD3_18B_ZQ
0.47UF 0.47UF 0.068UF 0.068UF
RLD3_18B_WE_B F6 WE_B 2 10V 2 10V 2 16V 2 16V
RLD3_18B_REF_B F8 REF_B GND
1 R1007 X5R X5R X7R X7R
RLD3_18B_CK_P H7 CK
RLD3_18B_CK_N G7 CK_B ZQ 240
1/10W
RLD3_18B_RESET_B A13 2 1%
B RESET_B B
RLD3_18B_CS_B E12 CS_B GND
RLD3_18B_MF E7 MF
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19
VSSQ20
GND
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

R1357 1 1 R1375
100 0
1/10W 1/10W
A2
A12
B2
B12
E1
E13
G1
G4
G6
G8
G10
G13
J7
M2
M12
N1
N13

B4
B10
C5
C9
D2
D6
D8
D12
E3
E11
J3
J11
K2
K6
K8
K12
L5
L9
M4
M10
1% 2 2 5%

GND GND
An NOT USED GND GND

40 OHM INTERFACE
VCC1V2_FPGA
RLD3 18B Data [17-0]
1 C2662
0.1UF
2 25V
1 R1670
1 R1671
36 36
TITLE: RLD3 18B Data [17-0] ASSY P/N: 0431880
1/10W 1/10W
A 2 2 SCHEM, ROHS COMPLIANT PCB P/N: 1280790
1% 1%
HW-U1-VCU110_REV1_0 SCH P/N: 0381622
RLD3_18B_CK_P
TEST P/N: TSS0174
A
RLD3_18B_CK_N
DATE: 09/21/2015:13:58 VER: 1.0

SHEET SIZE: B REV: 01

RLD3 MEMORY DATA[17:0] SHEET


30
OF
92
DRAWN BY:
BF

4 3 2 1
4 3 2 1

RLD3_VTERM_0V6

1%
1

1%

1%

1%

1%

1%

1%

1%

1%

1%

1%

1%

1%

1%

1%

1%

1%
R1341
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

R1313

R1319

R1317

R1315

R1342

R1347

R1345

R1323

R1324

R1330

R1336

R1334

R1332

R1329

R1327

R1337
2 40 OHM TERMINATIONS

40.2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

39.2

39.2

39.2

39.2

39.2

39.2

39.2

39.2

39.2

39.2

39.2

39.2

39.2

39.2

39.2

39.2
D PLACE TERM RESISTORS D

1%
1

1%

1%

1%

1%

1%

1%

1%

1%

1%

1%

1%

1%

1%

1%

1%

1%

1%

1%
IN "FLYBY" CONFIGURATION

R1325
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

R1320

R1321

R1318

R1316

R1314

R1348

R1322

R1344

R1343

R1340

R1346

R1335

R1333

R1331

R1328

R1326

R1339

R1338
2
AFTER LAST COMPONENT

39.2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

39.2

39.2

39.2

39.2

39.2

39.2

39.2

39.2

39.2

39.2

39.2

39.2

39.2

39.2

39.2

39.2

39.2

39.2
RLD3_36B_WE_B
RLD3_36B_REF_B
RLD3_36B_CS_B

RLD3_36B_BA0
RLD3_36B_BA1
RLD3_36B_BA2
RLD3_36B_BA3
RLD3_36B_A0
RLD3_36B_A3
RLD3_36B_A4
RLD3_36B_A5
RLD3_36B_A8
RLD3_36B_A9
RLD3_36B_A10
RLD3_36B_A13
RLD3_36B_A14
C RLD3_36B_A17 C
RLD3_36B_A18

RLD3_18B_WE_B
RLD3_18B_REF_B
RLD3_18B_CS_B

RLD3_18B_BA0
RLD3_18B_BA1
RLD3_18B_BA2
RLD3_18B_BA3
RLD3_18B_A0
RLD3_18B_A3
RLD3_18B_A4
RLD3_18B_A5
RLD3_18B_A8
RLD3_18B_A9
RLD3_18B_A10
RLD3_18B_A13
RLD3_18B_A14
B B
RLD3_18B_A17
RLD3_18B_A18

RLD3_VTERM_0V6
RLD3_VTERM_0V6

1 C1679 1 C1678 1 C1677 1 C1676 1 C1675 1 C1669 1 C1668 1 C1667 1 C1666 1 C1665
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
2 25V 2 25V 2 25V 2 25V 2 25V
2 25V 2 25V 2 25V 2 25V 2 25V
X5R X5R X5R X5R X5R
X5R X5R X5R X5R X5R
40 OHM INTERFACE
RLD3 Termination/Decoupling
GND RLD3 1x36 (36-BIT) TERMINATION RESISTOR DECOUPLING GND RLD3 1x18 (18-BIT) TERMINATION RESISTOR DECOUPLING
RLD3_VTERM_0V6
RLD3_VTERM_0V6

TITLE: RLD3 Termination/Decoupling ASSY P/N: 0431880


A SCHEM, ROHS COMPLIANT PCB P/N: 1280790
1 C1674 1 C1673 1 C1672 1 C1671 1 C1670 1 C1664 1 C1663 1 C1662 1 C1661 1 C1660 HW-U1-VCU110_REV1_0 SCH P/N: 0381622
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF TEST P/N: TSS0174
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
2 25V 2 25V 2 25V 2 25V 2 25V A
2 25V 2 25V 2 25V 2 25V 2 25V
X5R X5R X5R X5R X5R DATE: 09/21/2015:13:58 VER: 1.0
X5R X5R X5R X5R X5R
SHEET SIZE: B REV: 01

SHEET OF DRAWN BY:


GND
GND 31 92 BF

4 3 2 1
4 3 2 1

VCC1V5_FPGA
VCC1V5_FPGA
R1211
On VCU110, install soldered HMC 1
1.00K
1
R1477

device during assembly. MT43A4G80200NFH-S15


U30 2
1/16W
1% HMC_P_RST_B
1/10W
2 10.0K
D The socket is not part of the BOM. P_RST_N

REFCLK_BOOT_0
N1 HMC_REFCLK_BOOT_0
1%
1
R1479
D
U29 HMC_REFCLK_BOOT_1 1/10W
REFCLK_BOOT_1
2 10.0K
R30 HMC_SI5328_OUT1_C_N 1%
REFCLKN T30 VCC1V5_FPGA
REFCLKP HMC_SI5328_OUT1_C_P
V6 HMC_REFCLK_SEL J120
REFCLKSEL
1
VCC12_SW R28 IIC_SCL_HMC_LS VCC1V5_FPGA
SCL T24
SDA IIC_SDA_HMC_LS HMC_TDO 2
T5 HMC_TCK VCC1V5_FPGA HMC_TDI 3
TCK P7 1 R1683
1 R1682
1 R1684
TDI HMC_TDI
T1 HMC_TDO DNP DNP 0 HMC_TMS 4
TDO R5
TMS HMC_TMS DNP DNP 1/10W
22_11_2036 R7 2 2 2
TRST_N HMC_TRST_B DNP DNP 5% HMC_TCK 5
1

R1234
V25 HMC_TRST_B 6
2 CUB_0 P24

1/10W
R1233
CUB_1 W7 IIC_SCL_HMC_LS 7

200
3 NC CUB_2

1%
1/10W
AA2 IIC_SDA_HMC_LS 8

200
J130 EXTRESBN 1 R1658 1 R1686
1 R1685
1 R1681

1%
AB1

2
EXTRESBP K2 1.00K 0 0 DNP
EXTRESTN 9
J1 1/16W 1/10W 1/10W DNP
R1657

2
EXTRESTP 2 1% 2 5% 2 5% 2 DNP 1 1
R1478
U5 4.32K
GND FERR_N HMC_FERR_B 1/10W HDR_1X9
1/10W
2 1% 2 10.0K GND
C SOC_BGA_HMC_896_IRON 1% C
U160 GND
HMC Fan Header 1 R1209
1 R1212
1.00K 1.00K
GND
1/16W 1/16W
2 1% 2 1%
1 R1210
1.00K
1/16W
2 1%
UTIL_3V3

GND VCC1V5_FPGA 1 R1242


200K
1/10W
2 1%
1 C1580
1
R1239
1
R1240
0.1UF
1/16W 1/16W
2 25V
MT43A4G80200NFH-S15 2 4.70K 2 4.70K
E1 1% 1%
DNU0 NC PCA9306DCTR
P1 NC 2 7
DNU1 R1 VREF1 VREF2
DNU2 NC GND
U1 NC IIC_SCL_HMC_LS 3 6 IIC_SCL_HMC
DNU3 AF1 SCL1 SCL2
DNU4 NC
B R3 B
DNU5 NC IIC_SDA_HMC_LS 4 5 IIC_SDA_HMC
U3 SDA1 SDA2
DNU6 NC
P4 NC 1 8
DNU7 U4 GND EN
DNU8 NC
P5 NC DCT_R_PDSO_G8
DNU9 M7 NC
U159
DNU10 N7
DNU11 NC GND
VCC1V5_FPGA UTIL_3V3 T7
DNU12 NC
U7 NC
DNU13 V7
DNU14 NC
C2680 1 1 C2681 DNU15
N8 NC 1 C1647
0.1UF 0.1UF R8 NC 1000PF
SN74AVC1T45 DNU16 P9
25V 2 2 25V DNU17 NC 2 50V
P10 NC X7R
UTIL_3V3 DNU18 C12
6 1 DNU19 NC
VCCB VCCA
HMC_FERR_B 4 B A 3
R1687 DS56 DNU20
AH12
V23
NC
NC
GND
1 2
DNU21 C24 NC
1

DNU22 AH24
5 2 LED-RED-SMT NC
DIR GND 261
1/10W
DNU23
DNU24
N25 NC HMC Control
P25 NC
1% DNU25 P26 NC
U202 SC70_6 DNU26 U26
DNU27 NC
GND GND P27 NC
DNU28 U27
DNU29 NC
P28 NC
DNU30 T28
DNU31 NC TITLE: HMC Control ASSY P/N: 0431880
A J30 NC SCHEM, ROHS COMPLIANT PCB P/N: 1280790
DNU32 AB30
DNU33 NC HW-U1-VCU110_REV1_0 SCH P/N: 0381622
TEST P/N: TSS0174
SOC_BGA_HMC_896_IRON A
U160 DATE: 09/21/2015:13:58 VER: 1.0

SHEET SIZE: B REV: 01

SHEET OF DRAWN BY:


32 92 BF

4 3 2 1
4 3 2 1

MT43A4G80200NFH-S15 MT43A4G80200NFH-S15 MT43A4G80200NFH-S15 MT43A4G80200NFH-S15


G18 HMC_L0TX_0_P D2 NC AG2 NC
L0RXP_0 AD18 HMC_L1TX_0_P L2RXP_0 L3RXP_0
G17 HMC_L0TX_0_N L1RXP_0 D3 NC AG3 NC
L0RXN_0 AD17 HMC_L1TX_0_N L2RXN_0 L3RXN_0
F19 HMC_L0TX_1_P L1RXN_0 C1 NC AH1 NC
L0RXP_1 AE19 HMC_L1TX_1_P L2RXP_1 L3RXP_1
F18 HMC_L0TX_1_N L1RXP_1 C2 NC AH2 NC
L0RXN_1 AE18 HMC_L1TX_1_N L2RXN_1 L3RXN_1
A16 HMC_L0TX_2_P L1RXN_1 M3 NC W3 NC
L0RXP_2 AK16 HMC_L1TX_2_P L2RXP_2 L3RXP_2
A15 HMC_L0TX_2_N L1RXP_2 M4 NC W4 NC
L0RXN_2 AK15 HMC_L1TX_2_N L2RXN_2 L3RXN_2
A24 HMC_L0TX_3_P L1RXN_2 L1 NC Y1 NC
L0RXP_3 AK24 HMC_L1TX_3_P L2RXP_3 L3RXP_3
D A23 HMC_L0TX_3_N L1RXP_3 L2 NC Y2 NC D
L0RXN_3 AK23 HMC_L1TX_3_N L2RXN_3 L3RXN_3
E20 HMC_L0TX_4_P L1RXN_3 E3 NC AF3 NC
L0RXP_4 AF20 HMC_L1TX_4_P L2RXP_4 L3RXP_4
E19 HMC_L0TX_4_N L1RXP_4 E4 NC AF4 NC
L0RXN_4 AF19 HMC_L1TX_4_N L2RXN_4 L3RXN_4
D21 HMC_L0TX_5_P L1RXN_4 F4 NC AE4 NC
L0RXP_5 AG21 HMC_L1TX_5_P L2RXP_5 L3RXP_5
D20 HMC_L0TX_5_N L1RXP_5 F5 NC AE5 NC
L0RXN_5 AG20 HMC_L1TX_5_N L2RXN_5 L3RXN_5
C22 HMC_L0TX_6_P L1RXN_5 G5 NC AD5 NC
L0RXP_6 AH22 HMC_L1TX_6_P L2RXP_6 L3RXP_6
C21 HMC_L0TX_6_N L1RXP_6 G6 NC AD6 NC
L0RXN_6 AH21 HMC_L1TX_6_N L2RXN_6 L3RXN_6
B23 HMC_L0TX_7_P L1RXN_6 H6 NC AC6 NC
L0RXP_7 AJ23 HMC_L1TX_7_P L2RXP_7 L3RXP_7
B22 HMC_L0TX_7_N L1RXP_7 H7 NC AC7 NC
L0RXN_7 AJ22 HMC_L1TX_7_N L2RXN_7 L3RXN_7
L30 HMC_L0TX_8_P L1RXN_7 A7 NC AK7 NC
L0RXP_8 Y30 HMC_L1TX_8_P L2RXP_8 L3RXP_8
L29 HMC_L0TX_8_N L1RXP_8 A8 NC AK8 NC
L0RXN_8 Y29 HMC_L1TX_8_N L2RXN_8 L3RXN_8
M28 HMC_L0TX_9_P L1RXN_8 F15 NC AE15 NC
L0RXP_9 W28 HMC_L1TX_9_P L2RXP_9 L3RXP_9
M27 HMC_L0TX_9_N L1RXP_9 F16 NC AE16 NC
L0RXN_9 W27 HMC_L1TX_9_N L2RXN_9 L3RXN_9
C30 HMC_L0TX_10_P L1RXN_9 F12 NC AE12 NC
L0RXP_10 AH30 HMC_L1TX_10_P L2RXP_10 L3RXP_10
C29 HMC_L0TX_10_N L1RXP_10 F13 NC AE13 NC
L0RXN_10 AH29 HMC_L1TX_10_N L2RXN_10 L3RXN_10
D29 HMC_L0TX_11_P L1RXN_10 G13 NC AD13 NC
L0RXP_11 AG29 HMC_L1TX_11_P L2RXP_11 L3RXP_11
D28 HMC_L0TX_11_N L1RXP_11 G14 NC AD14 NC
L0RXN_11 AG28 HMC_L1TX_11_N L2RXN_11 L3RXN_11
H25 HMC_L0TX_12_P L1RXN_11 B8 NC AJ8 NC
L0RXP_12 AC25 HMC_L1TX_12_P L2RXP_12 L3RXP_12
H24 HMC_L0TX_12_N L1RXP_12 B9 NC AJ9 NC
L0RXN_12 AC24 HMC_L1TX_12_N L2RXN_12 L3RXN_12
G26 HMC_L0TX_13_P L1RXN_12 C9 NC AH9 NC
L0RXP_13 AD26 HMC_L1TX_13_P L2RXP_13 L3RXP_13
G25 HMC_L0TX_13_N L1RXP_13 C10 NC AH10 NC
L0RXN_13 AD25 HMC_L1TX_13_N L2RXN_13 L3RXN_13
F27 HMC_L0TX_14_P L1RXN_13 D10 NC AG10 NC
L0RXP_14 AE27 HMC_L1TX_14_P L2RXP_14 L3RXP_14
F26 HMC_L0TX_14_N L1RXP_14 D11 NC AG11 NC
L0RXN_14 AE26 HMC_L1TX_14_N L2RXN_14 L3RXN_14
E28 HMC_L0TX_15_P L1RXN_14 E11 NC AF11 NC
L0RXP_15 AF28 HMC_L1TX_15_P L2RXP_15 L3RXP_15
E27 HMC_L0TX_15_N L1RXP_15 E12 NC AF12 NC
L0RXN_15 AF27 HMC_L1TX_15_N L2RXN_15 L3RXN_15
L1RXN_15
E24 HMC_L0RX_0_P C5 NC AH5 NC
L0TXP_0 AF24 HMC_L1RX_0_P L2TXP_0 L3TXP_0
E23 HMC_L0RX_0_N L1TXP_0 C6 NC AH6 NC
C L0TXN_0 AF23 HMC_L1RX_0_N L2TXN_0 L3TXN_0 C
F23 HMC_L0RX_1_P L1TXN_0 G9 NC AD9 NC
L0TXP_1 AE23 HMC_L1RX_1_P L2TXP_1 L3TXP_1
F22 HMC_L0RX_1_N L1TXP_1 G10 NC AD10 NC
L0TXN_1 AE22 HMC_L1RX_1_N L2TXN_1 L3TXN_1
D17 HMC_L0RX_2_P L1TXN_1 L5 NC Y5 NC
L0TXP_2 AG17 HMC_L1RX_2_P L2TXP_2 L3TXP_2
D16 HMC_L0RX_2_N L1TXP_2 L6 NC Y6 NC
L0TXN_2 AG16 HMC_L1RX_2_N L2TXN_2 L3TXN_2
C18 HMC_L0RX_3_P L1TXN_2 K4 NC AA4 NC
L0TXP_3 AH18 HMC_L1RX_3_P L2TXP_3 L3TXP_3
C17 HMC_L0RX_3_N L1TXP_3 K5 NC AA5 NC
L0TXN_3 AH17 HMC_L1RX_3_N L2TXN_3 L3TXN_3
D25 HMC_L0RX_4_P L1TXN_3 A3 NC AK3 NC
L0TXP_4 AG25 HMC_L1RX_4_P L2TXP_4 L3TXP_4
D24 HMC_L0RX_4_N L1TXP_4 A4 NC AK4 NC
L0TXN_4 AG24 HMC_L1RX_4_N L2TXN_4 L3TXN_4
B27 HMC_L0RX_5_P L1TXN_4 G1 NC AD1 NC
L0TXP_5 AJ27 HMC_L1RX_5_P L2TXP_5 L3TXP_5
B26 HMC_L0RX_5_N L1TXP_5 G2 NC AD2 NC
L0TXN_5 AJ26 HMC_L1RX_5_N L2TXN_5 L3TXN_5
A20 HMC_L0RX_6_P L1TXN_5 H2 NC AC2 NC
L0TXP_6 AK20 HMC_L1RX_6_P L2TXP_6 L3TXP_6
A19 HMC_L0RX_6_N L1TXP_6 H3 NC AC3 NC
L0TXN_6 AK19 HMC_L1RX_6_N L2TXN_6 L3TXN_6
B19 HMC_L0RX_7_P L1TXN_6 J3 NC AB3 NC
L0TXP_7 AJ19 HMC_L1RX_7_P L2TXP_7 L3TXP_7
B18 HMC_L0RX_7_N L1TXP_7 J4 NC AB4 NC
L0TXN_7 AJ18 HMC_L1RX_7_N L2TXN_7 L3TXN_7
K27 HMC_L0RX_8_P L1TXN_7 C13 NC AH13 NC
L0TXP_8 AA27 HMC_L1RX_8_P L2TXP_8 L3TXP_8
K26 HMC_L0RX_8_N L1TXP_8 C14 NC AH14 NC
L0TXN_8 AA26 HMC_L1RX_8_N L2TXN_8 L3TXN_8
L26 HMC_L0RX_9_P L1TXN_8 D14 NC AG14 NC
L0TXP_9 Y26 HMC_L1RX_9_P L2TXP_9 L3TXP_9
L25 HMC_L0RX_9_N L1TXP_9 D15 NC AG15 NC
L0TXN_9 Y25 HMC_L1RX_9_N L2TXN_9 L3TXN_9
G22 HMC_L0RX_10_P L1TXN_9 F8 NC AE8 NC
L0TXP_10 AD22 HMC_L1RX_10_P L2TXP_10 L3TXP_10
G21 HMC_L0RX_10_N L1TXP_10 F9 NC AE9 NC
L0TXN_10 AD21 HMC_L1RX_10_N L2TXN_10 L3TXN_10
C26 HMC_L0RX_11_P L1TXN_10 E7 NC AF7 NC
L0TXP_11 AH26 HMC_L1RX_11_P L2TXP_11 L3TXP_11
C25 HMC_L0RX_11_N L1TXP_11 E8 NC AF8 NC
L0TXN_11 AH25 HMC_L1RX_11_N L2TXN_11 L3TXN_11
J28 HMC_L0RX_12_P L1TXN_11 B12 NC AJ12 NC
L0TXP_12 AB28 HMC_L1RX_12_P L2TXP_12 L3TXP_12
J27 HMC_L0RX_12_N L1TXP_12 B13 NC AJ13 NC
L0TXN_12 AB27 HMC_L1RX_12_N L2TXN_12 L3TXN_12
H29 HMC_L0RX_13_P L1TXN_12 A11 NC AK11 NC
L0TXP_13 AC29 HMC_L1RX_13_P L2TXP_13 L3TXP_13
H28 HMC_L0RX_13_N L1TXP_13 A12 NC AK12 NC
L0TXN_13 AC28 HMC_L1RX_13_N L2TXN_13 L3TXN_13
G30 HMC_L0RX_14_P L1TXN_13 B4 NC AJ4 NC
L0TXP_14 AD30 HMC_L1RX_14_P L2TXP_14 L3TXP_14
B G29 HMC_L0RX_14_N L1TXP_14 B5 NC AJ5 NC B
L0TXN_14 AD29 HMC_L1RX_14_N L2TXN_14 L3TXN_14
A28 HMC_L0RX_15_P L1TXN_14 D6 NC AG6 NC
L0TXP_15 AK28 HMC_L1RX_15_P L2TXP_15 L3TXP_15
A27 HMC_L0RX_15_N L1TXP_15 D7 NC AG7 NC
L0TXN_15 AK27 HMC_L1RX_15_N L2TXN_15 L3TXN_15
L1TXN_15
U28 HMC_L0RXPS N6 P2
L0RXPS P29 HMC_L1RXPS L2RXPS L3RXPS
N24 HMC_L0TXPS L1RXPS U2 NC P3 NC
L0TXPS V24 HMC_L1TXPS L2TXPS L3TXPS
L1TXPS
SOC_BGA_HMC_896_IRON SOC_BGA_HMC_896_IRON SOC_BGA_HMC_896_IRON
U160 SOC_BGA_HMC_896_IRON U160 U160
U160 1 R1213 1 R1214
4.70K 4.70K
1/16W 1/16W
2 1% 2 1%

GND GND
FPGA TX transmitter connects to HMC RX reciever pins
HMC Links
FPGA RX reciever connects to HMC TX transmitter pins

TITLE: HMC Links ASSY P/N: 0431880


A SCHEM, ROHS COMPLIANT PCB P/N: 1280790
HW-U1-VCU110_REV1_0 SCH P/N: 0381622
TEST P/N: TSS0174
A
DATE: 09/21/2015:13:58 VER: 1.0

SHEET SIZE: B REV: 01

SHEET OF DRAWN BY:


33 92 BF

4 3 2 1
4 3 2 1

SYS_2V5
SYS_2V5 MT43A4G80200NFH-S15
(VCP) U24
VCCP_U24 VDDPLLA0_K17
K17
K19
VDDPLLA_FILT1
VDDPLLA_FILT2
VDDPLLA0_K19 AA17
VDDPLLA1_AA17 VDDPLLA_FILT3
UTIL_0V9 AA19
C2179 VDDPLLA1_AA19 VDDPLLA_FILT4
C2214 C2215
1 C2258
1 1 100UF 1 VDDPLLA2_K13
K13 VDDPLLA_FILT5
D N9 K15 VDDPLLA_FILT6 D
4.7UF 4.7UF 0.47UF 6.3V T9 VDD_N9 VDDPLLA2_K15 AA13
VDD_T9 VDDPLLA3_AA13 VDDPLLA_FILT7
6.3V 2 6.3V 2 10V 2 X6S 2 V9 AA15
VDD_V9 VDDPLLA3_AA15 VDDPLLA_FILT8
X5R X5R X5R N10 K16
VDD_N10 VDDPLLB0_K16 VDDPLLB_FILT1
T10 K18 VDDPLLB_FILT2
V11 VDD_T10 VDDPLLB0_K18 AA16

R1410

2 1/10W
VDD_V11 VDDPLLB1_AA16 VDDPLLB_FILT3
N12 AA18 VDDPLLB_FILT4
GND VDD_N12 VDDPLLB1_AA18

10

1%
R12 K12 VDDPLLB_FILT5
T13 VDD_R12 VDDPLLB2_K12 K14 VDDPLLB_FILT6

1
UTIL_0V9 VDD_T13 VDDPLLB2_K14 HMC1V2
(VDD) V13
N14 VDD_V13 VDDPLLB3_AA12
AA12
AA14
VDDPLLB_FILT7
VDDPLLB_FILT8 FERRITE-220
R14 VDD_N14 VDDPLLB3_AA14 P30
VDD_R14 VDDPLLR VDDPLLR_FILT
T15
C2085 C2086 C2087 C2088 C2089 C2090 C2091 C2092 C2093 C2094 C2095 C2096

2
1 1 1 1 1 1 1 1 1 1 1 1 V15 VDD_T15 HMC1V2 C1615
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF N16 VDD_V15 J8
1
2.2UF
L89
2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V R16 VDD_N16 VTR_J8 L8
VDD_R16 VTR_L8 2 10V
X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R T17 Y9
VDD_T17 VTR_Y9 X6S
V17 AB9
N18 VDD_V17 VTR_AB9 J11
R18 VDD_N18 VTR_J11 Y11 GND
T19 VDD_R18 VTR_Y11 AB11
GND VDD_T19 VTR_AB11
V19 L12
N20 VDD_V19 VTR_L12 J15
UTIL_0V9
(VDD) T21 VDD_N20
VDD_T21
VTR_J15
VTR_Y15
Y15
V21 L16
N22 VDD_V21 VTR_L16 AB16
C2097 C2098 C2099 C2100 C2101 C2102 C2103 C2104 C2105 C2106 C2107 C2108 T23 VDD_N22 VTR_AB16 Y19
1 1 1 1 1 1 1 1 1 1 1 1 VDD_T23 VTR_Y19
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF J20
C VTR_J20 L20 C
2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V VTR_L20
VCC1V5_FPGA AB20
X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R VTR_AB20 J22
R4 VTR_J22 L22
R6 VDDK_R4 VTR_L22 Y23
R10 VDDK_R6 VTR_Y23 AB23
GND VDDK_R10 VTR_AB23
T25
R27 VDDK_T25
VDDK_R27 AA8
UTIL_0V9 (VDD) VTT_AA8
VTT_K9
K9
J10
VTT_J10 L10
C2210 1 1 C2254
1 C2175
1 C2173
1 C2176
1 C2174
1 C2251
1 C2252
1 C2253
1 C2250 VTT_L10 AA10
VTT_AA10 K11
4.7UF 330PF 2.2UF 2.2UF 2.2UF 2.2UF 220PF 220PF 220PF 10UF VTT_K11
6.3V 2 2 50V 2 10V 2 10V 2 10V 2 10V 2 50V 2 50V 2 50V 2 6.3V J13
VTT_J13 Y13
X5R X7R X6S X6S X6S X6S X7R X7R X7R X6S VTT_Y13 L14
VTT_L14 AB14
VTT_AB14 J17
VTT_J17 Y17
GND VTT_Y17
UTIL_0V9 L18
VTT_L18
UTIL_0V9 (VDD) VTT_AB18
AB18
AA20
VTT_AA20 K21
VTT_K21 Y21
C2184 C21851 C2546C2211 C2212 C2213 1 1 1 1 1 1 VTT_Y21
C2345 C2348 AB21
1 1 1 1 1 100UF 100UF 100UF 100UF 100UF 100UF VTT_AB21
470UF 470UF 470UF AA22
4.7UF 4.7UF 4.7UF 2 2 2 2 2 2 4V C2346 C2349 VTT_AA22
2V 2V 2V K23
B 6.3V 2 6.3V 2 6.3V 2 X6S VTT_K23 B
2 SP 2 SP 2 SP C2347 C2350
X5R X5R X5R
U8
VDDM_U8 W8
GND VDDM_W8 M9
GND 100UF VDDM_M9 U10
1 1 1 1 1 1 VDDM_U10 W10
C2351 C2354 VDDM_W10
100UF 100UF 100UF 100UF 100UF M11
2 2 2 2 2 2 4V C2352 C2355 VDDM_M11 P11
X6S VDDM_P11 U12
C2474 C2356 VDDM_U12 W12
VDDM_W12 M13
VDDM_M13 P13
UTIL_0V9 (VDD) GND VDDM_P13
VDDM_U14
U14
W14
VDDM_W14 M15
C2186 C2187 C2188 C2189 C2190 C2191 C2192 C2193 C2194 C2195 C2196 C2197 VDDM_M15
1 1 1 1 1 1 1 1 1 1 1 1 P15
0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF
VDDM_P15 U16
16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V VDDM_U16
2 2 2 2 2 2 2 2 2 2 2 2
X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R VDDM_W16
W16
M17
HMC Power
VDDM_M17 P17
VDDM_P17 U18
VDDM_U18 W18
GND VDDM_W18 M19
VDDM_M19 P19
VCC1V5_FPGA (VDDK) VDDM_P19
VDDM_U20
U20
TITLE: HMC Power ASSY P/N: 0431880
W20
A VDDM_W20 M21 SCHEM, ROHS COMPLIANT PCB P/N: 1280790
VDDM_M21 P21 HW-U1-VCU110_REV1_0 SCH P/N: 0381622
C2217 C2216
1 C2259
1 C2260
1 1
VDDM_P21 U22 TEST P/N: TSS0174
VDDM_U22 W22 A
4.7UF 4.7UF 0.47UF 0.47UF VDDM_W22 M23 DATE: 09/21/2015:13:58 VER: 1.0
6.3V 2 6.3V 2 10V 2 10V 2 VDDM_M23
X5R X5R X5R X5R P23
VDDM_P23 SHEET SIZE: B REV: 01

SHEET OF DRAWN BY:


SOC_BGA_HMC_896_IRON
GND
U160 34 92 BF

4 3 2 1
4 3 2 1

HMC1V2 HMC1V2 HMC1V2 HMC1V2 HMC1V2 HMC1V2 HMC1V2 HMC1V2


FERRITE-600 FERRITE-600 FERRITE-600 FERRITE-600 FERRITE-600 FERRITE-600 FERRITE-600 FERRITE-600
VDDPLLA_FILT1 VDDPLLA_FILT2 VDDPLLA_FILT3 VDDPLLA_FILT4 VDDPLLA_FILT5 VDDPLLA_FILT6 VDDPLLA_FILT7 VDDPLLA_FILT8

2
L106 L107 L108 L109 L110 L111 L112 L113
C2234 1 C2235 1 C2236 1 C2237 1 C2238 1 C2239 1 C2240 1 C2241 1
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
10V 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 2
X6S X6S X6S X6S X6S X6S X6S X6S
D D

GND GND GND GND GND GND GND GND

HMC1V2 HMC1V2 HMC1V2 HMC1V2 HMC1V2 HMC1V2 HMC1V2 HMC1V2


FERRITE-600 FERRITE-600 FERRITE-600 FERRITE-600 FERRITE-600 FERRITE-600 FERRITE-600 FERRITE-600
VDDPLLB_FILT1 VDDPLLB_FILT2 VDDPLLB_FILT3 VDDPLLB_FILT4 VDDPLLB_FILT5 VDDPLLB_FILT6 VDDPLLB_FILT7 VDDPLLB_FILT8
1

2
L114 L115 L116 L117 L118 L119 L120 L121
C2242 1 C2243 1 C2244 1 C2245 1 C2246 1 C2247 1 C2248 1 C2249 1
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
10V 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 2
X6S X6S X6S X6S X6S X6S X6S X6S

GND GND GND GND GND GND GND GND

HMC1V2 (VDDM)
HMC1V2 Maxim Bulk
C2218 C2219
1
C2220
1
C2221
1
C2222
1
C2223
1
C2224
1
C2225
1 1
C2344 C2343
C 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF C
1 1 1 1 1 1 1 1
6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 C2333 C2336
100UF 100UF 100UF 100UF 100UF 100UF 100UF 100UF
X5R X5R X5R X5R X5R X5R X5R X5R
2 2 2 2 2 2 2 2 4V C2334 C2337
X6S
C2335 C2338
GND
HMC1V2 (VDDM) HMC1V2
GND
(VDDM)
C2181 1 1 C2140
1 C2141
1 C2142
1 C2143
1 C2144
1 C2145
1 C2146
1 C2147
1 C2148
1 C2149
1 C2150
1 C2151
100UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF C2182 1 1 C2152
1 C2153
1 C2154
1 C2155
1 C2156
1 C2157
1 C2158
1 C2159
1 C2160
1 C2161
1 C2162
1 C2163
4V 2 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 100UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
X6S X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R 4V 2 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V
X6S X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R

GND
GND

HMC1V2 (VTT, VTR) HMC1V2 (VTT, VTR)


1
C2198
1
C2199
1
C2200
1
C2201
1
C2202
1
C2203
1
C2204
1
C2205
1
C2206
1
C2207
1
C2208
1
C2226
C2209 C2227
1
C2228
1
C2229
1
C2230
1
C2231
1
C2232
1
C2233
1 1
0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF
4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF
16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V
B 2 2 2 2 2 2 2 2 2 2 2 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 B
X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
X5R X5R X5R X5R X5R X5R X5R X5R

GND
GND HMC1V2 (VTT)
1 C2257
1 C2256
1 C2255
1 C2177
1 C2178
HMC1V2 (VTT) 330PF 330PF 330PF 2.2UF 2.2UF
2 50V 2 50V 2 50V 2 10V 2 10V
X7R X7R X7R X6S X6S

C2183 1 1 C2164
1 C2165
1 C2166
1 C2167
1 C2168
1 C2169
1 C2170
1 C2171
1 C2172
1 C2113
1 C2114
1 C2115
1 C2116
1 C2117
1 C2118
1 C2119
1 C2120
1 C2121
100UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
4V 2 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V 2 25V
GND
X6S X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
HMC Decoupling
GND

HMC1V2 (VTR)
TITLE: HMC Decoupling ASSY P/N: 0431880
A