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FET Amplifiers

221308 Engineering Electronic I

Mr. Kriangkrai Sooksood

Analog Signals And Linear Amp FET Linear Amplifier

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Graphical Analysis and AC Equivalent Graphical Analysis and AC Equivalent
(cont’d) (cont’d)

id
gm = = 2 K n (VGSQ − VTN )
vgs
∂iD
gm = = 2 K n (VGSQ − VTN ) = 2 K n I DQ
∂vGS
I DQ = K n (VGSQ − VTN ) 2

Small-Signal Equivalent Circuit

Small-Signal Equivalent Circuit
(cont’d)
z Finite output resistance, from

iD = K n ⎡⎣ (VGSQ − VTN ) 2 (1 + λ vDS ) ⎤⎦

z where λ is the channel-length modulation, the small-signal

output resistance is defined as
−1
⎛ ∂i ⎞ −1 −1
rO = ⎜ D ⎟ = ⎡⎣λ K n (vGS − VTN ) 2 ⎤⎦ ≅ ⎡⎣ λ I DQ ⎤⎦
⎝ ∂vDS ⎠ vGS =VGSQ = const.

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Small-Signal Equivalent Circuit Small-Signal Equivalent Circuit
(cont’d) (cont’d)
z Small-signal equivalent circuit for NMOS z Small-signal equivalent circuit for PMOS

Problem Solving Technique: AC Small-Signal Equivalent Circuit

Analysis (cont’d)
z Analyze the circuit with only the dc sources present. This Modeling the body effect
solution is the dc or quiescent solution. The transistor must be
The body effect occurs in a MOSFET in which the
biased in the saturation region in order to produce a linear
amplifier. substrate, or body, is not connected to the source.
z Replace each element in the circuit with its small-signal model,
which means replacing the transistor by its small-signal
equivalent circuit.
z Analyze the small-signal equivalent circuit, setting the dc
source components equal to zero, to produce the response of
the circuit to the time-varying input signals only.

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Small-Signal Equivalent Circuit
Common-Source Amplifier
(cont’d)
Back-
Back-gate transconductance

∂iD
g mb = = g mη
∂vBS Q − pt

In general, we will neglect gmb

in our hand analyses and
designs, but will investigate
the body effect in PSpice
analysis.

Common-Source Amplifier with

Example
Source Resistor
z Determine the small-signal voltage gain, input
resistance, and output resistance of a common-source
amplifier. The parameters are: VDD = 10 V, R1 = 70.9
kΩ, R2 = 29.1 kΩ, and RD = 5 k. The transistor
parameters are: VTN = 1.5 V, Kn = 0.5 mA/V2, and λ =
0.01 V-1. Assume RSi = 4 kΩ.

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Common-Source Amplifier with Common-Drain (Source-Follower)
Source Bypass Capacitor Amplifier

Common-Gate Amplifier Summary of Three Basic Amplifiers

z Table 4.2

Configuration Av Ai Ri Ro

Common >1 - RTH Moderate to

source high
Common ≈1 - RTH Low
drain
Common gate >1 ≈1 Low Moderate to
high

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Single-Stage Integrated Circuit Single-Stage Integrated Circuit
MOSFET Amplifiers MOSFET Amplifiers (cont’d)
z Load Line Revisited z NMOS Amp. with
Enhancement load

Single-Stage Integrated Circuit Single-Stage Integrated Circuit

MOSFET Amplifiers (cont’d) MOSFET Amplifiers (cont’d)

− g mD K nD (W / L) D
Av = =− =−
g mL K nL (W / L) L

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Single-Stage Integrated Circuit Single-Stage Integrated Circuit
MOSFET Amplifiers (cont’d) MOSFET Amplifiers (cont’d)
z NMOS Amp. with
Depletion load

Single-Stage Integrated Circuit Single-Stage Integrated Circuit

MOSFET Amplifiers (cont’d) MOSFET Amplifiers (cont’d)
z CMOS Common-
Common-
Source Amplifier
Av = − g mD (rOD || rOL )

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Single-Stage Integrated Circuit Single-Stage Integrated Circuit
MOSFET Amplifiers (cont’d) MOSFET Amplifiers (cont’d)
z CMOS Source-
Source- z CMOS Common-
Common-
Follower Gate Amplifier
Amplifier

Multistage Amplifiers: Cascade Multistage Amplifiers: Cascode

Configuration Configuration

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 Design Application: Two-Stage
Basic JFET Amplifier
Amplifier
z Small-
Small-Signal Equivalent Circuit z Specifications: Assume the resistance R2 in the
voltage divider circuit varies linearly as a function of
temperature, pressure, or some other variable. The
output of the amplifier is to be zero volts when δ = 0.

2 I DSS ⎛ VGS ⎞
gm = ⎜1 − ⎟
VP ⎝ VP ⎠
−1
⎡ ⎛ V ⎞ ⎤
2
−1
rO = ⎢λ I DSS ⎜1 − GS ⎟ ⎥ ≅ ⎡⎣λ I DQ ⎤⎦
⎢⎣ ⎝ VP ⎠ ⎥
⎦

Design Application: Two-Stage

Additional Reading
Amplifier (cont’d)
z A. S. Sedra and K. C. Smith, “Microelectronic Circuit”
z Y. Tsividis, “The MOS Transistor”
z C. D. Ferris, “Elements of Electronic Design”

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Homeworks
z For an n-channel MOSFET biased in the saturation region, the
parameters are Kn = 0.5 mA/V2, VTN = 0.8 V, and λ = 0.01 V-1, and
IDQ = 0.75 mA. Determine gm and rO.
z The parameters of an n-channel MOSFET are: VTN = 1 V, ½µnCox =
18 µA/V2, and λ = 0.015 V-1. The transistor is to be biased in the
saturation region with IDQ = 2 mA. Design the width-to-length retio
such that the transconductance is gm = 3.4 mA/V. Calculate rO for
this condition.
z The parameters for the circuit in Figure 4.8 are VDD = 12 V and RD =
6 kΩ. The transistor parameters are: VTP = -1 V, Kp = 2 mA/V2, and λ
= 0. (a) Determine VSG such that VSDQ = 7 V. (b) Determine gm and
rO, and calculate the small-signal voltage gain.
z The common-source amplifier in Figure 4.26 has transistor
parameters VTN = 1.5 V, ½µnCox = 20 µA/V2, W/L = 25, and λ = 0.
Design the circuit such that IDQ = 0.5 mA and the small-signal
voltage gain is Av = -4.0.
z Consider the circuit shown in Figure 4.32 with circuit parameters
VDD = 5 V, RS = 5 kΩ, R1 = 70.7 kΩ, R2 = 9.3 kΩ, and RSi = 500 Ω.
The transistor parameters are: VTP = -0.8 V, Kp = 0.4 mA/V2, and λ =
0. Calculate the small-signal voltage gain Av= vo/vi and the output
resistance Ro seen looking back into the circuit.
Homeworks (cont’d)
z Consider the circuit shown in Figure 4.39 with circuit parameters
V+ = 5 V, V- = -5 V, RS = 4 kΩ, RD = 2 kΩ, RL = 4 kΩ and RG = 50
kΩ. The transistor parameters are: Kp = 1 mA/V2, VTP = -0.8 V,
and λ = 0. Draw the small-signal equivalent circuit, determine the
small-signal voltage gain Av = Vo/Vi, and find the input resistance
Ri.
z For the enhancement load amplifier shown in Figure 4.43(a), the
parameters are: VTND = VTNL = 0.8 V, ḱn = 40 µA/V2, (W/L)D = 80,
(W/L)L = 1, and VDD = 5 V. Determine the small-signal voltage
gain. Determine VGS such that the Q-point is in the middle of the
saturation region.
z The supply voltages to the cascode circuit shown in Figure 4.55
are changed to V+ = 10 V, and V- = -10 V. The transistor
parameters are: Kn1 = Kn2 = 1.2 mA/V2, VTN1 = VTN2 = 2 V, and λ1 =
λ2 = 0. (a) Let R1 + R2 + R3 = 500 kΩ. and RS = 10 kΩ. Design the
circuit such that IDQ = 1 mA and VDSQ1 = VDSQ2 = 3.5 V. (b)
Determine the small-signal voltage gain.
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