VHDL TERMS

ENTITY
Entity is the description of the interface between a design and its external environment. It may
also specify the declarations and statements that are part of the design entity. A given entity
declaration may be shared by many design entities, each of which has a different architecture.
Thus, an entity declaration can potentially represent a class of design entities, each having the
same interface. All VHDL designs have only one entity. But more than one configuration and
architecture can be used for that specific entity.

Note that => DESIGN ENTITY= ENTITY UNIT + ARCHITECTURAL UNIT

If an entity has generics, these must be declared before the ports. They do not have a mode, as
by definition they can only pass information into the entity:

entity AN2_GENERIC is
generic (DELAY: time := 1.0 ns);
port (A,B : in std_ulogic;
Z : out std_ulogic);
end AN2_GENERIC;

Ex:

entity entity_name is
generic (generic_list);
port (port_list);
end entity_name;

entity HALFADD is
port(A,B : in bit;
SUM, CARRY : out bit);
end HALFADD;
It is possible to write an entity without any generics, ports and passive statements. In fact this
is used in constructing testbenches.
entity TB_DISPLAY is
end TB_DISPLAY;

architecture TEST of TB_DISPLAY is

-- signal declarations
-- component declaration(s)
begin
-- component instance(s)
-- test processes
end TEST;

Each entity port acts like a signal which is visible in the architecture(s) of the entity. The
mode (i.e.direction) of each port determines whether it may be read from or written to in the
architecture:
Mode Read in Architecture Write in Architecture
in Yes No
out No Yes
inout Yes Yes
buffer Yes Yes
library IEEE;
use IEEE.std_logic_1164.all;
entity BCD_Decoder is
port (
BCD : in Bit_Vector (2 downto 0);
Enable : in Bit;
LED : out Std_Ulogic_Vector (3 downto 0));
constant ZERO : Std_Ulogic_Vector(3 downto 0) := "0000";
begin
assert (BCD /= "111") report "BCD = 7 " severity note;
end entity BCD_Decoder;

The above example illustrates several important issues related to entities. First two lines
contain a call to the IEEE library and to the std_logic_1164 package, respectively. These two
lines are required because the Std_Ulogic_Vector type used for the output signal LED is not a
standard type but it is defined in the mentioned package. If LED would be of Bit_Vector type
then the two lines could have been omitted.

The BCD_Decoder identifier, which is following the entity keyword, is a name assigned by
the designer to the entity. Note that this name is repeated at the very end of the entity.

The above listed entity contains the specification of ports only. In this case there are two
inputs (BCD and Enable) and one output (LED). The mode for each of them is supported after
a colon and is followed by a specification of the signal's type. See ports for more details on
modes and types of ports.The Declarative part of the above entity contains two declarations:
constant and assert statements. The constant introduced here will be visible in all architectures
of the BCD_Decoder entity. This type of a declaration makes sense if there are more than one
such architectures. Otherwise, it might be better to place it in the architecture section to make
the entity more clear.

The assert statement is a concurrent statement which will be active whenever any of the
BCD_Decoder architectures is active. This particular statement will generate a Message listed
in the report clause, whenever BCD will be equal to "111" ("BCD = 7"). Note that the
condition in the assert statement should be interpreted as "if not condition - then report".

port (

A, B, C, D: in STD_LOGIC;

F : out STD_LOGIC

);

The entity declaration includes the name of the entity and a set of port declarations. A port
may correspond to a pin on an IC, an edge connector on a board, or any logical channel of
communication with a block of hardware. Each port declaration includes the name of one or
more ports ( e.g., A, B), the direction that information is allowed to flow through the ports
(in, out or inout), and the data type of the ports (i.e., STD_LOGIC).

Note that ports declarations are signal declarations and port signals need not to be re-declared.
ARCHITECTURE
A body associated with an entity declaration to describe the internal organization or operation
of a design entity. An architecture body is used to describe the behavior, data flow, or
structure of a design entity.

Architecture assigned to an entity describes internal relationship between input and output
ports of the entity. It consists of two parts: declarations and concurrent statements.

First (declarative) part of an architecture may contain declarations of types, signals, constants,
subprograms (functions and procedures), components, and groups.

Concurrent statements in the architecture body define the relationship between inputs and
outputs. This relationship can be specified using different types of statements: concurrent
signal assignment, process statement, component instantiation, concurrent procedure
call, generate statement, concurrent assertion statement and block statement. It can be written
in different styles: structural, dataflow, behavioral (functional) or mixed.

The description of structural body is based on component instantiation and generate

statements. It allows to create hierarchical projects, from simple gates to very complex
components, describing entire subsystems. The connections among components are realized
through ports.

The Dataflow description is built with concurrent signal assignment statements. Each of the
statements can be activated when any of its input signals changes its value. While these
statements describe the behavior of the circuit, a lot of information about its structure can be
extracted form the description as well.

The architecture body describes only the expected functionality (behavior) of the circuit,
without any direct indication as to the hardware implementation. Such description consists
only of one or more processes, each of which contains sequential statements.

The architecture body may contain statements that define both behavior and structure of the
circuit at the same time. Such architecture description is called mixed .

Ex:

architecture Structure of Decoder_bcd is

signal S:Bit_Vector(0 to 1);
component AND_Gate
port(A,B:in Bit;D:out Bit);
end component;
component Inverter
port(A:in Bit;B:out Bit);
end component;
begin
Inv1:Inverter port map(A=>bcd(0),B=>S(0));
 Inv2:Inverter port map(A=>bcd(1), B=>S(1));
A1:AND_Gate port map(A=>bcd(0), B=>bcd(1), D=>led(3));
A2:AND_Gate port map(A=>bcd(0), B=>S(1), D=>led(2));
A3:AND_Gate port map(A=>S(0), B=>bcd(1), D=>led(1));
A4:AND_Gate port map(A=>S(0), B=>S(1), D=>led(0));
end Structure;

All declarations defined in an entity are fully visible and accessible within each architecture
assigned to this entity.

Single entity can have several architectures, but architecture cannot be assigned to different
entities.

architecture Mixed of Decoder_bcd is

signal S: Bit_Vector(0 to 2);
component Inverter
port(A: in Bit; B: out Bit);
end component;
begin
Inv1: Inverter port map (A=>bcd(0), B=>S(0));
Inv2: Inverter port map (A=>bcd(1), B=>S(1));
P: process (S, bcd)
begin
led(0) <= S(0) and S(1) after 5 ns;
led(1) <= S(0) and bcd(1) after 5 ns;
led(2) <= bcd(0) and S(1) after 5 ns;
led(3) <= bcd(0) and bcd(1) after 5 ns;
end process;
end Mixed;
architecture procedural of Decoder_bcd is
signal S: bit_vector (3 downto 0);
begin
P1: process (bcd, S)
begin
case bcd is
when "00" => S <= "0001" after 5 ns;
when "01" => S <= "0010" after 5 ns;
when "10" => S <= "0100" after 5 ns;
when "11" => S <= "1000" after 5 ns;
end case;
led <= S;
end process;
end procedural;

COMPONENT
All declarations
Ex:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity and_gate is
Port (in1 : in STD_LOGIC;
in2 : in STD_LOGIC;
output: out STD_LOGIC);
end and_gate;

architecture Behavioral of and_gate is

begin
output<=in1 and in2;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity nand_gate is
Port (A: in STD_LOGIC;
B: in STD_LOGIC;
C: out STD_LOGIC);
end nand_gate;

architecture Behavioral of nand_gate is

--Modülün programa tanıtılması

COMPONENT and_gate
PORT(in1: IN std_logic;
in2: IN std_logic;
output: OUT std_logic );
END COMPONENT;

signal ara_baglanti :std_logic;

begin

--Modülün program içerisinde çağrılması

U: and_gate PORT MAP( in1 =>A ,
in2 =>B ,
output => ara_baglanti );

C<= NOT ara_baglanti;

end Behavioral;