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AN2312
Authors: Somsak Sukittanon, Ph.D., Stephen G. Dame, MSEE
Associated Project: Yes
Associated Part Family: CY8C21xxx, CY8C24xxxA, CY8C24794, CY8C27xxx, CY8C29xxx
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Software Version: PSoC Designer™ 4.2
Associated Application Notes: AN2038
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AN2312
k (1 − z1Z −1 ) (1 − z2 Z −1 )
mov A,[X-5]
H (Z ) = Equation 4 call LoadBiquadState
(1 − p1Z −1 )(1 − p2 Z −1 )
;;; FEEDBACK PART
k is a constant. For the real filter, z1 is the conjugate of
; ((-a1/2) * u[n-1])*2
z2 and p1 is the conjugate of p2 .
Multiply32s_16s_16s (cTemp), (iACoff+0),
k (1 − z1Z )(1 − z Z )
−1 * −1 (iDelay+0)
H (Z ) =
1
(1 − p Z )(1 − p Z )
−1 * −1
call ShiftLeft32BitsBuffer
1 1
=
(
k 1 − 2 Re { z1} Z −1 + z1 Z −2
2
) ; -a2 * u[n-2]
(1 − 2 Re{ p } Z 1
−1
+ p1 Z −2
2
) Equation 5
MultiplyAndSum32s_16s_16s
(iACoff+2), (iDelay+2)
(cTemp),
call ShiftLeft32BitsBuffer
For a stable and minimum phase IIR filter, Re {p1 },
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AN2312
Feedforward Algorithm
Similar to a1 , b1 is always less than 2 so we prescale all
nth Order IIR Filter
In the previous section, we discussed the implementation
bi by 0.5 and post scale the final result back by a factor of of a second order IIR filter. In this section, we discuss the
2 (using a left shift operation). This method also prevents extension of the Biquad to higher order IIR filters. Suppose
filter overflow. The filter state delays are updated after the we are required to design a 6th order IIR filter. The transfer
feedforward operation. The following is PSoC assembly function can be written as:
code for computing y[n] :
b0 + b1Z −1 + L + b6 Z −6
H (Z ) = .
Code 2. Feedforward Operation 1 + a1Z −1 + L + a6 Z −6 Equation 6
;;; FORWARD PART
Equation 6 can also be represented in pole-zero form as:
; (b0/2) * u[n]
Multiply32s_16s_16s cTemp, (iBCoff+0), k (1 − z1Z −1 )(1 − z1* Z −1 )L (1 − z3* Z −1 )
H (Z ) =
(iUn+0) (1 − p Z )(1 − p Z )L (1 − p Z )
1
−1 *
1
−1 *
3
−1
Equation 7
⎛ k (1 − z Z )(1 − z Z ) ⎞
−1 * −1
=⎜ ⎟
1 1 1
; (b1/2) * u[n-1] ⎜ (1 − p Z )(1 − p Z ) ⎟−1 * −1
⎝ 1 ⎠ 1
⎜ (1 − p Z )(1 − p Z ) ⎟ −1 * −1
⎝ 2 ⎠ 2
×⎜ ⎟.
3 3 3
⎜ (1 − p Z )(1 − p Z ) ⎟ −1 * −1
MultiplyAndSum32s_16s_16s (cTemp), ⎝ 3 ⎠ 3
(iBCoff+4), (iDelay+2)
call ShiftLeft32BitsBuffer Equivalently, Equation 6 can be expressed as 3 cascaded
Biquad IIR filters. Each Biquad structure requires a
call ShiftLeft32BitsBuffer different set of ai , bi , ki , and filter state delays. To
mov [iBuffer+1],[cTemp+1] implement a cascaded Biquad IIR filter, we can use the
mov [iBuffer], [cTemp] same previous PSoC assembly code but the Biqaud
structure is dynamically loaded each time prior to each
Biquad filtering iteration. The filter state delays are saved
; swap delays after each Biquad operation. The following is the PSoC
; delay1 <--- delay 0 assembly code for dynamically loading the Biquad
structure:
; delay0 <--- u[n]
mov [iDelay+2],[iDelay+0]
mov [iDelay+3],[iDelay+1]
mov [iDelay+0],[iUn+0]
mov [iDelay+1],[iUn+1]
mov A,iDn
add A,[cStateDelay]
mov [cTemp],A
mov [cTemp+1],iDelay
call SwapDelays
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AN2312
Figure 2. Pole-Zero Plot (Left) and Frequency Response of 6th Order IIR Filter (Right)
200
1
Magnitude (dB)
0.8 0
0.6
-200
0.4
Imaginary Part
0.2 -400
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0 Normalized Frequency (×π rad/sample)
-0.2 0
Phase (degrees)
-0.4
-200
-0.6
-0.8 -400
-1
-600
-1 -0.5 0 0.5 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Real Part Normalized Frequency (×π rad/sample)
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AN2312
Figure 3. (Left) IIR Filtering Design Graphical Tool using MATLAB (Right) an Output File Used in PSoC
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AN2312
GetSignedMSB
Summary adc [@0],A
In this Application Note we present the implementation of
a high order IIR filter for PSoC. Many practical design and ; (2)
implementation issues, signed representation or overflow, PushMulY (@2 + 1)
were discussed. We also presented an easy way to
generate several filters, i.e., low pass, high pass, band GetXsYuMSB (@1 ), (@2+1)
pass, or notch filters, and plug coefficients into PSoC cmp A,128
projects. The graphical design tool is currently running on jc . + 4 ;pass on carry
MATLAB and can generate PSoC filter code in one click.
dec [@0]
add [@0 + 1],A
Appendix
adc [@0],0
The multiply and sum operation is modified from
Multiply32s_16s_16s (Application Note AN2038). Instead GetLSB
of storing into the first parameter, we add to the previous add [@0+2],A
value.
adc [@0+1],0
Code 4. Multiply and Sum Code adc [@0],0
macro MultiplyAndSum32s_16s_16s
; @0 = @0+(@1 * @2) ; (3)
; 16bit by 16 bit signed multiply PushMulX (@1 +1)
; with 32 bit signed result and added to GetUnsignedMSB (@1+1),(@2 + 1)
prior 32 bits
add [@0+2],A
;
adc [@0+1],0
; X(s) X+1(u)
adc [@0],0
; +-----+-----+
GetLSB
; | /| /|
add [@0+3],A
; | / | / |
adc [@0+2],0
; R | (1) | (4) |Y(s) Napier Matrix
adc [@0+1],0
; | /v | /^ |
adc [@0],0
; |/ v |/ ^ |
; +--v--|--^--+
; (4)
; | v /| ^ /|
PushMulY (@2)
; | v/ | ^/ |
GetXuYsMSB, (@1 + 1),(@2)
; R+1| (2)>>>(3) |Y+1(u)
push A
; | / | / |
cmp A,128
; |/ |/ |
jc .+ 4
; +-----+-----+
dec [@0]
; R+2 R+3
GetLSB
; @0 = @0+(@1* @2)
add [@0 + 2],A
pop A
; (1)
adc [@0 +1],A
PushMulX @1
adc [@0],0
PushMulY @2
GetLSB
endm
add [@0 + 1],A
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AN2312
Contact: somsak@virtual-dsp.com
Contact: steve@virtual-dsp.com
In March of 2007, Cypress recataloged all of its Application Notes using a new documentation number and revision code. This new documentation
number and revision code (001-xxxxx, beginning with rev. **), located in the footer of the document, will be used in all subsequent revisions.
PSoC is a registered trademark of Cypress Semiconductor Corp. "Programmable System-on-Chip," PSoC Designer, and PSoC Express are trademarks
of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are the property of their respective owners.
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