`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:47:53 07/03/2018
// Design Name:
// Module Name: mat_add
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

module mat_add(

input clk,
input [7:0] in_1,
input [7:0] in_2,
input [7:0] in_3,
input [7:0] in_4,
output [31:0] given_in,
output [31:0] trans_out
);

wire [7:0] temp [1:0][1:0];

wire [7:0] trans_temp [1:0][1:0];
genvar ROW,COLUMN;

assign temp[0][0] = in_1;

assign temp[0][1] = in_2;
assign temp[1][0] = in_3;
assign temp[1][1] = in_4;

for (COLUMN=0;COLUMN<2;COLUMN=COLUMN+1)
begin
for (ROW=0;ROW<2;ROW=ROW+1)
begin
assign trans_temp[COLUMN][ROW] = temp[ROW][COLUMN];
end
end

initial
begin
#100$display("the original matrix");
#100$display("%b\t %b",temp[0][0],temp[0][1]);
#100$display("%b\t %b",temp[1][0],temp[1][1]);
#100$display("the transposed matrix");
#100$display("%b\t %b",trans_temp[0][0],trans_temp[0][1]);
#100$display("%b\t %b",trans_temp[1][0],trans_temp[1][1]);
end
assign given_in = {{temp[1][1]},{temp[1][0]},{temp[0][1]},{temp[0][0]}};
assign trans_out = {trans_temp[0][0],trans_temp[0][1],trans_temp[1]
[0],trans_temp[1][1]};
endmodule
`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:51:27 07/03/2018
// Design Name: mat_add
// Module Name: E:/matrix/mat_add/test1.v
// Project Name: mat_add
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: mat_add
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////

module test1;

// Inputs
reg clk;
reg [7:0] in_1;
reg [7:0] in_2;
reg [7:0] in_3;
reg [7:0] in_4;

// Outputs
wire [31:0] given_in;
wire [31:0] trans_out;

// Instantiate the Unit Under Test (UUT)

mat_add uut (
.clk(clk),
.in_1(in_1),
.in_2(in_2),
.in_3(in_3),
.in_4(in_4),
.given_in(given_in),
.trans_out(trans_out)
);

initial begin
// Initialize Inputs
clk = 0;
in_1 = 0;
in_2 = 0;
in_3 = 0;
in_4 = 0;
// Wait 100 ns for global reset to finish
 #100;
clk = 1;
in_1 = 8'd12;
in_2 = 8'd23;
in_3 = 8'd45;
in_4 = 8'd32;
// Add stimulus here
end
endmodule