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Applications
Pin Configuration
• Front Side Bus VTT (1.2V/3A)
= Exposed Pad
(connected to VIN plane for better heat
dissipation)
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Block Diagram
EN VCNTL VIN
Power-
On-Reset
Soft-Start
UV and Thermal
Control Logic Limit
0.4V
VREF EAMP
0.8V
VOUT
FB Current
Limit
POK Delay
GND
90%
VREF
POK
VCNTL
CCNTL +5V
1µF
VIN
+1.5V
6
R3 CIN
1k VCNTL 100µF
POk
7
POk VIN 5
3
VOUT VOUT
4 +1.2V / 3A
VOUT
COUT
APL5913 220µF
8 2
EN EN FB
Enable GND R1
R2 1k
1
2k
C1
33nF (in the range of 12 ~ 48nF)
VIN
+1.5V
6
R3 CIN
1k VCNTL 22µF
POk
7
POk VIN 5
3
VOUT VOUT
4 +1.2V / 3A
VOUT
COUT
APL5913 22µF
8 2
EN EN FB
Enable GND R1
R2 39k
1
78k
C1
56pF
Thermal Characteristics
Symbol Parameter Value Unit
(Note1) o
θ JA Junction-to-Ambient Thermal Resistance in Free Air 42 C/W
(Note 2) o
θ JC Junction-to-Case Thermal Resistance in Free Air 18 C/W
Note 1 : θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
of SOP-8P is soldered directly on the PCB.
Note 2 : The “Thermal Pad Temperature” is measured on the PCB copper area connected to the thermal pad of package.
1 8
2 7
VIN
3 6
4 5
Measured Point
PCB Copper
Electrical Characteristics
Refer to the typical application circuit. These specifications apply over, VCNTL = 5V, VIN = 1.5V, VOUT = 1.2V and TA = 0
to 70°C, unless otherwise specified. Typical values refer to TA = 25°C.
APL5913
Symbol Parameter Test Conditions Unit
Min Typ Max
SUPPLY CURRENT
ICNTL VCNTL Supply Current EN = VCNTL, VFB is well regulated 0.4 1 2 mA
ISD VCNTL Shutdown Current EN = GND 180 380 µA
POWER-ON-RESET
VCNTL POR Threshold VCNTL Rising 2.7 2.9 3.1 V
VCNTL POR Hysteresis 0.4 V
VIN POR Threshold VIN Rising 0.8 0.9 1.0
VIN POR Hysteresis 0.5 V
OUTPUT VOLTAGE
VREF Reference Voltage FB =VOUT 0.8 V
Output Voltage Accuracy IOUT=0A ~ 3A, TJ= -25 ~125oC -1.5 +1.5 %
DROPOUT VOLTAGE
o
IOUT = 3A, VCNTL=5V, TJ= 25 C 0.17 0.25 V
Dropout Voltage o
IOUT = 3A, VCNTL=5V, TJ= -50~125 C 0.3 V
PROTECTION
VCNTL=5V, TJ= 25oC 4.8 5.7 6.6 A
VCNTL=5V, TJ= -25 ~ 125oC 4 A
ILIM Current Limit o
VCNTL=3.3V, TJ= 25 C 4.6 5.5 6.4 A
o
VCNTL=3.3V, TJ= -25 ~ 125 C 3.8 A
o
TSD Thermal Shutdown Temperature TJ Rising 150 C
o
Thermal Shutdown Hysteresis 50 C
Under-Voltage Threshold VFB Falling 0.4 V
ENABLE AND SOFT-START
EN Logic High Threshold Voltage VEN Rising 0.3 0.4 0.5 V
EN Hysteresis 30 mV
EN Pin Pull-Up Current EN=GND 10 µA
TSS Soft-Start Interval 2 ms
POWER OK AND DELAY
POK Threshold Voltage for Power
VPOK VFB Rising 90% 92% 94% VREF
OK
POK Threshold Voltage for Power
VPNOK VFB Falling 79% 81% 83% VREF
Not OK
POK Low Voltage POK sinks 5mA 0.25 0.4 V
TDELAY POK Delay Time 1 3 10 ms
0.9 5.4
VCNTL=5V
0.8 5.3
0.3 4.8
0.2 4.7
VCNTL=3.3V
0.1 4.6
0.0 4.5
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Dropout Voltage vs. Output Current Dropout Voltage vs. Output Current
450 250
VCNTL=3.3V VCNTL=5V
400 VOUT=1.2V TJ=125°C VOUT=1.2V
Dropout Voltage (mV)
200 TJ=0°C
100
150 TJ=0°C
TJ=-25°C
100 50 TJ=-25°C
50
0 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0
4.3
Reference Voltage, VREF (mV)
0.806
4.1
0.800 3.5
3.3 VCNTL=3.3V
0.798
3.1
0.796
2.9
0.794 2.7
0.792 2.5
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
-40.00
-50
-50.00 -60
-60.00 -70
100 1000 10000 100000 1000000 100 1000 10000 100000 1000000
Operating Waveforms
Test Circuit
R4
C2 2.2 L1
1µF 1µH
+5V
5
C3 C4
C8 D1
R8 1µF 470µF x2 C9
470pF VCC 1N4148 VCNTL
8.2k 47µF
1 +5V
BOOT CVCNTL
7 OCSET 1µF POK
C6
Q1
0.1µF
APM2014N
6
Q3 2
UGATE L2 VIN VCNTL
+1.5 R3
3.3µH
8 V 5 7 1k
Shutdown PHASE VIN POK VOUT
U2 CIN
+1.2V/3A
C5 3
APW7057 Q2 100µF VOUT
6 4 1000µF x2 4
FB LGATE APM2014N VOUT
U1 COUT
GND APL5913 220µF
8 2
R5 EN EN FB
3
1.75k GND R1
Enable
R2 1k
1
2k
R7
2k C1
C7 R6 33nF
0.1µF 0
IOUT IOUT
IOUT
2
R1=39kΩ, R2=78kΩ
C1=56pF VOUT VOUT
VOUT
1 1 1
2
IOUT IOUT
IOUT
2 2
VIN
Ch1 Ch1 V
VIN
IN
VOUT
VOUT
VOUT
Ch2 VCNTL Ch2
VVCNTL
CNTL
VPOK
VVPOK
POK
Ch3 Ch3
Ch4 Ch4
Shutdown Enable
VEN
V VEN
Ch1
EN VEN
Ch1
VOUT
OUT VVOUT
OUT
Ch2 Ch2
IIOUT
OUT IIOUT
OUT
Ch3 Ch3
VPOK
V POK VVPOK
POK
Ch4 Ch4
4. POK Delay :
- VIN = 1.5V, VCNTL = 5V,VOUT = 1.2V
- COUT = 220µF/6.3V (ESR = 30mΩ), CIN = 100µF/6.3V, RL=1Ω
VVIN
IN
Ch1
POK Delay
VVOUT
OUT
Ch2
VPOK
V POK
Ch3
Ground pin of the circuitry. All voltage levels are mea- Power input pin of the control circuitry. Connecting this
sured with respect to this pin. pin to a +5V (recommended) supply voltage provides
the bias for the control circuitry. The voltage at this pin is
FB (Pin 2)
monitored for Power-On-Reset purpose.
Connecting this pin to an external resistor divider receives
POK (Pin 7)
the feedback voltage of the regulator. The output voltage
set by the resistor divider is determined by: Power-OK signal output pin. This pin is an open-drain
R1 output used to indicate status of output voltage by sens-
VOUT = 0.8 ⋅ 1+ (V)
R2 ing FB voltage. This pin is pulled low when the rising FB
where R1 is connected from VOUT to FB with Kelvin sens- voltage is not above the VPOK threshold or the falling FB
ing and R2 is connected from FB to GND. A bypass ca- voltage is below the VPNOK threshold, indicating the output
pacitor may be connected with R1 in parallel to improve is not OK.
load transient response.
EN (Pin 8)
VOUT (Pin 3,4)
Enable control pin. Pulling and holding this pin below 0.
Output of the regulator. Please connect Pin 3 and 4 to- 3V shuts down the output. When re-enabled, the IC un-
gether using wide tracks. It is necessary to connect a dergoes a new soft-start cycle. When leave this pin open,
output capacitor with this pin for closed-loop compen- an internal current source 10µA pulls this pin up to VCNTL
sation and improve transient responses. voltage, enabling the regulator.
VIN (Pin 5) and Exposed Pad
Function Description
Power-On-Reset Internal Soft-Start
A Power-On-Reset (POR) circuit monitors both input volt- An internal soft-start function controls rising rate of the
ages at VCNTL and VIN pins to prevent wrong logic output voltage to limit the current surge at start-up. The
controls. The POR function initiates a soft-start process typical soft-start interval is about 2ms.
after the two supply voltages exceed their rising POR
Output Voltage Regulation
threshold voltages during powering on. The POR func-
tion also pulls low the POK pin regardless the output An error amplifier works with a temperature- compen-
voltage when the VCNTL voltage falls below its falling sated 0.8V reference and an output NMOS regulates out-
POR threshold. put to the preset voltage. The error amplifier is designed
with high bandwidth and DC gain provides very fast tran-
sient response and less load regulation. It compares the
Application Information
Power Sequencing Output Capacitor
The power sequencing of VIN and VCNTL is not necessary to The APL5913 requires a proper output capacitor to
be concerned. However, do not apply a voltage to VOUT maintain stability and improve transient response over
for a long time when the main voltage applied at VIN is not temperature and current. The output capacitor selection
present. The reason is the internal parasitic diode from is to select proper ESR (equivalent series resistance)
VOUT to VIN conducts and dissipates power without pro- and capacitance of the output capacitor for good stability
tections due to the forward-voltage. and load transient response.
Output Capacitor (Cont.) and FB pins. It works with the internal error amplifier to
provide proper frequency response for the linear regulator.
The APL5913 is designed with a programmable feedback
The ESR is the equivalent series resistance of the output
compensation adjusted by an external feedback network
capacitor. The C OUT is ideal capacitance in the output
for the use of wide ranges of ESR and capacitance in all
capacitor. The VOUT is the setting of the output voltage.
applications. Ultra-low-ESR capacitors (such as ceramic
chip capacitors) and low-ESR bulk capacitors (such as
solid Tantalum, POSCap, and Aluminum electrolytic VOUT
VOUT
capacitors) can all be used as an output capacitor. The APL5913
value of the output capacitors can be increased without
limit. R1 ESR
C1
FB
During load transients, the output capacitors, depending V ERR
EAMP VFB C OUT
on the stepping amplitude and slew rate of load current,
VREF R2
are used to reduce the slew rate of the current seen by
the APL5913 and help the device to minimize the variations
of output voltage for good transient response. For the
Figure 1
applications with large stepping load current, the low-
ESR bulk capacitors are normally recommended. The feedback network selection depends on the values
of the ESR and COUT which has been classified into three
Decoupling ceramic capacitors must be placed at the load
conditions:
and ground pins as close as possible and the impedance
of the layout must be minimized. • Condition 1 : Large ESR ( ≥18mΩ )
- Select the R1 in the range of 400Ω ~ 2.4kΩ
Input Capacitor
- Calculate the R2 as the following :
The APL5913 requires proper input capacitors to supply 0.8(V)
R2(kΩ) = R1(kΩ) ⋅ .......... (1)
VOUT(V) - 0.8(V)
current surge during stepping load transients to prevent
the input rail from dropping. Because the parasitic in- - Calculate the C1 as the following :
ductor from the voltage sources or other bulk capacitors
VOUT(V) VOUT(V)
to the VIN pin limit the slew rate of the surge currents, 10 ⋅ ≤ C1(nF) ≤ 40 ⋅ ...... (2)
R1(kΩ ) R1(kΩ )
more parasitic inductance needs more input capacitance.
Ultra-low-ESR capacitors (such as ceramic chip • Condition 2 : Middle ESR
capacitors) and low-ESR bulk capacitors (such as solid - Calculate the R1 as the following:
tantalum, POSCap, and Aluminum electrolytic capacitors) 2157
R1(kΩ) = − 37.5 ⋅ VOUT(V) + 15 ......... (3)
can all be used as an input capacitor of VIN. For most of ESR(mΩ)
applications, the recommended input capacitance of VIN Select a proper R1(selected) to be a little larger than
is 10µF at least. If the drop of the input voltage is not the calculated R1.
cared, the input capacitance can be less than 10µF. More - Calculate the C1 as the following :
capacitance reduces the variations of the input voltage of COUT(µF)
C1(pF) = [0.71 ⋅ ESR(mΩ ) + 101] ⋅ ........ (4)
VIN pin. R1(kΩ)
Where R1=R1(selected)
Feedback Network Select a proper C1(selected) to be a little smaller
Figure 1 shows the feedback network among VOUT, GND, than the calculated C1.
- The C1 calculated from equation (4) must meet
the following equation:
143 37.5 ⋅ VOUT(V) 1. Please solder the Exposed Pad and VIN together on
C1(pF) ≥ 7.2 ⋅ 1 + ⋅ 1 + .. (5)
ESR(m Ω) R1(kΩ) the PCB. The main current flow is through the ex
posed pad.
Where R1=R1(calculated) from equation (3)
2. Please place the input capacitors for VIN and VCNTL
If the C1(calculated) can not meet the equation (5), pins near pins as close as possible.
please use the Condition 3.
3. Ceramic decoupling capacitors for load must be
- Use equation (2) to calculate the R2. placed near the load as close as possible.
• Condition 3 : Low ESR (eg. Ceramic Capacitors) 4. To place APL5913 and output capacitors near the load
is good for performance.
- Calculate the R1 as the following:
5. The negative pins of the input and output capaci-tors
R1(kΩ) = (2.1⋅ ESR(mΩ) + 300) ⋅ COUT(µF) − 37.5 ⋅ VOUT(V) .. (6) and the GND pin of the APL5913 are connected to the
ground plane of the load.
Select a proper R1(selected) to be a little larger than
6. Please connect PIN 3 and 4 together by a wide track.
the calculated R1. The minimum selected R1 is
equal to 1kΩ when the calculated R1 is smaller 7. Large current paths must have wide tracks.
than 1k or negative. 8. See the Typical Application
- Calculate the C1 as the following : (See Figure 2)
37.5 ⋅ VOUT(V) - Connect the one pin of the R2 to the GND of APL5913
C1(pF) = (0.24⋅ ESR(mΩ) + 34.2)⋅ COUT(µF) ⋅ 1+ .. (7)
R1(kΩ)
- Connect the one pin of R1 to the Pin 3 of APL5913
Where R1=R1(selected)
- Connect the one pin of C1 to the Pin 3 of APL5913
Select a proper C1(selected) to be a little smaller
than the calculated C1.
VCNTL
- The C1 calculated from equation (7) must meet
CCNTL
the following equation : CIN
VCNTL
1.25 ⋅ VOUT (V)
C1(pF) ≥ 0.033 + ⋅ ESR(m Ω ) ⋅ COUT (µF) .(8) VIN VIN
R1(kΩ )
APL5913
VOUT
Where R1=R1(calculated) from equation (6) VOUT
VOUT COUT
If the C1(calculated) can not meet the equation (8),
C1
please use the Condition 2. R1
FB
Load
- Use equation (2) to calculate the R2. GND
R2
The reason to have three conditions described above is
to optimize the load transient responses for all kinds of
the output capacitor. For stability only, the Condition 2, Figure 2
regardless of equation (5), is enough for all kinds of output
capacitor.
102 mil
1 8
2 7
118 mil SOP-8-P
SOP-8P
3 6
4 5
Top Exposed
VOUT Die Pad Top
plane VIN
plane
Ambient
Air
PCB
Figure 3
Recommended Minimum Footprint
0.024
8 7 6 5
0.072
0.138
0.212
0.118
1 2 3 4
Package Information
SOP-8P
D
SEE VIEW
A
D1
E1
E2
THERMAL
PAD E
°
h X 45
e b c
0.25
A2
GAUGE PLANE
SEATING PLANE
A1
L 0
VIEW A
S SOP-8P
Y
M MILLIMETERS INCHES
B
O
L MIN. MAX. MIN. MAX.
A 1.60 0.063
A2 1.25 0.049
b 0.31 0.51 0.012 0.020
c 0.17 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
D1 2.25 3.50 0.098 0.138
0 0o 8o 0o 8o
Note : 1. Follow JEDEC MS-012 BA.
2. Dimension "D" does not include mold flash, protrusions
or gate burrs. Mold flash, protrusion or gate burrs shall not
exceed 6 mil per side .
3. Dimension "E" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
OD0 P0 P2 P1 A
E1
F
W
B0
K0 A0 OD1 B A
B
SECTION A-A
T
SECTION B-B
d
H
A
T1
Application A H T1 C d D W E1 F
330.0± 12.4+2.00 13.0+0.50
50 MIN. 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05
2.00 -0.00 -0.20
SOP-8(P) P0 P1 P2 D0 D1 T A0 B0 K0
1.5+0.10 0.6+0.00
4.0±0.10 8.0±0.10 2.0±0.05 1.5 MIN. 6.40±0.20 5.20±0.20 2.10±0.20
-0.00 -0.40
(mm)
TP tp
Critical Zone
TL to TP
Ramp-up
TL
Temperature
tL
Tsmax
Tsmin
Ramp-down
ts
Preheat
t 25°C to Peak
25
Time
Reliability Test Program
Test item Method Description
SOLDERABILITY MIL-STD-883D-2003 245°C, 5 sec
HOLT MIL-STD-883D-1005.7 1000 Hrs Bias @125°C
PCT JESD-22-B, A102 168 Hrs, 100%RH, 121°C
TST MIL-STD-883D-1011.9 -65°C~150°C, 200 Cycles
ESD MIL-STD-883D-3015.7 VHBM > 2KV, VMM > 200V
Latch-Up JESD 78 10ms, 1tr > 100mA
Customer Service
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838