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APL5913

0.8V Reference Ultra Low Dropout (0.25V@3A) Linear Regulator

Features General Description


• Ultra Low Dropout The APL5913 is a 3A ultra low dropout linear regulator.
- 0.25V(typical) at 3A Output Current This product is specifically designed to provide well sup-
• Low ESR Output Capacitor (Multi-layer Chip pl y vo la tag e fo r fro nt -s id e-b us t er m in at io n on
Capacitors (MLCC)) Applicable motherboards and NB applications. The IC needs two
• 0.8V Reference Voltage supply voltages, a control voltage for the circuitry and a
• High Output Accuracy main supply voltage for power conversion, to reduce
- ±1.5% over Line, Load and Temperature power dissipation and provide extremely low dropout.
• Fast Transient Response
The APL5913 integrates many functions. A Power-On-Re-
• Adjustable Output Voltage by External
set (POR) circuit monitors both supply voltages to pre-
Resistors
vent wrong operations. A thermal shutdown and current
• Power-On-Reset Monitoring on Both VCNTL and
limit functions protect the device against thermal and cur-
VIN Pins
rent over-loads. A POK indicates the output status with
• Internal Soft-Start
time delay which is set internally. It can control other con-
• Current-Limit Protection
verter for power sequence. The APL5913 is enabled by
• Under-Voltage Protection
other power system. Pulling and holding the EN pin be-
• Thermal Shutdown with Hysteresis
low 0.3V shuts off the output.
• Power-OK Output with a Delay Time
• Shutdown for Standby or Suspend Mode The APL5913 is available in SOP-8P package which fea-
• Simple SOP-8P Package with Exposed Pad tures small size as SOP-8 and an Exposed Pad to reduce
• Lead Free and Green Devices Available the junction-to-case resistance, being applicable in
(RoHS Compliant) 2~2.4W applications.

Applications
Pin Configuration
• Front Side Bus VTT (1.2V/3A)

• Note Book PC Applications


GND 1 8 EN
• Motherboard Applications FB 2
VIN
7 POK
VOUT 3 6 VCNTL
VOUT 4 5 VIN

SOP-8P (Top View)

= Exposed Pad
(connected to VIN plane for better heat
dissipation)

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Rev. A.7 - Apr., 2008
APL5913

Ordering and Marking Information


APL5913 Package Code
KA : SOP-8P
Assembly Material Operating Ambient Temperature Range
Handling Code C : 0 to 70 oC
Handing Code
Temperature Range
TR : Tape & Reel
Package Code Assembly Material
L : Lead Free Device
G : Halogen and Lead Free Device
APL5913
APL5913 KA : XXXXX - Date Code
XXXXX

Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).

Block Diagram
EN VCNTL VIN

Power-
On-Reset

Soft-Start
UV and Thermal
Control Logic Limit
0.4V

VREF EAMP
0.8V

VOUT
FB Current
Limit

POK Delay
GND
90%
VREF

POK

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Rev. A.7 - Apr., 2008
APL5913

Typical Application Circuits

1. Using an Output Capacitor with ESR≥18mΩ

VCNTL
CCNTL +5V
1µF

VIN
+1.5V

6
R3 CIN
1k VCNTL 100µF
POk
7
POk VIN 5

3
VOUT VOUT
4 +1.2V / 3A
VOUT
COUT
APL5913 220µF
8 2
EN EN FB
Enable GND R1
R2 1k
1

2k

C1
33nF (in the range of 12 ~ 48nF)

2. Using an MLCC as the Output Capacitor


VCNTL
CCNTL +5V
1µF

VIN
+1.5V
6

R3 CIN
1k VCNTL 22µF
POk
7
POk VIN 5

3
VOUT VOUT
4 +1.2V / 3A
VOUT
COUT
APL5913 22µF
8 2
EN EN FB
Enable GND R1
R2 39k
1

78k

C1
56pF

VOUT (V) R1 (kΩ) R2 (kΩ) C1 (pF)


1.05 43 137.6 47
1.5 27 30.86 82
1.8 15 12 150

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Rev. A.7 - Apr., 2008
APL5913

Absolute Maximum Ratings

Symbol Parameter Rating Unit


VCNTL VCNTL Supply Voltage (VCNTL to GND) -0.3 ~ 7 V
VIN VIN Supply Voltage (VIN to GND) -0.3 ~ 3.3 V
VI/O EN and FB to GND -0.3 ~ VCNTL+0.3 V
VPOK POK to GND -0.3 ~ 7 V
PD Power Dissipation 3 W
o
TJ Junction Temperature 150 C
o
TSTG Storage Temperature -65 ~ 150 C
o
TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 C

Thermal Characteristics
Symbol Parameter Value Unit
(Note1) o
θ JA Junction-to-Ambient Thermal Resistance in Free Air 42 C/W
(Note 2) o
θ JC Junction-to-Case Thermal Resistance in Free Air 18 C/W

Note 1 : θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
of SOP-8P is soldered directly on the PCB.
Note 2 : The “Thermal Pad Temperature” is measured on the PCB copper area connected to the thermal pad of package.

1 8
2 7
VIN
3 6
4 5
Measured Point
PCB Copper

Recommended Operating Conditions


Symbol Parameter Range Unit
VCNTL VCNTL Supply Voltage 3.1 ~ 6 V
VIN VIN Supply Voltage 1.1 ~ 3.3 V
Output Voltage
VOUT VCNTL=3.3±5% 0.8 ~ 1.2 V
VCNTL=5.0±5% 0.8 ~ VIN-0.2

IOUT VOUT Output Current 0~4 A


o
TJ Junction Temperature -25 ~ 125 C

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Rev. A.7 - Apr., 2008
APL5913

Electrical Characteristics
Refer to the typical application circuit. These specifications apply over, VCNTL = 5V, VIN = 1.5V, VOUT = 1.2V and TA = 0
to 70°C, unless otherwise specified. Typical values refer to TA = 25°C.

APL5913
Symbol Parameter Test Conditions Unit
Min Typ Max
SUPPLY CURRENT
ICNTL VCNTL Supply Current EN = VCNTL, VFB is well regulated 0.4 1 2 mA
ISD VCNTL Shutdown Current EN = GND 180 380 µA
POWER-ON-RESET
VCNTL POR Threshold VCNTL Rising 2.7 2.9 3.1 V
VCNTL POR Hysteresis 0.4 V
VIN POR Threshold VIN Rising 0.8 0.9 1.0
VIN POR Hysteresis 0.5 V
OUTPUT VOLTAGE
VREF Reference Voltage FB =VOUT 0.8 V
Output Voltage Accuracy IOUT=0A ~ 3A, TJ= -25 ~125oC -1.5 +1.5 %

Line Regulation VCNTL=3.3 ~ 5.5V -0.13 0 0.13 %/V

Load Regulation IOUT=0A ~ 3A 0.06 0.15 %

DROPOUT VOLTAGE
o
IOUT = 3A, VCNTL=5V, TJ= 25 C 0.17 0.25 V
Dropout Voltage o
IOUT = 3A, VCNTL=5V, TJ= -50~125 C 0.3 V
PROTECTION
VCNTL=5V, TJ= 25oC 4.8 5.7 6.6 A
VCNTL=5V, TJ= -25 ~ 125oC 4 A
ILIM Current Limit o
VCNTL=3.3V, TJ= 25 C 4.6 5.5 6.4 A
o
VCNTL=3.3V, TJ= -25 ~ 125 C 3.8 A
o
TSD Thermal Shutdown Temperature TJ Rising 150 C
o
Thermal Shutdown Hysteresis 50 C
Under-Voltage Threshold VFB Falling 0.4 V
ENABLE AND SOFT-START
EN Logic High Threshold Voltage VEN Rising 0.3 0.4 0.5 V
EN Hysteresis 30 mV
EN Pin Pull-Up Current EN=GND 10 µA
TSS Soft-Start Interval 2 ms
POWER OK AND DELAY
POK Threshold Voltage for Power
VPOK VFB Rising 90% 92% 94% VREF
OK
POK Threshold Voltage for Power
VPNOK VFB Falling 79% 81% 83% VREF
Not OK
POK Low Voltage POK sinks 5mA 0.25 0.4 V
TDELAY POK Delay Time 1 3 10 ms

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Rev. A.7 - Apr., 2008
APL5913

Typical Operating Characteristics

VCNTL Supply Current vs. Current-limit vs.


Junction Temperature Junction Temperature
1.0 5.5
VCNTL Supply Current, ICNTL (mA)

0.9 5.4
VCNTL=5V
0.8 5.3

Current-limit, ILIM (A)


0.7 5.2

0.6 5.1 VCNTL=5V


0.5 5
VCNTL=3.3V
0.4 4.9

0.3 4.8

0.2 4.7
VCNTL=3.3V
0.1 4.6

0.0 4.5
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125

Junction Temperature (°C) Junction Temperature (°C)

Dropout Voltage vs. Output Current Dropout Voltage vs. Output Current

450 250
VCNTL=3.3V VCNTL=5V
400 VOUT=1.2V TJ=125°C VOUT=1.2V
Dropout Voltage (mV)

350 200 TJ=125°C


TJ=75°C
Dropout Voltage (mV)

300 TJ=25°C TJ=75°C


150
250 TJ=25°C

200 TJ=0°C
100
150 TJ=0°C
TJ=-25°C
100 50 TJ=-25°C
50

0 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0

Output Current, lOUT(A) Output Current, lOUT(A)

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Rev. A.7 - Apr., 2008
APL5913

Typical Operating Characteristics

Reference Voltage vs. POK Delay Time vs.


Junction Temperature Junction Temperature
0.808 4.5

4.3
Reference Voltage, VREF (mV)

0.806
4.1

POK Delay Time (ms)


0.804
3.9
VCNTL=5V
0.802 3.7

0.800 3.5

3.3 VCNTL=3.3V
0.798
3.1
0.796
2.9
0.794 2.7

0.792 2.5
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125

Junction Temperature (°C) Junction Temperature (°C)

VCNTL PSRR VIN PSRR


0.00 0
VCNTL = 5V
VCNTL = 4.5V~5.5V VIN = 1.5V(lower bound)
VIN = 1.5V -10 VINPK-PK = 100mV
-10.00
VOUT = 1.2V CIN = 47µF
Ripple Rejection (dB)

IOUT = 3A COUT = 330µF(30mΩ)


-20
CIN = 100µF IOUT = 3A
-20.00
Amplitude (dB)

COUT = 330µF(ESR=30mΩ) VOUT = 1.2V


-30
-30.00
-40

-40.00
-50

-50.00 -60

-60.00 -70
100 1000 10000 100000 1000000 100 1000 10000 100000 1000000

Frequency (Hz) Frequency (Hz)

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Rev. A.7 - Apr., 2008
APL5913

Operating Waveforms
Test Circuit
R4

C2 2.2 L1
1µF 1µH
+5V
5

C3 C4
C8 D1
R8 1µF 470µF x2 C9
470pF VCC 1N4148 VCNTL
8.2k 47µF
1 +5V
BOOT CVCNTL
7 OCSET 1µF POK
C6
Q1
0.1µF
APM2014N

6
Q3 2
UGATE L2 VIN VCNTL
+1.5 R3
3.3µH
8 V 5 7 1k
Shutdown PHASE VIN POK VOUT
U2 CIN
+1.2V/3A
C5 3
APW7057 Q2 100µF VOUT
6 4 1000µF x2 4
FB LGATE APM2014N VOUT
U1 COUT
GND APL5913 220µF
8 2
R5 EN EN FB
3

1.75k GND R1
Enable
R2 1k

1
2k
R7
2k C1
C7 R6 33nF
0.1µF 0

1. Load Transient Response :


1.1 Using an Output Capacitor with ESR≥18mΩ
- COUT = 220µF/6.3V (ESR = 30mΩ), CIN = 100µF/6.3V
- IOUT = 10mA to 3A to 10mA, Rise time = Fall time = 1µs

IOUT = 10mA ->3A IOUT = 10mA -> 3A ->10mA IOUT = 3A ->10mA

R1=1kΩ, R2=2kΩ, C1=33n F


VOUT VOUT
VOUT
1

IOUT IOUT

IOUT
2

Ch1 : VOUT, 50mV/Div Ch1 : VOUT, 50mV/Div Ch1 : VOUT, 50mV/Div


Ch2 : IOUT, 1A/Div Ch2 : IOUT, 1A/Div Ch2 : IOUT, 1A/Div
Time : 2µs/Div Time : 20µs/Div Time : 2µs/Div

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Rev. A.7 - Apr., 2008
APL5913

Operating Waveforms (Cont.)

1.2 Using a MLCC as the Output Capacitor


- COUT = 22µF/6.3V (ESR = 3mΩ), CIN = 22µF/6.3V
- IOUT = 10mA to 3A to 10mA, Rise time = Fall time = 1µs

IOUT = 10mA ->3A IOUT = 10mA -> 3A ->10mA IOUT = 3A ->10mA

R1=39kΩ, R2=78kΩ
C1=56pF VOUT VOUT
VOUT
1 1 1

2
IOUT IOUT

IOUT
2 2

Ch1 : VOUT, 100mV/Div Ch1 : VOUT, 100mV/Div Ch1 : VOUT, 100mV/Div


Ch2 : IOUT, 1A/Div Ch2 : IOUT, 1A/Div Ch2 : IOUT, 1A/Div
Time : 2µs/Div Time : 20µs/Div Time : 2µs/Div

2. Power ON and Power OFF :


- VIN = 1.5V, VCNTL = 5V,VOUT = 1.2V
- COUT = 220µF/6.3V (ESR = 30mΩ), CIN = 100µF/6.3V, RL=1Ω

Power ON Power OFF

VIN
Ch1 Ch1 V
VIN
IN

VOUT
VOUT
VOUT
Ch2 VCNTL Ch2
VVCNTL
CNTL

VPOK
VVPOK
POK

Ch3 Ch3

Ch4 Ch4

Ch1 : VIN, 1V/div Ch1 : VIN, 1V/div


Ch2 : VOUT, 1V/div Ch2 : VOUT, 1V/div
Ch3 : VPOK, 1V/div Ch3 : VPOK, 1V/div
Ch4 : VCNTL, 2V/div Ch4 : VCNTL, 2V/div
Time : 10ms/div Time : 10ms/div

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Rev. A.7 - Apr., 2008
APL5913

Operating Waveforms (Cont.)

3. Shutdown and Enable :


- VIN = 1.5V, VCNTL = 5V,VOUT = 1.2V
- COUT = 220µF/6.3V (ESR = 30mΩ), CIN = 100µF/6.3V, RL=1Ω

Shutdown Enable

VEN
V VEN
Ch1
EN VEN
Ch1

VOUT
OUT VVOUT
OUT
Ch2 Ch2

IIOUT
OUT IIOUT
OUT
Ch3 Ch3
VPOK
V POK VVPOK
POK

Ch4 Ch4

Ch1 : VEN, 5V/div Ch1 : VEN, 5V/div


Ch2 : VOUT, 1V/div Ch2 : VOUT, 1V/div
Ch3 : IOUT, 1A/div Ch3 : IOUT, 1A/div
Ch4 : VPOK, 1V/div Ch4 : VPOK, 1V/div
Time : 1ms/div Time : 1ms/div

4. POK Delay :
- VIN = 1.5V, VCNTL = 5V,VOUT = 1.2V
- COUT = 220µF/6.3V (ESR = 30mΩ), CIN = 100µF/6.3V, RL=1Ω

VVIN
IN

Ch1
POK Delay

VVOUT
OUT

Ch2

VPOK
V POK
Ch3

Ch1 : VIN, 1V/div


Ch2 : VOUT, 1V/div
Ch3 : VPOK, 1V/div
Time : 1ms/div

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Rev. A.7 - Apr., 2008
APL5913

Functional Pin Description


GND (Pin 1) VCNTL (Pin 6)

Ground pin of the circuitry. All voltage levels are mea- Power input pin of the control circuitry. Connecting this
sured with respect to this pin. pin to a +5V (recommended) supply voltage provides
the bias for the control circuitry. The voltage at this pin is
FB (Pin 2)
monitored for Power-On-Reset purpose.
Connecting this pin to an external resistor divider receives
POK (Pin 7)
the feedback voltage of the regulator. The output voltage
set by the resistor divider is determined by: Power-OK signal output pin. This pin is an open-drain
 R1  output used to indicate status of output voltage by sens-
VOUT = 0.8 ⋅ 1+  (V)
 R2  ing FB voltage. This pin is pulled low when the rising FB
where R1 is connected from VOUT to FB with Kelvin sens- voltage is not above the VPOK threshold or the falling FB
ing and R2 is connected from FB to GND. A bypass ca- voltage is below the VPNOK threshold, indicating the output
pacitor may be connected with R1 in parallel to improve is not OK.
load transient response.
EN (Pin 8)
VOUT (Pin 3,4)
Enable control pin. Pulling and holding this pin below 0.
Output of the regulator. Please connect Pin 3 and 4 to- 3V shuts down the output. When re-enabled, the IC un-
gether using wide tracks. It is necessary to connect a dergoes a new soft-start cycle. When leave this pin open,
output capacitor with this pin for closed-loop compen- an internal current source 10µA pulls this pin up to VCNTL
sation and improve transient responses. voltage, enabling the regulator.
VIN (Pin 5) and Exposed Pad

Main supply input pins for power conversions. The Ex-


posed Pad provides a very low impedance input path for
the main supply voltage. Please tie the Exposed Pad and
VIN Pin (Pin 8) together to reduce the dropout voltage. The
voltage at this pins is monitored for Power-On-Reset
purpose.

Function Description
Power-On-Reset Internal Soft-Start

A Power-On-Reset (POR) circuit monitors both input volt- An internal soft-start function controls rising rate of the
ages at VCNTL and VIN pins to prevent wrong logic output voltage to limit the current surge at start-up. The
controls. The POR function initiates a soft-start process typical soft-start interval is about 2ms.
after the two supply voltages exceed their rising POR
Output Voltage Regulation
threshold voltages during powering on. The POR func-
tion also pulls low the POK pin regardless the output An error amplifier works with a temperature- compen-
voltage when the VCNTL voltage falls below its falling sated 0.8V reference and an output NMOS regulates out-
POR threshold. put to the preset voltage. The error amplifier is designed
with high bandwidth and DC gain provides very fast tran-
sient response and less load regulation. It compares the

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Rev. A.7 - Apr., 2008
APL5913

Function Description (Cont.)


Output Voltage Regulation (Cont.) For normal operation, device power dissipation should
reference with the feedback voltage and amplifies the dif- be externally limited so that junction temperatures will
ference to drive the output NMOS which provides load not exceed +125°C.
current from VIN to VOUT. Enable Control
Current-Limit The APL5913 has a dedicated enable pin (EN). A logic
The APL5913 monitors the current via the output NMOS low signal (VEN< 0.3V) applied to this pin shuts down the
and limits the maximum current to prevent load and output. Following a shutdown, a logic high signal re-en-
APL5913 from damages during overload or short-circuit ables the output through initiation of a new softstart cycle.
conditions. when leave it opens, this pin is pulled up by an internal
current source (10µA, typical) to enable operation. It’s not
Under-Voltage Protection (UVP) necessary to use an external transistor to save cost.
The APL5913 monitors the voltage on FB pin after soft- Power-OK and Delay
start process is finished. Therefore, the UVP is disable
during soft-start. When the voltage on FB pin falls below The APL5913 indicates the status of the output voltage by
the under-voltage threshold, the UVP circuit shuts off the monitoring the feedback voltage (VFB) on FB pin. As the
output immediately. After a while, the APL5913 starts a VFB rises and reaches the rising Power-OK threshold
new soft-start to regulate output. (VPOK), an internal delay function starts to perform a delay
time. At the end of the delay time, the IC turns off the
Thermal Shutdown internal NMOS of the POK to indicate the output is OK. As
A thermal shutdown circuit limits the junction temperature of the VFB falls and reaches the falling Power-OK threshold
APL5913. When the junction temperature exceeds +150°C, (VPNOK), the IC immediately turns on the NMOS of the POK
a thermal sensor turns off the output NMOS, allowing the to indicate the output is not OK without a delay time.
device to cool down. The regulator regulates the output again
through initiation of a new soft-start cycle after the junc-
tion temperature cools by 50°C, resulting in a pulsed
output during continuous thermal overload conditions.
The thermal shutdown is designed with a 50oC hyster-
esis to lower the average junction temperature during
continuous thermal overload conditions, extending life-
time of the device.

Application Information
Power Sequencing Output Capacitor
The power sequencing of VIN and VCNTL is not necessary to The APL5913 requires a proper output capacitor to
be concerned. However, do not apply a voltage to VOUT maintain stability and improve transient response over
for a long time when the main voltage applied at VIN is not temperature and current. The output capacitor selection
present. The reason is the internal parasitic diode from is to select proper ESR (equivalent series resistance)
VOUT to VIN conducts and dissipates power without pro- and capacitance of the output capacitor for good stability
tections due to the forward-voltage. and load transient response.

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Rev. A.7 - Apr., 2008
APL5913

Application Information (Cont.)

Output Capacitor (Cont.) and FB pins. It works with the internal error amplifier to
provide proper frequency response for the linear regulator.
The APL5913 is designed with a programmable feedback
The ESR is the equivalent series resistance of the output
compensation adjusted by an external feedback network
capacitor. The C OUT is ideal capacitance in the output
for the use of wide ranges of ESR and capacitance in all
capacitor. The VOUT is the setting of the output voltage.
applications. Ultra-low-ESR capacitors (such as ceramic
chip capacitors) and low-ESR bulk capacitors (such as
solid Tantalum, POSCap, and Aluminum electrolytic VOUT
VOUT
capacitors) can all be used as an output capacitor. The APL5913
value of the output capacitors can be increased without
limit. R1 ESR
C1
FB
During load transients, the output capacitors, depending V ERR
EAMP VFB C OUT
on the stepping amplitude and slew rate of load current,
VREF R2
are used to reduce the slew rate of the current seen by
the APL5913 and help the device to minimize the variations
of output voltage for good transient response. For the
Figure 1
applications with large stepping load current, the low-
ESR bulk capacitors are normally recommended. The feedback network selection depends on the values
of the ESR and COUT which has been classified into three
Decoupling ceramic capacitors must be placed at the load
conditions:
and ground pins as close as possible and the impedance
of the layout must be minimized. • Condition 1 : Large ESR ( ≥18mΩ )
- Select the R1 in the range of 400Ω ~ 2.4kΩ
Input Capacitor
- Calculate the R2 as the following :
The APL5913 requires proper input capacitors to supply 0.8(V)
R2(kΩ) = R1(kΩ) ⋅ .......... (1)
VOUT(V) - 0.8(V)
current surge during stepping load transients to prevent
the input rail from dropping. Because the parasitic in- - Calculate the C1 as the following :
ductor from the voltage sources or other bulk capacitors
VOUT(V) VOUT(V)
to the VIN pin limit the slew rate of the surge currents, 10 ⋅ ≤ C1(nF) ≤ 40 ⋅ ...... (2)
R1(kΩ ) R1(kΩ )
more parasitic inductance needs more input capacitance.
Ultra-low-ESR capacitors (such as ceramic chip • Condition 2 : Middle ESR
capacitors) and low-ESR bulk capacitors (such as solid - Calculate the R1 as the following:
tantalum, POSCap, and Aluminum electrolytic capacitors) 2157
R1(kΩ) = − 37.5 ⋅ VOUT(V) + 15 ......... (3)
can all be used as an input capacitor of VIN. For most of ESR(mΩ)
applications, the recommended input capacitance of VIN Select a proper R1(selected) to be a little larger than
is 10µF at least. If the drop of the input voltage is not the calculated R1.
cared, the input capacitance can be less than 10µF. More - Calculate the C1 as the following :
capacitance reduces the variations of the input voltage of COUT(µF)
C1(pF) = [0.71 ⋅ ESR(mΩ ) + 101] ⋅ ........ (4)
VIN pin. R1(kΩ)

Where R1=R1(selected)
Feedback Network Select a proper C1(selected) to be a little smaller
Figure 1 shows the feedback network among VOUT, GND, than the calculated C1.
- The C1 calculated from equation (4) must meet
the following equation:

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Rev. A.7 - Apr., 2008
APL5913

Application Information (Cont.)

Feedback Network (Cont.) PCB Layout Consideration (See Figure 2)

 143   37.5 ⋅ VOUT(V)  1. Please solder the Exposed Pad and VIN together on
C1(pF) ≥ 7.2 ⋅ 1 +  ⋅ 1 +  .. (5)
 ESR(m Ω)   R1(kΩ)  the PCB. The main current flow is through the ex
posed pad.
Where R1=R1(calculated) from equation (3)
2. Please place the input capacitors for VIN and VCNTL
If the C1(calculated) can not meet the equation (5), pins near pins as close as possible.
please use the Condition 3.
3. Ceramic decoupling capacitors for load must be
- Use equation (2) to calculate the R2. placed near the load as close as possible.
• Condition 3 : Low ESR (eg. Ceramic Capacitors) 4. To place APL5913 and output capacitors near the load
is good for performance.
- Calculate the R1 as the following:
5. The negative pins of the input and output capaci-tors
R1(kΩ) = (2.1⋅ ESR(mΩ) + 300) ⋅ COUT(µF) − 37.5 ⋅ VOUT(V) .. (6) and the GND pin of the APL5913 are connected to the
ground plane of the load.
Select a proper R1(selected) to be a little larger than
6. Please connect PIN 3 and 4 together by a wide track.
the calculated R1. The minimum selected R1 is
equal to 1kΩ when the calculated R1 is smaller 7. Large current paths must have wide tracks.
than 1k or negative. 8. See the Typical Application
- Calculate the C1 as the following : (See Figure 2)
 37.5 ⋅ VOUT(V) - Connect the one pin of the R2 to the GND of APL5913
C1(pF) = (0.24⋅ ESR(mΩ) + 34.2)⋅ COUT(µF) ⋅ 1+  .. (7)
 R1(kΩ) 
- Connect the one pin of R1 to the Pin 3 of APL5913
Where R1=R1(selected)
- Connect the one pin of C1 to the Pin 3 of APL5913
Select a proper C1(selected) to be a little smaller
than the calculated C1.
VCNTL
- The C1 calculated from equation (7) must meet
CCNTL
the following equation : CIN
VCNTL
 1.25 ⋅ VOUT (V) 
C1(pF) ≥ 0.033 +  ⋅ ESR(m Ω ) ⋅ COUT (µF) .(8) VIN VIN
 R1(kΩ ) 
APL5913
VOUT
Where R1=R1(calculated) from equation (6) VOUT
VOUT COUT
If the C1(calculated) can not meet the equation (8),
C1
please use the Condition 2. R1
FB
Load
- Use equation (2) to calculate the R2. GND
R2
The reason to have three conditions described above is
to optimize the load transient responses for all kinds of
the output capacitor. For stability only, the Condition 2, Figure 2
regardless of equation (5), is enough for all kinds of output
capacitor.

Copyright  ANPEC Electronics Corp. 14 www.anpec.com.tw


Rev. A.7 - Apr., 2008
APL5913

Application Information (Cont.)


Thermal Consideration
See Figure 3. The SOP-8P is a cost-effective package fea-
turing a small size like a standard SOP-8 and a bottom
exposed pad to minimize the thermal resistance of the
package, being applicable to high current applications.
The exposed pad must be soldered to the top VIN plane.
The copper of the VIN plane on the Top layer conducts heat
into the PCB and air. Please enlarge the area to reduce the
case-to-ambient resistance (θCA).

102 mil

1 8
2 7
118 mil SOP-8-P
SOP-8P
3 6
4 5

Top Exposed
VOUT Die Pad Top
plane VIN
plane
Ambient
Air
PCB

Figure 3
Recommended Minimum Footprint

0.024

8 7 6 5
0.072

0.138
0.212

0.118

1 2 3 4

0.050 Unit : Inch

Copyright  ANPEC Electronics Corp. 15 www.anpec.com.tw


Rev. A.7 - Apr., 2008
APL5913

Package Information

SOP-8P
D

SEE VIEW
A
D1

E1
E2

THERMAL
PAD E

°
h X 45

e b c

0.25
A2

GAUGE PLANE
SEATING PLANE
A1

L 0
VIEW A
S SOP-8P
Y
M MILLIMETERS INCHES
B
O
L MIN. MAX. MIN. MAX.
A 1.60 0.063

A1 0.00 0.15 0.000 0.006

A2 1.25 0.049
b 0.31 0.51 0.012 0.020
c 0.17 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
D1 2.25 3.50 0.098 0.138

E 5.80 6.20 0.228 0.244


E1 3.80 4.00 0.150 0.157
E2 2.00 3.00 0.079 0.118
e 1.27 BSC 0.050 BSC
h 0.25 0.50 0.010 0.020
L 0.40 1.27 0.016 0.050

0 0o 8o 0o 8o
Note : 1. Follow JEDEC MS-012 BA.
2. Dimension "D" does not include mold flash, protrusions
or gate burrs. Mold flash, protrusion or gate burrs shall not
exceed 6 mil per side .
3. Dimension "E" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.

Copyright  ANPEC Electronics Corp. 16 www.anpec.com.tw


Rev. A.7 - Apr., 2008
APL5913

Carrier Tape & Reel Dimensions

OD0 P0 P2 P1 A

E1
F

W
B0

K0 A0 OD1 B A
B

SECTION A-A

T
SECTION B-B

d
H
A

T1

Application A H T1 C d D W E1 F
330.0± 12.4+2.00 13.0+0.50
50 MIN. 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05
2.00 -0.00 -0.20
SOP-8(P) P0 P1 P2 D0 D1 T A0 B0 K0
1.5+0.10 0.6+0.00
4.0±0.10 8.0±0.10 2.0±0.05 1.5 MIN. 6.40±0.20 5.20±0.20 2.10±0.20
-0.00 -0.40
(mm)

Devices Per Unit


Package Type Unit Quantity
SOP- 8P Tape & Reel 2500

Copyright  ANPEC Electronics Corp. 17 www.anpec.com.tw


Rev. A.7 - Apr., 2008
APL5913

Reflow Condition (IR/Convection or VPR Reflow)

TP tp
Critical Zone
TL to TP
Ramp-up

TL
Temperature

tL
Tsmax

Tsmin
Ramp-down
ts
Preheat

t 25°C to Peak
25

Time
Reliability Test Program
Test item Method Description
SOLDERABILITY MIL-STD-883D-2003 245°C, 5 sec
HOLT MIL-STD-883D-1005.7 1000 Hrs Bias @125°C
PCT JESD-22-B, A102 168 Hrs, 100%RH, 121°C
TST MIL-STD-883D-1011.9 -65°C~150°C, 200 Cycles
ESD MIL-STD-883D-3015.7 VHBM > 2KV, VMM > 200V
Latch-Up JESD 78 10ms, 1tr > 100mA

Classification Reflow Profiles


Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Average ramp-up rate
3°C/second max. 3°C/second max.
(TL to TP)
Preheat
100°C 150°C
- Temperature Min (Tsmin)
150°C 200°C
- Temperature Max (Tsmax)
60-120 seconds 60-180 seconds
- Time (min to max) (ts)
Time maintained above:
183°C 217°C
- Temperature (TL)
60-150 seconds 60-150 seconds
- Time (tL)
Peak/Classification Temperature (Tp) See table 1 See table 2
Time within 5°C of actual
10-30 seconds 20-40 seconds
Peak Temperature (tp)
Ramp-down Rate 6°C/second max. 6°C/second max.
Time 25°C to Peak Temperature 6 minutes max. 8 minutes max.
Note: All temperatures refer to topside of the package. Measured on the body surface.

Copyright  ANPEC Electronics Corp. 18 www.anpec.com.tw


Rev. A.7 - Apr., 2008
APL5913

Classification Reflow Profiles (Cont.)

Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures


3 3
Package Thickness Volume mm Volume mm
<350 ≥350
<2.5 mm 240 +0/-5°C 225 +0/-5°C
≥2.5 mm 225 +0/-5°C 225 +0/-5°C

Table 2. Pb-free Process – Package Classification Reflow Temperatures


3 3 3
Package Thickness Volume mm Volume mm Volume mm
<350 350-2000 >2000
<1.6 mm 260 +0°C* 260 +0°C* 260 +0°C*
1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C*
≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C*
*Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the
stated classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C)
at the rated MSL level.

Customer Service

Anpec Electronics Corp.


Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan
Tel : 886-3-5642000
Fax : 886-3-5642050

Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838

Copyright  ANPEC Electronics Corp. 19 www.anpec.com.tw


Rev. A.7 - Apr., 2008