Lab 1 – CMOS Inverter

1. Introduction
In this lab, you will explore some of the DC and transient properties of a CMOS inverter. The
CMOS inverter is an extremely important circuit as it forms the basic building block of
complementary CMOS logic, which is used in the majority of digital designs today. Simulations
will be performed in LTSpice. The models for the NMOS and PMOS devices are given below.

.MODEL MN NMOS LEVEL=2 LD=0.15U TOX=200.0E-10

+ NSUB=5.36726E+15 VTO=0.7 KP=8.00059E-05 GAMMA=0.543
+ PHI=0.6 U0=655.881 UEXP=0.157282 UCRIT=31443.8
+ DELTA=2.39824 VMAX=55260.9 XJ=0.25U LAMBDA=0
+ NFS=1E+12 NEFF=1.001 NSS=1E+11 TPG=1.0 RSH=70.00
+ CGDO=4.3E-10 CGSO=4.3E-10 PB=0.58

.MODEL MP PMOS LEVEL=2 LD=0.15U TOX=200.0E-10

+ NSUB=4.3318E+15 VTO=-0.7 KP=2.70E-05 GAMMA=0.58
+ PHI=0.6 U0=261.977 UEXP=0.323932 UCRIT=65719.8
+ DELTA=1.79192 VMAX=25694 XJ=0.25U LAMBDA=0
+ NFS=1E+12 NEFF=1.001 NSS=1E+11 TPG=-1.0 RSH=120.6
+ CGDO=4.3E-10 CGSO=4.3E-10 PB=0.64

In this lab, use the following sizes for the devices:

NMOS L = 5 µm W = 124 µm
PMOS L = 5 µm W = 480 µm

Note that with these parameters, both behave as long-channel devices. The supply voltage VDD
is 5 V.
2. DC Characteristics of NMOS and PMOS

Figure 2.1: Load curves for the NMOS and PMOS transistors

(a) Generate the load curves for the NMOS and PMOS transistors, similar to what is shown in
Figure 1. Plot these curves for VGS and VSG going from 0V to 5V in ½ V increments. You can
do this in LTSpice by performing a DC sweep on VDS and selecting a secondary sweep on VGS.
Hint: easiest is to first get the setup for the NMOS and then figuring out how you can generate
the appropriate VSG and VSD for the PMOS such that both transistors are plotted correctly
together. Make a few copies of this plot as you will need them later on (better still, save them
electronically).
 Figure 2.2: Schematic circuit of NMOS

Figure 2.3: Graph of ID vs VDS with VGS from 0V to 5V

 Figure 2.4: Schematic circuit of PMOS

Figure 2.5: Graph of ID vs VSD with VSG from 0V to 5V

 Figure 2.6: Load curves for the NMOS and PMOS transistors

(b) A CMOS inverter can be built by appropriately connecting an NMOS and PMOS device
together. From your simulations of part 2a, you can find a set of (Vin, Vout) –pairs of the voltage-
transfer characteristic (VTC) of the inverter. Find all these pairs (they will be at ½ V increments
of Vin) and put them in a table. Also mark on the plot of part 2a where you found all these pairs.

Figure 2.6: Schematic of CMOC inverter

 Figure 2.7: Voltage Transfer Curve (VTC) of CMOS inverter

Table 2.1: A set of (Vin, Vout) –pairs of the voltage-transfer characteristic (VTC) of the inverter
Vin Vout
0V 5V
0.5V 4.99999V
1.0V 4.97609V
1.5V 4.85825V
2.0V 4.58952V
2.5V 3.51308V
3.0V 564.639mV
3.5V 199.917mV
4.0V 35.1583mV
4.5V 22.0072μV
5.0V -30.8103nV ≈ 0V
3. Switching Delay

Figure 2: Basic inverter setup

(a) Here, we will simulate the inverter with a capacitive load CL of 10 pF. This load,which we
define explicitly, could model the input capacitance of fanout gates,wire capacitance, pin
capacitance of a chip, etc. Remember that in addition to these, the gate also has some intrinsic
capacitances due to the NMOS and PMOS devices themselves.
(b) Apply a 100 ns pulse at the input, with Tin = 0.1 ns (see Figure 2).
(c) Plot the transient behavior and find tpHL and tpHL.

Figure 3.1: Schematic of inverter with 10pF capacitor load

 Figure 3.2: Transient analysis showing the delay of the input and output signal

tpHL = 103.305ns – 100.1ns

= 3.205ns
tpHL = 203.536ns – 200ns
= 3.536ns