Three types of specifying delays in continuous assignment are :

1)regular assignment delay

output out;
input i1,i2;
assign #10 out=i1^i2;

2)Imilicit continuous assignment delay : Both the definition and the

declaration of the delay
is done at once. So there is implicit continuous assignment.

wire #10 out=i1&i2;

3) Net declaration delay : delay is specified on the net at the time of
declaration
wire #10 out;
assign out=i1&i2;
-----------------
Inertial delay:
If the chnage in right hand side parameter takes place before the regular
assignment delay,
then the value of the input parameter at the time of recomputation will
be considered.
This is known as inertial delay.
An input pulse that is shorter than the delay of the assignment statement
does not propagate
-------------------
Anything that envloves equal to sign(=) needs to be written using assign
command.
--
during addition if any of the bits happened to be 'x' then the entire sum
is going to be 'x'
--
(?)modulus operator produces remainder and takes the sign of the first
operand
--
printing the result using $monitor, the output must change else there
will be no print
--
unary + and - operator have higher precedence over binary + or -
operator
--
unary + nad - are used to specify the sign of a number
--
negative numbers of the type integer and real should be
only used else they are considered as unsigned
--
if you have not declared a variable as signed , its not going to store
negative number as negative
but as 2's complement of the negative no.
for example
i=-4'd5
so i= 2's complement of(5=0101)=1011=11
i=-4'd15=2's complement of(15=1111)=0001=1(bit width=4)
--
Any number which is not 0 is treated as logical 1 for logical
operations to carry out
logicall operators :
||
&&
!
for example
!(-3)=0
which is equivalent to
!(1)=0
-
(-99)||0=1
since logically -99 is equaln to 1
--------------------
logical(||,&&,!), relational(>,<,>=,<=), equality(==,!=,===,!==), and
reduction(&,^,~^,~&,|,~|)
are all results in either 1 or 0
----------------
Bitwise operators except negation(~, which complements all bit),
iteratively perform operation between

-----
in case of relational operators if there are any bit as x or z in the bit
width of an operand then the
logical value of the comparison will be ambiguous(x).
ex:
A=4'b1010
B=4'b1011
C=4'b10xx
A>=B//gives 0
A<C//gives x
---------Equality operators(==,!=,===,!==)
unlike == and !=,case operators(equality,unequality) takes into
consideration xand z values also
Ex :A=4'b1xxx,B=4'b1xxz,C=4'b1xxx
A==B//results x
A!=C//results x
A===B//results 0
A===C//results 1
-------------------------
-----
Bitwise operators : they perform operations on two operands(exeption
negation which complements every bit)
with bits in the same significant position in the two operands.
for example :
MSB of the first operand will be anded/xored/xnored/ored with the MSB of
the second operand
ans similarly for every significant bit positions in both the operands.
In case bit size of the operand are different then left padding with
zeros is done to the operand
with less bit width.
Exception :~, which operates on a singl operand
-----------------------------------
Reduction operands:acts on a single operand and reduces it to a single
logical value.
the compiutation is done iteratively starting from right to left and
evaluating
the intermediate result with the next less significant bit.
------------------------------------
Shift operators :
arithmatic shift operators(<<<,>>>)
<<< and<< ares same
but >>> and >> differs since >>> copies the msb to the leftvaccant
position upon right shift
while >> copies 0 to vaccant positions.
regualar shift operators(>>,<<)
-----------
module top;
reg signed [7:0] in;
wire signed [7:0] out,out1;
shift s0(out,out1,in);
initial
$monitor(out,"\t",out1);
initial
begin
in=-8'd5;
#5
in=8'd35;
#5 $finish;
end
endmodule

module shift(out,out1,in);
output signed [7:0] out,out1;
input signed [7:0] in;
assign out=in>>>2;
assign out1=in<<<5;
endmodule
------------
-2 96
8 96

--------------
Concatenation operand
-operands must be sized
-no restriction on the operand can nbe scalar/vector/part selct,
net/register or sized constants
sized constants : 3'b101
a={b,c,d};
b has higher significant bit compared to bit in c nad d;
the total bit in a is equal to the sum of the bit widths of b,c and d;
replication is an extension to conacatenation
with each type to be repeated is enclosed within curly braces and the
number of times it is going to repeat depends
on the repetition factor present at the left hand side of it.
example
a=2'b10
b={4{i'b1},3a}
so
b=10'b1111101010
--------------------------
conditional operator(ternary in c)
conditional expressio?true expression:false expression
if condition is true then true expression is evaluated else false
expression
is evaluated.if the conditional exp.is evaluated as ambiguous(x) then,
both expression are evaluated,and compared bit by bit.
if bit are same at same bit positions, the bit(matched bit) is returned
as it is
else an 'x' is returned if bits are different
ex:
a=1==x?4'b1010:4'b1000;//a=4'b10xx;
this expression is similar to functionality of 2:1 mux in which condition
is the select line and
true exp. is the i1 and false is i0
-nesting of conditional expression is posiible in which instead of true
exp, a new conditional exp.
is written. the level of nesting can go up to whatever depth required.

----------------
Declaring multiple assign statements at once
assign a=k,b=k1,c=k2;
----------------
in two initial block at the same time try to assign different value to
the
same variable then the second initial(in sequence) block operation will
be discarded.
----
module top;
reg [2:0] i1,i2;
wire [5:0] out;
con c0(out,i1,i2);
initial
$monitor($time,"\t","out=%b",out);
initial
begin
i1=3'b101;
i2=3'b100;
#2 i1<= #5 i2;
i2<= #8 i1;
#1 i2=3'b111;
#15 i1=3'b000;
#20 $finish;
end
initial
begin
#4 i2=3'b110;
end
endmodule
module con(out,i1,i2);
output [5:0] out;
input [2:0] i1,i2;
assign out={i1,i2};
endmodule
----------
0 out=101100
3 out=101111
4 out=101110
7 out=100110
10 out=100101
18 out=000101
---------------------------------------
module top;
reg [2:0] i1,i2;
wire [5:0] out;
con c0(out,i1,i2);
initial
$monitor($time,"\t","out=%b",out);
initial
begin
i1=3'b101;
i2=3'b100;
#2 i1<= #5 i2;
i2<= #8 i1;
#1 i2=3'b111;
#15 i1=3'b000;
#20 $finish;
end
initial
begin
#3 i2=3'b110;
end
endmodule
module con(out,i1,i2);
output [5:0] out;
input [2:0] i1,i2;
assign out={i1,i2};
endmodule
------------------------------------
0 out=101100
3 out=101111
7 out=100111
10 out=100101
18 out=000101
------------------------------------
Swapping values with non blocking statements
always @(posedge clk)
a<= b;
always @(posedge clk)
b<= a;
swapping can only be achieved wit the help of non blocking operator
------------------------------------
In the above implementation if blocking operators are replaced by
blocking operator
one of them will be executed before the other and this will lead to both
numbers with
the same value. So no parallel execution in this scenario.
--
module top;
reg [2:0] i1=3'b110;
reg [2:0] i2=3'b100;
reg clk=1'b0;
wire [5:0] out;
con c0(out,i1,i2,clk);
initial
begin
$monitor($time,"\t","out=%b",out);
#40 $finish;
end
always
#5 clk=~clk;
always @(posedge clk)
i2=i1;
always @(posedge clk)
i1=i2;
/*always @(posedge clk)
i2=i1;*/
endmodule
module con(out,i1,i2,clk);
output [5:0] out;
input [2:0] i1,i2;
input clk;
assign out={i1,i2};
endmodule
-----------------------------------
0 out=110100
5 out=100100
------------------------------------
In the above program , there is a race around condition between the two
events.
--------------------------------------------------------
Non blocking statements are broken down to three operation :
1) reading of the values from the left hand side
2) writing the read values into a temporary variables
3) and then storing the values from the temporary variables into the left
hand side register
Non blocking assignments require more memory due to use of temp
variables.
------------------------
In case of continuous assignment :
-rhs can be net or reg
-lhs is net
In case of procedural assignment :
-lhs can be any reg type(time,reg,integer,real, integer,memeory)
-rhs can be nay constant, oart select, or naythinhg that returns a value
----------------------------
-----Zero delay control example-------------
module try(out,in,ini);
output out;
input in,ini;
assign out=in&&ini;
endmodule
module top;
reg in,ini;
wire out;
try t0(out,in,ini);
initial
begin
$monitor($time,"\t",out);
in=1'b0;
ini=1'b0;
end
initial
begin
#0 in=1'b1;//this delay ensures delay in its execution.
ini=1'b1;
end
endmodule
-----------------------------------------
0 1
-----------------------------------------
In case of named event control
if certain condition is met, then the the named event is triggered and @
feels the change happend and the always block corresponding to that
gets executed. It can also be achieved by using a flag signal instead of
event.
--
module try(out,in,in2,clk);
output reg [1:0] out=2'b00;
input in,in2,clk;
event just;
always @(posedge clk)
->just;
always @(just)
out={in,in2};

endmodule
module top;
reg in=1'b0;
reg in2=1'b1;
reg clk=1'b0;
wire [1:0] out;
try t0(out,in,in2,clk);
initial
begin
$monitor($time,"\t",out);
#90 $finish;
end

always
#5 clk=~clk;
always @(negedge clk)
begin
in<=in2;
in2<=in;
end
endmodule
------------------------------------------
0 0
5 1
15 2
25 1
35 2
45 1
55 2
65 1
75 2
85 1
-------------------------------------------
Note : whenever using a always block in the design block
and trying to assign something using blocking statement to the output
declare the output as register
-----------------------------------------------------------
Example:
module mux(out,i0,i1,i2,i3,s0,s1);
output reg out;
input i0,i1,i2,i3,s0,s1;
//output out;
always @(s0,s1,i0,i1,i2,i3)
begin
case({s1,s0})
2'd0: begin
$display("First port to go");
out=i0;
end
2'd1: begin
$display("second port to go");
out=i1;
end
2'd2: begin
$display("third port to go");
out=i2;
end
2'd3: begin
$display("Fourth port to go");
out=i3;
end
default:$display("Invalid control signals\n");
endcase
end
endmodule
module top;
reg s0,s1,i0,i1,i2,i3;
wire out;
mux m0(out,i0,i1,i2,i3,s0,s1);
initial begin
$monitor($time,"\t",out);
i0=1'b0;
i1=1'b1;
i2=1'b0;
i3=1'b1;
s0=1'b0;
s1=1'b0;
#5
s0=1'b1;
s1=1'b0;
#5
s0=1'b0;
s1=1'b1;
#5
s0=1'b1;
s1=1'b1;
#10 $finish;
end
endmodule
----------------------------------------
First port to go
0 0
second port to go
5 1
third port to go
10 0
Fourth port to go
15 1
-----------------------------------------
Implementing the same with if else
-----------------------------------------
module mux(out,i0,i1,i2,i3,s0,s1);
output reg out;
input i0,i1,i2,i3,s0,s1;
//output out;
always @(s0,s1,i0,i1,i2,i3)
begin
if({s1,s0}==2'd0)
out=i0;
else if({s1,s0}==2'd1)
out=i1;
else if({s1,s0}==2'd2)
out=i2;
else if({s1,s0}==2'd3)
out=i3;
else $display("Invalid input");
end
endmodule
module top;
reg s0,s1,i0,i1,i2,i3;
wire out;
mux m0(out,i0,i1,i2,i3,s0,s1);
initial begin
$monitor($time,"\t",out);
i0=1'b0;
i1=1'b1;
i2=1'b0;
i3=1'b1;
s0=1'b0;
s1=1'b0;
#5
s0=1'b1;
s1=1'b0;
#5
s0=1'b0;
s1=1'b1;
#5
s0=1'b1;
s1=1'b1;
#5
s0=1'bx;
#10 $finish;
end
endmodule
----------------------------------
$iverilog -o main *.v
$vvp main
0 0
5 1
10 0
15 1
Invalid input
-----------------------------
For multiple condition if the same objective has to be achieved then the
nultiple condition ahas to be separted by commas
example
case({s1,s0})
2'd0,2'd1: begin
$display("first input has higher priority over second");
end
--------------------
---case can even be used to execute task meant for bit stream with the
combination of 1,0,x,z
--- THE TWO VARINTS OF CASE STSTEMENT----
casex:
treats all 'x' and 'z 'values in the case alternative as don't cares
casez:
treats all 'z' values in the case alternatives as don't cares . the z can
also be represented by ?
in the case alternative
-----------------------------------------
looping in verilog :
for, while, repeat, forever
all looping statements can only occur inside always or initial block;
--In verilog for more than one statement, begin and end are used.
--while loop example
module loo();

integer i=0;
initial

begin

while(i < 7)

begin

$display("the value of counter is %d",i);

i=i+1;

end

end

endmodule
---------------------
$iverilog -o main *.v
$vvp main
the value of counter is 0
the value of counter is 1
the value of counter is 2
the value of counter is 3
the value of counter is 4
the value of counter is 5
the value of counter is 6
-----------------------------
while loop is mofre general purpose as for loop cannot be used some place
while /while loop can.
for /for loop all the three segment in the definition :
/*initialisation
termination condition
procedure assignment for iteration
*/
need to be present as it woul may throw error

---------------------------------------------
module loo();
integer i=0;
initial
begin
repeat(10)
begin
$display("the value of counter is %d",i);
i=i+1;
end
$display("the value of counter is %d",i);
end
endmodule
--------------------------------------------
$iverilog -o main *.v
$vvp main
the value of counter is 0
the value of counter is 1
the value of counter is 2
the value of counter is 3
the value of counter is 4
the value of counter is 5
the value of counter is 6
the value of counter is 7
the value of counter is 8
the value of counter is 9
the value of counter is 10
--------------------------------------------
module try(out,in,in2);
//'define just [2:0];
output [2:0] out;
//output reg [2:0] out;
input in,in2;
assign out={in,in2,in};
/*always @(in,in2)
out={in,in2,in};*/
endmodule

module top;
reg in,in2;
wire [2:0] out;
try t0(out,in,in2);
initial
begin
$monitor($time,"\t",out);
in=1'b0;
in2=1'b1;
#5
in=1'b1;
in2=1'b0;
#5
in=1'b1;
in2=1'b1;
#10 $finish;
end
endmodule
-----------------------
$iverilog -o main *.v
$vvp main
0 2
5 5
10 7
-----------------------------
forever is usually used in conjuction with timing control constructs.
if timing control constructs are not used the loop will run until the
finish task does its job of
stopping the simulation.
example
forever @(posedge clk)
x=y;
-----------------------------
A forever loop can be exited with the help of disable statement.
-----------------------------
sequential block: the statements enclosed between begin and end are the
sequential block.
-----------------------------
paralle blocks :
using fork and join;
1. the only difference between fork-join and non blocking statements is
that in case of
non blocking, the rhs are evaluated at zero simulation time and are
stored at temporary variables and are awaited to be assigned
to the lhs based on the intra assignment delay; the value of the
variables involved in the rhs
expression is taken from their value at zero simulation time.
while in case of fork- join, the evaluation/parallelism of all the
statements take place based on
the sole regular assignment delay. the statement is not touched until
their delay satisfies the simulation time
the time at which each statement has to be executed depends on the time
before them.

--regular assignment delay

assign #10 out =i&j;
here the change in i or j must persist for at least 10 time units, then
only chnage will be seen at the output
else will be nullified.
comnsider a situation
at time 0;
i=1,j=1
at time=4
i=0 for 5 time units
so at time=9
i=1
and at time t=11
j=0 for 10 time units
so out=1 for time 1-21
at time =21, out =21
------------------------
module regular(out,a,b);
output out;
input a,b;
assign #10 out=a&b;
endmodule

module top;
reg a=1'b1,b=1'b1;
wire out;
regular r0(out,a,b);
initial
begin
$monitor($time,"\t",out);
#14 a=1'b0;
#5 a=1'b1;
#2 b=1'b0;
#10 b=1'b1;
end
endmodule
-------------------------
0 x

10 1

31 0

41 1
-------------------------
module try(out,a,b,c);
output[3:0] out;
input a,b,c;
assign out = {a,b,a,c};
endmodule
module top;
reg a=1'b0;
reg b=1'b0;
reg c=1'b1;
wire [3:0] out;
try t0(out,a,b,c);
initial
$monitor($time,"\t",out);
initial
fork
a<=#1 c;
b<=#2 a;
c<=#5 a;
join
endmodule
-----------------
0 1
1 11
5 10
-----------------
module try(out,a,b,c);
output[3:0] out;
input a,b,c;
assign out = {a,b,a,c};
endmodule
module top;
reg a=1'b0;
reg b=1'b0;
reg c=1'b1;
wire [3:0] out;
try t0(out,a,b,c);
initial
$monitor($time,"\t",out);
initial
begin
a=#1 c;
b=#2 a;
c=#5 a;
end
endmodule
-----------------
0 1
1 11
3 15
here intra assignment delay is same as regular delay control. infact we
can never implement
intra assignmnet delay control using blockinf=g statement.the example
below makes more clear

---------------------------
module try(out,a,b,c);
output[3:0] out;
input a,b,c;
assign out = {a,b,a,c};
endmodule
module top;
reg a=1'b0;
reg b=1'b0;
reg c=1'b1;
wire [3:0] out;
try t0(out,a,b,c);
initial
$monitor($time,"\t",out);
initial
begin
a=#1 c;
b=#2 a;
c=#5 1'b0;
end
endmodule
----------------------------
$iverilog -o main *.v
$vvp main
0 1
1 11
3 15
8 14

---------------------------
module try(out,a,b,c);
output[3:0] out;
input a,b,c;
assign out = {a,b,a,c};
endmodule
module top;
reg a=1'b0;
reg b=1'b0;
reg c=1'b1;
wire [3:0] out;
try t0(out,a,b,c);
initial
$monitor($time,"\t",out);
initial
begin
a<=#1 c;
b<=#2 a;
c<=#5 a;
end
endmodule
-----------------------
0 1
1 11
5 10
---------------------------
module try(out,a,b,c);
output[3:0] out;
input a,b,c;
assign out = {a,b,a,c};
endmodule
module top;
reg a=1'b0;
reg b=1'b0;
reg c=1'b1;
wire [3:0] out;
try t0(out,a,b,c);
initial
$monitor($time,"\t",out);
initial
fork
a=#1 c;
b=#2 a;
c=#5 a;
join
endmodule-
--------------------

0 1
1 11
5 10
- for blocking statement5
-here with the help of
--------------------------
limitations of fork-join is race condition(multiple statement execution
without any delay involved)
----------------------------

the different initialisation

reg a=1'b0,b=1'b0,c=1'b1;
the above initialisation happens before the actual simulation has begin
so all the values will start form these values
.
so when the simulatiipon begin at o time
a ,b and c will have the initialised value and would impact output
depending on thsese
values.
----
module try(out,a,b,c);
output[3:0] out;
input a,b,c;
assign out = {a,b,a,c};
endmodule
module top;
reg a=1'b0,b=1'b0,c=1'b1;
wire [3:0] out;
try t0(out,a,b,c);
initial
$monitor($time,"\t",out);
initial
fork
a=#1c;
b=#2 a;
c=#5 1'b0;
join
endmodule
---
0 1

1 11

5 10
-----------------
delay can only exist at two places in procedural assignment
i) a=#5 c;
ii) #5a=c;
The below assignment would throw error
a #5=c.
this is only happens in case of continuous assignment and primitive gate
example :
assign out #5 =i&j;//line1
and #5 n0(out,i,j);//line 2
line and line 2 both implementation wise same

----------------
in casee of regular assignment delay(dataflow), the initialisation even
leads to no effect in the output.
as the initialisation must last till the delay.
---------Example1---------
module try(out,i,j);
output out;
input i,j;
assign #10 out =i&j;
endmodule
module top;
reg i=1'b1,j=1'b1;
wire out;
try t0(out,i,j);
initial
begin
$monitor($time,"\t",out);
#1
i=1'b0;
end
endmodule
--------------
0 x
11 0
--------------
however with the change in delay in initial block from 1 to 10 causes
the following result.
0 x

10 1

--------------
begin-end and fork-join can be nested
20 0
----------------------------Four varinats-------------
------I----------
assign out = {a,b,a,c};
reg a=1'b0;

reg b=1'b0;

reg c=1'b1;

initial
$monitor($time,"\t",out);
initial
fork
#1 a=c;
#2 b=a;
#5 c=a;
join
-----II---------------
assign out = {a,b,a,c};
reg a=1'b0;

reg b=1'b0;
reg c=1'b1;
initial
$monitor($time,"\t",out);
initial
fork
a=#1c;
b=#2a;
c=#5a;
join
------III----------
assign out = {a,b,a,c};
reg a=1'b0;

reg b=1'b0;

reg c=1'b1;

initial
$monitor($time,"\t",out);
initial
begin
#1 a=c;
#2 b=a;
#5 c=a;
end
-----IV---------------
assign out = {a,b,a,c};
reg a=1'b0;

reg b=1'b0;

reg c=1'b1;

initial
$monitor($time,"\t",out);
initial
begin
a=#1c;
b=#2a;
c=#5a;
end
========================
=====Ecpected Output====
I-----------------------
0 1
1 11
2 15
explanation
for paralles the delay but rest assignment are sequential
II----------------------
0 1
1 11
5 10
in this case no difference in = and<= sign
= acting as <=
III---------------------
0 1
1 11
3 15
IV----------------------
0 1
1 11
3 15

sushmitha.l@graphsemi.com