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Compal Confidential
2 2

PEW71_81_91 UMA <LA-6582P> M/B Schematics Document


Intel Arrandale Processor with DDRIII + Ibex Peak-M

2010-07-08 3

REV:1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW71 M/B LA-6582P Schematic
Date: Thursday, July 08, 2010 Sheet 1 of 48
A B C D E
A B C D E

Compal Confidential
Model Name PEW71_81_91 UMA
File Name : LA-6582P
1 1

ZZZ1 ZZZ2

46@
Fan Control Intel Memory BUS(DDRIII)
M/B PCB HDMI+HDCP LOGO page 26
Dual Channel 204pin DDRIII-SO-DIMM X2
DAZ0FO00400 RO0000003HM Arrandale (UMA) BANK 0, 1, 2, 3 page 10,11
1.5V DDRIII 800/1066/1333
Processor 6.4G/8.5G/10.6G
100M/133M/166M(CFD)
rPGA988A

page 4,5,6,7,8,9 USB conn x3


USB port 0 (Left Low) Bluetooth CMOS Mini card Card
(UMA) DMI x4 USB Port 1 (Left High)
FDI x8 100MHz USB port 2 (sub board)
Conn Camera USB port 12 Reader
100MHz 1GB/s x4
USB port 11 USB port 8 USB port 9
page 29 page 29 page 22 page 26 page 29
2.7GT/s
2 USBx14 3.3V 48MHz 2
LVDS Conn. LVDS(UMA)
page 22
CRT(UMA)
Intel 3.3V 24MHz
CRT Conn. HD Audio
page 23 Ibex Peak-M
HDMI Conn. Level Shift HDMI(UMA) SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S) 100MHz
page 24 page 24 PCI-Express x 8 (ABD PCIE1 2.5GT/S CKD PCIE1/2 2.5/5GT/S) 100MHz PCH HDA Codec
page 13,14,15,16,17
18,19,20,21 ALC272X
port 2,4 port 1 SPI page 33

MINI Card x1 GIGA LAN port 0 port 1


WLAN BCM57780 page 27 SPI ROM SATA HDD SATA ODD Audio AMP
page 26 Conn. Conn.
page 13 page 25 page 25
TPA6017
page 34
RJ45 Conn.
page 28
3 LPC BUS 3

33MHz Int. Speaker


page 34

RTC CKT. LS-6581P USB/B ENE KB926


page 30

Power ON/Off CKT. LS-6582P PWR/B


Touch Pad Int.KBD Clock Generator
page 31 page 31 IDT: 9LRS3199AKLFT
DC/DC Interface CKT. LS-6583P ODD/B SILEGO: SLG8SP587
133/120/100/96/14.318MHZ to PCH
BIOS ROM 48MHZ to CardReader
Power Circuit DC/DC CKT. page 31 page 12

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW71 M/B LA-6582P Schematic
Date: Thursday, July 08, 2010 Sheet 2 of 48
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A B C D E

SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
Power Plane Description S1 S3 S5
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) N/A N/A N/A
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1 1
+CPU_CORE Core voltage for CPU ON ON OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+0.75VS 0.75V switched power rail for DDR terminator ON OFF OFF
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.05VS 1.05V switched power rail for PCH ON OFF OFF
+1.05VS_VTT 1.05V switched power rail (1.05 for AUB CPU) ON OFF OFF
Project ID / Board ID Table for EC-AD channel
+1.5V 1.5V power rail for DDRIII ON ON OFF
Vcc 3.3V +/- 5%
+1.5VS 1.5V switched power rail ON OFF OFF
+1.8VS 1.8V switched power rail ON OFF OFF
Ra/Rc 100K +/- 5%
Rb / Rd V AD_BID min VAD_BID typ V AD_BID max Board ID Project ID
+3VALW 3.3V always on power rail ON ON ON*
0 0 0 V 0 V 0 V 0.1 Original NEW70/80/90/50/71/91
+3V_LAN 3.3V power rail for LAN ON ON ON*
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V 0.2 PEW71/81/91 Audio Mono/Crystal
+3VS 3.3V switched power rail ON OFF OFF
2 18K +/- 5% 0.436 V 0.503 V 0.538 V 0.3
+5VALW 5V always on power rail ON ON ON*
+5VS 5V switched power rail ON OFF OFF
3 33K +/- 5% 0.712 V 0.819 V 0.875 V 1.0
4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+VSB VSB always on power rail ON ON ON*
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+RTCVCC RTC power ON ON ON
6 200K +/- 5% 1.935 V 2.200 V 2.341 V PEW71/81/91 Audio Mono/SUSCLK
7 NC 2.500 V 3.300 V 3.300 V NEW71/91 Optumis
2 2

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
BTO Option Table
BTO Item BOM Structure
External PCI Devices HDMI HDMI@
Device IDSEL# REQ#/GNT# Interrupts

EC SM Bus1 address EC SM Bus2 address


Device Address Device Address
Smart Battery 0001 011X b

Ibex SM Bus address USB Port Table


3
Device Address 3
Clock Generator
4 External 3 External
(9LRS3199AKLFT, SLG8SP587)
1101 0010b USB 2.0 USB 1.1 Port USB Port USB Port
DDR DIMM0 1001 000Xb 0 Ext1 Left Low USB Ext1 Left Low USB
DDR DIMM2
UHCI0
1001 010Xb 1 Ext2 Left High USB Ext2 Left High USB
2 Ext3 Right USB Ext3 Right USB
UHCI1
3
EHCI1
4
UHCI2
5
6
UHCI3
7
8 Camera Camera
UHCI4
9 Card Reader Card Reader
10
EHCI2 UHCI5
11 Blue Tooth Blue Tooth
4 4
12 1st Min-Card 1st Min-Card
UHCI6
13

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW71 M/B LA-6582P Schematic
Date: Thursday, July 08, 2010 Sheet 3 of 48

A B C D E
5 4 3 2 1

JCPU1E

JCPU1A AJ13
PEG_IRCOMP RSVD32
PEG_ICOMPI B26 1 2 RSVD33 AJ12
A26 R1 49.9_0402_1%
DMI_PTX_HRX_N0 PEG_ICOMPO
A24 DMI_RX#[0] PEG_RCOMPO B27 AP25 RSVD1
DMI_PTX_HRX_N1 C23 A25 EXP_RBIAS 1 2 AL25 AH25
DMI_PTX_HRX_N2 DMI_RX#[1] PEG_RBIAS R3 750_0402_1% RSVD2 RSVD34
B22 DMI_RX#[2] AL24 RSVD3 RSVD35 AK26
DMI_PTX_HRX_N3 A21 K35 AL22
DMI_RX#[3] PEG_RX#[0] RSVD4
PEG_RX#[1] J34 AJ33 RSVD5 RSVD36 AL26
DMI_PTX_HRX_P0 B24 J33 AG9 AR2
DMI_PTX_HRX_P1 DMI_RX[0] PEG_RX#[2] RSVD6 RSVD_NCTF_37
D23 DMI_RX[1] PEG_RX#[3] G35 M27 RSVD7

DMI
DMI_PTX_HRX_P2 B23 G32 L28 AJ26
DMI_PTX_HRX_P3 DMI_RX[2] PEG_RX#[4] RSVD8 RSVD38
D A22 DMI_RX[3] PEG_RX#[5] F34 J17 SA_DIMM_VREF (CFD Only) RSVD39 AJ27 D
PEG_RX#[6] F31 H17 SB_DIMM_VREF (CFD Only)
DMI_HTX_PRX_N0 D24 D35 G25
DMI_HTX_PRX_N1 DMI_TX#[0] PEG_RX#[7] RSVD11
G24 DMI_TX#[1] PEG_RX#[8] E33 G17 RSVD12
DMI_HTX_PRX_N2 F23 C33 E31 AP1
DMI_HTX_PRX_N3 DMI_TX#[2] PEG_RX#[9] RSVD13 RSVD_NCTF_40
H23 DMI_TX#[3] PEG_RX#[10] D32 E30 RSVD14 RSVD_NCTF_41 AT2
PEG_RX#[11] B32
DMI_HTX_PRX_P0 D25 C31 AT3
DMI_HTX_PRX_P1 DMI_TX[0] PEG_RX#[12] RSVD_NCTF_42
F24 DMI_TX[1] PEG_RX#[13] B28 RSVD_NCTF_43 AR1
DMI_HTX_PRX_P2 E23 B30
DMI_HTX_PRX_P3 DMI_TX[2] PEG_RX#[14]
G23 DMI_TX[3] PEG_RX#[15] A31

J35 R5 AL28
PEG_RX[0] 3.01K_0402_1% RSVD45
PEG_RX[1] H34 1 @ 2 CFG0 AM30 CFG[0] RSVD46 AL29
PEG_RX[2] H33 AM28 CFG[1] RSVD47 AP30
H_FDI_TXN0 E22 F35 R6 AP31 AP32
H_FDI_TXN1 FDI_TX#[0] PEG_RX[3] 3.01K_0402_1% CFG[2] RSVD48
D21 FDI_TX#[1] PEG_RX[4] G33 1 @ 2 CFG3 AL32 CFG[3] RSVD49 AL27
H_FDI_TXN2 D19 E34 R7 1 @ 2 CFG4 AL30 AT31
H_FDI_TXN3 FDI_TX#[2] PEG_RX[5] 3.01K_0402_1% CFG[4] RSVD50
D18 FDI_TX#[3] PEG_RX[6] F32 AM31 CFG[5] RSVD51 AT32
H_FDI_TXN4 G21 D34 AN29 AP33
H_FDI_TXN5 FDI_TX#[4] PEG_RX[7] R8 CFG[6] RSVD52
1 @ CFG7
H_FDI_TXN6
E19
F21
FDI_TX#[5]
FDI_TX#[6]
PCI EXPRESS -- GRAPHICS PEG_RX[8]
PEG_RX[9]
F33
B33 3.01K_0402_1%
2 AM32
AK32
CFG[7]
CFG[8]
RSVD53
RSVD_NCTF_54
AR33
AT33
Intel(R) FDI

H_FDI_TXN7 G18 D31 AK31 AT34

RESERVED
FDI_TX#[7] PEG_RX[10] CFG[9] RSVD_NCTF_55
PEG_RX[11] A32 AK28 CFG[10] RSVD_NCTF_56 AP35
PEG_RX[12] C30 WW41 Recommend not pull down AJ28 CFG[11] RSVD_NCTF_57 AR35
H_FDI_TXP0 D22 A28 AN30 AR32
H_FDI_TXP1 FDI_TX[0] PEG_RX[13] PCIE2.0 Jitter is over on ES1 CFG[12] RSVD58
C21 FDI_TX[1] PEG_RX[14] B29 AN32 CFG[13]
H_FDI_TXP2 D20 A30 AJ32
H_FDI_TXP3 FDI_TX[2] PEG_RX[15] CFG[14]
C18 FDI_TX[3] AJ29 CFG[15] RSVD_TP_59 E15
C H_FDI_TXP4 G22 L33 AJ30 F15 C
H_FDI_TXP5 FDI_TX[4] PEG_TX#[0] CFG[16] RSVD_TP_60
E20 FDI_TX[5] PEG_TX#[1] M35 AK30 CFG[17] KEY A2
H_FDI_TXP6 F20 M33 H16 D15 R9
H_FDI_TXP7 FDI_TX[6] PEG_TX#[2] RSVD_TP_86 RSVD62 0_0402_5%
G19 FDI_TX[7] PEG_TX#[3] M30 RSVD63 C15
L31 AJ15 RSVD64_R 2 @ 1
PEG_TX#[4] RSVD64 RSVD65_R 2 @
<15> H_FDI_FSYNC0 F17 FDI_FSYNC[0] PEG_TX#[5] K32 RSVD65 AH15 1
E17 M29 R10
<15> H_FDI_FSYNC1 FDI_FSYNC[1] PEG_TX#[6]
J31 B19 0_0402_5%
PEG_TX#[7] R11 RSVD15
<15> H_FDI_INT C17 FDI_INT PEG_TX#[8] K29 A19 RSVD16
H30 0_0402_5%
PEG_TX#[9] @ H_RSVD17_R
<15> H_FDI_LSYNC0 F18 FDI_LSYNC[0] PEG_TX#[10] H29 1 2 A20 RSVD17
D17 F29 1 @ 2 H_RSVD18_R B20
<15> H_FDI_LSYNC1 FDI_LSYNC[1] PEG_TX#[11] RSVD18
PEG_TX#[12] E28 RSVD_TP_66 AA5
D29 R12 U9 AA4
PEG_TX#[13] 0_0402_5% RSVD19 RSVD_TP_67
PEG_TX#[14] D27 T9 RSVD20 RSVD_TP_68 R8
PEG_TX#[15] C26 RSVD_TP_69 AD3
AC9 RSVD21 RSVD_TP_70 AD2
PEG_TX[0] L34 AB9 RSVD22 RSVD_TP_71 AA2
PEG_TX[1] M34 RSVD_TP_72 AA1
PEG_TX[2] M32 DMI_PTX_HRX_N[0..3] <15> RSVD_TP_73 R9
PEG_TX[3] L30 DMI_PTX_HRX_P[0..3] <15> RSVD_TP_74 AG7
PEG_TX[4] M31 C1 RSVD_NCTF_23 RSVD_TP_75 AE3
PEG_TX[5] K31 DMI_HTX_PRX_N[0..3] <15> A3 RSVD_NCTF_24
PEG_TX[6] M28 DMI_HTX_PRX_P[0..3] <15>
PEG_TX[7] H31 RSVD_TP_76 V4
PEG_TX[8] K28 H_FDI_TXN[0..7] <15> RSVD_TP_77 V5
PEG_TX[9] G30 H_FDI_TXP[0..7] <15> RSVD_TP_78 N2
PEG_TX[10] G29 J29 RSVD26 RSVD_TP_79 AD5
PEG_TX[11] F28 J28 RSVD27 RSVD_TP_80 AD7
B B
PEG_TX[12] E27 RSVD_TP_81 W3
PEG_TX[13] D28 A34 RSVD_NCTF_28 RSVD_TP_82 W2
PEG_TX[14] C27 A33 RSVD_NCTF_29 RSVD_TP_83 N3
PEG_TX[15] C25 RSVD_TP_84 AE5
C35 RSVD_NCTF_30 RSVD_TP_85 AD9
B35 RSVD_NCTF_31
IC,AUB_CFD_rPGA,R1P0 AP34
CONN@ VSS

IC,AUB_CFD_rPGA,R1P0
CONN@

eDP Signals Mapping CFG0 - PCI-Express Configuration Select CFG4 - Display Port Presence

eDP Singal PEG Singals Lane Reversal *1:Single PEG *1:Disabled; No Physical Display Port
eDP_TX0 PEG_HTX_C_GRX_P15 PEG_HTX_C_GRX_P0 0:Bifurcation enabled attached to Embedded Display Port
0:Enabled; An external Display Port
eDP_TX#0 PEG_HTX_C_GRX_N15 PEG_HTX_C_GRX_N0 device is connected to the Embedded
eDP_TX1 PEG_HTX_C_GRX_P14 PEG_HTX_C_GRX_P1 CFG3 - PCI-Express Static Lane Reversal
Display Port

eDP_TX#1 PEG_HTX_C_GRX_N14 PEG_HTX_C_GRX_N1 *:Default


A eDP_TX2 PEG_HTX_C_GRX_P13 PEG_HTX_C_GRX_P2 *1 :Normal Operation A
0 :Lane Numbers Reversed
eDP_TX#2 PEG_HTX_C_GRX_N13 PEG_HTX_C_GRX_N2 15 -> 0, 14 -> 1, ...
eDP_TX3 PEG_HTX_C_GRX_P12 PEG_HTX_C_GRX_P3
eDP_TX#3 PEG_HTX_C_GRX_N12 PEG_HTX_C_GRX_N3 Security Classification Compal Secret Data Compal Electronics, Inc.
eDP_AUX PEG_GTX_C_HRX_P13 PEG_GTX_C_HRX_P2 Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

eDP_AUX# PEG_GTX_C_HRX_N13 PEG_GTX_C_HRX_N2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR (1/6) DMI,FDI,PEG
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
eDP_HPD# PEG_GTX_C_HRX_P12 PEG_GTX_C_HRX_P3 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW71 M/B LA-6582P Schematic
Date: Thursday, July 08, 2010 Sheet 4 of 48
5 4 3 2 1
5 4 3 2 1

JCPU1B
R18 2 1 20_0402_1% H_COMP3 AT23 COMP3
BCLK A16 CLK_CPU_BCLK <18>

MISC
R19 2 1 20_0402_1% H_COMP2 AT24 B16
COMP2 BCLK# CLK_CPU_BCLK# <18>
R20 1 49.9_0402_1% H_COMP1

CLOCKS
2 G16 COMP1 BCLK_ITP AR30
AT30 del net for XDP remove
R21 BCLK_ITP#
2 1 49.9_0402_1% H_COMP0 AT26 COMP0
PEG_CLK E16 CLK_CPU_DMI <14>
D16 SM_RCOMP_0 R38 1 2 100_0402_1%
PEG_CLK# CLK_CPU_DMI# <14>
@ SKTOCC#_R AH24 SM_RCOMP_1 R39 1 2 24.9_0402_1%
T24 PAD SKTOCC#
A18 SM_RCOMP_2 R40 1 2 130_0402_1%
DPLL_REF_SSCLK CLK_CPU_DP <14>
D
DPLL_REF_SSCLK# A17 CLK_CPU_DP# <14> D
H_CATERR# AK14 CATERR#

THERMAL
2009/08/14 #425302
SM_DRAMRST# F6 SM_DRAMRST# <10> CP_S3PowerReduction
R26 1 2 H_PECI_R AT15
<18> H_PECI PECI WhitePaper_Rev0.9 del R27 / R29 / R30 / R31 / R33 for XDP remove
0_0402_5% AL1 SM_RCOMP_0 1 2
SM_RCOMP[0] SM_RCOMP_1 R28 100K_0402_5% +1.05VS_VTT
SM_RCOMP[1] AM1
AN1 SM_RCOMP_2
H_PROCHOT# SM_RCOMP[2] R32
<45> H_PROCHOT# AN26 PROCHOT# 1 2 10K_0402_5%
AN15 PM_EXTTS#0 R34 1 2 10K_0402_5%
PM_EXT_TS#[0]

DDR3
MISC
AP15 PM_EXTTS#1_R R35 1 2 0_0402_5%
PM_EXT_TS#[1] PM_EXTTS#0_1 <10,11>
R36 1 2 H_THERMTRIP#_R AK15 XDP_TRST# R37 1 2 51_0402_5%
<18> H_THERMTRIP# THERMTRIP#
0_0402_5%

AT28 XDP_TDO 1 2 +1.05VS_VTT


PRDY# R70 51_0402_5%
PREQ# AP27

AN28 H_TCK @ PAD T25 XDP_TDO_M


H_CPURST# TCK H_TMS @
AP26 RESET_OBS# TMS AP28 PAD T26

1
PWR MANAGEMENT
AT27 XDP_TRST#
TRST# R45

JTAG & BPM


R42 1 2 H_PM_SYNC_R AL15 AT29 H_TDI @ del R41 / R43 / R48 / R49
<15> H_PM_SYNC PM_SYNC TDI PAD T27 XDP remove
0_0402_5% AR27 XDP_TDO 20100610 Add 0_0402_5%
TDO XDP_TDI_M
AR29

2
R44 1 H_CPUPW RGD_1 TDI_M XDP_TDO_M XDP_TDI_M
2 AN14 VCCPWRGOOD_1 TDO_M AP29
0_0402_5%
AN25 XDP_DBR#_R R46 1 2 0_0402_5% XDP_DBRESET# XDP_DBRESET# <15> XDP_DBRESET# 1 2 +3VS
C R47 1 H_CPUPW RGD_0 DBR# R67 1K_0402_5% C
<18> H_CPUPW RGD 2 AN27 VCCPWRGOOD_0
0_0402_5%
BPM#[0] AJ22
R50 1 2 PM_DRAM_PW RGD_R AK13 AK22
<15> PM_DRAM_PW RGD SM_DRAMPWROK BPM#[1]
0_0402_5% AK24
BPM#[2]
BPM#[3] AJ24
H_VTTPW RGD 1 @ 2 H_VTTPW RGD_R AM15 AJ25 del net for XDP remove
R52 0_0402_5% VTTPWRGOOD BPM#[4]
BPM#[5] AH22
BPM#[6] AK23
del net for XDP remove AM26 AH23
TAPPWRGOOD BPM#[7]

R56 1 2 PLT_RST#_R AL14


<17,27,30> PLT_RST# RSTIN#
1.5K_0402_1%
1

2009/2/4
#414044 DG R57 IC,AUB_CFD_rPGA,R1P0
750_0402_1% CONN@
Update Rev1.11
2

+1.05VS_VTT

R58 2 1 49.9_0402_1% H_CATERR#


R59 2 1 68_0402_5% H_PROCHOT#
R60 2 @ 1 68_0402_5% H_CPURST#

B B
+3VALW 2009/8/14
change back to 2K
5

U1 R61
H_VTTPW RGD 2 2K_0402_1%
P

<43> H_VTTPW RGD B


4 1 2 H_VTTPW RGD_R
Y
1 A
G

MC74VHC1G08DFT2G_SC70-5 R62
3

1K_0402_1%
U1 / U2
2

change to SA00000OH00
#425302 +3VALW
CP_S3PowerReduction Need to check Voltage Level
WhitePaper_Rev0.7
5

U2
+1.5V_1 H_VTTPW RGD
B 2
P

4 Y
A 1
G
1

MC74VHC1G08DFT2G_SC70-5
3

R68 R69
@
1.1K_0402_1% 1.5K_0402_1%
2

A A

PM_DRAM_PW RGD_R
1
1

R72
R71
@ 750_0402_1% Security Classification Compal Secret Data Compal Electronics, Inc.
3.01K_0402_1% 2009/04/23 2009/08/01 2010/08/01 Title
Issued Date Deciphered Date
2

Intel CRB 1.55 Update PROCESSOR (2/6) CLK,JTAG


2

Change R68 to 1.1K_1%, R71 to 3.01K_1% THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW71 M/B LA-6582P Schematic
Date: Thursday, July 08, 2010 Sheet 5 of 48
5 4 3 2 1
5 4 3 2 1

JCPU1D
<11> DDR_B_D[0..63]
<11> DDR_B_DM[0..7]
JCPU1C
<10> DDR_A_D[0..63] <11> DDR_B_DQS#[0..7]
<10> DDR_A_DM[0..7] <11> DDR_B_DQS[0..7]
<10> DDR_A_DQS#[0..7] <11> DDR_B_MA[0..15]
<10> DDR_A_DQS[0..7]
<10> DDR_A_MA[0..15] SB_CK[0] W8 DDR_B_CLK0 <11>
SB_CK#[0] W9 DDR_B_CLK0# <11>
AA6 DDR_B_D0 B5 M3
SA_CK[0] DDR_A_CLK0 <10> SB_DQ[0] SB_CKE[0] DDR_B_CKE0 <11>
AA7 DDR_B_D1 A5
SA_CK#[0] DDR_A_CLK0# <10> SB_DQ[1]
P7 DDR_B_D2 C3
SA_CKE[0] DDR_A_CKE0 <10> SB_DQ[2]
DDR_A_D0 A10 DDR_B_D3 B3 V7
SA_DQ[0] SB_DQ[3] SB_CK[1] DDR_B_CLK1 <11>
DDR_A_D1 C10 DDR_B_D4 E4 V6
SA_DQ[1] SB_DQ[4] SB_CK#[1] DDR_B_CLK1# <11>
D DDR_A_D2 C7 DDR_B_D5 A6 M2 D
SA_DQ[2] SB_DQ[5] SB_CKE[1] DDR_B_CKE1 <11>
DDR_A_D3 A7 Y6 DDR_B_D6 A4
SA_DQ[3] SA_CK[1] DDR_A_CLK1 <10> SB_DQ[6]
DDR_A_D4 B10 Y5 DDR_B_D7 C4
SA_DQ[4] SA_CK#[1] DDR_A_CLK1# <10> SB_DQ[7]
DDR_A_D5 D10 P6 DDR_B_D8 D1
SA_DQ[5] SA_CKE[1] DDR_A_CKE1 <10> SB_DQ[8]
DDR_A_D6 E10 DDR_B_D9 D2
DDR_A_D7 SA_DQ[6] DDR_B_D10 SB_DQ[9]
A8 SA_DQ[7] F2 SB_DQ[10] SB_CS#[0] AB8 DDR_B_CS0# <11>
DDR_A_D8 D8 DDR_B_D11 F1 AD6
SA_DQ[8] SB_DQ[11] SB_CS#[1] DDR_B_CS1# <11>
DDR_A_D9 F10 AE2 DDR_B_D12 C2
SA_DQ[9] SA_CS#[0] DDR_A_CS0# <10> SB_DQ[12]
DDR_A_D10 E6 AE8 DDR_B_D13 F5
SA_DQ[10] SA_CS#[1] DDR_A_CS1# <10> SB_DQ[13]
DDR_A_D11 F7 DDR_B_D14 F3
DDR_A_D12 SA_DQ[11] DDR_B_D15 SB_DQ[14]
E9 SA_DQ[12] G4 SB_DQ[15] SB_ODT[0] AC7 DDR_B_ODT0 <11>
DDR_A_D13 B7 DDR_B_D16 H6 AD1
SA_DQ[13] SB_DQ[16] SB_ODT[1] DDR_B_ODT1 <11>
DDR_A_D14 E7 AD8 DDR_B_D17 G2
SA_DQ[14] SA_ODT[0] DDR_A_ODT0 <10> SB_DQ[17]
DDR_A_D15 C6 AF9 DDR_B_D18 J6
SA_DQ[15] SA_ODT[1] DDR_A_ODT1 <10> SB_DQ[18]
DDR_A_D16 H10 DDR_B_D19 J3
DDR_A_D17 SA_DQ[16] DDR_B_D20 SB_DQ[19]
G8 SA_DQ[17] G1 SB_DQ[20]
DDR_A_D18 K7 DDR_B_D21 G5 D4 DDR_B_DM0
DDR_A_D19 SA_DQ[18] DDR_B_D22 SB_DQ[21] SB_DM[0] DDR_B_DM1
J8 SA_DQ[19] J2 SB_DQ[22] SB_DM[1] E1
DDR_A_D20 G7 DDR_B_D23 J1 H3 DDR_B_DM2
DDR_A_D21 SA_DQ[20] DDR_B_D24 SB_DQ[23] SB_DM[2] DDR_B_DM3
G10 SA_DQ[21] J5 SB_DQ[24] SB_DM[3] K1
DDR_A_D22 J7 B9 DDR_A_DM0 DDR_B_D25 K2 AH1 DDR_B_DM4
DDR_A_D23 SA_DQ[22] SA_DM[0] DDR_A_DM1 DDR_B_D26 SB_DQ[25] SB_DM[4] DDR_B_DM5
J10 SA_DQ[23] SA_DM[1] D7 L3 SB_DQ[26] SB_DM[5] AL2
DDR_A_D24 L7 H7 DDR_A_DM2 DDR_B_D27 M1 AR4 DDR_B_DM6
DDR_A_D25 SA_DQ[24] SA_DM[2] DDR_A_DM3 DDR_B_D28 SB_DQ[27] SB_DM[6] DDR_B_DM7
M6 SA_DQ[25] SA_DM[3] M7 K5 SB_DQ[28] SB_DM[7] AT8
DDR_A_D26 M8 AG6 DDR_A_DM4 DDR_B_D29 K4
DDR_A_D27 SA_DQ[26] SA_DM[4] DDR_A_DM5 DDR_B_D30 SB_DQ[29]
L9 SA_DQ[27] SA_DM[5] AM7 M4 SB_DQ[30]
DDR_A_D28 L6 AN10 DDR_A_DM6 DDR_B_D31 N5
DDR_A_D29 SA_DQ[28] SA_DM[6] DDR_A_DM7 DDR_B_D32 SB_DQ[31]
K8 SA_DQ[29] SA_DM[7] AN13 AF3 SB_DQ[32]
DDR_A_D30 N8 DDR_B_D33 AG1
C DDR_A_D31 SA_DQ[30] DDR_B_D34 SB_DQ[33] DDR_B_DQS#0 C
P9 SA_DQ[31] AJ3 SB_DQ[34] SB_DQS#[0] D5
DDR_A_D32 AH5 DDR_B_D35 AK1 F4 DDR_B_DQS#1
DDR_A_D33 SA_DQ[32] DDR_B_D36 SB_DQ[35] SB_DQS#[1] DDR_B_DQS#2
AF5 SA_DQ[33] AG4 SB_DQ[36] SB_DQS#[2] J4
DDR_A_D34 AK6 C9 DDR_A_DQS#0 DDR_B_D37 AG3 L4 DDR_B_DQS#3
SA_DQ[34] SA_DQS#[0] SB_DQ[37] SB_DQS#[3]
DDR SYSTEM MEMORY A

DDR_A_D35 AK7 F8 DDR_A_DQS#1 DDR_B_D38 AJ4 AH2 DDR_B_DQS#4


SA_DQ[35] SA_DQS#[1] SB_DQ[38] SB_DQS#[4]

DDR SYSTEM MEMORY - B


DDR_A_D36 AF6 J9 DDR_A_DQS#2 DDR_B_D39 AH4 AL4 DDR_B_DQS#5
DDR_A_D37 SA_DQ[36] SA_DQS#[2] DDR_A_DQS#3 DDR_B_D40 SB_DQ[39] SB_DQS#[5] DDR_B_DQS#6
AG5 SA_DQ[37] SA_DQS#[3] N9 AK3 SB_DQ[40] SB_DQS#[6] AR5
DDR_A_D38 AJ7 AH7 DDR_A_DQS#4 DDR_B_D41 AK4 AR8 DDR_B_DQS#7
DDR_A_D39 SA_DQ[38] SA_DQS#[4] DDR_A_DQS#5 DDR_B_D42 SB_DQ[41] SB_DQS#[7]
AJ6 SA_DQ[39] SA_DQS#[5] AK9 AM6 SB_DQ[42]
DDR_A_D40 AJ10 AP11 DDR_A_DQS#6 DDR_B_D43 AN2
DDR_A_D41 SA_DQ[40] SA_DQS#[6] DDR_A_DQS#7 DDR_B_D44 SB_DQ[43]
AJ9 SA_DQ[41] SA_DQS#[7] AT13 AK5 SB_DQ[44]
DDR_A_D42 AL10 DDR_B_D45 AK2
DDR_A_D43 SA_DQ[42] DDR_B_D46 SB_DQ[45]
AK12 SA_DQ[43] AM4 SB_DQ[46]
DDR_A_D44 AK8 DDR_B_D47 AM3
DDR_A_D45 SA_DQ[44] DDR_B_D48 SB_DQ[47] DDR_B_DQS0
AL7 SA_DQ[45] AP3 SB_DQ[48] SB_DQS[0] C5
DDR_A_D46 AK11 C8 DDR_A_DQS0 DDR_B_D49 AN5 E3 DDR_B_DQS1
DDR_A_D47 SA_DQ[46] SA_DQS[0] DDR_A_DQS1 DDR_B_D50 SB_DQ[49] SB_DQS[1] DDR_B_DQS2
AL8 SA_DQ[47] SA_DQS[1] F9 AT4 SB_DQ[50] SB_DQS[2] H4
DDR_A_D48 AN8 H9 DDR_A_DQS2 DDR_B_D51 AN6 M5 DDR_B_DQS3
DDR_A_D49 SA_DQ[48] SA_DQS[2] DDR_A_DQS3 DDR_B_D52 SB_DQ[51] SB_DQS[3] DDR_B_DQS4
AM10 SA_DQ[49] SA_DQS[3] M9 AN4 SB_DQ[52] SB_DQS[4] AG2
DDR_A_D50 AR11 AH8 DDR_A_DQS4 DDR_B_D53 AN3 AL5 DDR_B_DQS5
DDR_A_D51 SA_DQ[50] SA_DQS[4] DDR_A_DQS5 DDR_B_D54 SB_DQ[53] SB_DQS[5] DDR_B_DQS6
AL11 SA_DQ[51] SA_DQS[5] AK10 AT5 SB_DQ[54] SB_DQS[6] AP5
DDR_A_D52 AM9 AN11 DDR_A_DQS6 DDR_B_D55 AT6 AR7 DDR_B_DQS7
DDR_A_D53 SA_DQ[52] SA_DQS[6] DDR_A_DQS7 DDR_B_D56 SB_DQ[55] SB_DQS[7]
AN9 SA_DQ[53] SA_DQS[7] AR13 AN7 SB_DQ[56]
DDR_A_D54 AT11 DDR_B_D57 AP6
DDR_A_D55 SA_DQ[54] DDR_B_D58 SB_DQ[57]
AP12 SA_DQ[55] AP8 SB_DQ[58]
DDR_A_D56 AM12 DDR_B_D59 AT9
DDR_A_D57 SA_DQ[56] DDR_B_D60 SB_DQ[59]
AN12 SA_DQ[57] AT7 SB_DQ[60]
DDR_A_D58 AM13 Y3 DDR_A_MA0 DDR_B_D61 AP9
DDR_A_D59 SA_DQ[58] SA_MA[0] DDR_A_MA1 DDR_B_D62 SB_DQ[61]
AT14 SA_DQ[59] SA_MA[1] W1 AR10 SB_DQ[62]
B DDR_A_D60 DDR_A_MA2 DDR_B_D63 DDR_B_MA0 B
AT12 SA_DQ[60] SA_MA[2] AA8 AT10 SB_DQ[63] SB_MA[0] U5
DDR_A_D61 AL13 AA3 DDR_A_MA3 V2 DDR_B_MA1
DDR_A_D62 SA_DQ[61] SA_MA[3] DDR_A_MA4 SB_MA[1] DDR_B_MA2
AR14 SA_DQ[62] SA_MA[4] V1 SB_MA[2] T5
DDR_A_D63 AP14 AA9 DDR_A_MA5 V3 DDR_B_MA3
SA_DQ[63] SA_MA[5] DDR_A_MA6 SB_MA[3] DDR_B_MA4
SA_MA[6] V8 SB_MA[4] R1
T1 DDR_A_MA7 DDR_B_BS0 AB1 T8 DDR_B_MA5
SA_MA[7] <11> DDR_B_BS0 SB_BS[0] SB_MA[5]
Y9 DDR_A_MA8 DDR_B_BS1 W5 R2 DDR_B_MA6
SA_MA[8] <11> DDR_B_BS1 SB_BS[1] SB_MA[6]
DDR_A_BS0 AC3 U6 DDR_A_MA9 DDR_B_BS2 R7 R6 DDR_B_MA7
<10> DDR_A_BS0 SA_BS[0] SA_MA[9] <11> DDR_B_BS2 SB_BS[2] SB_MA[7]
DDR_A_BS1 AB2 AD4 DDR_A_MA10 R4 DDR_B_MA8
<10> DDR_A_BS1 SA_BS[1] SA_MA[10] SB_MA[8]
DDR_A_BS2 U7 T2 DDR_A_MA11 R5 DDR_B_MA9
<10> DDR_A_BS2 SA_BS[2] SA_MA[11] SB_MA[9]
U3 DDR_A_MA12 DDR_B_CAS# AC5 AB5 DDR_B_MA10
SA_MA[12] <11> DDR_B_CAS# SB_CAS# SB_MA[10]
AG8 DDR_A_MA13 DDR_B_RAS# Y7 P3 DDR_B_MA11
SA_MA[13] <11> DDR_B_RAS# SB_RAS# SB_MA[11]
T3 DDR_A_MA14 <11> DDR_B_W E# DDR_B_W E# AC6 R3 DDR_B_MA12
DDR_A_CAS# SA_MA[14] DDR_A_MA15 SB_WE# SB_MA[12] DDR_B_MA13
<10> DDR_A_CAS# AE1 SA_CAS# SA_MA[15] V9 SB_MA[13] AF7
DDR_A_RAS# AB3 P5 DDR_B_MA14
<10> DDR_A_RAS# SA_RAS# SB_MA[14]
<10> DDR_A_W E# DDR_A_W E# AE9 N1 DDR_B_MA15
SA_WE# SB_MA[15]

IC,AUB_CFD_rPGA,R1P0
CONN@
IC,AUB_CFD_rPGA,R1P0
A
CONN@ A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR (3/6) DDRIII
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW71 M/B LA-6582P Schematic
Date: Thursday, July 08, 2010 Sheet 6 of 48
5 4 3 2 1
5 4 3 2 1

JCPU1F

WW15 MOW
+CPU_CORE
Peak 21A +1.05VS_VTT
48A Continuous 18A
10U_0805_6.3V6M
AG35 AH14 10U_0805_6.3V6M 10U_0805_6.3V6M
VCC1 VTT0_1
AG34 AH12
VCC2 VTT0_2 +CPU_CORE
AG33 AH11
VCC3 VTT0_3
AG32 AH10 1 1 1 1 1 1 1
D VCC4 VTT0_4 C66 C67 C68 C69 C70 C71 C72 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M D
AG31 J14
VCC5 VTT0_5
AG30 J13
VCC6 VTT0_6
AG29 H14 1 1 1 1 1 1 1 1 1
VCC7 VTT0_7 2 2 2 2 2 2 2 C73 C74 C75 C76 C77 C78 C79 C80 C81
AG28 H12
VCC8 VTT0_8
AG27 G14
VCC9 VTT0_9 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
AG26 G13
VCC10 VTT0_10 10U_0805_6.3V6M 2 2 2 2 2 2 2 2 2
AF35 G12
VCC11 VTT0_11
AF34 G11
VCC12 VTT0_12 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
AF33 F14
VCC13 VTT0_13
AF32
VCC14 VTT0_14
F13 (Place these capacitors between inductor and socket on Bottom)
AF31 F12
VCC15 VTT0_15 +1.05VS_VTT
AF30 VCC16 VTT0_16 F11
AF29 E14 +CPU_CORE
VCC17 VTT0_17
AF28 VCC18 VTT0_18 E12
AF27 D14 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VCC19 VTT0_19

1
AF26 VCC20 VTT0_20 D13
+ +

1.1V RAIL POWER


AD35 D12 C82 C83 1 1 1 1 1 1
VCC21 VTT0_21 330U_2.5V_M_R15 C84 C85 C86 C87 C88 C89
AD34 VCC22 VTT0_22 D11
AD33 C14

2
VCC23 VTT0_23
AD32 VCC24 VTT0_24 C13
2 2 2 2 2 2
AD31 VCC25 VTT0_25 C12
AD30 C11 330U_2.5V_M_R15
VCC26 VTT0_26 Change to OS-CON 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
AD29 VCC27 VTT0_27 B14
AD28 B12 20100414 (Place these capacitors under CPU socket, top layer)
VCC28 VTT0_28
AD27 VCC29 VTT0_29 A14
AD26 VCC30 VTT0_30 A13 CSC (Current Sense Configuration)
AC35 VCC31 VTT0_31 A12 8/25 +1.05VS_VTT
AC34 VCC32 VTT0_32 A11
AC33 VCC33
AC32 +1.05VS_VTT
VCC34 CPU_VID0 R73
AC31 VCC35 1 2 1K_0402_1%
AC30 AF10 22U_0805_6.3V6M R74 1 @ 2 1K_0402_1%
C VCC36 VTT0_33 C
AC29 VCC37 VTT0_34 AE10
AC28 AC10 CPU_VID1 R75 1 2 1K_0402_1% +CPU_CORE
VCC38 VTT0_35 1 1
CPU CORE SUPPLY

AC27 AB10 C91 C92 R76 1 @ 2 1K_0402_1%


VCC39 VTT0_36 22U_0805_6.3V6M 22U_0805_6.3V6M
AC26 VCC40 VTT0_37 Y10
AA35 W10 CPU_VID2 R77 1 2 1K_0402_1%
VCC41 VTT0_38 2 2 R78
AA34 VCC42 VTT0_39 U10 1 @ 2 1K_0402_1% 1 1 1 1 1
AA33 T10 C98 C94 C95 C96 C97
VCC43 VTT0_40 22U_0805_6.3V6M CPU_VID3 R79
AA32 J12 1 @ 2 1K_0402_1%
VCC44 VTT0_41 R80
AA31 J11 1 2 1K_0402_1%
VCC45 VTT0_42 2 2 2 2 2
AA30 J16
VCC46 VTT0_43 CPU_VID4 R81
AA29 J15 1 @ 2 1K_0402_1%
VCC47 VTT0_44 R82
AA28 1 2 1K_0402_1% 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCC48
AA27
VCC49 (Place these capacitors on CPU cavity, Bottom Layer)
AA26 CPU_VID5 R83 1 2 1K_0402_1%
VCC50 R84
Y35
VCC51 1 @ 2 1K_0402_1%
Y34
VCC52 CPU_VID6 R85
Y33 1 @ 2 1K_0402_1%
VCC53 R86 +CPU_CORE
Y32 1 2 1K_0402_1%
VCC54
Y31
VCC55 H_DPRSLPVR R87
Y30 1 2 1K_0402_1% 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCC56 R88
Y29
VCC57 1 @ 2 1K_0402_1%
Y28 1 1 1 1 1 1
VCC58 H_PSI# R89
Y27 1 @ 2 1K_0402_1% C99 C100 C101 C102 C103 C104
VCC59 R90
Y26 1 2 1K_0402_1%
VCC60
V35 AN33 H_PSI# <45>
VCC61 PSI# 2 2 2 2 2 2
V34
POWER

VCC62
V33
VCC63 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
V32 AK35 CPU_VID0 <45>
VCC64 VID[0]
V31
VCC65 VID[1]
AK33 CPU_VID1 <45> (Place these capacitors on CPU cavity, Bottom Layer)
V30 AK34 CPU_VID2 <45>
VCC66 VID[2]
V29 AL35 CPU_VID3 <45>
VCC67 VID[3]
CPU VIDS

V28 AL33 CPU_VID4 <45>


B VCC68 VID[4] B
V27 AM33 CPU_VID5 <45>
VCC69 VID[5]
V26 AM35 CPU_VID6 <45>
VCC70 VID[6]
U35 AM34 H_DPRSLPVR <45>
VCC71 PROC_DPRSLPVR
U34
VCC72
U33
VCC73
U32
VCC74 H_VTTVID1 @ 20090915 Modify
U31 G15 PAD T14
VCC75 VTT_SELECT
U30
VCC76
U29
VCC77
U28
VCC78 H_VTTVID1 = low, 1.1V VTT Rail
U27
VCC79
U26
VCC80 H_VTTVID1 = high, 1.05V
R35
VCC81 Auburndale +1.1VS_VTT=1.05V
R34
VCC82 Clarksfield +1.1VS_VTT=1.1V +CPU_CORE
R33
VCC83
R32
VCC84 ISENSE
AN35 IMVP_IMON <45> 4 x 470uF(4.5mohm@100kHz; 4.0mohm@SRF)
R31
VCC85
R30 1 2 +CPU_CORE 1 1 1 1
VCC86 R91 100_0402_1%
R29
VCC87 VCCSENSE C105 + C272 + C273 + C275 +
SENSE LINES

R28 AJ34 VCCSENSE <45>


VCC88 VCC_SENSE VSSSENSE Del C106
R27 AJ35 VSSSENSE <45>
VCC89 VSS_SENSE 330U_D2E_2.5VM_R6M
R26
VCC90 2 2 2 2
P35 1 2
VCC91 R94 100_0402_1% 330U_D2E_2.5VM_R6M 330U_D2E_2.5VM_R6M
P34 B15 VTT_SENSE <43>
VCC92 VTT_SENSE VSS_SENSE_VTT 330U_D2E_2.5VM_R6M
P33 A15
VCC93 VSS_SENSE_VTT R95
P32 1 2 0_0402_5% TOP side (under inductor)
VCC94
P31
VCC95
P30
VCC96
P29
VCC97 +CPU-CORE C,uF ESR, mohm Stuffing Option
P28
P27
VCC98 Decoupling
VCC99
A
P26 VCC100 SPCAP,Polymer 4X470uF 4m ohm/4 2X470uF A

16X22uF 3m ohm/12
MLCC 0805 X5R
16X10uF 3m ohm/16

IC,AUB_CFD_rPGA,R1P0 Security Classification Compal Secret Data Compal Electronics, Inc.


CONN@ 2009/08/01 2010/08/01 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR (4/6) PWR,Bypass
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW71 M/B LA-6582P Schematic
Date: Thursday, July 08, 2010 Sheet 7 of 48
5 4 3 2 1
5 4 3 2 1

+VGFX_CORE
JCPU1G
10U_0805_6.3V6M
22U_0805_6.3V6M AT21 VAXG1
AT19 VAXG2 VAXG_SENSE AR22 VCC_AXG_SENSE <44>

SENSE
LINES
1 1 1 1 1 AT18 VAXG3 VSSAXG_SENSE AT22 VSS_AXG_SENSE <44>
C110 C111 C112 C113 AT16
C107 + VAXG4
D AR21 VAXG5 D
AR19 VAXG6
2 2 2 2
AR18 VAXG7
330U_D2E_2.5VM_R6M 2
AR16 VAXG8 GFX_VID[0] AM22 GFXVR_VID_0 <44>
AP21 VAXG9 GFX_VID[1] AP22 GFXVR_VID_1 <44>

GRAPHICS VIDs
22U_0805_6.3V6M AP19 AN22
VAXG10 GFX_VID[2] GFXVR_VID_2 <44>
10U_0805_6.3V6M AP18 AP23 GFXVR_EN 1 2
VAXG11 GFX_VID[3] GFXVR_VID_3 <44>
AP16 15A AM23 R167 470_0402_5%
VAXG12 GFX_VID[4] GFXVR_VID_4 <44>
AN21 VAXG13 GFX_VID[5] AP24 GFXVR_VID_5 <44>

GRAPHICS
AN19 AN24 PD 470ohm 20091105
VAXG14 GFX_VID[6] GFXVR_VID_6 <44>
AN18 VAXG15
AN16 VAXG16
AM21 AR25 GFXVR_EN
VAXG17 GFX_VR_EN GFXVR_EN <44>
AM19 AT25 GFXVR_DPRSLPVR_R R97 1 2 0_0402_5%
VAXG18 GFX_DPRSLPVR GFXVR_DPRSLPVR <44> +1.5V_1 +1.5V
AM18 VAXG19 GFX_IMON AM24 GFXVR_IMON <44>
AM16 VAXG20
AL21 VAXG21
AL19
AL18
VAXG22 Reserved for +1.5V to +1.5V_1
VAXG23 J1
AL16 VAXG24
AK21 AJ1 1U_0402_6.3V6K 1U_0402_6.3V6K 22U_0805_6.3V6M 2 1
VAXG25 VDDQ1 2 1
AK19 VAXG26 VDDQ2 AF1
AK18 AE7 1 1 1 1 1 1 1 1 @ JUMP_43X118

- 1.5V RAILS
VAXG27 VDDQ3 C114 C115 C116 C117 C118 C119 C120
AK16 VAXG28 VDDQ4 AE4
AJ21 AC1 + C121
VAXG29 VDDQ5 330U_D2E_2.5VM_R6M J3
AJ19 VAXG30 VDDQ6 AB7
2 2 2 2 2 2 2
AJ18 VAXG31 VDDQ7 AB4 2 2 1 1 +1.5VS
2
AJ16 VAXG32 3A VDDQ8 Y1
@ JUMP_43X118
AH21 VAXG33 VDDQ9 W7

POWER
C AH19 W4 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K C
VAXG34 VDDQ10 22U_0805_6.3V6M
AH18 VAXG35 VDDQ11 U1
AH16 VAXG36 VDDQ12 T7
T4
Reserved for +1.5VS to +1.5V_1
VDDQ13
VDDQ14 P1
+1.05VS_VTT N7
VDDQ15
VDDQ16 N4

DDR3
VDDQ17 L1
J24 VTT1_45 VDDQ18 H1 11/03 add four 0.1u 0402

FDI
J23 VTT1_46 Intel suggest
1 1 H25 VTT1_47
C122 C123 +1.05VS_VTT
+1.5V_1 +1.5V
22U_0805_6.3V6M 22U_0805_6.3V6M P10
2 2 VTT0_59
VTT0_60 N10
VTT0_61 L10 1 1 2
K10 C124 C670 0.1U_0402_16V4Z
VTT0_62
1 2
+1.05VS_VTT 10U_0805_6.3V6M C671 0.1U_0402_16V4Z
2
1 2
+1.05VS_VTT C672 0.1U_0402_16V4Z

1.1V
VTT1_63 J22 1 2
K26 J20 C673 0.1U_0402_16V4Z
VTT1_48 VTT1_64
J27 VTT1_49 VTT1_65 J18 1

PEG & DMI


1 1 J26 H21 C127
C125 C126 VTT1_50 VTT1_66
J25 VTT1_51 VTT1_67 H20
H27 H19 22U_0805_6.3V6M
22U_0805_6.3V6M 22U_0805_6.3V6M VTT1_52 VTT1_68 2
G28 VTT1_53
2 2
G27 VTT1_54
B B
G26 VTT1_55
F26 +1.8VS
VTT1_56 R99
E26 VTT1_57 VCCPLL1 L26

1.8V
E25 0.6A L27 0_0805_5%
VTT1_58 VCCPLL2 +1.8VS_VCCSFR 2.2U_0603_6.3V6K
VCCPLL3 M26 1 2

1 1 1 1 1
C128 C129 C130 C131 C132

1U_0402_6.3V6K
2 2 2 2 2 22U_0805_6.3V6M

IC,AUB_CFD_rPGA,R1P0 1U_0402_6.3V6K 4.7U_0805_10V4Z


CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR (5/6) PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW71 M/B LA-6582P Schematic
Date: Thursday, July 08, 2010 Sheet 8 of 48
5 4 3 2 1
5 4 3 2 1

JCPU1H JCPU1I

AT20 VSS1 VSS81 AE34


AT17 VSS2 VSS82 AE33
AR31 VSS3 VSS83 AE32 K27 VSS161
AR28 VSS4 VSS84 AE31 K9 VSS162
AR26 VSS5 VSS85 AE30 K6 VSS163
AR24 VSS6 VSS86 AE29 K3 VSS164
D AR23 VSS7 VSS87 AE28 J32 VSS165 D
AR20 VSS8 VSS88 AE27 J30 VSS166
AR17 VSS9 VSS89 AE26 J21 VSS167
AR15 VSS10 VSS90 AE6 J19 VSS168
AR12 VSS11 VSS91 AD10 H35 VSS169
AR9 VSS12 VSS92 AC8 H32 VSS170
AR6 VSS13 VSS93 AC4 H28 VSS171
AR3 VSS14 VSS94 AC2 H26 VSS172
AP20 VSS15 VSS95 AB35 H24 VSS173
AP17 VSS16 VSS96 AB34 H22 VSS174
AP13 VSS17 VSS97 AB33 H18 VSS175
AP10 VSS18 VSS98 AB32 H15 VSS176
AP7 VSS19 VSS99 AB31 H13 VSS177
AP4 VSS20 VSS100 AB30 H11 VSS178
AP2 VSS21 VSS101 AB29 H8 VSS179
AN34 VSS22 VSS102 AB28 H5 VSS180
AN31 VSS23 VSS103 AB27 H2 VSS181
AN23 VSS24 VSS104 AB26 G34 VSS182
AN20 VSS25 VSS105 AB6 G31 VSS183
AN17 VSS26 VSS106 AA10 G20 VSS184
AM29 VSS27 VSS107 Y8 G9 VSS185
AM27 VSS28 VSS108 Y4 G6 VSS186
AM25 VSS29 VSS109 Y2 G3 VSS187
AM20 VSS30 VSS110 W35 F30 VSS188
AM17 VSS31 VSS111 W34 F27 VSS189
AM14 VSS32 VSS112 W33 F25 VSS190
AM11 VSS33 VSS113 W32 F22 VSS191
AM8 VSS34 VSS114 W31 F19 VSS192
AM5 VSS35 VSS115 W30 F16 VSS193
C AM2 W29 E35 C
VSS36 VSS116 VSS194
AL34 W28 E32
AL31
AL23
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
W27
W26
E29
E24
VSS195
VSS196
VSS197
VSS
AL20 VSS40 VSS120 W6 E21 VSS198
AL17 VSS41 VSS121 V10 E18 VSS199
AL12 VSS42 VSS122 U8 E13 VSS200
AL9 VSS43 VSS123 U4 E11 VSS201
AL6 VSS44 VSS124 U2 E8 VSS202
AL3 VSS45 VSS125 T35 E5 VSS203
AK29 T34 E2 AT35 H_NCTF1 @ PAD T2
VSS46 VSS126 VSS204 VSS_NCTF1 H_NCTF2 @
AK27 VSS47 VSS127 T33 D33 VSS205 VSS_NCTF2 AT1 PAD T3
AK25 VSS48 VSS128 T32 D30 VSS206 VSS_NCTF3 AR34
AK20 VSS49 VSS129 T31 D26 VSS207 VSS_NCTF4 B34
AK17 T30 D9 B2

NCTF
VSS50 VSS130 VSS208 VSS_NCTF5 H_NCTF6 @
AJ31 VSS51 VSS131 T29 D6 VSS209 VSS_NCTF6 B1 PAD T4
AJ23 T28 D3 A35 H_NCTF7 @ PAD T5
VSS52 VSS132 VSS210 VSS_NCTF7
AJ20 VSS53 VSS133 T27 C34 VSS211
AJ17 VSS54 VSS134 T26 C32 VSS212
AJ14 VSS55 VSS135 T6 C29 VSS213
AJ11 VSS56 VSS136 R10 C28 VSS214
AJ8 VSS57 VSS137 P8 C24 VSS215
AJ5 VSS58 VSS138 P4 C22 VSS216
AJ2 VSS59 VSS139 P2 C20 VSS217
AH35 VSS60 VSS140 N35 C19 VSS218
AH34 VSS61 VSS141 N34 C16 VSS219
AH33 VSS62 VSS142 N33 B31 VSS220
AH32 VSS63 VSS143 N32 B25 VSS221
AH31 VSS64 VSS144 N31 B21 VSS222
B B
AH30 VSS65 VSS145 N30 B18 VSS223
AH29 VSS66 VSS146 N29 B17 VSS224
AH28 VSS67 VSS147 N28 B13 VSS225
AH27 VSS68 VSS148 N27 B11 VSS226
AH26 VSS69 VSS149 N26 B8 VSS227
AH20 VSS70 VSS150 N6 B6 VSS228
AH17 VSS71 VSS151 M10 B4 VSS229
AH13 VSS72 VSS152 L35 A29 VSS230
AH9 VSS73 VSS153 L32 A27 VSS231
AH6 VSS74 VSS154 L29 A23 VSS232
AH3 VSS75 VSS155 L8 A9 VSS233
AG10 VSS76 VSS156 L5
AF8 VSS77 VSS157 L2
AF4 VSS78 VSS158 K34
AF2 VSS79 VSS159 K33
AE35 VSS80 VSS160 K30

IC,AUB_CFD_rPGA,R1P0 IC,AUB_CFD_rPGA,R1P0
CONN@ CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR (6/6) VSS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW71 M/B LA-6582P Schematic
Date: Thursday, July 08, 2010 Sheet 9 of 48
5 4 3 2 1
5 4 3 2 1

+1.5V +1.5V
DIMMA VREFDQ M1 Circuit JDIMM1
<6> DDR_A_DQS#[0..7] +DIMM_VREFDQA 1 VREF_DQ VSS1 2
+1.5V 3 4 DDR_A_D4
<6> DDR_A_D[0..63] VSS2 DQ4
DDR_A_D0 5 6 DDR_A_D5
DDR_A_D1 DQ0 DQ5
<6> DDR_A_DM[0..7] 7 DQ1 VSS3 8

1
9 10 DDR_A_DQS#0
R101 +DIMM_VREFDQA DDR_A_DM0 VSS4 DQS#0 DDR_A_DQS0
<6> DDR_A_DQS[0..7] 11 DM0 DQS0 12
13 VSS5 VSS6 14
1K_0402_1% <6> DDR_A_MA[0..15] DDR_A_D2 15 16 DDR_A_D6
DDR_A_D3 DQ2 DQ6 DDR_A_D7
17 18
2

DQ3 DQ7
M1 Circuit 19 VSS7 VSS8 20
DDR_A_D8 21 22 DDR_A_D12
DQ8 DQ12
1

+DIMM_VREFDQA DDR_A_D9 23 24 DDR_A_D13


R104 DQ9 DQ13
25 26
D DDR_A_DQS#1 VSS9 VSS10 DDR_A_DM1 D
27 28
1K_0402_1% DDR_A_DQS1 DQS#1 DM1 DIMM_DRAMRST#
29 30
DQS1 RESET#
1 1 31 32
2

C134 C133 DDR_A_D10 VSS11 VSS12 DDR_A_D14


33 34
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 36
0.1U_0402_16V4Z 2.2U_0603_6.3V6K DQ11 DQ15
37 38
2 2 DDR_A_D16 VSS13 VSS14 DDR_A_D20
39 40
DDR_A_D17 DQ16 DQ20 DDR_A_D21
41 42
DQ17 DQ21
43 44
DDR_A_DQS#2 VSS15 VSS16 DDR_A_DM2
45 46
DDR_A_DQS2 DQS#2 DM2
DIMMA & DIMMB VREFCA circuit 47
DQS2 VSS17
48
49 50 DDR_A_D22
+1.5V DDR_A_D18 VSS18 DQ22 DDR_A_D23
51 DQ18 DQ23 52
DDR_A_D19 53 54
DQ19 VSS19 DDR_A_D28
55 VSS20 DQ28 56
1

DDR_A_D24 57 58 DDR_A_D29
R106 +DIMM_VREFCA DDR_A_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_A_DQS#3
1K_0402_1% DDR_A_DM3 VSS22 DQS#3 DDR_A_DQS3
63 DM3 DQS3 64
65 66
2

+1.5V DDR_A_D26 VSS23 VSS24 DDR_A_D30


#425302 67 DQ26 DQ30 68
DDR_A_D27 69 70 DDR_A_D31
CP_S3PowerReduction DQ27 DQ31
1

71 72
WhitePaper_Rev1.0 VSS25 VSS26

1
R107 R102
0_0402_5% R103
1K_0402_1% 1 @ 2
1K_0402_1% DDR_A_CKE0 73 74 DDR_A_CKE1
<6> DDR_A_CKE0 DDR_A_CKE1 <6>
2

CKE0 CKE1
75 76

2
VDD1 VDD2 DDR_A_MA15
77 NC1 A15 78

D
3 1 DIMM_DRAMRST# DDR_A_BS2 79 80 DDR_A_MA14
<5> SM_DRAMRST# DIMM_DRAMRST# <11> <6> DDR_A_BS2 BA2 A14
Q2 81 82
BSS138LT1G_SOT23-3 DDR_A_MA12 VDD3 VDD4 DDR_A_MA11
83 A12/BC# A11 84
C DDR_A_MA9 DDR_A_MA7 C
85 86

G
C617

2
A9 A7
87 VDD5 VDD6 88
RST_GATE 1 2 DDR_A_MA8 89 90 DDR_A_MA6
<18> RST_GATE DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
93 VDD7 VDD8 94
0.047U_0402_16V7K DDR_A_MA3 DDR_A_MA2
95 A3 A2 96
DDR_A_MA1 97 98 DDR_A_MA0
A1 A0
99 100
DDR_A_CLK0 VDD9 VDD10 DDR_A_CLK1
101 102 DDR_A_CLK1 <6>
<6> DDR_A_CLK0 DDR_A_CLK0# CK0 CK1 DDR_A_CLK1#
103 104 DDR_A_CLK1# <6>
<6> DDR_A_CLK0# CK0# CK1#
105 106
DDR_A_MA10 VDD11 VDD12 DDR_A_BS1
107 108 DDR_A_BS1 <6>
DDR_A_BS0 A10/AP BA1 DDR_A_RAS#
<6> DDR_A_BS0 109 110 DDR_A_RAS# <6>
BA0 RAS#
111 112
DDR_A_WE# VDD13 VDD14 DDR_A_CS0#
113 114 DDR_A_CS0# <6>
<6> DDR_A_WE# DDR_A_CAS# WE# S0# DDR_A_ODT0
<6> DDR_A_CAS# 115 116 DDR_A_ODT0 <6>
CAS# ODT0
117 118
DDR_A_MA13 VDD15 VDD16 DDR_A_ODT1 +DIMM_VREFCA
119 120 DDR_A_ODT1 <6>
DDR_A_CS1# A13 ODT1
121 122
<6> DDR_A_CS1# S1# NC2
123 124
VDD17 VDD18 DDR_VREF_CA_DIMMA R108 1
125
NCTEST VREF_CA
126 2 0_0402_5%
127 128
DDR_A_D32 VSS27 VSS28 DDR_A_D36
129 130
DDR_A_D33 DQ32 DQ36 DDR_A_D37
131 132
DQ33 DQ37
Layout Note: DDR_A_DQS#4
133
VSS29 VSS30
134
DDR_A_DM4
135 136
Place near JDIMM1 DDR_A_DQS4 DQS#4 DM4
137 138 1 1
DQS4 VSS31 DDR_A_D38 C135 C136
139 140
DDR_A_D34 VSS32 DQ38 DDR_A_D39
141 142
DDR_A_D35 DQ34 DQ39 2.2U_0603_6.3V6K 0.1U_0402_16V4Z
Layout Note: Place these 4 Caps near Command 143
DQ35 VSS33
144
DDR_A_D44 2 2
145 146
and Control signals of DIMMA DDR_A_D40 VSS34 DQ44 DDR_A_D45
147 148
B DDR_A_D41 DQ40 DQ45 B
149 150
+1.5V DQ41 VSS35 DDR_A_DQS#5
151 152
DDR_A_DM5 VSS36 DQS#5 DDR_A_DQS5
153 154
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z DM5 DQS5
155 156
DDR_A_D42 VSS37 VSS38 DDR_A_D46
157 158
DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 160
DQ43 DQ47
1

1 1 1 1 1 1 1 1 1 1 161 162
C137 C138 C139 C140 C141 C142 C143 C144 C145 C146 + @ C147 DDR_A_D48 VSS39 VSS40 DDR_A_D52
163 164
330U_2.5V_M_R15 DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 166
DQ49 DQ53
167 168
2

2 2 2 2 2 2 2 2 2 2 DDR_A_DQS#6 VSS41 VSS42 DDR_A_DM6


169 170
DDR_A_DQS6 DQS#6 DM6
171 172
DQS6 VSS43 DDR_A_D54
173 174
DDR_A_D50 VSS44 DQ54 DDR_A_D55
175 176
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z DDR_A_D51 DQ50 DQ55
177 178
DQ51 VSS45 DDR_A_D60
179 180
DDR_A_D56 VSS46 DQ60 DDR_A_D61
181 182
DDR_A_D57 DQ56 DQ61
183 184
DQ57 VSS47 DDR_A_DQS#7
185 186
DDR_A_DM7 VSS48 DQS#7 DDR_A_DQS7
187 188
DM7 DQS7
189 190
DDR_A_D58 VSS49 VSS50 DDR_A_D62
Layout Note: DDR_A_D59
191
DQ58 DQ62
192
DDR_A_D63
193 194
Place near JDIMM1.203 & JDIMM1.204 DQ59 DQ63
195 196
R109 1 VSS51 VSS52 PM_EXTTS#0_1
2 10K_0402_5% 197 198 PM_EXTTS#0_1 <5,11>
SA0 EVENT# D_CK_SDATA
+3VS 199 200 D_CK_SDATA <11,12>
VDDSPD SDA D_CK_SCLK
201 202 D_CK_SCLK <11,12>
SA1 SCL
1 1 203 204 +0.75VS
VTT1 VTT2
1

+0.75VS C148 C149


2.2U_0603_6.3V6K R110 205 206
1U_0402_6.3V6K 1U_0402_6.3V6K 0.1U_0402_16V4Z G1 G2
2 2 10K_0402_5% FOX_AS0A626-U8RN-7F
A
DDR3 SO-DIMM A A
2

1 1 1 1 1
C154
Change to Reverse Type
C150
2
C151
2
C152
2
C153
2 2
10U_0805_6.3V6M 8mm High
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title
1U_0402_6.3V6K 1U_0402_6.3V6K
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom PEW71 M/B LA-6582P Schematic 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, July 08, 2010 Sheet 10 of 48
5 4 3 2 1
5 4 3 2 1

+1.5V
+1.5V
2008/9/8 #400755 JDIMM2
+DIMM_VREFDQB 1 2
<6> DDR_B_DQS#[0..7] Calpella Clarksfield VREF_DQ VSS1 DDR_B_D4
3 4
DDR3 SO-DIMM DDR_B_D0 5
VSS2 DQ4
6 DDR_B_D5
<6> DDR_B_D[0..63] DQ0 DQ5
VREFDQ Platform DDR_B_D1 7 8
DQ1 VSS3 DDR_B_DQS#0
<6> DDR_B_DM[0..7] Design Guide Change Details 9 VSS4 DQS#0 10
DDR_B_DM0 11 12 DDR_B_DQS0
DM0 DQS0
<6> DDR_B_DQS[0..7] 13 VSS5 VSS6 14
DDR_B_D2 15 16 DDR_B_D6
DDR_B_D3 DQ2 DQ6 DDR_B_D7
<6> DDR_B_MA[0..15] 17 18
DQ3 DQ7
19 20
DDR_B_D8 VSS7 VSS8 DDR_B_D12
21 22
D DDR_B_D9 DQ8 DQ12 DDR_B_D13 D
23 24
DQ9 DQ13
M1 Circuit 25
VSS9 VSS10
26
DDR_B_DQS#1 27 28 DDR_B_DM1
DDR_B_DQS1 DQS#1 DM1 DIMM_DRAMRST#
+DIMM_VREFDQB 29 30 DIMM_DRAMRST# <10>
DQS1 RESET#
DIMMB VREFDQ M1 Circuit 31
VSS11 VSS12
32
DDR_B_D10 33 34 DDR_B_D14
+1.5V DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 36
DQ11 DQ15
1 1 37 38
C155 C156 DDR_B_D16 VSS13 VSS14 DDR_B_D20
39 40
DQ16 DQ20
1

DDR_B_D17 41 42 DDR_B_D21
R113 +DIMM_VREFDQB 2.2U_0603_6.3V6K DQ17 DQ21
43 44
2 2 DDR_B_DQS#2 VSS15 VSS16 DDR_B_DM2
45 DQS#2 DM2 46
1K_0402_1% DDR_B_DQS2 47 48
DQS2 VSS17 DDR_B_D22
49 50
2

0.1U_0402_16V4Z DDR_B_D18 VSS18 DQ22 DDR_B_D23


51 DQ18 DQ23 52
DDR_B_D19 53 54
DQ19 VSS19
1

55 56 DDR_B_D28
R114 DDR_B_D24 VSS20 DQ28 DDR_B_D29
57 DQ24 DQ29 58
DDR_B_D25 59 60
1K_0402_1% DQ25 VSS21 DDR_B_DQS#3
61 VSS22 DQS#3 62
DDR_B_DM3 63 64 DDR_B_DQS3
2

DM3 DQS3
65 VSS23 VSS24 66
DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 DQ27 DQ31 70
71 VSS25 VSS26 72

DDR_B_CKE0 73 74 DDR_B_CKE1
<6> DDR_B_CKE0 CKE0 CKE1 DDR_B_CKE1 <6>
75 VDD1 VDD2 76
77 78 DDR_B_MA15
DDR_B_BS2 NC1 A15 DDR_B_MA14
<6> DDR_B_BS2 79 BA2 A14 80
C C
81 VDD3 VDD4 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD7 VDD8 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 98
A1 A0
99 100
DDR_B_CLK0 VDD9 VDD10 DDR_B_CLK1
101 102 DDR_B_CLK1 <6>
<6> DDR_B_CLK0 DDR_B_CLK0# CK0 CK1 DDR_B_CLK1#
103 104 DDR_B_CLK1# <6>
<6> DDR_B_CLK0# CK0# CK1#
105 106
DDR_B_MA10 VDD11 VDD12 DDR_B_BS1
107 108 DDR_B_BS1 <6>
DDR_B_BS0 A10/AP BA1 DDR_B_RAS#
<6> DDR_B_BS0 109 110 DDR_B_RAS# <6>
BA0 RAS#
111 112
DDR_B_WE# VDD13 VDD14 DDR_B_CS0#
113 114 DDR_B_CS0# <6>
<6> DDR_B_WE# DDR_B_CAS# WE# S0# DDR_B_ODT0
<6> DDR_B_CAS# 115 116 DDR_B_ODT0 <6>
CAS# ODT0
Layout Note: DDR_B_MA13
117
VDD15 VDD16
118
DDR_B_ODT1
119 120 DDR_B_ODT1 <6>
Place near JDIMM2 DDR_B_CS1# A13 ODT1 +DIMM_VREFCA
121 122
<6> DDR_B_CS1# S1# NC2
123 124
VDD17 VDD18 DDR_VREF_CA_DIMMB R115 1
Layout Note: Place these 4 Caps near Command 125 126 2 0_0402_5%
NCTEST VREF_CA
127 128
and Control signals of DIMMB DDR_B_D32 129
VSS27 VSS28
130 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
131 132
+1.5V DQ33 DQ37
133 134
DDR_B_DQS#4 VSS29 VSS30 DDR_B_DM4
135 136
10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z DDR_B_DQS4 DQS#4 DM4
137 138 1 1
DQS4 VSS31 DDR_B_D38 C157 C158
139 140
DDR_B_D34 VSS32 DQ38 DDR_B_D39
141 142
DQ34 DQ39
1

1 1 1 1 1 1 1 1 1 1 DDR_B_D35 143 144 2.2U_0603_6.3V6K 0.1U_0402_16V4Z


B C159 C160 C161 C162 C163 C164 C165 C166 C167 C168 + C169 DQ35 VSS33 DDR_B_D44 2 2 B
145 146
330U_2.5V_M_R15 DDR_B_D40 VSS34 DQ44 DDR_B_D45
147 148
DDR_B_D41 DQ40 DQ45
149 150
2

10U_0805_6.3V6M 2 2 2 2 2 2 2 2 2 2 DQ41 VSS35 DDR_B_DQS#5


151 152
DDR_B_DM5 VSS36 DQS#5 DDR_B_DQS5
153 154
DM5 DQS5
155 156
DDR_B_D42 VSS37 VSS38 DDR_B_D46
157 158
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 160
DQ43 DQ47
161 162
DDR_B_D48 VSS39 VSS40 DDR_B_D52
163 164
DDR_B_D49 DQ48 DQ52 DDR_B_D53
165 166
DQ49 DQ53
167 168
DDR_B_DQS#6 VSS41 VSS42 DDR_B_DM6
169 170
DDR_B_DQS6 DQS#6 DM6
Layout Note: 171
DQS6 VSS43
172
DDR_B_D54
173 174
Place near JDIMM2.203 & JDIMM2.204 DDR_B_D50 175
VSS44 DQ54
176 DDR_B_D55
DDR_B_D51 DQ50 DQ55
177 178
DQ51 VSS45 DDR_B_D60
179 180
DDR_B_D56 VSS46 DQ60 DDR_B_D61
181 182
DDR_B_D57 DQ56 DQ61
183 184
+0.75VS DQ57 VSS47 DDR_B_DQS#7
185 186
DDR_B_DM7 VSS48 DQS#7 DDR_B_DQS7
187 188
1U_0402_6.3V6K 1U_0402_6.3V6K DM7 DQS7
189 190
DDR_B_D58 VSS49 VSS50 DDR_B_D62
191 192
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 194
DQ59 DQ63
195 196
VSS51 VSS52 PM_EXTTS#0_1
1 1 1 1 1 C174 R116 1 2 10K_0402_5% 197
SA0 EVENT#
198 PM_EXTTS#0_1 <5,10>
199 200 D_CK_SDATA
+3VS VDDSPD SDA D_CK_SCLK D_CK_SDATA <10,12>
1 2 201 202 D_CK_SCLK <10,12>
C170 C171 C172 C173 10U_0805_6.3V6M R117 10K_0402_5% SA1 SCL
203 204 +0.75VS
2 2 2 2 2 VTT1 VTT2
1 1
C175 C176 205 206
A
2.2U_0603_6.3V6K 0.1U_0402_16V4Z
G1
FOX_AS0A626-U4RN-7F
G2
DDR3 SO-DIMM B A

1U_0402_6.3V6K 1U_0402_6.3V6K 2 2 CONN@ Reverse Type


4mm High
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS PEW71 M/B LA-6582P Schematic 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, July 08, 2010 Sheet 11 of 48
5 4 3 2 1
A B C D E F G H

+CLK_3VS
+CLK_1.05VS

+1.05VS L1 2 1 0.1U_0402_16V4Z +3VS L2 2 1 0.1U_0402_16V4Z


FBMA-L11-201209-221LMA30T_0805 FBMA-L11-201209-221LMA30T_0805
1 1 1 1 1 1 1 1
C178 C179 C180 C181 C182 C183 C184
change to +1.05VS C177
20100429 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z
2 2 2 2 2 2 2 2
1 1

0.1U_0402_16V4Z Del 3G solution 10U_0805_10V4Z 0.1U_0402_16V4Z Del 3G solution


Del L3

+CLK_1.5VS

+1.5VS L4 2 1 0.1U_0402_16V4Z
FBMA-L11-201209-221LMA30T_0805
1 1 1 1 1
C186 C187 C188 C189
C185
10U_0805_10V4Z 10U_0805_10V4Z
2 2 2 2 2

0.1U_0402_16V4Z 0.1U_0402_16V4Z Del 3G solution

2 +CLK_3VS 2
+CLK_3VS

+CLK_1.5VS Clock Generator


U3

1 32 D_CK_SCLK
VDD_USB_48 SCL D_CK_SCLK <10,11>
2 31 D_CK_SDATA
VSS_48M SDA D_CK_SDATA <10,11>
CLK_BUF_DREF_96M 3 30 REF_0/CPU_SEL R118 1 2 33_0402_5%
<14> CLK_BUF_DREF_96M DOT_96 REF_0/CPU_SEL CLK_BUF_ICH_14M <14>
CLK_BUF_DREF_96M# 4 29
<14> CLK_BUF_DREF_96M# DOT_96# VDD_REF
5 28 CLK_XTAL_IN
VDD_27 XTAL_IN CLK_XTAL_OUT
6 27MHZ XTAL_OUT 27
7 27MHZ_SS VSS_REF 26
For Cardreader 1 2 CLK_SD_48M_R 8 25 CK505_PW RGD
<29> CLK_SD_48M USB_48 CKPWRGD/PD#
R119 33_0402_5%
9 VSS_27M VDD_CPU 24
CLK_BUF_PCIE_SATA 10 23 CLK_BUF_CPU_BCLK
<14> CLK_BUF_PCIE_SATA SATA CPU_0 CLK_BUF_CPU_BCLK <14>
CLK_BUF_PCIE_SATA# 11 22 CLK_BUF_CPU_BCLK#
<14> CLK_BUF_PCIE_SATA# SATA# CPU_0# CLK_BUF_CPU_BCLK# <14>
12 VSS_SRC VSS_CPU 21
CLK_BUF_CPU_DMI 13 20
<14> CLK_BUF_CPU_DMI SRC_1 CPU_1
CLK_BUF_CPU_DMI# 14 19
<14> CLK_BUF_CPU_DMI# SRC_1# CPU_1#
+CLK_1.05VS 15 VDD_SRC_IO VDD_CPU_IO 18 +CLK_1.05VS
H_STP_CPU# 16 17 +CLK_1.5VS
CPU_STOP# VDD_SRC
33 TGND
IDT SA00003HR00
SLG8SP587VTR_QFN32_5X5

3 IDT: 9LRS3199AKLFT, SA000030P00 3

SILEGO: SLG8SP587V(WF), SA00002XY10


+3VS
Low Power:
IDT: 9LVS3199AKLFT, SA00003HR00

2
Realtek: RTM890N-631-GRT, SA00003HQ00 R120
10K_0402_5%
R122
+3VS +3VS 0_0402_5%

1
Silego Have Internal Pull-Up R123 CK505_PW RGD 1 @ 2 VGATE <15,45>
4.7K_0402_5%
D
2

1
1 2 +3VS
R121 1 2 10K_0402_5% H_STP_CPU# 2 CLK_ENABLE# <45>
<14,26> PCH_SMBDATA 6 1 D_CK_SDATA G
S Q5

3
Q4A 2N7002_SOT23
2N7002DW -T/R7_SOT363-6

+3VS
IDT Have Internal Pull-Down R125
4.7K_0402_5% C190
5

1 2 +3VS CLK_XTAL_IN 2 1
R124 1 2 10K_0402_5% REF_0/CPU_SEL Y1 Change to SJ100009R00

1
3 4 D_CK_SCLK 33P_0402_50V8J 20091117
<14,26> PCH_SMBCLK
Y1
Q4B 14.31818MHZ 20PF 7A14300003
2N7002DW -T/R7_SOT363-6 C191

2
4 4
Change to 5x3.2 CLK_XTAL_OUT 2 1
Change to 2N7002DW
20100416 33P_0402_50V8J
PIN 30 CPU_0 CPU_1

0 (Default) 133MHz 133MHz Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title
1 100MHz 100MHz Clock Generator (CK505)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW71 M/B LA-6582P Schematic
Date: Thursday, July 08, 2010 Sheet 12 of 48
A B C D E F G H
5 4 3 2 1

+RTCVCC 1 2 PCH_RTCRST#
R126 C192
20K_0402_1% RC Delay 18~25mS 18P_0402_50V8J
2 1 PCH_RTCX1
X1 Change to mini type
close to RAM door X1 20091102

1
1 2 3 4 +RTCVCC +CHGRTC +RTCBATT
R127 @ NC OSC R128 D1
10K_0603_5% 2 1 2
C193 NC OSC 10M_0402_5% U4A
1
1U_0402_6.3V6K 32.768KHZ_12.5PF_Q13MC14610002
REV1.0 3 1 2

2
1 2 C195 B13 D33 LPC_AD0 R129 1K_0402_5%
RTCX1 FWH0 / LAD0 LPC_AD0 <30>
D 2 1 PCH_RTCX2 D13 B33 LPC_AD1 DAN202UT106_SC70-3 D
RTCX2 FWH1 / LAD1 LPC_AD1 <30>
C32 LPC_AD2
FWH2 / LAD2 LPC_AD2 <30>
18P_0402_50V8J A32 LPC_AD3
FWH3 / LAD3 LPC_AD3 <30>
+RTCVCC 1 2 PCH_SRTCRST# PCH_RTCRST# C14 RTCRST#
20100421 Modify
R132 C34 LPC_FRAME#
+RTCVCC FWH4 / LFRAME# LPC_FRAME# <30>
20K_0402_1% RC Delay 18~25mS PCH_SRTCRST# D17 SRTCRST#
A34

RTC

LPC
R133 1 LDRQ0#
close to RAM door 2 1M_0402_5% SM_INTRUDER# A16 INTRUDER# LDRQ1# / GPIO23 F34
1 2 modify to 330K
R130 @ R134 1 2 330K_0402_1% PCH_INTVRMEN A14 AB9 SERIRQ
INTVRMEN SERIRQ SERIRQ <30>
10K_0603_5% INTVRMEN - Integrated SUS +RTCBATT
C194
1U_0402_6.3V6K
1.1V VRM Enable High - Enable Internal VRs
1 2 <33> HDA_BITCLK_AUDIO 1 2 HDA_BITCLK_PCH A30 HDA_BCLK

1
R135 33_0402_5% AK7 SATA_DTX_C_PRX_N0 SATA_DTX_C_PRX_N0 <25> @
HDA_SYNC_PCH SATA0RXN SATA_DTX_C_PRX_P0 JBATT1
1 2 D29 AK6 SATA_DTX_C_PRX_P0 <25> SATA for HDD1

+
<33> HDA_SYNC_AUDIO HDA_SYNC SATA0RXP
HDA for AUDIO R131 33_0402_5% AK11 SATA_PTX_DRX_N0
PCH_SPKR SATA0TXN SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 <25>
<33> PCH_SPKR P1 SPKR SATA0TXP AK9 SATA_PTX_DRX_P0 <25>
1 2 HDA_RST_PCH# C30
<33> HDA_RST_AUDIO# HDA_RST#
R136 33_0402_5% AH6 SATA_DTX_C_PRX_N1 SATA_DTX_C_PRX_N1 <25>
SATA1RXN SATA_DTX_C_PRX_P1
+3VS SATA1RXP AH5 SATA_DTX_C_PRX_P1 <25> SATA for ODD
R137 <33> HDA_SDIN0 G30 AH9 SATA_PTX_DRX_N1
1K_0402_5% HDA_SDIN0 SATA1TXN SATA_PTX_DRX_P1 SATA_PTX_DRX_N1 <25>
SATA1TXP AH8 SATA_PTX_DRX_P1 <25>
1 @ 2 PCH_SPKR F30 HDA_SDIN1
Have internal PD SATA2RXN AF11
2/10 SATA2, SATA3 not support on HM55

-
E32 AF9

IHDA
SERIRQ HDA_SDIN2 SATA2RXP SUYIN_060003HA002G202ZL
1 2 AF7

2
R138 SATA2TXN
F32 HDA_SDIN3 SATA2TXP AF6
C 10K_0402_5% C
AH3 20100416 add
HDA_SDOUT_PCH SATA3RXN
<33> HDA_SDOUT_AUDIO 1 2 B29 HDA_SDO SATA3RXP AH1
R139 33_0402_5% AF3
SATA3TXN
SATA3TXP AF1
PCH_GPIO33# H32

SATA
HDA_DOCK_EN# / GPIO33
SATA4RXN AD9
If GPIO33 pull down, ME will not working. GPIO33 can not pull down J30 HDA_DOCK_RST# / GPIO13 SATA4RXP AD8
For factory update ME, pull down resistor pull (manufacturing environments) SATA4TXN AD6
SATA4TXP AD5
under door.
PCH_GPIO33# PCH_JTAG_TCK M3 AD3
GPIO21 Project
PCH_JTAG_TCK JTAG_TCK SATA5RXN
K3
SATA5RXP AD1
AB3
0 NEW50/70/80/90
D PCH_JTAG_TMS JTAG_TMS SATA5TXN
1

2 K1
SATA5TXP AB1 1 NEW71/91
<30> ME_OVERRIDE PCH_JTAG_TDI JTAG_TDI +1.05VS
G Q7

JTAG
1

S PCH_JTAG_TDO J2 AF16 GPIO19 GPIO37


3

R140 2N7002_SOT23 JTAG_TDO SATAICOMPO


100K_0402_5% J4 AF15 SATA_COMP R141 1 2 37.4_0402_1% PCH_GPIO19 VGA_PRSNT_L#
PCH_JTAG_RST# TRST# SATAICOMPI

dGPU 0 0
2

PCH_SPI_CLK_1 R142 1 2 0_0402_5% PCH_SPI_CLK +3VS


BA2 SPI_CLK iGPU 0 1
PCH_SPI_CS0# R143 1 2 15_0402_5% PCH_SPI_CS0#_R AV3 R144 1 2 10K_0402_5%
SPI_CS0# SG 1 X
GPIO33 has a weak internal pull-up PAD @ PCH_SPI_CS1# AY3 T3 SATA_LED#
T6 SPI_CS1# SATALED# SATA_LED# <32> +3VS
B NOTE: Asserting the GPIO33 low on the B
rising edge of PWROK will also halt Intel PCH_SPI_MOSI_1 R145 1 2 15_0402_5% PCH_SPI_MOSI AY1 Y9 PCH_GPIO21 1 2
SPI_MOSI SATA0GP / GPIO21
Management Engine after chipset bringup R146 @ 10K_0402_5%

SPI
and disable runtime Intel Management PCH_SPI_MISO_1 R147 1 2 33_0402_5% PCH_SPI_MISO AV1 V1 PCH_GPIO19 1 2
SPI_MISO SATA1GP / GPIO19 R148 @ 10K_0402_5%
Engine features. This is a debug mode and

1
must not be asserted after manfacturing/ IBEXPEAK-M_FCBGA107
debug. R149 R150

10K_0402_5% 10K_0402_5%
+3VS

2
PCH_SPI_MOSI R157 1 @ 2 1K_0402_5%
enable iTPM: SPI_MOSI High
+1.05VS
PCH_JTAG_TCK R158 1 2 4.7K_0402_5%
+3VALW CRB 1.0 Change to 4.7K
+3VS
PCH_JTAG_TMS R151 1 @ 2 51_0402_5% U18 @ @
R478 1 2 200_0402_1% PCH_SPI_CS0# 1 8 PCH_SPI_CLK_1 1 2 1 2
R479 1 CS# VCC
2 100_0402_5% +3VS R155 1 2 3.3K_0402_5% SPI_W P1# 3 WP# SCLK 6 PCH_SPI_CLK_1 R340 10_0402_5% C557 10P_0402_50V8J
R156 1 2 3.3K_0402_5% SPI_HOLD1# 7 5 PCH_SPI_MOSI_1 For 3G team
PCH_JTAG_TDO R152 1 @ HOLD# SI Close to U5 20090915
2 51_0402_5% 4 GND SO 2 PCH_SPI_MISO_1
R480 1 2 200_0402_1%
A
R481 1 2 100_0402_5% MX25L1605DM2I-12G SOP 8P A
SA000021A00
PCH_JTAG_TDI R153 1 @ 2 51_0402_5% SPI ROM Footprint 200mil
R482 1 2 200_0402_1%
R483 1 2 100_0402_5%

PCH_JTAG_RST# R154 1 @ 2 51_0402_5%


R484 1 2 20K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
R485 1 2 10K_0402_5% 2009/08/01 2010/08/01 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (1/9) SATA,HDA,SPI, LPC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW71 M/B LA-6582P Schematic
Date: Thursday, July 08, 2010 Sheet 13 of 48
5 4 3 2 1
5 4 3 2 1

U4B 1. Connect Directly


REV1.0 EXPRESS CARD, MINI1, MINI2
PCIE_DTX_C_PRX_N1 BG30 B9 EC_LID_OUT# 2. Level Shift1, Pull-Up to +3VS
<27> PCIE_DTX_C_PRX_N1 PERN1 SMBALERT# / GPIO11 EC_LID_OUT# <30>
PCIE_DTX_C_PRX_P1 BJ30
<27> PCIE_DTX_C_PRX_P1 PERP1 CLOCK GEN, DIMM1, DIMM2
For PCIE LAN <27> PCIE_PTX_C_DRX_N1 C197 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_N1 BF29 H14 PCH_SMBCLK PCH_SMBCLK <12,26>
C198 2 0.1U_0402_16V7K PCIE_PTX_DRX_P1 PETN1 SMBCLK
<27> PCIE_PTX_C_DRX_P1 1 BH29 PETP1 PCH_SMBDATA
3. Level Shift2, Pull-Up to +3VS
SMBDATA C8 PCH_SMBDATA <12,26>
<26> PCIE_DTX_C_PRX_N2
PCIE_DTX_C_PRX_N2 AW30 LAN
PCIE_DTX_C_PRX_P2 BA30 PERN2
<26> PCIE_DTX_C_PRX_P2
C199 2 0.1U_0402_16V7K PCIE_PTX_DRX_N2 BC30 PERP2 PCH_GPIO60
4. Level Shift3, Pull-Up to +3VS
For Wireless LAN <26> PCIE_PTX_C_DRX_N2
C200 2
1
0.1U_0402_16V7K PCIE_PTX_DRX_P2 BD30 PETN2 SML0ALERT# / GPIO60 J14
CPU & PCH XDP
<26> PCIE_PTX_C_DRX_P2 1 PETP2
D
SML0CLK C6 D
AU30

SMBus
PERN3
AT30 PERP3 SML0DATA G8
AU32 PETN3
AV32 PETP3
M14 PCH_GPIO74
SML1ALERT# / GPIO74
BA32 PERN4
BB32 E10 PCH_SML1CLK
PERP4 SML1CLK / GPIO58
BD32 PETN4
BE32 G12 PCH_SML1DAT
PETP4 SML1DATA / GPIO75

PCI-E*
BF33 PERN5
BH33 T13 +3VALW
PERP5 CL_CLK1

Controller
BG32 PETN5
BJ32 PETP5 CL_DATA1 T11

2
Link
BA34 T9 R159
PERN6 CL_RST1# 10K_0402_5%
AW34 PERP6
BC34 PETN6
BD34

1
PETP6 PEG_CLKREQ#
PEG_A_CLKRQ# / GPIO47 H1
AT34 PERN7
2/10 PCIE7, PCIE8 not support on HM55 AU34 20090915 Add
PERP7
AU36 PETN7 CLKOUT_PEG_A_N AD43
AV36 PETP7 CLKOUT_PEG_A_P AD45

BG34 PERN8 CLKOUT_DMI_N AN4 CLK_CPU_DMI# <5>

PEG
BJ34 PERP8 CLKOUT_DMI_P AN2 CLK_CPU_DMI <5>
BG36 PETN8
C BJ36 C
PETP8
CLKOUT_DP_N / CLKOUT_BCLK1_N AT1 CLK_CPU_DP# <5>
CLKOUT_DP_P / CLKOUT_BCLK1_P AT3 CLK_CPU_DP <5>
<27> CLK_PCIE_LAN# AK48 CLKOUT_PCIE0N
For PCIE LAN <27> CLK_PCIE_LAN AK47 CLKOUT_PCIE0P

From CLK BUFFER


CLKIN_DMI_N AW24 CLK_BUF_CPU_DMI# <12>
R164 1 2 0_0402_5% PCH_GPIO73 P9 BA24
<27> LAN_CLKREQ# PCIECLKRQ0# / GPIO73 CLKIN_DMI_P CLK_BUF_CPU_DMI <12>

For Wireless LAN <26> CLK_PCIE_MINI1# AM43 CLKOUT_PCIE1N CLKIN_BCLK_N AP3 CLK_BUF_CPU_BCLK# <12>
<26> CLK_PCIE_MINI1 AM45 CLKOUT_PCIE1P CLKIN_BCLK_P AP1 CLK_BUF_CPU_BCLK <12>
R165 1 2 0_0402_5% PCH_GPIO18 U4
<26> MINI1_CLKREQ# PCIECLKRQ1# / GPIO18
CLKIN_DOT_96N F18 CLK_BUF_DREF_96M# <12> 6/9 MOW23 Request add 25MHz crystal
E18 CLK_BUF_DREF_96M <12>
AM47
CLKIN_DOT_96P supporting Integrated Graphics
CLKOUT_PCIE2N
AM48 CLKOUT_PCIE2P
CLKIN_SATA_N / CKSSCD_N AH13 CLK_BUF_PCIE_SATA# <12>
PCH_GPIO20 N4 AH12
PCIECLKRQ2# / GPIO20 CLKIN_SATA_P / CKSSCD_P CLK_BUF_PCIE_SATA <12>
1 2 1 2
AH42 P41 R338 10_0402_5% C555 10P_0402_50V8J
CLKOUT_PCIE3N REFCLK14IN
AH41 CLKOUT_PCIE3P CLK_BUF_ICH_14M <12>
PCH_GPIO25 A8 J42
PCIECLKRQ3# / GPIO25 CLKIN_PCILOOPBACK CLK_PCI_FB <17>
C203
27P_0402_50V8J
AM51 AH51 XTAL25_IN 1 2
CLKOUT_PCIE4N XTAL25_IN XTAL25_OUT
AM53 CLKOUT_PCIE4P XTAL25_OUT AH53

1
B B
PCH_GPIO26 M9 AF38 XCLK_RCOMP R169 1 2 90.9_0402_1% +1.05VS R170 Y2
PCIECLKRQ4# / GPIO26 XCLK_RCOMP 1M_0402_5% 25MHZ_20PF_7A25000012

2
+3VS Change to 5x3.2
AJ50 T45 Project Port ID

2
CLKOUT_PCIE5N CLKOUTFLEX0 / GPIO64
AJ52 CLKOUT_PCIE5P 1 2

PCH_GPIO44 H6 P43 PROJECT_ID1 R171 1 2 10K_0402_5% C204


Clock Flex

PCIECLKRQ5# / GPIO44 CLKOUTFLEX1 / GPIO65 27P_0402_50V8J


1 2
@ R172 10K_0402_5%
AK53 T42 PROJECT_ID0 @ R174 1 2 10K_0402_5%
CLKOUT_PEG_B_N CLKOUTFLEX2 / GPIO66
AK51 CLKOUT_PEG_B_P 1 2
R175 10K_0402_5%
PCH_GPIO56 P13 N50 +3VS
+3VS PEG_B_CLKRQ# / GPIO56 CLKOUTFLEX3 / GPIO67

2
IBEXPEAK-M_FCBGA107

PCH_SML1CLK 6 1 EC_SMB_CK2 EC_SMB_CK2 <30>


MINI1_CLKREQ# R177 1 2 10K_0402_5% 0602 GPIO65 no use
PCH_GPIO20 R178 1 2 10K_0402_5% 2N7002DW -T/R7_SOT363-6
+3VALW PULL HIGH:PVT Q9A
PULL DOWN:DVT
+3VS
Pull high +3VS at KB926 side
EC_LID_OUT# R179 1 2 10K_0402_5% GPIO66 6L/8L
PCH_SMBCLK R180 1 2 2.2K_0402_5%

5
PCH_SMBDATA R181 1 2 2.2K_0402_5% SATA register separe
PCH_GPIO60 R182 1 2 10K_0402_5% PCH_SML1DAT EC_SMB_DA2
A
+3VALW 0 6L * 3 4 EC_SMB_DA2 <30> A

PCH_SML1CLK R183 1 2 2.2K_0402_5%


GPIO66 2N7002DW -T/R7_SOT363-6
2009/09/23:Change to +3VALW PCH_SML1DAT R184 1 2 2.2K_0402_5%
1 8L Q9B
PCH_GPIO26 R166 1 2 10K_0402_5%
PCH_GPIO74 R185 1 2 10K_0402_5%

PCH_GPIO25 R186 1 2 10K_0402_5%


Security Classification Compal Secret Data Compal Electronics, Inc.
2009/08/13: Change back to +3VALW Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title
PCH_GPIO44 R187 1 2 10K_0402_5%
PCH_GPIO56 R188 1 2 10K_0402_5% THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (2/9) PCIE, SMBUS, CLK
PCH_GPIO73 R189 1 2 10K_0402_5% Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW71 M/B LA-6582P Schematic
Date: Thursday, July 08, 2010 Sheet 14 of 48
5 4 3 2 1
5 4 3 2 1

D U4C D
H_FDI_TXN0 H_FDI_TXN[0..7]
DMI_HTX_PRX_N[0..3] DMI_HTX_PRX_N0 BC24
REV1.0 FDI_RXN0 BA18
BH17 H_FDI_TXN1
H_FDI_TXN[0..7] <4>
<4> DMI_HTX_PRX_N[0..3] DMI0RXN FDI_RXN1 H_FDI_TXP[0..7]
DMI_HTX_PRX_N1 BJ22 BD16 H_FDI_TXN2
DMI_HTX_PRX_P[0..3] DMI1RXN FDI_RXN2 H_FDI_TXP[0..7] <4>
DMI_HTX_PRX_N2 AW20 BJ16 H_FDI_TXN3
<4> DMI_HTX_PRX_P[0..3] DMI2RXN FDI_RXN3
DMI_HTX_PRX_N3 BJ20 BA16 H_FDI_TXN4
DMI_PTX_HRX_N[0..3] DMI3RXN FDI_RXN4 H_FDI_TXN5
<4> DMI_PTX_HRX_N[0..3] FDI_RXN5 BE14
DMI_HTX_PRX_P0 BD24 BA14 H_FDI_TXN6
DMI_PTX_HRX_P[0..3] DMI_HTX_PRX_P1 DMI0RXP FDI_RXN6 H_FDI_TXN7
<4> DMI_PTX_HRX_P[0..3] BG22 DMI1RXP FDI_RXN7 BC12
DMI_HTX_PRX_P2 BA20
DMI_HTX_PRX_P3 DMI2RXP H_FDI_TXP0
BG20 DMI3RXP FDI_RXP0 BB18
BF17 H_FDI_TXP1
DMI_PTX_HRX_N0 FDI_RXP1 H_FDI_TXP2
BE22 DMI0TXN FDI_RXP2 BC16
+3VS DMI_PTX_HRX_N1 BF21 BG16 H_FDI_TXP3
DMI_PTX_HRX_N2 DMI1TXN FDI_RXP3 H_FDI_TXP4
BD20 DMI2TXN FDI_RXP4 AW16
1 2 PM_CLKRUN# DMI_PTX_HRX_N3 BE18 BD14 H_FDI_TXP5
R190 8.2K_0402_5% DMI3TXN FDI_RXP5 H_FDI_TXP6
FDI_RXP6 BB14
DMI_PTX_HRX_P0 BD22 BD12 H_FDI_TXP7
DMI_PTX_HRX_P1 DMI0TXP FDI_RXP7
BH21 DMI1TXP
+3VALW DMI_PTX_HRX_P2 BC20
DMI_PTX_HRX_P3 DMI2TXP
BD18 DMI3TXP FDI_INT BJ14 H_FDI_INT <4>
+1.05VS

DMI
FDI
1 2 SUS_PW R_ACK BF13 H_FDI_FSYNC0 <4>
R191 10K_0402_5% R192 FDI_FSYNC0
BH25 DMI_ZCOMP
1 2 PCH_GPIO72 49.9_0402_1% BH13 H_FDI_FSYNC1 <4>
R193 8.2K_0402_5% DMI_COMP FDI_FSYNC1
1 2 BF25 DMI_IRCOMP
1 2 EC_SW I# BJ12 H_FDI_LSYNC0 <4>
R194 10K_0402_5% FDI_LSYNC0
1 2 PCH_PCIE_W AKE# R195 Change to 10K for WW37 BG14
20090916 FDI_LSYNC1 H_FDI_LSYNC1 <4>
C R195 10K_0402_5% C
1 @ 2 PM_SLP_LAN#
R196 10K_0402_5%

XDP_DBRESET# T6 J12 PCH_PCIE_W AKE#


<5> XDP_DBRESET# SYS_RESET# WAKE# PCH_PCIE_W AKE# <26,27>

SYS_PW ROK R197 2 1 0_0402_5% SYS_PW ROK_R M6 Y1 PM_CLKRUN#


SYS_PWROK CLKRUN# / GPIO32 PM_CLKRUN# <30>
VGATE R198 2 @ 1 0_0402_5%

System Power Management


SYS_PW ROK B17 PWROK

K5 P8 PCH_GPIO61 @ PAD
MEPWROK SUS_STAT# / GPIO61 T7

LAN_RST# A10 LAN_RST# SUSCLK / GPIO62 F3 PCH_SUSCLK <30> 32.768KHZ ouput for remove EC crystal
20091103

<5> PM_DRAM_PW RGD D9 DRAMPWROK SLP_S5# / GPIO63 E4 PM_SLP_S5# <30>

PCH_RSMRST# C16 H7 PM_SLP_S4# <30>


RSMRST# SLP_S4#

SUS_PW R_ACK M1 P12 PM_SLP_S3# <30>


B <30> SUS_PW R_ACK SUS_PWR_DN_ACK / GPIO30 SLP_S3# B
10/2
R199 Intel suggestion change to 10K
PBTN_OUT# P5 K8 PM_SLP_M# @ PAD @
<30> PBTN_OUT# PWRBTN# SLP_M# T9
+3VALW 1 2 R200 2 1 0_0402_5%
R199 10K_0402_5% Q11
1 2 PCH_ACIN P7 N2 PM_SLP_DSW # @ PAD MMBT3906_SOT23-3
<30> EC_ACIN ACPRESENT / GPIO31 TP23 T10
D2 PCH_RSMRST# 1 3

C
EC_RSMRST# <30>
CH751H-40PT_SOD323-2

E
PCH_GPIO72 A6 BJ10
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC <5>

B
2
R201 1 2 +3VALW
EC_SW I# F14 F6 PM_SLP_LAN# 10K_0402_5% R202 4.7K_0402_5%
<30> EC_SW I# RI# SLP_LAN# / GPIO29
D3A

2
IBEXPEAK-M_FCBGA107 1
6
R203 2 @ 1 0_0402_5% 2
+3VS BAV99DW -7_SOT363

D3B
5

U6 4
2 EC_PW ROK 3
P

B EC_PW ROK <30>


SYS_PW ROK 4 5
Y

1
1 VGATE
A VGATE <12,45>
G

BAV99DW -7_SOT363 R204


MC74VHC1G08DFT2G_SC70-5 2.2K_0402_5%
3

U6 change to SA00000OH00

2
A A

SYS_PW ROK 1 2
R205 10K_0402_5%

EC_PW ROK 1
R206
2
10K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title
LAN_RST# 1
R207
2
10K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (3/9) DMI, FDI, PM
No used Integrated LAN, Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
connecting LAN_RST# to GND DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW71 M/B LA-6582P Schematic
Date: Thursday, July 08, 2010 Sheet 15 of 48
5 4 3 2 1
5 4 3 2 1

U4D

ENBKL ENBKL T48 BJ46


<30> ENBKL L_BKLTEN SDVO_TVCLKINN
<22> PCH_ENVDD T47 L_VDD_EN SDVO_TVCLKINP BG46

1
D <22> DPST_PW M Y48 L_BKLTCTL SDVO_STALLN BJ48 D
R209 BG48
PCH_LCD_CLK SDVO_STALLP
100K_0402_5% <22> PCH_LCD_CLK AB48 L_DDC_CLK
<22> PCH_LCD_DATA PCH_LCD_DATA Y45 BF45
L_DDC_DATA SDVO_INTN
BH45

2
LCTLA_CLK SDVO_INTP
AB46 L_CTRL_CLK
LCTLB_DATA V48 SDVO_CTRLDATA strap Pull High at Level Shift Page
L_CTRL_DATA
R210 1 2 LVDS_IBG AP39 T51
LVD_IBG SDVO_CTRLCLK SDVO_SCLK <24>
2.37K_0402_1% AP41 T53
LVD_VBG SDVO_CTRLDATA SDVO_SDATA <24>
R211 1 2 LVD_VREF AT43
0_0402_5% LVD_VREFH R212 1
AT42 LVD_VREFL DDPB_AUXN BG44 2 100K_0402_5%
DDPB_AUXP BJ44
AU38 PCH_DPB_HPD
DDPB_HPD PCH_DPB_HPD <24>

LVDS
PCH_TXCLK- AV53
<22> PCH_TXCLK- LVDSA_CLK#
PCH_TXCLK+ AV51 BD42 PCH_DPB_N0 C205 2 1HDMI@ 0.1U_0402_16V7K PCH_TMDS_D2# <24>
<22> PCH_TXCLK+ LVDSA_CLK DDPB_0N
BC42 PCH_DPB_P0 C206 2 1HDMI@ 0.1U_0402_16V7K PCH_TMDS_D2 <24> HDMI D2
PCH_TXOUT0- DDPB_0P PCH_DPB_N1 C207
<22> PCH_TXOUT0- BB47 LVDSA_DATA#0 DDPB_1N BJ42 2 1HDMI@ 0.1U_0402_16V7K PCH_TMDS_D1# <24>
PCH_TXOUT1- BA52 BG42 PCH_DPB_P1 C208 2 1HDMI@ 0.1U_0402_16V7K PCH_TMDS_D1 <24> HDMI D1

Digital Display Interface


<22> PCH_TXOUT1- LVDSA_DATA#1 DDPB_1P
PCH_TXOUT2- AY48 BB40 PCH_DPB_N2 C209 2 1HDMI@ 0.1U_0402_16V7K PCH_TMDS_D0# <24>
<22> PCH_TXOUT2- LVDSA_DATA#2 DDPB_2N
AV47 BA40 PCH_DPB_P2 C210 2 1HDMI@ 0.1U_0402_16V7K PCH_TMDS_D0 <24> HDMI D0
+3VS LVDSA_DATA#3 DDPB_2P PCH_DPB_N3 C211
DDPB_3N AW38 2 1HDMI@ 0.1U_0402_16V7K PCH_TMDS_CK# <24>
PCH_TXOUT0+ BB48 BA38 PCH_DPB_P3 C212 2 1HDMI@ 0.1U_0402_16V7K PCH_TMDS_CK <24> HDMI CLK
<22> PCH_TXOUT0+ LVDSA_DATA0 DDPB_3P
PCH_TXOUT1+ BA50
<22> PCH_TXOUT1+ LVDSA_DATA1
R215 1 2 10K_0402_5% LCTLA_CLK PCH_TXOUT2+ AY49
<22> PCH_TXOUT2+ LVDSA_DATA2
AV48 LVDSA_DATA3 DDPC_CTRLCLK Y49
R216 1 2 10K_0402_5% LCTLB_DATA AB49
DDPC_CTRLDATA
C R217 1 2 2.2K_0402_5% PCH_CRT_CLK AP48 C
LVDSB_CLK#
AP47 LVDSB_CLK DDPC_AUXN BE44
R218 1 2 2.2K_0402_5% PCH_CRT_DATA BD44
DDPC_AUXP
AY53 LVDSB_DATA#0 DDPC_HPD AV40
AT49 LVDSB_DATA#1
AU52 LVDSB_DATA#2 DDPC_0N BE40
AT53 LVDSB_DATA#3 DDPC_0P BD40
DDPC_1N BF41
AY51 LVDSB_DATA0 DDPC_1P BH41
AT48 LVDSB_DATA1 DDPC_2N BD38
AU50 LVDSB_DATA2 DDPC_2P BC38
AT51 LVDSB_DATA3 DDPC_3N BB36
DDPC_3P BA36

1 2 PCH_CRT_B PCH_CRT_B AA52 U50


<23> PCH_CRT_B CRT_BLUE DDPD_CTRLCLK
R219 150_0402_1% PCH_CRT_G AB53 U52
<23> PCH_CRT_G CRT_GREEN DDPD_CTRLDATA
1 2 PCH_CRT_G PCH_CRT_R AD53
<23> PCH_CRT_R CRT_RED
R220 150_0402_1%
1 2 PCH_CRT_R BC46
R221 150_0402_1% PCH_CRT_CLK DDPD_AUXN
<23> PCH_CRT_CLK V51 CRT_DDC_CLK DDPD_AUXP BD46
PCH_CRT_DATA V53 AT38
<23> PCH_CRT_DATA CRT_DDC_DATA DDPD_HPD

DDPD_0N BJ40
<23> PCH_CRT_HSYNC Y53 CRT_HSYNC DDPD_0P BG40
<23> PCH_CRT_VSYNC Y51 CRT_VSYNC DDPD_1N BJ38
DDPD_1P BG38

CRT
DDPD_2N BF37
CRT_IREF AD48 BH37
B DAC_IREF DDPD_2P B
AB51 CRT_IRTN DDPD_3N BE36
REV1.0 DDPD_3P BD36

IBEXPEAK-M_FCBGA107
1

R222
1K_0402_1%

2/3 Change to 1K_0402_0.5% from Intel


2

Suggestion. (EDS 1.0 is incorrect)

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (4/9) LVDS, CRT, DPI
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW71 M/B LA-6582P Schematic
Date: Thursday, July 08, 2010 Sheet 16 of 48
5 4 3 2 1
5 4 3 2 1

U4E
+3VS +3VS
H40
N34
AD0 REV1.0 NV_CE#0 AY9
BD1 U7 change to SA00000OH00
AD1 NV_CE#1
C44 AD2 NV_CE#2 AP15

5
R229 1 2 8.2K_0402_5% PCI_PIRQA# A38 BD8 U7
R223 8.2K_0402_5% PCI_PIRQG# AD3 NV_CE#3 PLT_RST#
1 2 C36 2 B

P
R224 8.2K_0402_5% PCI_PIRQC# AD4
1 2 J34 AD5 NV_DQS0 AV9 Y 4 PLT_RST_BUF# <26>
R225 1 2 8.2K_0402_5% PCI_SERR# A40 BG8 1
AD6 NV_DQS1 A

1
D45 AD7
E36 AP7 MC74VHC1G08DFT2G_SC70-5 R226

3
AD8 NV_DQ0 / NV_IO0 100K_0402_5%
H48 AD9 NV_DQ1 / NV_IO1 AP6
E40 AD10 NV_DQ2 / NV_IO2 AT6
D C40 AT9 D

2
R230 8.2K_0402_5% PCI_PLOCK# AD11 NV_DQ3 / NV_IO3
1 2 M48 AD12 NV_DQ4 / NV_IO4 BB1
R227 1 2 8.2K_0402_5% PCI_PERR# M45 AV6
R231 8.2K_0402_5% PCI_PIRQE# AD13 NV_DQ5 / NV_IO5
1 2 F53 AD14 NV_DQ6 / NV_IO6 BB3
R232 1 2 8.2K_0402_5% PCI_STOP# M40 BA4
AD15 NV_DQ7 / NV_IO7

NVRAM
M43 AD16 NV_DQ8 / NV_IO8 BE4
J36 AD17 NV_DQ9 / NV_IO9 BB6
K48 AD18 NV_DQ10 / NV_IO10 BD6
F40 AD19 NV_DQ11 / NV_IO11 BB7
C42 AD20 NV_DQ12 / NV_IO12 BC8
R228 1 2 8.2K_0402_5% PCI_REQ0# K46 BJ8
R235 8.2K_0402_5% PCI_PIRQB# AD21 NV_DQ13 / NV_IO13
1 2 M51 AD22 NV_DQ14 / NV_IO14 BJ6
R236 1 2 8.2K_0402_5% PCI_PIRQF# J52 BG6
R237 8.2K_0402_5% PCI_REQ3# AD23 NV_DQ15 / NV_IO15
1 2 K51 AD24
L34 BD3 NV_ALE
AD25 NV_ALE NV_CLE
F42 AD26 NV_CLE AY6
J40 AD27
G46 AD28
R238 1 2 8.2K_0402_5% PCI_IRDY# F44 AU2 NV_RCOMP R239 1 @ 2 32.4_0402_1% +1.8VS
R240 8.2K_0402_5% PCI_PIRQD# AD29 NV_RCOMP
1 2 M47 AD30

PCI
R241 1 2 8.2K_0402_5% DGPU_SELECT# H36 AV7
R242 8.2K_0402_5% PCI_DEVSEL# AD31 NV_RB# NV_ALE R247 1 @
1 2 2 1K_0402_5%
J50 C/BE0# NV_WR#0_RE# AY8
G42 C/BE1# NV_WR#1_RE# AY5
H47 NV_CLE R248 1 @ 2 1K_0402_5%
C/BE2#
G34 C/BE3# NV_WE#_CK0 AV11
R243 1 2 8.2K_0402_5% PCI_FRAME# BF5
NV_WE#_CK1
R244 1 2 8.2K_0402_5% PCI_REQ1# PCI_PIRQA# G38 PIRQA#
Intel Anti-Theft Techonlogy
R245 1 2 8.2K_0402_5% PCI_PIRQH# PCI_PIRQB# H51 PIRQB#
C R246 1 2 8.2K_0402_5% PCI_TRDY# PCI_PIRQC# B37 PIRQC# USBP0N H18 USB20_N0
USB20_N0 <29> High=Endabled C
PCI_PIRQD# A44 PIRQD# USBP0P J18 USB20_P0
USB20_P0 <29> USB/B (Left Side Low) NV_ALE
USB20_N1 Low=Disable(floating)
PCI_REQ0# F51 REQ0#
USBP1N
USBP1P
A18
C18 USB20_P1
USB20_N1
USB20_P1
<29>
<29> USB Port (Left Side High) *
A16 swap overide Strap/Top-Block PCI_REQ1# A46 N20 USB20_N2
REQ1# / GPIO50 USBP2N USB20_N2 <29>
Swap Override jumper DGPU_SELECT# B45 REQ2# / GPIO52 USBP2P P20 USB20_P2
USB20_P2 <29> USB/B (Right Side) DMI Termination Voltage
PCI_REQ3# M53 J20
REQ3# / GPIO54 USBP3N
Low=A16 swap USBP3P L20 EHCI 1 Set to Vcc when HIGH
override/Top-Block PCI_GNT0# F48 GNT0# USBP4N F20 NV_CLE
PCI_GNT3# Swap Override enabled PCI_GNT1# K45 GNT1# / GPIO51 USBP4P G20 Set to Vss when LOW
High=Default * @ DGPU_PW MSEL# F36 A20
T11 PAD GNT2# / GPIO53 USBP5N
PCI_GNT3# H53 C20
GNT3# / GPIO55 USBP5P
USBP6N M22
PCI_PIRQE# B41 N22 2/10 USB6, USB7 not NV_ALE

PCI_PIRQF# PIRQE# / GPIO2 USBP6P Enable Intel Anti-Theft
K53 PIRQF# / GPIO3 USBP7N B21 support on HM55
PCI_PIRQG# A36 D21 Technology 8.2K PU to +3VS
PCI_PIRQH# PIRQG# / GPIO4 USBP7P USB20_N8
A48 H22


PIRQH# / GPIO5 USBP8N USB20_N8 <22>
USBP8P J22 USB20_P8
USB20_P8 <22> CMOS Camera (LVDS) Disable Intel Anti-Theft

USB
@ TP_PCI_RST# K6 E22 USB20_N9 Technology floating(internal PD)
T12 PAD PCIRST# USBP9N USB20_N9 <29>
F22 USB20_P9 Card Reader
USBP9P USB20_P9 <29>
PCI_SERR# E44 SERR# USBP10N A22 NV_CLE
PCI_PERR# E50 PERR# USBP10P C22 Del SIM Card USB
USBP11N G24 USB20_N11
USB20_N11 <29> EHCI 2 DMI termination voltage.
H24 USB20_P11 Bluetooth weak internal PU, don't PD
USBP11P USB20_P11 <29>
PCI_IRDY# A42 L24 USB20_N12
IRDY# USBP12N USB20_N12 <26>
H44 M24 USB20_P12 Mini Card(WLAN)
PAR USBP12P USB20_P12 <26>
PCI_DEVSEL# F46 A24
DEVSEL# USBP13N
PCI_FRAME# C46 FRAME# USBP13P C24 Del 3G Card USB
B PCI_PLOCK# B
D49 PLOCK#
B25 USB_BIAS 1 2
PCI_STOP# USBRBIAS# R249
D41 STOP#
PCI_TRDY# C48 D25 22.6_0402_1%
TRDY# USBRBIAS
M7 PME#
N16 USB_OC#0_R R250 1 2 0_0402_5% (For USB Port0, 2)
OC0# / GPIO59 USB_OC#0 <29>
PLT_RST# D5 J16 USB_OC#1_R
<5,27,30> PLT_RST# PLTRST# OC1# / GPIO40
F16 USB_OC#2_R R251 1 2 0_0402_5% (For USB Port1)
OC2# / GPIO41 USB_OC#2 <29>
N52 L16 USB_OC#3_R
CLKOUT_PCI0 OC3# / GPIO42 USB_OC#4_R
P53 CLKOUT_PCI1 OC4# / GPIO43 E14
P46 G16 USB_OC#5_R
R252 CLKOUT_PCI2 OC5# / GPIO9
<30> CLK_PCI_LPC 1 2 22_0402_5% CLK_PCI_LPC_R P51 CLKOUT_PCI3 OC6# / GPIO10 F12 USB_OC#6_R RP1
R253 1 2 22_0402_5% CLK_PCI_FB_R P48 T15 USB_OC#7_R USB_OC#3_R 1 8 +3VALW
<14> CLK_PCI_FB CLKOUT_PCI4 OC7# / GPIO14 USB_OC#5_R 2 7
USB_OC#6_R 3 6
2008/1/6 2009MOW01 change to 22 ohm IBEXPEAK-M_FCBGA107 USB_OC#7_R 4 5
<BOM Structure> OC[0..3] use for EHCI 1
10K_1206_8P4R_5%
OC[4..7] use for EHCI 2

Boot BIOS Strap


PCI_GNT0# R254 1 @ 2 1K_0402_5%
PCI_GNT#0 PCI_GNT#1 Boot BIOS Location Have internal PU USB_OC#1_R R255 1 2 10K_0402_5%

0 0 LPC PCI_GNT1# R256 1 @ 2 1K_0402_5% USB_OC#4_R R257 1 2 10K_0402_5%


Have internal PU
0 1 Reserved (NAND)
A
PCI_GNT3# R258 1 @ 2 1K_0402_5% A
1 0 PCI Have internal PU

* 1 1 SPI

A16 swap override Strap/Top-Block


Security Classification Compal Secret Data Compal Electronics, Inc.
Swap Override jumper Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

PCI_GNT#3 Low = A16 swap THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (5/9) PCI, USB, VRAM
High = Default Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW71 M/B LA-6582P Schematic
Date: Thursday, July 08, 2010 Sheet 17 of 48
5 4 3 2 1
5 4 3 2 1

+3VS

R259 1 2 10K_0402_5% DGPU_EDIDSEL#


R260 1 2 10K_0402_5% DGPU_HPD_INT#
U4F
R261 1 2 10K_0402_5% VGA_PRSNT_R#
R262 1 2 10K_0402_5% VGA_PRSNT_L# CRT_DET Y3 AH45
BMBUSY# / GPIO0 CLKOUT_PCIE6N
CLKOUT_PCIE6P AH46
R263 1 @ 2 10K_0402_5% DGPU_HOLD_RST# DGPU_EDIDSEL# C38 TACH1 / GPIO1
R264 1 2 10K_0402_5% PCH_GPIO22 DGPU_HPD_INT# D37 TACH2 / GPIO6
D
CLKOUT_PCIE7N AF48 D

MISC
R265 1 2 10K_0402_5% PCH_GPIO39 EC_SCI# J32 AF47 +3VS
<30> EC_SCI# TACH3 / GPIO7 CLKOUT_PCIE7P
EC_SMI# F10
<30> EC_SMI# GPIO8
R266 1 2 10K_0402_5% DGPU_PW R_EN EC_GA20 R267 1 2 10K_0402_5%
PCH_GPIO12 K9
(GPIO8 Should not be Pull-Low) U2 EC_GA20
R291 1 LAN_PHY_PWR_CTRL / GPIO12 A20GATE EC_GA20 <30>
2 10K_0402_5% CRT_DET EC_KBRST# R269 1 2 10K_0402_5%
PCH_GPIO15 T7
R270 1 GPIO15
2 10K_0402_5% PCH_GPIO48
R271 1 2 10K_0402_5% PCH_TEMP_ALERT# DGPU_HOLD_RST# AA2 AM3
SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLK_CPU_BCLK# <5>
R300 1 2 10K_0402_5% DGPU_PW ROK_1 DGPU_PW ROK_1 F38 AM1
20090915 Add TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P CLK_CPU_BCLK <5>
R273 1 2 10K_0402_5% PCH_GPIO34 PCH_GPIO22 Y7 BG10
SCLOCK / GPIO22 PECI H_PECI <5>

GPIO
R274 1 2 10K_0402_5% EC_SCI#
GPIO24 change PU +3VS to +3VALW PCH_GPIO24 H10 T1 EC_KBRST#
20090916 GPIO24 RCIN# EC_KBRST# <30>
+3VALW PCH_GPIO27 AB12 BE10
GPIO27 PROCPWRGD H_CPUPW RGD <5>

CPU
R275 1 2 10K_0402_5% PCH_GPIO12 PCH_GPIO28 V13 BD10 THRMTRIP_PCH# 2 1 H_THERMTRIP#
GPIO28 THRMTRIP# H_THERMTRIP# <5>
R277 1 2 10K_0402_5% EC_SMI# R276 56_0402_5%
PCH_GPIO34 M11 2 1 +1.05VS
R279 1 STP_PCI# / GPIO34
2 1K_0402_5% PCH_GPIO15 WW46 Platform/Design Updates R278 56_0402_5%
10/7 Not Use PCH_GPIO15 PU 1K to +3V PCH_GPIO35 V6 SATACLKREQ# / GPIO35 2008/11/17 54.9 1% ->56 5%
R268 1 @ 2 10K_0402_5% PCH_GPIO24 DGPU_PW R_EN AB7 BA22
SATA2GP / GPIO36 TP1
R280 1 2 10K_0402_5% PCH_GPIO28 VGA_PRSNT_L# AB13 AW22
R281 10K_0402_5% PCH_GPIO57 SATA3GP / GPIO37 TP2
1 2
C R282 1 2 10K_0402_5% PCH_GPIO45 VGA_PRSNT_R# V3 BB22 C
R283 10K_0402_5% RST_GATE SLOAD / GPIO38 TP3
1 2
PCH_GPIO39 P3 AY45
SDATAOUT0 / GPIO39 TP4
PCH_GPIO45 H3 AY46
PCIECLKRQ6# / GPIO45 TP5 MAINPW ON <37,38>
R286 1 2 10K_0402_5% DGPU_HOLD_RST# <10> RST_GATE RST_GATE F1 AV43
PCIECLKRQ7# / GPIO46 TP6 R288

1
PCH_GPIO48 AB6 AV45 @ 330_0402_5% C
R287 1 @ SDATAOUT1 / GPIO48 TP7
2 10K_0402_5% DGPU_PW ROK_1 +1.05VS 1 2 2 @
PCH_TEMP_ALERT# AA4 AF13 B Q12
<30> PCH_TEMP_ALERT# SATA5GP / GPIO49 TP8
R289 1 2 10K_0402_5% PCH_GPIO35 E 2SC2411KT146_SOT23-3

3
PCH_GPIO57 F8 M18
R290 1 @ GPIO57 TP9
2 10K_0402_5% PCH_GPIO27
GPIO27 (Have internal Pull-High) N18 H_THERMTRIP#
TP10
High: VCCVRM VR Enable A4 AJ24
VSS_NCTF_1 TP11
Low: VCCVRM VR Disable A49

NCTF
VSS_NCTF_2

RSVD
A5 VSS_NCTF_3 TP12 AK41
A50 VSS_NCTF_4
A52 VSS_NCTF_5 TP13 AK42
GPIO19 GPIO37 A53
B2
VSS_NCTF_6
M32
PCH_GPIO19 VGA_PRSNT_L# VSS_NCTF_7 TP14
B4 VSS_NCTF_8
B52 VSS_NCTF_9 TP15 N32
dGPU 0 0 B53
BE1
VSS_NCTF_10
M30
VSS_NCTF_11 TP16
iGPU 0 1 BE53
BF1
VSS_NCTF_12
N30
B VSS_NCTF_13 TP17 B
SG 1 0 BF53
BH1
VSS_NCTF_14
H12
VSS_NCTF_15 TP18
BH2 VSS_NCTF_16
BH52 VSS_NCTF_17 TP19 AA23
BH53 VSS_NCTF_18
BJ1 VSS_NCTF_19 NC_1 AB45
BJ2 VSS_NCTF_20
BJ4 VSS_NCTF_21 NC_2 AB38
BJ49 VSS_NCTF_22
BJ5 VSS_NCTF_23 NC_3 AB42
BJ50 VSS_NCTF_24
GPIO27 BJ52 VSS_NCTF_25 NC_4 AB41
On-Die PLL Voltage Regulator BJ53 VSS_NCTF_26
This signal has a weak internal pull up D1 T39


VSS_NCTF_27 NC_5 INIT3_3V
D2

:On-Die
VSS_NCTF_28
H voltage regulator enable
* L On-Die PLL Voltage Regulator disable
D53
E1
VSS_NCTF_29
VSS_NCTF_30 INIT3_3V# P6 (Have internal PD,Do not pull high) This signal has weak internal
E53 VSS_NCTF_31 PU, can't pull low
TP24_SST @
REV1.0 TP24 C10 PAD T13
GPIO8 IBEXPEAK-M_FCBGA107
This signal has a weak internal pull up
can't Pull low


GPIO15
L Intel ME Crypto Transport
Layer Security(TLS) chiper suite *
A A


with no confidentiality
H Intel ME Crypto Transport
Layer Security(TLS) chiper suite
with confidentiality
Security Classification Compal Secret Data Compal Electronics, Inc.
it have weak internal PU 20K Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (6/9) GPIO, CPU, MISC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW71 M/B LA-6582P Schematic
Date: Thursday, July 08, 2010 Sheet 18 of 48
5 4 3 2 1
5 4 3 2 1

+1.05VS For CRT Issue +3VS

U4G POWER Near AE50 20091105


10U_0805_10V4Z 1U_0402_6.3V6K AB24 AE50 +VCCADAC 0.01U_0402_16V7K 1 2
VCCCORE[1] VCCADAC[1] L5
1 1 AB26 VCCCORE[2] 1 1 1 1 60mA
D AB28 69mA AE52 C215 C216 C217 C221 MBK1608221YZF_2P D
C213 C214 VCCCORE[3] VCCADAC[2] L5 Change to 220ohm bead
AD26 VCCCORE[4]1524mA 220 ohm bead,350mA 20091116

CRT
AD28 AF53 0.1U_0402_16V4Z 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 VCCCORE[5] VSSA_DAC[1] 2 2 2 2
AF26 VCCCORE[6]
CRB 0.9 is 180 ohm @ 100MHz

VCC CORE
AF28 VCCCORE[7] VSSA_DAC[2] AF51
Near AB24 Near AB24 AF30 VCCCORE[8] +3VS DG0.8 is 600 ohm FB (Page 290)
AF31 VCCCORE[9]
Top Side AH26 VCCCORE[10] +VCCA_LVDS R293
AH28 VCCCORE[11] 1 2 0_0805_5%
AH30 VCCCORE[12] 300mA Change to 0_0805_5%
Intel suggest follow CRB 8/21 AH31 VCCCORE[13] VCCALVDS AH38
AJ30 20090923
VCCCORE[14]
AJ31 VCCCORE[15] VSSA_LVDS AH39
All Ibex Peak-M Power rails with netnames +1.1VS and
+1.1V rails are actually +1.05VS and +1.05V rails +1.05VS 59mA +1.8VS
VCCTX_LVDS[1] AP43
VCCTX_LVDS[2] AP45
AT46 Near AP43 L6

LVDS
VCCTX_LVDS[3] +VCCTX_LVDS C220
AK24 VCCIO[24] VCCTX_LVDS[4] AT45 2 1
C218 1 1 1 0.1UH_MLF1608DR10KT_10%_1608
42mA 0.01U_0402_16V7K 22U_0805_6.3V6M 0.1uH inductor, 200mA
@ +VCCAPLL_EXP BJ24 C219
T20 PAD VCCAPLLEXP
AB34 0.01U_0402_16V7K
VCC3_3[2] 2 2 2
DG 1.6 (Page 329)
Have Internal VRM AN20 VCCIO[25] VCC3_3[3] AB35
AN22

HVCMOS
VCCIO[26]
AN23 VCCIO[27] VCC3_3[4] AD35 +3VS
AN24 VCCIO[28]
AN26 VCCIO[29] 1
C AN28 C222 C
VCCIO[30]
BJ26 VCCIO[31]
BJ28 0.1U_0402_16V4Z Near AB34
VCCIO[32] 2
AT26 VCCIO[33]
AT28 R296 1 @ 2 0_0805_5% +1.05VS
VCCIO[34]
AU26 VCCIO[35]
+1.05VS AU28 +VCCVRM R297 1 @ 2 0_0805_5%
VCCIO[36] +1.5VS
AV26 VCCIO[37] 35mA R298 1
Near AN20 AV28 VCCIO[38] VCCVRM[2] AT24 2 0_0805_5% +1.8VS
10U_0805_10V4Z 1U_0402_6.3V6K 1U_0402_6.3V6K AW26 3208mA
VCCIO[39]
1 1 1 1 1 AW28 VCCIO[40] 61mA +1.05VS

DMI
BA26 VCCIO[41] VCCDMI[1] AT16
C223 C224 C225 C226 C227 BA28 VCCIO[42] +VCC_DMI R299 1
BB26 VCCIO[43] VCCDMI[2] AU16 2 0_0402_5%
2 2 2 2 2
BB28 VCCIO[44] 1
Change to 0_0402
Top Side BC26 VCCIO[45] 20090914

PCI E*
1U_0402_6.3V6K 1U_0402_6.3V6K BC28 C228
VCCIO[46] 1U_0402_6.3V6K
BD26 VCCIO[47] 2
BD28 VCCIO[48] 156mA
BE26 VCCIO[49] VCCPNAND[1] AM16 Near AT16
BE28 VCCIO[50] VCCPNAND[2] AK16
BG26 VCCIO[51] VCCPNAND[3] AK20
BG28 VCCIO[52] VCCPNAND[4] AK19
Near AN35 BH27 VCCIO[53] VCCPNAND[5] AK15
+1.8VS
VCCPNAND[6] AK13
Follow Intel suggestion 8/21 +3VS AN30 AM12
VCCIO[54] VCCPNAND[7]

NAND / SPI
AN31 VCCIO[55] VCCPNAND[8] AM13
VCCPNAND[9] AM15
0.1U_0402_16V4Z 1
B C229 2 C230 B
1 AN35 VCC3_3[1]
0.1U_0402_16V4Z
2
+VCCVRM AT22 VCCVRM[1]
@ +VCCAPLL_FDI
85mA Near AK13
T21 PAD BJ18 VCCFDIPLL 6mA VCCME3_3[1] AM8
+3VS
VCCME3_3[2] AM9
FDI

DG 1.6 (Page 329) +1.05VS AM23 VCCIO[1] VCCME3_3[3] AP11


Have Internal VRM VCCME3_3[4] AP9
1
C232
REV1.0
IBEXPEAK-M_FCBGA107 0.1U_0402_16V4Z
2
Near AM8

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (7/9) PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW71 M/B LA-6582P Schematic
Date: Thursday, July 08, 2010 Sheet 19 of 48
5 4 3 2 1
5 4 3 2 1

U4J POWER
@ +1.1VS_VCCACLK AP51
52mA REV1.0 V24
T22 PAD VCCACLK[1] VCCIO[5] +1.05VS
VCCIO[6] V26 2 09/09/21 WW37 remove
DG 1.6 (Page 329) AP53 Y24 +1.05VS +VCCADPLLA
VCCACLK[2] VCCIO[7] C240
+VCCADPLLA,+VCCADPLLB external 1U
Have Internal VRM VCCIO[8] Y26
344mA 1U_0402_6.3V6K
+1.05VS 1
AF23 VCCLAN[1] VCCSUS3_3[1] V28
+3VALW L10
Near BB51
R303 1 @ +VCCLAN VCCSUS3_3[2] U28 Near V24 1 2
10UH_LB2012T100MR_20%
2 AF24 VCCLAN[2] VCCSUS3_3[3] U26
0_0603_5% 1 U24 10uH inductor, 120mA 1
VCCSUS3_3[4]

1
P28 1 1 @
VCCSUS3_3[5]

1
D R302 C241 +PCH_VCCD6W Y20 P26 C242 C243 C244 + C245 D
0_0402_5% 1U_0402_6.3V6K DCPSUSBYP VCCSUS3_3[6] 1U_0402_6.3V6K R304
1 VCCSUS3_3[7] N28
@ 2 C246 0.1U_0402_16V4Z 0.1U_0402_16V4Z 220U_6.3V_M_R17 2 0_0402_5%
1998mA N26

2
VCCSUS3_3[8] 2 2
Near AF23 AD38 M28

2
0.1U_0402_16V4Z VCCME[1] VCCSUS3_3[9]
M26 Near A26 Near U23

2
2 VCCSUS3_3[10] +VCCADPLLB
AD39 L28

USB
VCCME[2] VCCSUS3_3[11]
Near Y20 VCCSUS3_3[12] L26
AD41 VCCME[3] VCCSUS3_3[13] J28
J26 @ L11 1 2
+1.05VS VCCSUS3_3[14] 10UH_LB2012T100MR_20%
Follow Intel suggestion AF43 VCCME[4] VCCSUS3_3[15] H28
VCCSUS3_3[16] H26 10uH inductor, 120mA 1

1
22U_0805_6.3V6M AF41 163mA G28 @
VCCME[5] VCCSUS3_3[17] @ + C248
1 1 1 1 1 VCCSUS3_3[18] G26
@ AF42 F28 C247 1U_0402_6.3V6K
C235 C236 C237 C238 C239 VCCME[6] VCCSUS3_3[19] 220U_6.3V_M_R17 2
F26

2
22U_0805_6.3V6M 1U_0402_6.3V6K VCCSUS3_3[20] +3VALW
2 2 2 2 2
V39 VCCME[7] VCCSUS3_3[21] E28 Near BD51
E26

Clock and Miscellaneous


VCCSUS3_3[22] D4
V41 VCCME[8] VCCSUS3_3[23] C28

2
22U_0805_6.3V6M Near AD38 1U_0402_6.3V6K Near V39 C26 CH751H-40PT_SOD323-2
VCCSUS3_3[24]
V42 VCCME[9] VCCSUS3_3[25] B27
VCCSUS3_3[26] A28
Y39 VCCME[10] VCCSUS3_3[27] A26
+1.05VS
All Ibex Peak-M Power rails with netnames +1.1VS and

1
Y41 U23 2/12 Follow EDS1.11 +3VS
+1.1V rails are actually +1.05VS and +1.05V rails VCCME[11] VCCSUS3_3[28] +5VALW
Change to 100 ohm
Y42 VCCME[12] VCCIO[56] V23

2
R305 D5
Near V9 C249 >1mA F24 +VCC5REFSUS 1 2 100_0402_5% CH751H-40PT_SOD323-2
0.1U_0402_16V4Z V5REF_SUS
C 1 2 +VCCRTCEXT V9 2 1 C250 2/12 Follow EDS1.11 C
DCPRTC 1U_0402_6.3V6K R306
Change to 100 ohm

1
>1mA Near F24 100_0402_5%
K49 +VCC5REF 1 2 +5VS
V5REF
+VCCVRM AU24 VCCVRM[3] Change to 1U for power

PCI/GPIO/LPC
357mA 2 1 C251
sequence issue on ICH9 1U_0402_6.3V6K
72mA VCC3_3[8] J38
+VCCADPLLA BB51 VCCADPLLA[1] Near K49
BB53 VCCADPLLA[2] VCC3_3[9] L38
+3VS
73mA VCC3_3[10] M36
+VCCADPLLB BD51 VCCADPLLB[1]
+1.05VS BD53 N36
VCCADPLLB[2] VCC3_3[11]
1
AH23 P36 C252
VCCIO[21] VCC3_3[12]
AJ35 VCCIO[22]
1 1 Near AF32 AH35 U35 0.1U_0402_16V4Z
C255 VCCIO[23] VCC3_3[13] 2 +3VS
C253 1 2 +PCH_VCCIO AF34 Near J38
1U_0402_6.3V6K 1U_0402_6.3V6K R337 0_0603_5% VCCIO[2]
2 2 VCC3_3[14] AD13 Near AD13
1 2 AH34 VCCIO[3]
Near AH35 C254 1 2 C256
Near AH23 1U_0402_6.3V6K AF32 32mA 0.1U_0402_16V4Z
VCCIO[4]
VCCSATAPLL[1] AK3
1 2 +VCCSST V12 AK1 +VCCSATAPLL @ PAD T23
C257 DCPSST VCCSATAPLL[2]
0.1U_0402_16V4Z
Near V12
DG 1.6 (Page 329)
+1.05VS Have Internal VRM
1 2 +VCCSUS Y22
B C260 DCPSUS B
+3VALW 0.1U_0402_16V4Z
Near Y22 VCCIO[9] AH22

P18 VCCSUS3_3[29] VCCVRM[4] AT20 +VCCVRM


1
C261 U19
SATA

VCCSUS3_3[30] +1.05VS
PCI/GPIO/LPC

VCCIO[10] AH19
0.1U_0402_16V4Z U20
2 VCCSUS3_3[31]
VCCIO[11] AD20
Near P18 U22 VCCSUS3_3[32]
VCCIO[12] AF22 1
+3VS
AD19 C262
VCCIO[13] 1U_0402_6.3V6K
V15 VCC3_3[5] VCCIO[14] AF20
2
1 VCCIO[15] AF19
C263 V16 AH20 Near AB19
VCC3_3[6] VCCIO[16]
0.1U_0402_16V4Z Y16 AB19
2 VCC3_3[7] VCCIO[17]
VCCIO[18] AB20
+1.05VS +1.05VS
Near V15 VCCIO[19] AB22
> 1mA VCCIO[20] AD22
AT18 V_CPU_IO[1]
1 1 1 AA34 PCH_VCCME13 R309 1 2 0_0603_5%
CPU

C265 C266 C267 VCCME[13] PCH_VCCME14 R310 0_0603_5%


VCCME[14] Y34 1 2
AU18 Y35 PCH_VCCME15 R311 1 2 0_0603_5%
4.7U_0805_10V4Z 0.1U_0402_16V4Z V_CPU_IO[2] VCCME[15] PCH_VCCME16 R312 0_0603_5%
VCCME[16] AA35 1 2
2 2 2
0.1U_0402_16V4Z Near AT18 2mA 6mA
RTC

A A12 VCCRTC VCCSUSHDA L30 +3VALW A


HDA

C268 1 2 1U_0402_6.3V6K
IBEXPEAK-M_FCBGA107
+RTCVCC Near L30
1 1 1
C270 C271
C269 Security Classification Compal Secret Data Compal Electronics, Inc.
1U_0402_6.3V6K 0.1U_0402_16V4Z 2009/08/01 2010/08/01 Title
2 2 2 Issued Date Deciphered Date
Near A12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (8/9) PWR
0.1U_0402_16V4Z Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW71 M/B LA-6582P Schematic
Date: Thursday, July 08, 2010 Sheet 20 of 48
5 4 3 2 1
5 4 3 2 1

U4I U4H
AY7 VSS[159] VSS[259] H49 AB16 VSS[0]
B11 VSS[160] VSS[260] H5
B15 VSS[161] VSS[261] J24 AA19 VSS[1] VSS[80] AK30
B19 VSS[162] VSS[262] K11 AA20 VSS[2] VSS[81] AK31
B23 VSS[163] VSS[263] K43 AA22 VSS[3] VSS[82] AK32
B31 VSS[164] VSS[264] K47 AM19 VSS[4] VSS[83] AK34
B35 VSS[165] VSS[265] K7 AA24 VSS[5] VSS[84] AK35
B39 VSS[166] VSS[266] L14 AA26 VSS[6] VSS[85] AK38
B43 VSS[167] VSS[267] L18 AA28 VSS[7] VSS[86] AK43

Del PCH XDP


B47 VSS[168] VSS[268] L2 AA30 VSS[8] VSS[87] AK46
B7 VSS[169] VSS[269] L22 AA31 VSS[9] VSS[88] AK49
D BG12 VSS[170] VSS[270] L32 AA32 VSS[10] VSS[89] AK5 D
BB12 VSS[171] VSS[271] L36 AB11 VSS[11] VSS[90] AK8
BB16 VSS[172] VSS[272] L40 AB15 VSS[12] VSS[91] AL2
BB20 VSS[173] VSS[273] L52 AB23 VSS[13] VSS[92] AL52
BB24 VSS[174] VSS[274] M12 AB30 VSS[14] VSS[93] AM11
BB30 VSS[175] VSS[275] M16 AB31 VSS[15] VSS[94] BB44
BB34 VSS[176] VSS[276] M20 AB32 VSS[16] VSS[95] AD24
BB38 VSS[177] VSS[277] N38 AB39 VSS[17] VSS[96] AM20
BB42 VSS[178] VSS[278] M34 AB43 VSS[18] VSS[97] AM22
BB49 VSS[179] VSS[279] M38 AB47 VSS[19] VSS[98] AM24
BB5 VSS[180] VSS[280] M42 AB5 VSS[20] VSS[99] AM26
BC10 VSS[181] VSS[281] M46 AB8 VSS[21] VSS[100] AM28
BC14 VSS[182] VSS[282] M49 AC2 VSS[22] VSS[101] BA42
BC18 VSS[183] VSS[283] M5 AC52 VSS[23] VSS[102] AM30
BC2 VSS[184] VSS[284] M8 AD11 VSS[24] VSS[103] AM31
BC22 VSS[185] VSS[285] N24 AD12 VSS[25] VSS[104] AM32
BC32 VSS[186] VSS[286] P11 AD16 VSS[26] VSS[105] AM34
BC36 VSS[187] VSS[287] AD15 AD23 VSS[27] VSS[106] AM35
BC40 VSS[188] VSS[288] P22 AD30 VSS[28] VSS[107] AM38
BC44 VSS[189] VSS[289] P30 AD31 VSS[29] VSS[108] AM39
BC52 VSS[190] VSS[290] P32 AD32 VSS[30] VSS[109] AM42
BH9 VSS[191] VSS[291] P34 AD34 VSS[31] VSS[110] AU20
BD48 VSS[192] VSS[292] P42 AU22 VSS[32] VSS[111] AM46
BD49 VSS[193] VSS[293] P45 AD42 VSS[33] VSS[112] AV22
BD5 VSS[194] VSS[294] P47 AD46 VSS[34] VSS[113] AM49
BE12 VSS[195] VSS[295] R2 AD49 VSS[35] VSS[114] AM7
BE16 VSS[196] VSS[296] R52 AD7 VSS[36] VSS[115] AA50
BE20 VSS[197] VSS[297] T12 AE2 VSS[37] VSS[116] BB10
BE24 VSS[198] VSS[298] T41 AE4 VSS[38] VSS[117] AN32
C BE30 T46 AF12 AN50 C
VSS[199] VSS[299] VSS[39] VSS[118]
BE34 VSS[200] VSS[300] T49 Y13 VSS[40] VSS[119] AN52
BE38 VSS[201] VSS[301] T5 AH49 VSS[41] VSS[120] AP12
BE42 VSS[202] VSS[302] T8 AU4 VSS[42] VSS[121] AP42
BE46 VSS[203] VSS[303] U30 AF35 VSS[43] VSS[122] AP46
BE48 VSS[204] VSS[304] U31 AP13 VSS[44] VSS[123] AP49
BE50 VSS[205] VSS[305] U32 AN34 VSS[45] VSS[124] AP5
BE6 VSS[206] VSS[306] U34 AF45 VSS[46] VSS[125] AP8
BE8 VSS[207] VSS[307] P38 AF46 VSS[47] VSS[126] AR2
BF3 VSS[208] VSS[308] V11 AF49 VSS[48] VSS[127] AR52
BF49 VSS[209] VSS[309] P16 AF5 VSS[49] VSS[128] AT11
BF51 VSS[210] VSS[310] V19 AF8 VSS[50] VSS[129] BA12
BG18 VSS[211] VSS[311] V20 AG2 VSS[51] VSS[130] AH48
BG24 VSS[212] VSS[312] V22 AG52 VSS[52] VSS[131] AT32
BG4 VSS[213] VSS[313] V30 AH11 VSS[53] VSS[132] AT36
BG50 VSS[214] VSS[314] V31 AH15 VSS[54] VSS[133] AT41
BH11 VSS[215] VSS[315] V32 AH16 VSS[55] VSS[134] AT47
BH15 VSS[216] VSS[316] V34 AH24 VSS[56] VSS[135] AT7
BH19 VSS[217] VSS[317] V35 AH32 VSS[57] VSS[136] AV12
BH23 VSS[218] VSS[318] V38 AV18 VSS[58] VSS[137] AV16
BH31 VSS[219] VSS[319] V43 AH43 VSS[59] VSS[138] AV20
BH35 VSS[220] VSS[320] V45 AH47 VSS[60] VSS[139] AV24
BH39 VSS[221] VSS[321] V46 AH7 VSS[61] VSS[140] AV30
BH43 VSS[222] VSS[322] V47 AJ19 VSS[62] VSS[141] AV34
BH47 VSS[223] VSS[323] V49 AJ2 VSS[63] VSS[142] AV38
BH7 VSS[224] VSS[324] V5 AJ20 VSS[64] VSS[143] AV42
C12 VSS[225] VSS[325] V7 AJ22 VSS[65] VSS[144] AV46
C50 VSS[226] VSS[326] V8 AJ23 VSS[66] VSS[145] AV49
D51 VSS[227] VSS[327] W2 AJ26 VSS[67] VSS[146] AV5
B B
E12 VSS[228] VSS[328] W52 AJ28 VSS[68] VSS[147] AV8
E16 VSS[229] VSS[329] Y11 AJ32 VSS[69] VSS[148] AW14
E20 VSS[230] VSS[330] Y12 AJ34 VSS[70] VSS[149] AW18
E24 VSS[231] VSS[331] Y15 AT5 VSS[71] VSS[150] AW2
E30 VSS[232] VSS[332] Y19 AJ4 VSS[72] VSS[151] BF9
E34 VSS[233] VSS[333] Y23 AK12 VSS[73] VSS[152] AW32
E38 VSS[234] VSS[334] Y28 AM41 VSS[74] VSS[153] AW36
E42 VSS[235] VSS[335] Y30 AN19 VSS[75] VSS[154] AW40
E46 VSS[236] VSS[336] Y31 AK26 VSS[76] VSS[155] AW52
E48 VSS[237] VSS[337] Y32 AK22 VSS[77] VSS[156] AY11
E6 VSS[238] VSS[338] Y38 AK23 VSS[78] VSS[157] AY43
E8
F49
VSS[239] VSS[339] Y43
Y46
AK28 VSS[79] REV1.0 VSS[158] AY47
VSS[240] VSS[340] IBEXPEAK-M_FCBGA107
F5 VSS[241] VSS[341] P49
G10 VSS[242] VSS[342] Y5
G14 VSS[243] VSS[343] Y6
G18 VSS[244] VSS[344] Y8
G2 VSS[245] VSS[345] P24
G22 VSS[246] VSS[346] T43
G32 VSS[247] VSS[347] AD51
G36 VSS[248] VSS[348] AT8
G40 VSS[249] VSS[349] AD47
G44 VSS[250] VSS[350] Y47
G52 VSS[251] VSS[351] AT12
AF39 VSS[252] VSS[352] AM6
H16 VSS[253] VSS[353] AT13
H20 VSS[254] VSS[354] AM5
H30 VSS[255] VSS[355] AK45
A H34 VSS[256] VSS[356] AK39 A
H38 VSS[257] VSS[366] AV14
H42 VSS[258]

REV1.0
IBEXPEAK-M_FCBGA107 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (9/9) VSS & PCH XDP Port
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW71 M/B LA-6582P Schematic
Date: Thursday, July 08, 2010 Sheet 21 of 48
5 4 3 2 1
5 4 3 2 1

+LCDVDD LCD POWER CIRCUIT


+3VALW +3VS
W=60mils

1
R724

1
1
300_0603_5% R725 C618 Add R96 for SA00000U500 part
100K_0402_5% +3VS 20091216

6 2
4.7U_0805_10V4Z U8
2 74AHCT1G125GW_SOT353-5 1 2

1
Q65A R726 R96 100K_0402_5%

3
S
1K_0402_5% Q17 change to SB934130020

OE#
P
D
G D
2N7002DW-T/R7_SOT363-6 2 2 1 2 Q17 2 4 INVTPWM
<16> DPST_PWM A Y
AO3413_SOT23-3

G
D
1
1

1
3

1
C619 +LCDVDD

3
W=60mils R727
0.047U_0402_16V7K
5 Q65B 2 1 @ 2 10K_0402_5%
<16> PCH_ENVDD
1 1 R728 0_0402_5%

2
2N7002DW-T/R7_SOT363-6 C620 C621
4
1

4.7U_0805_10V4Z 0.1U_0402_16V4Z U8 change to SA00000U500


R729 2 2
20091216
100K_0402_5%
2

LED PANEL Conn.


+3VS

JLVDS1
1 1 1 +INVPWR_B+
C626 41 2
C G1 2 C
42 G2 3 3
43 G3 4 4
2 0.1U_0402_16V4Z
44 G4 5 5 +LCDVDD W=60mils
45 G5 6 6
46 7 R731 0_0402_5% BKOFF# R730 1 2 0_0402_5% DISPOFF#
G6 7 +3VS <30> BKOFF#
8 INVTPWM 2 @ 1 R732 1 2 10K_0402_5%
8 DISPOFF# INVT_PWM <30>
9 9
+INVPWR_B+ 10 PCH_LCD_CLK
10 PCH_LCD_DATA PCH_LCD_CLK <16>
11 PCH_LCD_DATA <16>
L12 2 11
1 B+ 12 DAC_BRIG <30>
FBMA-L11-201209-221LMA30T_0805 12 PCH_TXOUT0-
W=40mils 13
13
PCH_TXOUT0+
PCH_TXOUT0- <16>
14 PCH_TXOUT0+ <16>
L13 2 14
1 15
15
FBMA-L11-201209-221LMA30T_0805 16 PCH_TXOUT1-
16 PCH_TXOUT1+ PCH_TXOUT1- <16>
1 1 17 PCH_TXOUT1+ <16>
C622 C623 17
18
470P_0402_50V7K 68P_0402_50V8J 18 PCH_TXOUT2-
19 PCH_TXOUT2- <16>
19 PCH_TXOUT2+
20 PCH_TXOUT2+ <16>
2 2 20
21
21 PCH_TXCLK-
22 PCH_TXCLK- <16>
22 PCH_TXCLK+
23 PCH_TXCLK+ <16>
23
24
24
25
25
26
26 LOCAL_DIM
27 1 @ R15 2 0_0402_5%
INVTPWM 27 LOCAL_DIM <30>
1 2 28
C624 220P_0402_50V7K 28
29
DISPOFF# 29 COLOR_ENG_EN
1 2 30
30 1 @ R16 2 0_0402_5%
C625 220P_0402_50V7K COLOR_ENG_EN <30>
31
31
32
32
33
33
34
B 34 B
35
+3VS 35 For Camera
36
36
11/21 intel JIM suggest Pull high at LVDS Conn 37
37 +3VS
38 USB20_N8
38 USB20_N8 <17>
39 USB20_P8
PCH_LCD_CLK 39 USB20_P8 <17>
R735 1 2 2.2K_0402_5% 40
40
R736 1 2 2.2K_0402_5% PCH_LCD_DATA STARC_107K40-000001-G2
CONN@

@ D10
6 3 USB20_N8
CH3 CH2

+3VS 5 2
Vp Vn

USB20_P8 4 1
CH4 CH1
CM1293-04SO_SOT23-6

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW71 M/B LA-6582P Schematic
Date: Thursday, July 08, 2010 Sheet 22 of 48
5 4 3 2 1
A B C D E

CRT Connector D7 D8 D9
W=40mils
+5VS +R_CRT_VCC +CRT_VCC
D7 / D8 / D9
DAN217_SC59 DAN217_SC59 DAN217_SC59
change to SC6BAV99390 D6 F2

1
2 1 1 2

RB491D_SC59-3 1.1A_6VDC_FUSE

D6 change to SCS00002000 1

3
C501
+3VS 0.1U_0402_16V4Z
1 2 1

PCH_CRT_R 1 2 CRT_R_1 1 2 CRT_R_2 JCRT1


<16> PCH_CRT_R
L24 FBMA-L11-160808-800LMT_0603 L25 FBMA-L11-160808-800LMT_0603 6
11
PCH_CRT_G 1 2 CRT_G_1 1 2 CRT_G_2 1
<16> PCH_CRT_G
L27 FBMA-L11-160808-800LMT_0603 L26 FBMA-L11-160808-800LMT_0603 7
12
PCH_CRT_B 1 2 CRT_B_1 1 2 CRT_B_2 2
<16> PCH_CRT_B
L28 FBMA-L11-160808-800LMT_0603 L29 FBMA-L11-160808-800LMT_0603 8
13

1
1 1 1 1 1 1 1 1 1 3
R473 R475 R474 C505 C506 C507 C508 C509 C510 9
C511 C512 C513 14 G 16
150_0402_1% 150_0402_1% 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 4 17
2 2 2 2 2 2 2 2 2 G
10

2
10P_0402_50V8J 10P_0402_50V8J 22P_0402_50V8J 15
22P_0402_50V8J 1 5
150_0402_1% 10P_0402_50V8J 22P_0402_50V8J Change to 12pf for Discrete C514
C-H_13-12201513CP
100P_0402_50V8J CONN@
2

1 2 CRT_HSYNC_2
+CRT_VCC L33 MBC1608121YZF_0603 DSUB_12

C515 1 2 0.1U_0402_16V4Z R476 2 1 10K_0402_5% 1 2 CRT_VSYNC_2 1


L34 MBC1608121YZF_0603 1 1

1
U22 C516 C517 DSUB_15
2 10P_0402_50V8J 10P_0402_50V8J C518 2 2

OE#
P
PCH_CRT_HSYNC2 4 CRT_HSYNC_1 2 2 68P_0402_50V8J 1
<16> PCH_CRT_HSYNC A Y

G
C519
74AHCT1G125GW_SOT353-5 68P_0402_50V8J

3
2
+CRT_VCC

C520 1 2 0.1U_0402_16V4Z

1
U23

OE#
P
PCH_CRT_VSYNC 2 4 CRT_VSYNC_1
<16> PCH_CRT_VSYNC A Y

G
74AHCT1G125GW_SOT353-5

3 +CRT_VCC 3

+3VS

1
R742 R743
2.2K_0402_5% 2.2K_0402_5%

2
2
PCH_CRT_DATA 1 6 DSUB_12
<16> PCH_CRT_DATA

pull-up 2.2k on PCH side Q19A

5
2N7002DW-T/R7_SOT363-6
pull-up 2k on GPU SIDE PCH_CRT_CLK DSUB_15
<16> PCH_CRT_CLK 4 3

Q19B
2N7002DW-T/R7_SOT363-6

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW71 M/B LA-6582P Schematic
Date: Thursday, July 08, 2010 Sheet 23 of 48
A B C D E
5 4 3 2 1

+3VS
+3VS
+HDMI_5V_OUT NAL00 HDMI connector

1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z JHDMI1
R745 HDMI_HPD 19 HP_DET
1 1 1 1 1 1 1 10K_0402_5% +HDMI_5V_OUT 18 +5V
C645 C646 C644 C647 C648 C649 C650 W=40mils HDMI@ 17
HDMI@ HDMI@ HDMI@ HDMI@ HDMI@ HDMI@ HDMI@ HDMI@ F1 HDMI_SDATA DDC/CEC_GND
16

2
OE# HDMI_SCLK SDA
+5VS 1 2 15 SCL
2
0.1U_0402_16V4Z 2 2 2 2 2 2
1 D 14 Reserved

1
1.1A_6VDC_FUSE HDMI@ 13
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C651 Q20 HDMI_HPD HDMI_R_CK- CEC
2 12 CK- GND 20
0.1U_0402_16V4Z 2N7002_SOT23 G 11 21
CK_shield GND

1
2 HDMI@ S HDMI_R_CK+
D 1 10 22 D

3
C652 R746 HDMI_R_D0- CK+ GND
CG0 CG1 CG2 Swing Pre-amp Slew-rate 9 D0- GND 23
HDMI@ HDMI@ 8
U11 0.1U_0402_16V4Z 100K_0402_5% HDMI_R_D0+ D0_shield
0 0 0 450 0 0 2
7 D0+
HDMI_R_D1- 6
0 0 1 420 0 -3db

2
D1-
5 D1_shield
0 1 0 450 0 -3db (default) +3VS +3VS 25 OE# HDMI_R_D1+ 4
OE# HDMI@ HDMI_R_D2- D1+
0 1 1 460 0 -4db 3 D2-
2 D12 CH751H-40PT_SOD323-2 2
1 0 0 340 0 0 VCC3V HDMI_SCLK R749 1 HDMI@ 2 2.2K_0402_5% 1 HDMI_R_D2+ D2_shield
11 VCC3V SCL_SINK 28 2 +HDMI_5V_OUT 1 D2+
1 0 1 400 2db 0 15 VCC3V
21 29 HDMI_SDATA R747 1 HDMI@ 2 2.2K_0402_5% 1 2 HDMI Conn. SUYIN_100042MR019S153ZL
VCC3V SDA_SINK

2
1 1 0 400 2db 0 Change to DC232000900

@ R748

@ R750
26

2.2K_0402_5%

2.2K_0402_5%
VCC3V CONN@
33 D17 CH751H-40PT_SOD323-2 20090917
1 1 1 420 0 0 40
VCC3V
30 HDMI_HPD
VCC3V HPD_SINK HDMI@
46 VCC3V
32 R751 1 HDMI@ 2 2.2K_0402_5%+3VS HDMI_CLK- R752 1 HDMI@ 2 0_0402_5% HDMI_R_CK-

1
DDC_EN
R753 1 @ 2 2.2K_0402_5% +3VS 1 2
R755 1 HDMI@ 2 4.7K_0402_5% HDMI_CG0 3 R754 HDMI@ 0_0402_5% L14 1 2
CG_0 EQ_0 34 1 2
R756 1 @ 2 2.2K_0402_5% HDMI_CG1 4 35 EQ_S1 R757 1 @ 2 2.2K_0402_5% W CM-2012-900T_0805
CG_1 EQ_1 R758 HDMI@ 0_0402_5% @
1 2 4 4 3 3

R759 1 HDMI@ 2 4.32K_0402_1% OC_S2 6 HDMI_CLK+ R760 1 2 0_0402_5% HDMI_R_CK+


REXT HDMI@
LS_HDMI_DET 7 EQ0 EQ1 Equalization
R761 1 HDMI@ 2 2.2K_0402_5% HPD#
+3VS
SDVO_SDATA 8 HDMI_TX0- R762 1 HDMI@ 2 0_0402_5% HDMI_R_D0-
<16> SDVO_SDATA
R763 1 HDMI@ 2 2.2K_0402_5% SDA 0 0 12dB
C SDVO_SCLK 9 0 1 9dB 1 2 C
<16> SDVO_SCLK SCL 1 2
1 0 6dB L15
1 1 3dB (default) W CM-2012-900T_0805
+3VS R764 1 @ 2 HDMI_CG2 10 @ 4 3
2.2K_0402_5% CG_2 4 3
2

HDMI_TX0+ 1 2 0_0402_5% HDMI_R_D0+


HDMI@ HDMI_TX2+ 13 48 R765 HDMI@
OUT_D4+ IN_D4+ PCH_TMDS_D2 <16>
R766 HDMI_TX2- 14 47
OUT_D4- IN_D4- PCH_TMDS_D2# <16>
0_0402_5% HDMI_TX1- R767 1 HDMI@ 2 0_0402_5% HDMI_R_D1-
HDMI_TX1+ 16 45 PCH_TMDS_D1 <16>
1

HDMI_TX1- OUT_D3+ IN_D3+


17 OUT_D3- IN_D3- 44 PCH_TMDS_D1# <16> 1 1 2 2
L16
HDMI_CLK+ 19 42 W CM-2012-900T_0805
OUT_D2+ IN_D2+ PCH_TMDS_CK <16>
HDMI_CLK- 20 41 @ 4 3
OUT_D2- IN_D2- PCH_TMDS_CK# <16> 4 3
+3VS HDMI_TX0+ 22 39 HDMI_TX1+ R768 1 2 0_0402_5% HDMI_R_D1+
OUT_D1+ IN_D1+ PCH_TMDS_D0 <16>
HDMI_TX0- 23 38 HDMI@
OUT_D1- IN_D1- PCH_TMDS_D0# <16>
1

R769 HDMI_TX2- R770 1 HDMI@ 2 0_0402_5% HDMI_R_D2-


20K_0402_5%
@ 1 1 2
GND PCH_TMDS_CK @ L17 1 2
5 1 2
2

GND
1 HDMI@ 2 12 GND GND 49 R777 2.2K_0402_5% W CM-2012-900T_0805
R771 PCH_DPB_HPD <16> 18 PCH_TMDS_CK# 1 @ 2 @ 4 3
0_0402_5% GND R778 2.2K_0402_5% 4 3
D 24 GND
1

27 HDMI_TX2+ R772 1 2 0_0402_5% HDMI_R_D2+


LS_HDMI_DET Q21 GND HDMI@
2 31 GND
1

G 36
@ GND For HDMI SW Issue
S
2N7002_SOT23

37
3

B R773 GND B
43 GND
20K_0402_5%
@
2

ASM1442T_QFN48_7X7
HDMI@
Change to TI P/N: SA00003DS00
20100608

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/4/15 Deciphered Date 2010/04/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI Level Shife & Conn
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW71 M/B LA-6582P Schematic
Date: Thursday, July 08, 2010 Sheet 24 of 48
5 4 3 2 1
A B C D E F G H

H1
H_3P0
H2
H_3P0
H4
H_3P0
H6
H_3P0
H7
H_3P0
H8
H_3P0
H9
H_3P0
H12
H_3P0
SATA HDD1 Conn.
CL 4.0 mm
@ @ @ @ @ @ @ @ JHDD1

1
1 GND
C658 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 2
<13> SATA_PTX_DRX_P0 A+
C659 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N0 3
<13> SATA_PTX_DRX_N0 A-
4
H21 H22 H23 H24 C661 1 SATA_DTX_PRX_N0 GND
2 0.01U_0402_16V7K 5
B-
1 H_4P2 H_4P2 H_4P2 H_4P2 <13> SATA_DTX_C_PRX_N0 C660 1 SATA_DTX_PRX_P0 1
<13> SATA_DTX_C_PRX_P0 2 0.01U_0402_16V7K 6
B+
7
GND
@ @ @ @
1

1
+3VS 8
+3VS V33
9
V33
10
+5VS V33
1 11
C653 GND
12
GND
13
H18 H41 H42 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z GND
14
H_3P4 H_3P0X3P5N H_3P0N 2 V5
15 V5
1 1 1 1 16 V5
C654 C655 C656 C657 17
@ JMINI1 @ @ GND
18
1

1
Reserved
Stand-off 2 2 2 2
19 GND
20 V12
21 V12 GND 24
1000P_0402_50V7K 1U_0603_10V6K 22 23
V12 GND
FD8 FD7 FD5 FD6
SANTA_192301-1
CONN@
@ @ @ @
1

1
20090915 Update to SANTA
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80

2 2

SATA ODD
FFC Conn.
JODD1
1
C666 1 SATA_PTX_C_DRX_P1 1
<13> SATA_PTX_DRX_P1 2 0.01U_0402_16V7K 2
2
C667 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N1 3
<13> SATA_PTX_DRX_N1 3
4
C668 1 SATA_DTX_PRX_N1 4
<13> SATA_DTX_C_PRX_N1 2 0.01U_0402_16V7K 5
5
C669 1 2 0.01U_0402_16V7K SATA_DTX_PRX_P1 6
<13> SATA_DTX_C_PRX_P1 6
7
7
8
8
+5VS 9
9
10
10
11 13
11 GND
12 14
12 GND

ACES_85201-1205N
3 CONN@ 3

Change to 12P conn. for FFC


20100413

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title
HDD & ODD & Screw Hole
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PEW71 M/B LA-6582P Schematic
Date: Thursday, July 08, 2010 Sheet 25 of 48
A B C D E F G H
A B C D E

For Wireless LAN


+3VS +1.5VS +3VS

47P_0402_50V8J 0.1U_0402_16V4Z 47P_0402_50V8J


1 1 1 1 1 1 1 1
C1148 C1149 @ C1150 C1151 C1152 @ C1157
C37 C38 0.1U_0402_16V4Z
4.7U_0805_10V4Z 4.7U_0805_10V4Z
2 2 2 2 2 2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 20090915 Add for 3G team 20090915 Add for 3G team 1

JMINI1
PCH_PCIE_WAKE# R947 1 @ 2 0_0402_5% 1 2 +3VS
<15,27> PCH_PCIE_WAKE# 1 2
3 4
3 4
5 6 +1.5VS
5 6
<14> MINI1_CLKREQ# 7 8
7 8
9 10
<14> CLK_PCIE_MINI1# 11
13
9
11
10
12
12
14
Del 3G / GPS Module Connect
<14> CLK_PCIE_MINI1 13 14
15 16
15 16

17 17 18 18
19 20 WL_OFF#
19 20 PLT_RST_BUF# WL_OFF# <30>
21 21 22 22 PLT_RST_BUF# <17>
<14> PCIE_DTX_C_PRX_N2 23 24 R949 1 2 0_0603_5% +3VS
23 24 R950 1
<14> PCIE_DTX_C_PRX_P2 25 25 26 26 2 0_0603_5% +3VALW
27 28 @
27 28 PCH_SMBCLK
29 29 30 30 PCH_SMBCLK <12,14>
31 32 PCH_SMBDATA PCH_SMBDATA <12,14>
<14> PCIE_PTX_C_DRX_N2 31 32
<14> PCIE_PTX_C_DRX_P2 33 33 34 34
35 35 36 36 USB20_N12 <17>
37 37 38 38 USB20_P12 <17>
+3VS 39 39 40 40
41 41 42 42 1 R14 2 0_0402_5%
43 43 44 44 Mini1_LED# <30>
45 45 46 46

1
0_0402_5%
R952 1 2 E51TXD_P80DATA_R
47
49
47 48 48
50
(9~16mA)
<30> E51TXD_P80DATA 49 50
E51RXD_P80CLK 51 52 R953
<30> E51RXD_P80CLK 51 52 100K_0402_5%
2 G1 2
G2
G3
G3

2
ACES_88910-5204
53
54
55
56
CONN@ Change to PU +3VS


+3VS 20091230

5.2 mm
Mini Card Power Rating
Power Primary Power (mA) Auxiliary Power (mA)
Peak Normal Normal
+3VS 1000 750
+3V 330 250 250 (wake enable)
+1.5VS 500 375 5 (Not wake enable)

3
FAN1 Conn 3

+5VS
@ C1160 10U_0805_10V4Z
1 2

U60
1 8
EN GND
2 7
+VCC_FAN1 VIN GND
3 6
VOUT GND
<30> EN_DFAN1 4 5
VSET GND
APL5607KI-TRG_SO8

C1166
10U_0805_10V4Z
1 2
+3VS C1167
1000P_0402_50V7K
1 2
1

R956
10K_0402_5%
40mil
JFAN1
2

+VCC_FAN1 1
1
<30> FAN_SPEED1 2 4