IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 59, NO.
4, AUGUST 2012
Impact of Strained-Si PMOS Transistors on SRAM
Soft Error Rates
Nihaar N. Mahatme, Bharat L. Bhuva, Senior Member, IEEE, Yi-Pin Fang, and
Anthony S. Oates, Senior Member, IEEE
Abstract—For advanced deep sub-micron technology nodes, the
use of strained-Si is fast becoming the norm. The experimental Soft
Error Rate of 40 nm technology Deep-N-well SRAMs that incorpo-
rate strained-Si PMOS transistors are compared with the SER for
90 nm, 65 nm and 45 nm Deep-N-Well bulk CMOS SRAMs fabri-
cated without strain. Results indicate that the total SER decreases
by approximately 50% with strain. Most importantly, however, the
Multiple-Cell Upset Rate decreases significantly. The factors that
result in improved SER for strained SRAMs are investigated.
Index Terms—Deep-N-Well, Si-Ge PMOS, single event upsets,
SRAMs.
I. INTRODUCTION
O NE of the hurdles to technology scaling is achieving a
higher ON current to width ratio, while keeping
the leakage currents low. One solution that has been employed
by the semiconductor industry is the use of strain to increase
transistor currents [1], [2]. However, the race to manufacture
such smaller and faster transistors has made transistors more
susceptible to Single-Event Effects (SEE) due to reduced supply
voltages and nodal capacitances. The problem has begun af-
fecting semiconductor memories even in the terrestrial environ-
ment. In the terrestrial environment, commercial semiconductor
memories are affected by neutron radiation (1-1000 MeV) from
cosmic rays and alpha particles released by radioactive impu-
rities in the packaging materials of chips [3], [4]. In fact SEE
are considered the most dominant failure mechanisms for fu-
ture electronics circuits [5].
This work represents the first attempt to quantify the effects of
strained silicon devices on the SER of 40 nm bulk Deep-N-well
CMOS SRAMs. Results are compared with the (Soft Error Rate)
SER of 90 nm, 65 nm and 45 nm SRAMs fabricated in an iden-
tical Deep-N-well technology to gauge the SER trends with
technology scaling. The device and circuit level effects of strain
engineering and how they affect the Single-Bit Upset (SBU)
Manuscript received September 16, 2011; revised December 27, 2011; ac-
cepted February 01, 2012. Date of publication April 03, 2012; date of current
version August 14, 2012. This work was supported in part by the Defense Threat
Reduction Agency and Cisco System Inc., San Jose.
N. N. Mahatme and B. L. Bhuva are with the Department of Electrical
Engineering and Computer Science, Vanderbilt University, Nashville, TN
37212 USA (e-mail: nihaar.n.mahatme@vanderbilt.edu; bharat.bhuva@van-
derbilt.edu).
Y.-P. Fang and A. S. Oates are with the Technology Reliability Physics
Group, Taiwan Semiconductor Manufacturing Company, Hsinchu 300-77,
Taiwan (e-mail: ypfanga@tsmc.com; aoates@tsmc.com).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TNS.2012.2188040
0018-9499/$31.00 © 2012 IEEE
845
rate and Multiple Cell Upset (MCU) rate are explained. It is
important to quantify the impact of any technology changes on
the SBU and MCU rate. For the past few technology genera-
tions, several authors have shown that the MCU rate is of a
growing concern [6], [7]. In fact MCUs could account for a
greater percentage of total errors recorded from SRAMs, due
to radiation exposure. Therefore techniques that seek to reduce
the SER must tackle the problem of MCUs. This work shows
how strained silicon can be used to effectively reduce the MCU
rate, and hence the SER of Deep-N-well SRAMs. A discussion
on how strain can be used in other processes is also included.
II. STRAIN ENGINEERING
The most important advantage of strained devices is that the
carrier mobility increases thereby increasing the drive current.
Strain can be implemented for both NMOS and PMOS tran-
sistors. The choice of straining either or both is influenced by
the relative improvement in mobility that can be achieved. For
example, for PMOS transistors on a 100-plane (channel long
plane), there is significant improvement in hole mobility
in the channel region. However, similar improvement in mo-
bility may not result from straining NMOS transistors on 100-
plane (channel long plane). Hence for transistors on 100-
plane (channel long plane), usually the PMOS transis-
tors are strained. On the other hand for devices on 110 plane
with channel long plane, NMOS strain can be more ef-
fective [8]. For this reason, usually either NMOS transistors or
PMOS transistors are strained. For this study, the PMOS tran-
sistor channel was uniaxially and compressively strained with
Si-Ge in the source-drain.
A. Experimental Details & Results
For the purpose of the test, 90 nm, 65 nm, 45 nm and 40 nm
SRAMs fabricated using Deep-N-Well (DNW) technologies
were chosen for comparison. Apart from smaller sizes as a
result of scaling, the layouts of individual SRAM cell and
the cell array were the same for each technology node. Strain
was implemented only in the PMOS transistors of the 40 nm
SRAM. All_0, All_1 and checkerboard (CHB) patterns were
written into each of the four SRAM arrays and subjected to
neutron irradiation at the Los Alamos Neutron Science Center
(LANSCE). The chips were operated at room temperature and
nominal supply voltage. The supply voltage for 90 nm, 65 nm,
45 nm and 40 nm SRAMs was 1.2 V, 1 V, 0.9 V and 0.9 V
respectively. All the chips were oriented normally to the beam
direction. This orientation presents the metal over-layers in the
path of the beam. These over-layers are additional source of
secondary particles that can cause upsets [9]. For the purpose of
846
Fig. 1. Failure in Time normalized to 90 nm. The SER/bit decreases with tech-
nology scaling. But the SER for strained SRAMs is quite substantially less and
reduces by about 2 X compared to non-strained 40 nm SRAMs.
the test, multiple samples were tested and the part to part vari-
ation was found to be low. Tests were conducted in both static
and dynamic mode. No appreciable difference in cross-section
was observed between the two test results. Results presented
in this work are from neutron irradiation of SRAMs tested in
dynamic mode.
The test results for the total Failure in Time (FIT) Rates or
SER/Mbit are shown in Fig. 1. The reduction in SER due to tech-
nology scaling is about 7-9%. On the other hand, the FIT rates
decrease by a factor of almost 2 for the strained devices. Since
the layout for all technologies is the same, area scaling accounts
for a marginal decrease in SER/bit. But in the case of strained
devices, the decrease is much more than what is accounted by
scaling alone. In the following sections, the primary reasons for
the sizeable reduction in SER for the strained devices are iden-
tified. It will be shown that competing effects of transistor-level
single-event charge collection mechanisms and circuit-level in-
creased current drive influence the single-bit upset (SBU) rate.
The multiple-cell upset (MCU) rate however, is a strong func-
tion of the layout in addition to strain-induced effects.
III. SINGLE-BIT UPSET RATE
The SBU rates for the 40 nm SRAMs are normalized to the
45 nm SRAM SER in Fig. 2. It is important to note that the area
of the 45 nm SRAM is about 1.1 times the size of the 40 nm
SRAM cell. The decreased area will reduce SER due to lower
charge collection efficiency for 40 nm SRAM cell [10]. But 40
nm SRAM cells will have lower critical charge compared with
45 nm SRAM cell. These two competing mechanisms usually
result in a small decrease in the SER with scaling [11]. Addi-
tionally, for the 40 nm SRAM design considered for this study,
charge collection and charge removal processes are affected by
the use of strain. The experimental results show a small decrease
in the SBU rate for 40 nm strained technology compared to 45
nm unstrained technology as shown in Fig. 2.
The primary result of strain was that PMOS drive current in-
creased by about 30%. For an SRAM cell, if an OFF NMOS
transistor collects charge due to a Single-Event (SE) strike, the
corresponding PMOS transistor in the inverter will supply the
restoring current. The restoring current tries to force the affected
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 59, NO. 4, AUGUST 2012
Fig. 2. SBU rate decreases marginally for strained devices.
Fig. 3. Laser induced current transients and ratio of charge collected at time
to charge collected at time , measured a s a function of
mechanical stress [13].
node to revert back to the original value. However collected
charge tries to invert the stored data. The current from collected
charge and the restoring current create a single-event transient at
the affected node. If the voltage at the affected node due to this
transient stays inverted for long enough, a bit-flip occurs. The
critical charge, required to be collected for the cell to
flip in time (flipping-time) is given by [12].
(1)
Where is the critical charge required to flip the
SRAM bit in time , with supply voltage , output ca-
pacitance and restoring current drive . It is quite clear
that increasing the restoring current drive helps to restore the
original charge stored by the capacitor faster and prevent an
upset. The use of strain for PMOS transistors increases the
drive current leading to higher critical charge required for n-hit
to cause an upset. Thus at the circuit level, increased current
drive resulting from strain raises the n-hit upset threshold,
resulting in a reduction in SER.
On the other hand, the charge collection mechanism due to
single-event strikes can be affected by the introduction of strain.
The mechanism that primarily affects compressively strained
devices (such as those used in our work) results in increased
charge collection [13]. This is shown in Fig. 3. Results from [13]
were obtained by mechanically stressing the devices along the
MAHATME et al.: IMPACT OF STRAINED-SI PMOS TRANSISTORS ON SRAM SOFT ERROR RATES
Fig. 4. Aggregate MCU rate from All_1, All_0 and checkerboard input pat-
terns. MCU rate decreases substantially for strained devices. The trend reverses
for 40 nm strained silicon devices. MCU rate decreases. Decrease in MCU rate
is about 60% compared to SBU rate (15%).
direction for junction. This stress in turn affects
the electron mobility in the direction depending on the
kind of stress applied. Compressive strain decreases the electron
mobility and leads to increased charge collection from exper-
imentally measurement transients [13]. Assuming that mecha-
nisms for junctions are not very different under compres-
sive strain, the charge collection would likely increase for hits
on PMOS transistors considered in this study. This increased
charge collection will lead to higher upset probability for hits
on the strained PMOS transistors. Since the strain introduced
by mechanically stressing the device is much less than the strain
introduced by capping layers or strained lattices, such as Si-Ge,
additional study is necessary to fully characterize and determine
the physical effects of strain on the charge collection character-
istics.
Thus, strain-induced increased PMOS transistor drive current
reduces the n-hit upset probability, while increased charge col-
lection for PMOS transistors increases the p-hit upset proba-
bility. The overall effects on the single-event sensitivity of the
SRAM cell will be a combination of the two mechanisms de-
scribed above. On the whole however, the results suggest that
the SBU rate decreases compared to the non-strained devices as
seen in Fig. 2. This suggests that increased drive due to strain
has a stronger impact on the SBU rate for Deep-N-well SRAMs
compared to increased charge collection for PMOS devices due
to strain.
IV. MULTIPLE CELL UPSET RATE
Unlike SBU rate, the MCU rate decreased significantly for
the strained SRAMs, as shown in Fig. 4. In contrast, the MCU
rate increases with scaling until 45 nm for the unstrained tech-
nologies. The primary reason for this increased vulnerability to
MCUs is the fact that scaling has reduced the inter-cell spacing.
As the SRAM cells themselves and the spacing between them
decrease a single-event strike is able to upset many more cells
[14], [15].
However what is more important is that, despite the shrinkage
in technology and inter-cell spacing, the MCU rate reduces sub-
stantially for the strained SRAMs. In fact the trend of increasing
MCU rate for the previous technology generations is reversed as
847
Fig. 5. Combined MCU percentages for all data patterns written into the
SRAMs, i.e., All_1, All_0 and checkerboard. The size of MCU clusters
decreases for the strained devices.
Fig. 6. Layout of transistors for 6 T deep-N-Well SRAMs.
shown in Fig. 4. This indicates that strain seems to have a greater
impact on MCU rate than SBU rate for Deep-N-well SRAMs.
Firstly, the total MCU contribution in 40 nm SRAMs is about
30% compared to 70% for the unstrained 45 nm version. This
means that the total contribution of MCUs to the SER has re-
duced. But more importantly, the average cluster size of MCUs
in the 40 nm strained version are smaller compared to the un-
strained 45 nm SRAM. This is shown in Fig. 5.
The reduction in MCU rate can be better explained when the
effects of strain are studied along with information about the
layout. Since the layout for the strained SRAMs and the non-
strained version were identical, the decrease in MCU rate can
clearly be attributed to strain induced increased current drive.
The representational layout of the SRAM cell for each tech-
nology is as shown in Fig. 6.
Although the sizes scaled with technology, the layout and
placement of transistors remained the same. The word-line is
in the horizontal direction, perpendicular to the wells while the
bit-line is along the direction of the wells. For this particular
layout, the SRAM cell itself is flipped and then laid in the hori-
zontal direction as shown in Fig. 7. As a result the NMOS tran-
sistors from adjacent cells in the word-line (horizontal direction)
share the same P-well. PMOS transistors from adjacent cells in
the word-line do not share a well.
Since the structures were fabricated using Deep-N-Well
(DNW) technology, the P-well is confined within a large DNW
as shown in Fig. 8. When a neutron secondary deposits enough
charge within a p-well, the well potential is perturbed. This
848
Fig. 7. Two SRAM cells flipped and placed horizontally.
Fig. 8. Well structure for the SRAM array. p-wells and n-wells alternate. The
NMOS transistors in Fig. 7 in the p-well are shown here alongside each other
to illustrate the charge confinement that affects both 6-T SRAM cells.
results in parasitic bipolar injection at the source junction of
NMOS transistors in the p-well [15]. In fact this well de-bias
affects the potential at the source-body junction of multiple
NMOS transistors in a given well. What is important to note
is that NMOS transistors that are at the same distance from
the well taps, experience the same amount of parasitic bipolar
injection and charge collection. As result, NMOS transistors
of adjacent SRAM cells, in the same p-well, collect similar
amount of charge and the cells usually upset in pairs. Owing
to this, the even-sized MCU clusters are more common com-
pared to odd-sized clusters. This can be directly correlated to
the higher probability of 2, 4 and 6 bit clusters seen for both
45 nm and 40 nm SRAMs in Fig. 5. Also since the p-wells
run vertically in the bit-line direction, a characteristic double
column upset pattern is observed in the vertical direction for
this particular layout [16].
The probability of such patterns resulting from p-hits will be
very low (ion will have to deposit charge across two separate
n-wells). The similar mechanism of well potential collapse does
not affect the PMOS transistors fabricated in the n-well because
charges can diffuse out more easily in the n-well, which is elec-
trically coupled to the larger Deep-N-Well. Thus for this layout,
upsets due to n-hits dominate. In fact MCU events involving
NMOS transistor charge collection due to parasitic bipolar in-
jection account for a large proportion of the SRAM SER for this
particular layout [16].
From the impact of the layout, it is clear that most of the
MCU events can be attributed to NMOS transistor charge col-
lection events. Since the PMOS transistors are strained, the in-
creased drive current reduces the upset probability. Moreover,
since very few of the MCU events are due to PMOS transistor
charge collection events, the small increase in charge collec-
tion probability does not affect the MCU rate significantly. The
substantial reduction in MCU rate also confirms that increased
PMOS current drive for this particular technology and layout
has a greater impact on SER compared to charge collection.
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 59, NO. 4, AUGUST 2012
Fig. 9. Typical upset signature for All0 and All1 patterns. The double column
pattern shown in blue indicates that adjacent cells with NMOS transistors OFF,
upset.
Fig. 10. Typical upset signature for checkerboard pattern. The double column
pattern shown in blue indicates that adjacent cells with NMOS transistors OFF,
upset.
V. DATA PATTERN DEPENDENCE OF MCUS
A. All_1 and All_0
When the cells are loaded with All_0 or All_1 patterns,
NMOS transistors (in a given P-well) part of adjacent SRAM
cells are either OFF or ON. The NMOS transistors that are OFF
collect charge due to bipolar injection resulting from a neutron
secondary that de-biases the p-well. The SRAM cell upsets and
the resulting double column upset pattern is as shown in Fig. 9.
B. Checkerboard Pattern
The upset pattern for checkerboard input is shown in Fig. 10.
On the other hand, for Checkerboard patterns, only one of the
NMOS transistors of two adjacent SRAM cells is OFF. Con-
sequently only the SRAM cell, whose OFF NMOS transistor
collects charge from bipolar action, upsets. As a result the
well de-bias followed by NMOS charge collection results in a
checkerboard double-column upset pattern, where only one of
the adjacent cells upset. This is shown in Fig. 10.
VI. 3-D TCAD SIMULATION RESULTS
3-D Technology Computer Aided Design (TCAD) simula-
tions to verify experimentally observed lower SER for strained
SRAMs, were carried out for 40 nm technology node. The 40
nm models with and without strain were implemented, so that
simulation results could be used to eliminate the effects of tech-
nology scaling from that of strain. The structures confirmed to
the layout specification and dimensions of the particular tech-
nology library.
To observe the effect of SBUs, normal and angular incidence
ion-strikes that mimic secondary particles from neutron-spal-
lation reactions that intersect the OFF NMOS and PMOS
transistor drains were simulated. Several single-event strike
simulations were carried out on 6-T SRAMs with Linear
Energy Transfer (LET) of the incident particles between
MAHATME et al.: IMPACT OF STRAINED-SI PMOS TRANSISTORS ON SRAM SOFT ERROR RATES
Fig. 11. Percentage of single-bit upsets of 6-T SRAMs for ensemble normal
and angular incidence single-event strike simulations with charge deposition
values from to .
Fig. 12. The two 6-T SRAM cells modeled in a DNW process are encircled.
The appropriate well contact spacing for SRAMs with and without strain (not
shown separately) was included.
to [17], [18]. Equa-
tion (2) was used to calculate the SBU percentage by monitoring
the number of upsets over the total number of simulations
(2)
This is plotted as a percentage in Fig. 11. From the results
of 30 ensemble simulations, SBU percentage showed a clear
reduction in the SBU percentage with the inclusion of strain
(Fig. 11). PMOS charge collection values did not show a marked
difference, as observed in [13].
6-T SRAM simulations along with information about
well-tap distances, well-depth etc. were used to estimate the
reduction in MCU rate for strained SRAMs. Black et al., in
[19], reported a mechanism in which, the upset probability of
SRAM cells depends on the data values stored by the SRAM
cells and the charge deposition value and location. Certain
cells based upon the amount of charge deposited can reverse
their upset. This mechanism is found to affect PMOS devices
of the SRAMs tested and simulated in [19]. Since the PMOS
devices in this study were strained, simulations were carried
out to determine whether this mechanism could affect strained
devices and unstrained devices differently leading to difference
in MCU rates. The silicon block structure used for these simula-
tions, shown in Fig. 12 consists of two 6-T SRAM cells, placed
adjacent to each other in the center of the well. Using two cells
allowed the impact of data pattern on charge collection trends
in adjacent cells to be observed.
The layout of the two models with and without strain was
kept the same. Single event strikes were then simulated in raster
849
Fig. 13. Percentage of multiple-cell upsets of 6-T SRAMs for ensemble single-
event strike simulations.Strikes were simulated along the p-well and n-well.
scan fashion around the two SRAM cells, with strain and those
without strain. This simulation methodology was similar to that
adopted in [19], but with fewer SRAM cells. The key differ-
ence is these simulations compared to those for SBU rate was
that strikes were not simulated on the OFF drains. In each sim-
ulation, the data value written into the SRAMs, total charge de-
posited and strike location was kept the same for both SRAM
cell pairs; with and without strain. The location of these cells
was also varied with respect to the center of the well, to de-
termine the extent of the well-collapse and the impact PMOS
restoring current drive on upset probability. 80 ensemble sim-
ulations comparing the upset probability of strained versus un-
strained SRAMs were carried out. Equation (3) was used to cal-
culate the MCU percentage by monitoring the number of upsets
over the total number of simulations
(3)
The difference in upset sensitivity between the strained and
non-strained SRAMs was mainly due to the NMOS transistor
upset sensitivity. No clear differences in upset probability
between the strained and non-trained version due the upset
reversal mechanism, as explained in [19], was observed. This
dissimilarity could be attributed to different well-tap distances,
cell design and layout and well depth. The total number of
upsets over the ensemble of simulations is plotted as a per-
centage in Fig. 13. As Fig. 13 suggests, the incorporation of
strain clearly reduces the MCU rate as well. Simulation results
agree with experiments to suggest that the probability of upsets
decreases with incorporation of strain. Besides, the decrease in
MCU percentage for strained devices is more than the decrease
in SBU percentage as seen in Fig. 13, for the simulations
performed. This also confirms that n-hits dominate the MCU
rate and strained PMOS transistors have a greater impact on
the MCU rate.
VII. STRAIN ENGINEERING FOR FUTURE TECHNOLOGIES
In this work, the effects of strained silicon PMOS transis-
tors on the SER of Deep-N-Well SRAMs have been reported.
In Deep-N-Well technology, for the layout of SRAMs consid-
ered, NMOS transistor upsets account for a large percentage of
MCUs. In such cases, increased PMOS transistor drive helps re-
store the correct logic value and prevent upsets. Whether strain
engineering can be used effectively to reduce SER for other
850
technologies depends on which transistor is strained and to what
extent. Increasing strain increases the drive current and con-
sequently the . Since the dependence of the SER is
an exponential one [10], , a 3-5 X increase in
is likely to have a 10 X-100 X impact on the SER, which
could be a substantial soft error reliability improvement. As an
example, if strain were to be used to reduce the SER of con-
ventional twin-well SRAMs, then it would be necessary to de-
termine which transistor is more vulnerable to SEE. Based on
the layout information, the appropriate choice of transistor to
be strained should be made. The amount of strain required can
be determined by evaluating the relation between and in-
creased drive due to strain engineering. Strain could also be em-
ployed to reduce SER of comparable sub-50 nm SOI SRAMs.
Although, MCU rates in SOI technology are lower than bulk
SRAM MCU rates, the problem is increasing [21], [22]. As in
this work, a similar layout and data dependence was observed
for 45 nm SOI SRAMs [20]. Such observations related to layout
or knowledge of single-event sensitive transistors can be used
to strain the appropriate transistor for maximum SER reduction.
VIII. CONCLUSION
Data from neutron exposures of 90 nm, 65 nm, 45 nm and
40 nm SRAMs with unstrained and strained-Si fabrication pro-
cesses show strain engineering results in significant SER reduc-
tion. For the SRAM layout used in this study, n-hits dominate
the overall upset rates. For such a layout, introduction of in-
creased PMOS transistor current drive through strained-Si de-
creases the overall SER. This reduction in SER is mainly driven
by a substantial reduction in MCU rates. Most importantly how-
ever, the lower SER is achieved without any area penalty. 3 D
TCAD simulations are used to show that SER trends with and
without strained-Si fabrication process agree reasonably with
those observed experimentally. The results of this work can
be more generally applied to other layouts and fabrication ap-
proaches to mitigate SEE. However the effects on charge col-
lection due to strain and restoring current drives must be inves-
tigated to precisely quantify the reduction in SER.
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