M.

Tech VLSI 2017-2018

S.No PROJECT NAME Design IEEE
A Bit-Plane Decomposition Matrix-Based VLSI Integer
1 Front End 2017
Transform Architecture for HEVC

Probability-Driven Multibit Flip-Flop Integration With Clock

2 Front End 2017
Gating

Area-Time Efficient Architecture of FFT-Based Montgomery

3 Front End 2017
Multiplication

Reliable Low-Latency Viterbi Algorithm Architectures

4 Front End 2017
Benchmarked on ASIC and FPGA

Improved 64-bit Radix-16 Booth Multiplier Based on Partial

5 Front End 2017
Product Array Height Reduction

A Structured Visual Approach to GALS Modeling and

6 Front End 2017
Verification of Communication Circuits

Weighted Partitioning for Fast Multiplierless Multiple-

7 Front End 2017
Constant Convolution Circuit

Low-Latency, Low-Area, and Scalable Systolic-Like Modular

8 Multipliers for GF(2m) Based on Irreducible All-One Front End 2017
Polynomials

9 Probabilistic Error Modeling for Approximate Adders Front End 2017

10 LFSR-Based Generation of Multicycle Tests Front End 2017

Clock-Gating of Streaming Applications for Energy Efficient

11 Front End 2017
Implementations on FPGAs

An Improved DCM-Based Tunable True Random Number

12 Front End 2017
Generator for Xilinx FPGA

RoBA Multiplier: A Rounding-Based Approximate Multiplier

13 Front End 2017
for High-Speed yet Energy-Efficient Digital Signal Processing

14 DLAU: A Scalable Deep Learning Accelerator Unit on FPGA Front End 2017

15 A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices Front End 2017
 Design of Efficient Multiplierless Modified Cosine-Based Comb
16 Front End 2017
Decimation Filters: Analysis and Implementation

Efficient Hardware Implementation of Probabilistic Gradient

17 Front End 2017
Descent Bit-Flipping

Design of Efficient BCD Adders in Quantum-Dot Cellular

18 Front End 2017
Automata

19 Overloaded CDMA Crossbar for Network-On-Chip Front End 2017

High-Throughput and Energy-Efficient Belief Propagation

20 Front End 2017
Polar Code Decoder

21 Design of Power and Area Efficient Approximate Multipliers Front End 2017

An Efficient O(N) Comparison-Free Sorting Algorithm

22 Front End 2017

Energy-Efficient VLSI Realization of Binary64 Division With

23 Front End 2017
Redundant Number Systems

A General Digit-Serial Architecture for Montgomery Modular

24 Front End 2017
Multiplication

High-Speed Parallel LFSR Architectures Based on Improved

25 Front End 2017
State-Space Transformations

Scalable Approach for Power Droop Reduction During Scan-

26 Front End 2017
Based Logic BIST

Sign-Magnitude Encoding for Efficient VLSI Realization of

27 Front End 2017
Decimal Multiplication

A Memory-Based FFT Processor Design With Generalized

28 Front End 2017
Efficient Conflict-Free Address Schemes.

29 On the VLSI Energy Complexity of LDPC Decoder Circuits Front End 2017

30 Reconfigurable Constant Multiplication for FPGAs Front End 2017

LLR-Based Successive-Cancellation List Decoder for Polar Codes

31 Front End 2017
With Multibit Decision
 Area-Efficient Architecture for Dual-Mode Double Precision
32 Front End 2017
Floating Point Division

Digit-Level Serial-In Parallel-Out Multiplier Using Redundant

33 Front End 2017
Representation for a Class of Finite Fields.