Pollachi Institute of Engineering and Technology

Pollachi – 645 205

Academic Year 2017-18 (ODD Semester)
Department of Electronics and Communication Engineering

Name of the Faculty member : Ms.B.MENAKADEVI

Subject Code /Title : EC6009/ Advanced Computer Architecture
Name of the Course : Electronics and Communication Engineering
Semester / Branch : VII / ECE

Course Plan
1. Pre- requisite:
 Basic knowledge about hardware and software used in the system.
 Need to familiar with the concepts of memory related issues in multi-processors
 Well known information about computer organization, design and pipelining concepts

2. Objectives:
 Understand the micro-architectural design of processors
 Learn about the various techniques used to obtain performance improvement and power
savings in current processors

3. Curriculum Gaps:
 Computer Architecture
 Computer Networks

4. List of Text / Reference Books prescribed by University:

T1: John L Hennessey and David A Patterson, “Computer Architecture A Quantitative

Approach”, Morgan Kaufmann/ Elsevier, Fifth Edition, 2012.

R1: Kai Hwang and Faye Briggs, “Computer Architecture and Parallel Processing”,
Mc Graw- Hill International Edition, 2000.

R2: Sima D, Fountain T and Kacsuk P, ”Advanced Computer Architectures: A Design Space
Approach”, Addison Wesley, 2000
5. Other Related Books Available in Library:
1. S.S.Jadhav “ Advance Computer Architecture and computing ”, Technical publications , third
Edition, 2012.
2. A.P.Godse “Computer Organization and Architecture”, Technical publications,
second Edition, 2012.
3. I.A.Dhotre “ Advance Computer Architecture “ Technical publications , First Edition, 2016

6. Lesson Plan

Text / Ref No of Teaching Cumulative

Lecture
Topics to be covered book Page Periods aids / Number of
Hours
No. Planned Remarks period(s)

UNIT – I FUNDAMENTALS OF COMPUTER DESIGN

1. Review of Fundamentals of
CH1 :2-4 1 PPT 1
CPU
2. Memory and IO CH1 :5-7 1 PPT 2
3. Trends in technology CH1 :8 1 BB 3

4. Trends in technology in terms

CH1 :9 1 BB 4
of power

5. Trends in technology in terms

CH1 :10-12 1 BB 5
of energy and cost

6. Dependability of computer
CH1 :12-14 1 BB 6
design

7. Performance evaluation of
CH1 :16 1 BB 7
computer design

8. Review I - 1 BB 8

UNIT- II INSTRUCTION LEVEL PARALLELISM

9. ILP concepts CH2:2-15 1 BB 9

10. Pipelining overview CH2:16 1 BB 10

Compiler Techniques for
11. CH2:18 1 BB 11
Exposing ILP
PPT
12. Dynamic Branch Prediction CH2:20-23 1 12

PPT
13. Dynamic Scheduling CH2:26 1 13

14. Multiple instruction Issue CH2:28 1 BB 14

15. Hardware Based Speculation CH2:30 1 BB 15

16. Static scheduling CH2:35-37 1 BB 16

17. Multi-threading CH2:41 1 BB 17

Limitations of ILP-Case
18. CH2:42-44 1 BB 18
Studies
19. Review II CH2:45 1 PPT 19

UNIT – III DATA-LEVEL PARALLELISM

Vector architecture -
20. CH3:16 1 PPT 20
Introduction

Vector architecture and its CH3:17

21. 1 BB 21
types
PPT
22. SIMD extensions CH3:5 1 22
PPT
23. SIMD extensions procedure CH3:7-9 1 23

24. Graphics Processing units CH3:19 1 BB 24

25. Graphics Processing units CH3:19 1 BB 25

26. Loop level parallelism. CH3:24 1 BB 26

Loop level parallelism with

27. CH3:26 1 BB 27
some examples

28. Review III - 1 PPT 28

UNIT – IV THREAD LEVEL PARALLELISM

29. Symmetric Shared Memory

CH4:5-13 1 PPT 29
Architectures
Distributed Shared Memory
30. CH4:15-17 1 BB 30
Architectures
31. Performance Issues CH4:20 1 BB 31

32. Synchronization CH4:21-24 1 BB 32

Models of Memory
33. CH4:25-27 1 PPT 33
Consistency

34. Case studies: Intel i7 Processor CH4:29 1 PPT 34

35. SMT Processors CH4:32 1 BB 35

36. CMP Processors CH4:34 1 BB 36
 37. Review IV - 1 BB 37

UNIT – V MEMORY AND I/O

38. Cache Performance CH5:8 1 BB 38

39. Reducing Cache Miss Penalty CH5:8 1 BB 39

40. Reducing Cache Miss Rate CH5:9 1 BB 40

41. Reducing Hit Time CH5:10 1 BB 41

Main Memory and
42. CH5:15-19 1 PPT 42
Performance
43. Memory Technology CH5:21 1 PPT 43

44. Types of Storage Devices CH5:23-26 1 BB 44

45. Buses CH5:27-30 1 PPT 45

46. RAID CH5:34-40 1 BB 46

Reliability, Availability and

47. CH5:40 1 BB 47
Dependability
48. I/O Performance Measures CH5:42 1 BB 48

49. Review V - 1 PPT 49

Total No of Periods = 45 (49 Hours)

7. Web Resources
Sl. Unit
Topic Web Link
No. No.
1 1 Trends in http://www.intel.com/assets/pdf/general/servertrendsreleasecomp
technology, power,
lete-v25.pdf
energy and cost,
Dependability
2 3 SIMD extensions https://software.intel.com/en-us/articles/introduction-to-intel-
advanced-vector-extensions
3 3 Loop level http://insidehpc.com/2006/03/what-is-loop-level-parallelism/
parallelism.
4 5 Reducing Hit Time https://people.eecs.berkeley.edu/~pattrsn/252S98/Lec11-
memory.pdf
 8. Additional topics beyond the Syllabus
1. Parallel processing challenges.
2. Flynn's classification
9. Other Related Activities:
Sl. No. Name of the Activity No of activity Planned Details
1. Trends in technology,
power, energy and cost,
Dependability
1. Assignment 3 2. Compiler Techniques for
Exposing ILP
3. Graphics Processing units
2. Guest Lectures - -
3. Industrial Visit - -

10. Internal Test Portions:

Test No. Portion for Test No. of Units

Internal Test - I UNIT 1,2 1 and 1/2
Internal Test - II UNIT 3, 4 (Till topic) 1 and 1/2
Internal Test - III UNIT 4 (From Topic), UNIT 5 2

Faculty in Charge HoD/ ECE Principal

(Ms.B.Menakadevi) (Dr.K.P.Dhanabalakrishnan)