Outline

1. Block Diagram of a TFT-LCD Panel

2. TFT Array Structure
3. The Pixel of STN & TFT Panel
4. The Relationship of the TFT Array & Driving Signal
5. Pixel Layout Structure
6. Introduction to Pixel Design
7. Pixel Equivalent Circuit
8. Capacitor Effect
9. Polarity Reversal Schemes
10. High Aperture Pixel Structure

Passive vs. Active

Simple Matrix Equivalent Circuit Active Matrix Liquit Crystal Display

Simple matrix twisted nematic displays Use a switch device at each capacitor
from a grid of wires with capacitors to trap the charge.
at the crosspoints.

Each capacitor has liquit crystal as its This will hold the voltage across each
dielectric, making an electro optic capacitor throughout the frame time.
transducer.

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 Block Diagram of a TFT-LCD Panel

Timing Signal Vg
Control signal CST
Display R G B R G B
CLC
Controller
Display data D Vcom
S
Gate G
Gate Line
Driver Pixel
Input voltage Gray-Scale
Voltage Source Line TFT
Generator
Gate Line

Vcom
Common Vd
Voltage
Source (Data) Driver
Generator
Gray scale voltage

Vg : Gate Voltage CST : Storage Capa.

Vd : Source Voltage CLC : Liquid Crystal Capa.
Vcom : Common Voltage

TFT Array Structure

Gate Fan-out Line 1st Gate Line

1st Source Line

(1st Signal Line)

Display Area

Source Fan-out Line Transfer

Gate Line

ESD Protection Circuit

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 The Relationship of the TFT Array and Driving Signals

2nd Field

t = Ntp
Data waveform
1st Field

t = tp
t=0

t=0
Pixel on Pixel off

t = tp LC Pixel
Pixel off Pixel on
Gate Driving Pulse
( Progressive Scanning ) RLC CLC

Pixel Layout Structure

CST

Cs on Common Source Line

Cs on Gate

CST Storage Line Pixel ITO

electrode

Pixel ITO a-Si:H TFT

electrode

Gate Line

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 TFT Pixel Design:
Writing Data into the Pixel
Objective: To charge the pixel to the source line voltage.

For 6-bit accuracy, the TFT must be on for at least 5RTFTCpixel

Gate Line time constants. In a VGA display the TFT is on for about
TFT ( on )
30 usec, so the time constants must be ≤ 6 usec. Since
Cpixel = 0.5 pF, RTFT ≤ 12 M .
Ω

Cpixel For a-Si TFTs, µnε

RTFT ≈
L
MΩ K=
K (Vgs - Vth) W Tox
Source
Line
If typical gate overdrive (Vgs - Vth) = 10V, K = 100 and gate
length L = 8 um.
Therefore to accurately write data into the pixel, the TFT width
W ≥ 7 um

TFT Pixel Design:

Storing Data in the Pixel

Objective: To maintain the pixel voltage while the TFT is off.

For 6-bit accuracy, the pixel voltage must not decay more than
Gate Line V= 20mV while the pixel is off. Since Cpixel ≈ 0.5 pF, no
more than Q = Cpixel x V = 10 fC of charge can be allowed
TFT ( off )
to leak ot of the pixel.

Cpixel The TFT is off for almost the entire Tframe = 16.7 msec frame
time. Therefore the TFT leakage current must be less than
Q / Tframe = 0.6 pA.
Source
Line
This level of leakage current is easily obtained with the previously
defined 7 um x 8 um a-Si TFT.

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 TFT Pixel Design:
the Need for a Pixel Storage Capacitor

It is necessary to augment the intrinsic LC capacitance with an extra capacitor.

Three reasons:
1. Leakage effects
Gate Line In a-Si pixels, writing data into the pixel is easy, but there are
problems with leakage current when the TFT is off. Storing
charge in a pixel capacitor reduces the effects of TFT leakage.
2. Couple effects (Feedthrough)
LC When the TFT turns off, capacitive coupling in the TFT “pushes
down” the pixel voltage. A pixel storage capacitor reduces the
coupling effect.
Source 3. LC dielectric relaxation
Line Storage Capacitor
As the LC slowly reorients (after the TFT is turned off), the pixel
voltage changes. A pixel storage capacitor ballasts the pixel
voltage against this effect.

Pixel Equivalent Circuit ( CST on Common )

Last Pixel Electrode

Source Line Cgx Source Line
Gate Line
Cgd
Cgs
CgLC

Cds
Csx
CdLC CST CLC

Cdx
STO Vcom

CST : Storage Capa. Cgd, Cgs, Cds : Parasitic Capa.

CLC : Liquit Crystal Capa. Cgx, Csx, Cdx : Coupling Capa.
CgLC, CdLC : Stray Capa.

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 Pixel Equivalent Circuit ( CST on Gate )
Last Gate Line

CST
Source Line Source Line
Gate Line
Cgd
Cgs
CgLC

Cds
Csx
CdLC CLC

Vcom

CST : Storage Capa. Cgd, Cgs, Cds : Parasitic Capa.

CLC : Liquit Crystal Capa. Cgx, Csx, Cdx : Coupling Capa.
CgLC, CdLC : Stray Capa.

Array Equivalent Circuit ( CST on Gate )

Rson Rson

VSIGNAL VSIGNAL

Source Line Source Line

RC Loading RC Loading

Gate Line RC Loading

Rgon Vcom Vcom
VGATE
CST CLC CST6 CLC6

Gate Line RC Loading

Rgon TFT Vcom TFT Vcom
VGATE
CST CLC CST CLC

Gate Line RC Loading

Rgon TFT Vcom TFT Vcom
VGATE
CST CLC CST CLC

Gate Line RC Loading

Rgon TFT TFT

VGATE

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 Capacitor Effect - I

( A ) Cgs Effect Vd ( B ) Cds Effect Vd

Vg Vg
Cgs VLC
VLC Cds
CLC + CST CLC + CST

Vcom Vcom
Vg
Vd
Field Inversion

dVgs
dVds
VLC
Vcom voltage

Cgs Cds
dVgs = dVg x dVds = dVd x
Cgs + CLC + CST Cgs + CLC + CST

Capacitor Effect - II
( C ) Capa. & Resistor Loading Effect on the Gate Line

Gate Bonding Lead

Gate Line
Driving
Signal

( D ) Liquit Crystal Capa. Effect

Cgs Cgs
Omega = dVg x [ - ]
Cgs + CST + CLC( off ) Cgs + CST + CLC( on )

ε0ε A ε0ε A
C =
d
C =
d
ε= ε ε
CLC = CLC( on ) - CLC( off )
ε CLC L.C. Vth

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 Current Concentration for Horizontal Crosstalk (Line Inv.)
Rg
Gate Line
rg rg
Gate Driver

CLC CST CLC CST

Common
Common Line Line
rc rc
Rg
Gate Line
rg rg
Gate Driver
Off Voltage Voff

CLC CST CLC CST

Rc Common
Common Line
Electrode rc rc
Driver Vcom
Circuit
Source Line Source Line

Current Flow

Suppress Current Concentration by Column/Dot Inv.

Rg
Gate Line
rg rg
Gate Driver

CLC CST CLC CST

Common
Common Line Line
rc rc
Rg
Gate Line
rg rg
Gate Driver
Off Voltage Voff

CLC CST CLC CST

Common
Line
Common rc rc
Electrode
Power Vcom Source Line Source Line
Supply
Current Flow

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 ESD Protection in TFT Array
Source Line Pad

R R

R
Gate Lines

R
Gate Line Pad
Source Lines

Shorting Ring Standard

Potential Line Cs Line
Display
Area
A. Design consideration on B. Design consideration on ESD C. Design consideration on ESD
ESD with shorting ring with high impedance line with TFT resistor

Reasons Why Aperture Ratio Decrease in a

Large-Screen High-Resolution TFT-LCD

Large Screen Size Increase of Gate High Resolution

Line Number

Increase of Gate Decrease of TFT Increase of Increase of Reverse

Line Resistance Writing Data Period Cgs/CLC Ratio Tilt Domain Area /
Pixel Area

Increase of Gate Line

Increase of Vp
Time Constant

Degradation of Display Quality

Increase of Gate Increase of TFT Size (W/L) Increase of Increase of BM

Line Width CST Area Shielding Area

Decrease of Aperture Ratio

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 Design Methods of High Aperture Ratio of TFT-LCD

Early Announces :
1. Using Low Gate Metal Resistance and Reducing Gate Line Width

2. Using Self-Aligned TFT Technology

3. Increasing the Liquid Crystal Holding Ratio, Decreasing the CST Area

4. Storage Capacitor on Gate Line (CST on Gate Pixel Structure)

5. Storage Capacitor by ITO Material

Recent Announces :
1. Integrated Black Matrix on TFT-Array
- Make the process margin of cell alignment low.

2. Shield CST Pixel Structure

- Moves the storage capacitor area around the pixel electrode.
- Covers the area between the pixel electrode and the signal bus-line in the electrode
of the storage capacitor without the black matrix.

3. High Accuracy Process Technology

- Makes the signal bus line width narrow.

"Dual Light Shields" Pixel Structure

Light Source

Secondary Light Shield

Black Matrix ( TFT protector )
Opposite Glass Plate Opposite Glass Plate

Aperture

TFT channel Pixel electrode TFT channel Source Line

Aperture

TFT glass plate Source Line

Gate TFT glass plate

Main Light Shield

(Black Matrix / Storage Capa.) Light Source

Conventional Pixel Structure "Dual Light Shields" Pixel Structure

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 Integrated Black Matrix on TFT Arrays - I

Conventional : BM pattern shown on array pixel pattern is actually formed on

counter substrate, color filter.
TYPE1 : The top and bottom limit of aperture area is formed by data metal
and the right and left is formed by gate metal. The left side gate
metal width must prevent ″reverse tilt domain″ phenomena.
TYPE2 : The gate metals which formed aperture area are linked to the Cst
line, and this can reduce Cst line width.
TYPE3 : Top and bottom data metal which corrected aperture ratio are
removed.
TYPE4 : The gate metal on the right side, where the reverse tilt does not
occur, is removed.

( From SID 92 DIGEST, Page 789)

High Aperture Ratio Pixel Structure

Gate Line CST

Pixel
electrode
Source Line

Black Matrix

TFT

Pixel
Drain/Source
n+ Organic insulator Source Line

a-Si:H
SiNx
Gate Glass Substrate

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