 CPU must:

 Fetch instructions: The CPU reads an instruction

from memory.
 Interpret instructions: The instruction is
decoded to determine what action is required.
 Fetch data: The execution of an instruction may
require reading data from memory or an I/O
module.
 Process data: The execution of an instruction
may require performing some arithmetic or
logical operation on data.
 Write data: The results of an execution may
require writing data to memory or an I/O module.
 Every
CPU consists of the three basic
components shown in the figure below.
 The Arithmetic Logic Unit (ALU) performs the
actual operations.
 Registers hold the inputs of the ALU operations
and eventually receive the results.
 The Control Unit controls the operation of both
ALU and registers through the control signals.

Registers

Control
Unit

ALU
 CPU must have some working space
(temporary storage)
 Called registers
 Number and function vary between processor
designs
 One of the major design decisions
 Top level of memory hierarchy

The registers in the CPU perform two roles:

 User-visible registers
 Control and status registers
A user-visible register is one that may be
referenced by means of the machine
language that the CPU executes. Can be
characterized into the following
categories:
 General Purpose
 Data
 Address
 Condition Codes (flags)
 General purpose registers can be assigned to
a variety of functions by the programmer.
 May be true general purpose
 May be restricted
 May be used for data or addressing
 Data
 Accumulator
 Addressing
 Segment
 Make them general purpose
 Increase flexibility and programmer options
 Increase instruction size & complexity
 Make them specialized
 Smaller (faster) instructions
 Less flexibility
 Between 8 - 32
 Fewer = more memory references
 More does not reduce memory references
and takes up processor real estate
 There is, however, a new approach which
finds advantage of the use of hundreds of
registers exhibited in some RISC systems.
 Address registers should be large enough to
hold full address
 Data registers should be large enough to hold
full word
 Often possible to combine two data registers
 C programming
 double int a;
 long int a;
 Sets of individual bits
 e.g. result of last operation was zero
 Can be read (implicitly) by programs
 e.g. Jump if zero
 Can not (usually) be set by programs
 There are a number of CPU registers
employed to control its operation.
 Are not visible to the user on most machines.
Some may be visible to to machine
instructions executed in a control or
operating system mode.
 Four registers are essential to instruction
execution:
 Program Counter
 Instruction Decoding Register
 Memory Address Register
 Memory Buffer Register
 Program Counter (PC): Contains the address
of an instruction to be fetched.
 Instruction Decoding Register or Instruction
Register (IR): Contains the instruction most
recently fetched.
 Memory Address Register (MAR): Contains the
address of a location in memory.
 Memory Buffer Register (MBR): Contains a
word of data to be written to memory or the
word most recently read.
 In a bus-organized system, the MAR connects
directly to the address bus, and the MBR
connects directly to the data bus.
 All CPU designs include a register or set of registers, often known
as the program status word (PSW), that contain status information.
 The PSW typically contains condition codes plus other status
information.
 Common fields or flags include the following:
 Sign of last result
 Zero
 Carry
 Equal
 Overflow
 Interrupt enable/disable
 Supervisor (Indicates if CPU is executing in supervisor or user mode. Certain
privileged instructions can be executed in only supervisor mode, and certain
areas memory can be accessed only in supervisor mode.)
 instruction cycle includes the following
stages:
 Fetch: Read the next instruction from memory
into the processor.
 Execute: Interpret the opcode and perform
the indicated operation.
 Interrupt: If interrupts are enabled and an
interrupt has occurred, save the current
process state and service the interrupt.
Indirect Cycle
 May require memory access to fetch
operands
 Indirect addressing requires more memory
accesses
 Can be thought of as additional instruction
subcycle
 Depends on CPU design
 In general:

 Fetch
 PC contains address of next instruction
 Address moved to MAR
 Address placed on address bus
 Control unit requests memory read
 Result placed on data bus, copied to MBR, then to
IR
 Meanwhile PC incremented by 1
 IR is examined by the control unit
 If indirect addressing, indirect cycle is
performed
 Right most N bits of MBR, which contain the
address reference, transferred to MAR
 Control unit requests memory read
 Result (address of operand) moved to MBR
 May take many forms
 Depends on instruction being executed
 May include
 Memory read/write
 Input/Output
 Register transfers
 ALU operations
 Simple
 Predictable
 Current PC saved to allow resumption after
interrupt
 Contents of PC copied to MBR
 Special memory location (e.g. stack
pointer) loaded to MAR
 MBR written to memory
 PC loaded with address of interrupt
handling routine
 Next instruction (first of interrupt handler)
can be fetched
 Fetch accessing main memory
 Execution usually does not access main
memory
 Can fetch next instruction during execution
of current instruction
 Called instruction prefetch
 The ALU is the part of the microprocessor
that actually performs the arithmetic and
logical operations on data.
 The rest of the circuitry simply
 brings the data into the ALU,
 tells the ALU what to do with it, and
 takes the results out of the ALU.
Control Flags
Unit
ALU
Registers Registers
 Registers are used to:
 Bring data into the ALU
 Store the results of the ALU’s operations

 Thecontrol unit provides the signals that

control the operation of the ALU and the
movement of data into and out of the ALU

 Most of the operations in the ALU set the

flags to signify some condition.
 Control unit needs to:
 Generate signals for each register transfer action
and other operations specified, and
 Be able to sequence through the steps for
fetching/executing the instructions in the
program

Registers

Control
Unit

ALU
 Hardwired Control
 The control logic is implemented using flip flops,
gates, etc
 The unit is designed specifically for the digital
system being designed
 Modifying it is very tedious
 Microprogrammed Control
 The control information is stored in a Micro-
memory inside the CPU
 The Microprogram memory is loaded with the
sequence of control signals needed to implement
the different instructions
 The system clock produces a continuous sequence of pulses
in a specified duration and frequency. A sequence of steps
t0 , t1 , t2 , . . . , (t0< t1 < t2 . . .) are used to execute a
certain instruction.
 The op-code field of a fetched instruction is decoded to
provide the control signal generator with information
about the instruction to be executed.