BUSES AND SUPPORT DEVICES

INTRODUCTION

A ll of the basic components of the computer are tied together by communications paths
called buses. A computer bus is simply a parallel collection of conductors which carry
data and control signals from one unit to another. Any computer will have three major system
buses identified by the type of information which they carry. These are the address bus, the
data bus, and the control bus, as illustrated in Figure 1.

Figure 1:
System Buses

THE ADDRESS BUS

The address bus is a unidirectional pathway that carries addresses generated by the mP to the
memory and I/O elements of the computer. The size of the address bus, determined by the
number of conductors in the bus, determines the number of memory locations and/or I/O ele-
ments the mP can address. If the address bus is composed of 16 lines (or bits), the mP will be
able to generate 216, or 65,536 distinct address codes. If the address bus size is increased to a
20-bit word size, the mP’s ability to address memory and I/O elements is increased to 220, or
1,048,576 possible addresses.

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 When discussing addressing capacity, it is common to use the letter “K” to represent 1024
(210) addresses. Using this terminology, the first example above would be said to be capable
of addressing up to 64K of memory, while the latter example would be capable of directly ad-
dressing up to 1,000K of memory or 1-Megabyte.

When the mP wishes to access a memory location or I/O element to perform a Read or Write
operation, it does so by placing the appropriate address code on its address pins (A0-AN) and
generating the proper control signals to perform the operation. Since the memory unit is nor-
mally composed of several memory chips (RAM and ROM), special decoding circuitry is re-
quired to select the proper IC and single out the proper memory location (or I/O device) that
the mP is trying to address.

THE DATA BUS

In contrast to the address bus, the data bus is bi-directional in nature. Data flows along this
bus from the mP to memory and I/O, or visa-versa, depending on whether the mP is perform-
ing a Read or Write operation. Since all of the computer elements must share the data bus,
any device whose outputs are connected to the bus must have the ability to put its outputs in a
high impedance state (floating) when not involved in an operation with the mP. This prevents
data from more than one source from being placed on the bus at one time. If two devices at-
tempted to place data on the bus at the same time, confusion and damage to the devices would
result. The size of the data bus usually corresponds to the word size of the computer.

THE CONTROL BUS

The control bus carries all of the timing and control signals necessary to coordinate the ac-
tivities of the entire system. Unlike the other two busses, the control bus signals are not nec-
essarily related to each other; some are output signals from the mP, while others are input
signals to the mP from I/O elements. Each mP will have its own unique set of control signals
which it can generate or respond to. There are many control bus signals that are common to
most mPs (or similar to those used by most processors). Therefore, let’s discuss the more
common control signals in use today.

One of the most important control signals in any mP based system is the system clock. This
signal provides the timing information around which all of the system’s activities take place.
Depending on the type of mP being used, the clock signals may be generated on the mP chip or
by special IC signal generators. Microprocessors with internal clock generators usually re-
quire that an external crystal, or RC network, be connected to its clock input pins.

Figure 2 depicts a distributed clock signal scheme. The clock generator chip (U1) produces a
5 MHz output signal when its F/C signal is high and an 8 MHz signal is derived from the 24
MHz oscillator (Y2) and the 5 MHz signal comes from the RC/crystal network ay X1-X2.
The chip also creates a 14.318 MHz output signal at the OSC output.

BUSES AND SUPPORT DEVICES 2

 Figure 2:
A Distributed
Clock System
In addition to the basic clock frequency produced by the system clock, the computer also
may require derivatives of that frequency to coordinate activities within the system. The sim-
plest method of obtaining a derivative of any given frequency is to run it through a toggle-
type, master/slave flip-flop (f-f). The master/slave f-f is a two stage device which is a natu-
ral divide-by-two device. On the leading edge of the applied clock pulse, the master portion
of the f-f is loaded with an input state which will cause its output to toggle. On the falling
edge of the clock pulse, the master is disabled and the slave stage is enabled. With the slave
enabled, the output toggles from what ever logic state it’s in to the opposite logic level. In this
manner, the flip-flop divides the clock pulse by a factor of two. Both transitions of the clock
pulse are required to produce a single transition at the output.

If flip-flops are cascaded, a binary counter is produced. Every succeeding flip-flop requires
two pulses from the previous f-f to produce a single output change. When you compare this
concept to a binary count table, as depicted in Figure 3, you discover that the elements of the
counter behave in exactly the same manner as the weighted positions of the count table.

There are a number of IC counters available on the market. Some of these, like the divied-
by-six counter in Figure 2, count strictly in binary, while others are modified to count in
BCD. To be used as a counter, the outputs of each f-f element are used. In contrast, to use the
counter as a frequency divider, only those outputs which provide the desired division factor
are used.

BUSES AND SUPPORT DEVICES 3

 Figure 3:
A Digital Counter

The control bus also carries the signals which enable selected memory or I/O elements for
Read and Write operations. These signals may range from a simple Read/Write line (R/W) to
a collection of signals such as Memory Read (MEMR), Memory Write (MEMW), I/O Read
(IOR) and I/O Write (IOW). These signals are used by the mP in conjunction with addresses
on the address bus to perform Read and Write operations at selected memory or I/O loca-
tions.

From the preceding discussions, it should be apparent that I/O devices are treated like mem-
ory locations in that they have addresses. In reality, each I/O device must have its own spe-
cific address. There are two methods by which the
computer can handle I/O addressing. In some computers,
the mP addresses I/O in the same manner as it does memory
locations. This is because the I/O devices are granted a por-
tion of the available address codes and the same control sig-
nals are used to Read and Write both I/O and memory
locations. This method of I/O addressing is referred to as
memory-mapped I/O. A typical memory map for a 64K
computer showing RAM, ROM and I/O address alloca-
tions is depicted in Figure 4.

In other computers, separate control signals and address

decoders are used for I/O addressing. These computers use
outputs such as Memory Request (MREQ) and I/O Re-
quest (IORQ) to distinguish between memory and I/O op-
erations. These lines determine whether memory or I/O
elements will be enabled for a Read or Write operation.
Figure 4: Memory Map This practice of distinguishing between memory and I/O
addressing is referred to as direct I/O or isolated I/O.

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There are advantages and disadvantages to both addressing methods. In the memory-
mapped method, the same instructions used to reference memory can also be used to send
data to, or fetch data from, an I/O device. But, the I/O devices use up a portion of the available
address codes, limiting the actual amount of storage available in the memory. In direct I/O
systems, none of the memory allocations are used up by I/O devices, but extra control lines
are required.

SUPPORT DEVICES
Although the microprocessor is ultimately responsible for the operation of the system, a
great number of support devices are necessary to aid the mP in carrying out its various func-
tions. In addition to the basic digital logic gates (AND, OR, NAND, NOR and INVERTER gates)
depicted in Figure 5, the computer relies on a number of medium scale integration (MSI)
devices to perform many functions for the mP. The most basic of these MSI devices are
latches, registers, multiplexers, demultiplexers, and decoders.

Figure 5:
SSI Devices

Latches And Registers

Latches (also called D-type flip-flops) are basic memory devices normally used for short-
term information storage. The function of a latch is to hold or latch a value (logic level, or bi-
nary value) from the D input on its output. Once a value is placed on the D input and the En-
able line makes a transition from logic 1 to logic 0, the latch will hold this value at the output
even if the value on the input changes. The value on the output will be maintained until the
Enable line is activated again.

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 The latch, illustrated in Figure 6, is comprised of three fundamental sections. The basic latch
consists of a pair of cross-coupled NOR gates. This section is preceded by two AND gates
and an Inverter that transform the basic latch into a Data, or D-type, Latch. The NOR gate
and inverter that form the Enable input cause the latch to be accept input on a falling edge of
the clock.

Figure 6: Latch

Registers are simply multiple latches, like the one described in the previous section,
working together. An eight-bit register is shown in Figure 7. Registers can be found
inside intelligent IC’s, like microprocessors or smart controllers, or they can be dis-
crete IC’s used throughout the system. In smart IC’s, registers are used for temporary
storage of values inside of the device. A microprocessor will use the registers to hold
data values for the Arithmetic Logic Unit (ALU) and to hold address values that are
to be placed on the address bus. Data is placed on the D inputs in parallel and a com-
mon enable signal is used to latch the data to the Q outputs.

Multiplexers
Multiplexers (MUX’s) are devices which can accept digital logic levels or pulse train
signals on a number of different inputs and select ONE to be passed to a single output
line. Hence, the multiplexer is often referred to as a data selector. Which of the various
inputs is allowed to pass through to the output is determined by a binary code applied
to the multiplexer’s SELECT lines. This relationship is demonstrated in Figure 8.
The data present on Input-5 (I-5) passes through to the output because of the binary
coded 5 (101) on the select lines (S0 through S2). The designers of digital chips take
care to orient the relationship between the inputs and the select lines to the binary
number system. In other words, to select the logic level at any input for passage to the
output, simply apply its number (in binary code) to the Select lines.
Figure 7: Register

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 Figure 8:
Multiplexer

Demultiplexers
Demultiplexers (DEMUX’s) perform just the reverse function of the multiplexer.
Instead of selecting an input to be passed to an output, the DEMUX accepts a single
input and distributes the logic level, or digital pulse train, to a number of possible out-
puts, under the direction of the SELECT lines. This relationship is depicted in Figure
9, where a logic “1" at the input is passed to output O4, because of the binary 4 (1002)
at the SELECT lines. Notice that all other output pins are held low because they are
kept in their non-active state when they are not selected. Many commercially avail-
able demultiplexers use low-active output pins. With these devices, the Non-
Selected outputs will be held high and the Selected output will invert the logic level
present at the input. Therefore, when a low logic level is present at the input, the out-
put will produce a high logic level at the selected output, and visa-versa. Devices
with active low outputs are denoted on schematic diagrams by the presence of small
circles at their output pins.

Figure 9: Demultiplexer

Decoders
Decoders are digital devices which are very similar to
demultiplexers. However, instead of passing a logic
level from the input to a selected output, decoders use a
binary coded input to activate a single output, whose
number corresponds to the input code. This relation-
ship is shown in Figure 10, where a binary coded 6 is
applied to the input pins of the decoder and its number
6 output goes high. All other outputs are held low in
their non-active state. Like the demultiplexer, the de-
coder can also employ active-low outputs. With these
devices, all outputs are held high, except for the se-
lected output, which is low.
Figure 10: Decoder

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 Strobe Or Enable Inputs
Many IC manufacturers market their decoder devices as Decoder/Demultiplexers because of
their basic similarities. In order to see how this is possible, we must look at some special pins
which are present on most MSI, LSI, and VLSI devices. These are ENABLE, or STROBE,
inputs. These pins control the overall operation of the device, in that, the device functions
normally when the proper logic level is applied to them. When the opposite logic level is
present, the entire device is disabled and all inputs and outputs are placed in a high imped-
ance (floating) state. It is not uncommon for these devices to have more than one Enable pin.
Semiconductor memories often have multiple Enable pins added to them. These pins are
usually labeled as a Chip Select (CS) or Chip Enable (CE). In order to Enable the device, all
of the Enable pins must have their enabling logic levels applied to them.

Figure 11 shows a Decoder/Demultiplexer device being used for both applications. In part
(a) of the figure, all ENABLE pins are tied to enabling logic levels and the device is operating
as a decoder. In part (b) of the figure, the SELECT lines are used to select the desired output
and one of the ENABLE pins is used as the data input. The data is transmitted to the output by
using the data logic levels to alternately enable and disable the output. Thus, the input data is
actually recreated at the output by the enable/disable action of the ENABLE pin.

Figure 11:
Decoder/Demultiplexer

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